*/\n#define DAC_CR_CEN1_Pos (14U)\n#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */\n#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/\n\n#define DAC_CR_HFSEL_Pos (15U)\n#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */\n#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/\n\n#define DAC_CR_EN2_Pos (16U)\n#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\n#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/\n#define DAC_CR_CEN2_Pos (30U)\n#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */\n#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/\n\n/***************** Bit definition for DAC_SWTRIGR register ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!\n\n/** @addtogroup Peripheral_registers_structures\n * @{\n */\n\n/**\n * @brief Analog to Digital Converter\n */\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */\n __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */\n __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */\n __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */\n __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */\n __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */\n __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */\n uint32_t RESERVED1; /*!< Reserved, 0x1C */\n __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */\n __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */\n __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */\n uint32_t RESERVED2; /*!< Reserved, 0x2C */\n __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */\n __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */\n __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */\n __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */\n __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */\n uint32_t RESERVED3; /*!< Reserved, 0x44 */\n uint32_t RESERVED4; /*!< Reserved, 0x48 */\n __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */\n uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */\n __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */\n __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */\n __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */\n __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */\n uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */\n __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */\n __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */\n __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */\n __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */\n uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */\n __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */\n __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */\n uint32_t RESERVED8; /*!< Reserved, 0x0A8 */\n uint32_t RESERVED9; /*!< Reserved, 0x0AC */\n __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */\n __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */\n uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */\n __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */\n} ADC_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */\n uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */\n __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */\n __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */\n} ADC_Common_TypeDef;\n\n/**\n * @brief FD Controller Area Network\n */\n\ntypedef struct\n{\n __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */\n __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */\n uint32_t RESERVED1; /*!< Reserved, 0x008 */\n __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */\n __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */\n __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */\n __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */\n __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */\n __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */\n __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */\n __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */\n __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */\n uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */\n __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */\n __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */\n __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */\n uint32_t RESERVED3; /*!< Reserved, 0x04C */\n __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */\n __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */\n __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */\n __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */\n uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */\n __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */\n __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */\n __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */\n uint32_t RESERVED5; /*!< Reserved, 0x08C */\n __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */\n __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */\n __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */\n __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */\n uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */\n __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */\n __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */\n __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */\n __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */\n __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */\n __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */\n __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */\n __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */\n __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */\n __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */\n __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */\n} FDCAN_GlobalTypeDef;\n\n/**\n * @brief FD Controller Area Network Configuration\n */\n\ntypedef struct\n{\n __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */\n} FDCAN_Config_TypeDef;\n\n/**\n * @brief Comparator\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */\n} COMP_TypeDef;\n\n/**\n * @brief CRC calculation unit\n */\n\ntypedef struct\n{\n __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\n __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\n __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\n uint32_t RESERVED0; /*!< Reserved, 0x0C */\n __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\n __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\n} CRC_TypeDef;\n\n/**\n * @brief Clock Recovery System\n */\ntypedef struct\n{\n __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */\n __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */\n __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */\n __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */\n} CRS_TypeDef;\n\n/**\n * @brief Digital to Analog Converter\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\n __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\n __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\n __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\n __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\n __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\n __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\n __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\n __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\n __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\n __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\n __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\n __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */\n __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */\n __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */\n __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */\n __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */\n __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */\n __IO uint32_t RESERVED[2];\n __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */\n __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */\n __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */\n} DAC_TypeDef;\n\n/**\n * @brief Debug MCU\n */\n\ntypedef struct\n{\n __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\n __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\n __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */\n __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */\n __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */\n} DBGMCU_TypeDef;\n\n/**\n * @brief DMA Controller\n */\n\ntypedef struct\n{\n __IO uint32_t CCR; /*!< DMA channel x configuration register */\n __IO uint32_t CNDTR; /*!< DMA channel x number of data register */\n __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */\n __IO uint32_t CMAR; /*!< DMA channel x memory address register */\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */\n __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */\n} DMA_TypeDef;\n\n/**\n * @brief DMA Multiplexer\n */\n\ntypedef struct\n{\n __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */\n}DMAMUX_Channel_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */\n __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */\n}DMAMUX_ChannelStatus_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */\n}DMAMUX_RequestGen_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */\n __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */\n}DMAMUX_RequestGenStatus_TypeDef;\n\n/**\n * @brief External Interrupt/Event Controller\n */\n\ntypedef struct\n{\n __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */\n __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */\n __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */\n __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */\n __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */\n __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */\n uint32_t RESERVED1; /*!< Reserved, 0x18 */\n uint32_t RESERVED2; /*!< Reserved, 0x1C */\n __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */\n __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */\n __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */\n __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */\n __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */\n __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */\n} EXTI_TypeDef;\n\n/**\n * @brief FLASH Registers\n */\n\ntypedef struct\n{\n __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\n __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */\n __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */\n __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */\n __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */\n __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */\n __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */\n uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */\n __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */\n __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */\n __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */\n __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */\n __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */\n uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */\n __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */\n} FLASH_TypeDef;\n\n/**\n * @brief FMAC\n */\ntypedef struct\n{\n __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */\n __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */\n __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */\n __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */\n __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */\n __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */\n __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */\n __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */\n} FMAC_TypeDef;\n\n\n/**\n * @brief General Purpose I/O\n */\n\ntypedef struct\n{\n __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\n __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\n __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\n __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\n __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\n __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\n __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */\n __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\n __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\n __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */\n} GPIO_TypeDef;\n\n/**\n * @brief Inter-integrated Circuit Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\n __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\n __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\n __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\n __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\n __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\n __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\n __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\n __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\n __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */\n} I2C_TypeDef;\n\n/**\n * @brief Independent WATCHDOG\n */\n\ntypedef struct\n{\n __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\n __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\n __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\n __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\n __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\n} IWDG_TypeDef;\n\n/**\n * @brief LPTIMER\n */\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\n __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\n __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\n __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\n __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\n __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\n __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\n __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\n __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */\n} LPTIM_TypeDef;\n\n/**\n * @brief Operational Amplifier (OPAMP)\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */\n __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */\n __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */\n} OPAMP_TypeDef;\n\n/**\n * @brief Power Control\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */\n __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */\n __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */\n __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */\n __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */\n __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */\n uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */\n __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */\n __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */\n __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */\n __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */\n __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */\n __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */\n __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */\n __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */\n __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */\n __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */\n __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */\n __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */\n __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */\n __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */\n uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */\n __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */\n} PWR_TypeDef;\n\n\n/**\n * @brief Reset and Clock Control\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\n __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */\n __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\n __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */\n uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */\n uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */\n __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */\n __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */\n __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */\n uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */\n __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */\n __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */\n __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */\n uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */\n __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */\n __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */\n __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */\n uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */\n __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */\n __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */\n __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */\n uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */\n __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */\n __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */\n __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */\n uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */\n __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */\n __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */\n __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */\n uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */\n __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */\n __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */\n __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */\n uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */\n __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */\n uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */\n __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */\n __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */\n __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */\n __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */\n} RCC_TypeDef;\n\n/**\n * @brief Real-Time Clock\n */\n/*\n* @brief Specific device feature definitions\n*/\n#define RTC_TAMP_INT_6_SUPPORT\n#define RTC_TAMP_INT_NB 4u\n\n#define RTC_TAMP_NB 3u\n#define RTC_BACKUP_NB 16u\n\n\ntypedef struct\n{\n __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\n __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\n __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */\n __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */\n __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\n __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\n __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */\n uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */\n uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */\n __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\n __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */\n __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\n __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\n __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\n __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\n uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */\n __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */\n __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\n __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */\n __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */\n __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */\n __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */\n uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */\n __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */\n} RTC_TypeDef;\n\n/**\n * @brief Tamper and backup registers\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */\n uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */\n __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */\n uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */\n uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */\n __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */\n __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */\n __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */\n uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */\n __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */\n uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */\n __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */\n __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */\n __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */\n __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */\n __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */\n __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */\n __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */\n __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */\n __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */\n __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */\n __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */\n __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */\n __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */\n __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */\n __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */\n __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */\n} TAMP_TypeDef;\n\n/**\n * @brief Serial Audio Interface\n */\n\ntypedef struct\n{\n __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\n uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */\n __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */\n __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\n __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\n __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\n __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\n __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\n __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\n __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\n __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/**\n * @brief Serial Peripheral Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */\n __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */\n __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\n __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */\n __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */\n __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */\n __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\n __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n * @brief System configuration controller\n */\n\ntypedef struct\n{\n __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\n __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */\n __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */\n __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */\n __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */\n __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */\n} SYSCFG_TypeDef;\n\n/**\n * @brief TIM\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\n __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\n __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\n __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\n __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\n __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\n __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\n __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\n __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\n __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\n __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\n __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\n __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\n __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\n __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\n __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */\n __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */\n __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */\n __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */\n __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */\n __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */\n __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */\n __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */\n __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */\n uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */\n __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */\n __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */\n} TIM_TypeDef;\n\n/**\n * @brief Universal Synchronous Asynchronous Receiver Transmitter\n */\ntypedef struct\n{\n __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */\n __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\n __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */\n __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\n __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */\n __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\n __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\n __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\n __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\n __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\n __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */\n} USART_TypeDef;\n\n/**\n * @brief Universal Serial Bus Full Speed Device\n */\n\ntypedef struct\n{\n __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */\n __IO uint16_t RESERVED0; /*!< Reserved */\n __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */\n __IO uint16_t RESERVED1; /*!< Reserved */\n __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */\n __IO uint16_t RESERVED2; /*!< Reserved */\n __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */\n __IO uint16_t RESERVED3; /*!< Reserved */\n __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */\n __IO uint16_t RESERVED4; /*!< Reserved */\n __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */\n __IO uint16_t RESERVED5; /*!< Reserved */\n __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */\n __IO uint16_t RESERVED6; /*!< Reserved */\n __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */\n __IO uint16_t RESERVED7[17]; /*!< Reserved */\n __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */\n __IO uint16_t RESERVED8; /*!< Reserved */\n __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */\n __IO uint16_t RESERVED9; /*!< Reserved */\n __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */\n __IO uint16_t RESERVEDA; /*!< Reserved */\n __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */\n __IO uint16_t RESERVEDB; /*!< Reserved */\n __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */\n __IO uint16_t RESERVEDC; /*!< Reserved */\n __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */\n __IO uint16_t RESERVEDD; /*!< Reserved */\n __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */\n __IO uint16_t RESERVEDE; /*!< Reserved */\n} USB_TypeDef;\n\n/**\n * @brief VREFBUF\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */\n __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */\n} VREFBUF_TypeDef;\n\n/**\n * @brief Window WATCHDOG\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\n __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\n __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\n} WWDG_TypeDef;\n\n\n/**\n * @brief RNG\n */\ntypedef struct\n{\n __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\n __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\n __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n * @brief CORDIC\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */\n __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */\n __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */\n} CORDIC_TypeDef;\n\n/**\n * @brief UCPD\n */\n\ntypedef struct\n{\n __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */\n __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */\n __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */\n __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */\n __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */\n __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */\n __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */\n __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */\n __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */\n __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */\n __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */\n __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */\n __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */\n __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */\n __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */\n} UCPD_TypeDef;\n\n\n/**\n * @}\n */\n\n/** @addtogroup Peripheral_memory_map\n * @{\n */\n\n#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */\n#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */\n#define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */\n#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */\n#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */\n\n#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */\n#define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */\n#define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */\n#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */\n/* Legacy defines */\n#define SRAM_BASE SRAM1_BASE\n#define SRAM_BB_BASE SRAM1_BB_BASE\n\n#define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */\n#define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */\n#define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE PERIPH_BASE\n#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)\n\n\n/*!< APB1 peripherals */\n#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)\n#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)\n#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)\n#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)\n#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)\n#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)\n#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)\n#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)\n#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)\n#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */\n#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */\n#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)\n#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */\n#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)\n#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)\n#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)\n#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)\n#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)\n#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)\n\n/*!< APB2 peripherals */\n#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)\n#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)\n#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)\n#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)\n#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)\n#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)\n#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)\n#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)\n#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)\n#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)\n\n#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)\n#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)\n#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)\n#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)\n#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)\n#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)\n#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)\n#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)\n#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)\n#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)\n\n/*!< AHB1 peripherals */\n#define DMA1_BASE (AHB1PERIPH_BASE)\n#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)\n#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)\n#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)\n#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)\n#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)\n#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)\n#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)\n\n#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)\n#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)\n#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)\n#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)\n#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)\n#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)\n\n#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)\n#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)\n#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)\n#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)\n#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)\n#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)\n\n#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)\n#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)\n#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)\n#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)\n#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)\n#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)\n#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL)\n#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL)\n#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL)\n#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL)\n#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL)\n#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL)\n#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)\n#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)\n#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)\n#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)\n\n#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)\n#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)\n\n/*!< AHB2 peripherals */\n#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)\n\n#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)\n#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)\n#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)\n\n#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)\n#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)\n#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)\n\n#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)\n/* Debug MCU registers base address */\n#define DBGMCU_BASE (0xE0042000UL)\n\n#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */\n#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */\n/**\n * @}\n */\n\n/** @addtogroup Peripheral_declaration\n * @{\n */\n#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\n#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\n#define CRS ((CRS_TypeDef *) CRS_BASE)\n#define TAMP ((TAMP_TypeDef *) TAMP_BASE)\n#define RTC ((RTC_TypeDef *) RTC_BASE)\n#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\n#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\n#define USART2 ((USART_TypeDef *) USART2_BASE)\n#define USART3 ((USART_TypeDef *) USART3_BASE)\n#define UART4 ((USART_TypeDef *) UART4_BASE)\n#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\n#define USB ((USB_TypeDef *) USB_BASE)\n#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)\n#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)\n#define PWR ((PWR_TypeDef *) PWR_BASE)\n#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\n#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\n#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)\n#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)\n\n#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)\n#define COMP1 ((COMP_TypeDef *) COMP1_BASE)\n#define COMP2 ((COMP_TypeDef *) COMP2_BASE)\n#define COMP3 ((COMP_TypeDef *) COMP3_BASE)\n#define COMP4 ((COMP_TypeDef *) COMP4_BASE)\n\n#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)\n#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)\n#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)\n#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)\n\n#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\n#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\n#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\n#define USART1 ((USART_TypeDef *) USART1_BASE)\n#define TIM15 ((TIM_TypeDef *) TIM15_BASE)\n#define TIM16 ((TIM_TypeDef *) TIM16_BASE)\n#define TIM17 ((TIM_TypeDef *) TIM17_BASE)\n#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\n#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\n#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)\n#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)\n#define RCC ((RCC_TypeDef *) RCC_BASE)\n#define FMAC ((FMAC_TypeDef *) FMAC_BASE)\n#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\n#define CRC ((CRC_TypeDef *) CRC_BASE)\n\n#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\n#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\n#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)\n#define DAC ((DAC_TypeDef *) DAC_BASE)\n#define DAC1 ((DAC_TypeDef *) DAC1_BASE)\n#define DAC3 ((DAC_TypeDef *) DAC3_BASE)\n#define RNG ((RNG_TypeDef *) RNG_BASE)\n\n#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\n#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\n#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\n#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\n#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\n#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\n\n#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\n#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\n#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\n#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\n#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\n#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)\n\n#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)\n#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)\n#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)\n#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)\n#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)\n#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)\n#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)\n#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)\n#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)\n#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)\n#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)\n#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)\n\n#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)\n#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)\n#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)\n#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)\n\n#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)\n#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)\n\n\n\n#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\n\n/**\n * @}\n */\n\n/** @addtogroup Exported_constants\n * @{\n */\n\n /** @addtogroup Hardware_Constant_Definition\n * @{\n */\n#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */\n\n /**\n * @}\n */\n\n/** @addtogroup Peripheral_Registers_Bits_Definition\n * @{\n */\n\n/******************************************************************************/\n/* Peripheral Registers_Bits_Definition */\n/******************************************************************************/\n\n/******************************************************************************/\n/* */\n/* Analog to Digital Converter */\n/* */\n/******************************************************************************/\n\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\n\n/******************** Bit definition for ADC_ISR register *******************/\n#define ADC_ISR_ADRDY_Pos (0U)\n#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */\n#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */\n#define ADC_ISR_EOSMP_Pos (1U)\n#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */\n#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */\n#define ADC_ISR_EOC_Pos (2U)\n#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */\n#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */\n#define ADC_ISR_EOS_Pos (3U)\n#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */\n#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */\n#define ADC_ISR_OVR_Pos (4U)\n#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */\n#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */\n#define ADC_ISR_JEOC_Pos (5U)\n#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */\n#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */\n#define ADC_ISR_JEOS_Pos (6U)\n#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */\n#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */\n#define ADC_ISR_AWD1_Pos (7U)\n#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */\n#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */\n#define ADC_ISR_AWD2_Pos (8U)\n#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */\n#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */\n#define ADC_ISR_AWD3_Pos (9U)\n#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */\n#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */\n#define ADC_ISR_JQOVF_Pos (10U)\n#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */\n#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */\n\n/******************** Bit definition for ADC_IER register *******************/\n#define ADC_IER_ADRDYIE_Pos (0U)\n#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */\n#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */\n#define ADC_IER_EOSMPIE_Pos (1U)\n#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */\n#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */\n#define ADC_IER_EOCIE_Pos (2U)\n#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */\n#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */\n#define ADC_IER_EOSIE_Pos (3U)\n#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */\n#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */\n#define ADC_IER_OVRIE_Pos (4U)\n#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */\n#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */\n#define ADC_IER_JEOCIE_Pos (5U)\n#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */\n#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */\n#define ADC_IER_JEOSIE_Pos (6U)\n#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */\n#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */\n#define ADC_IER_AWD1IE_Pos (7U)\n#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */\n#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */\n#define ADC_IER_AWD2IE_Pos (8U)\n#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */\n#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */\n#define ADC_IER_AWD3IE_Pos (9U)\n#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */\n#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */\n#define ADC_IER_JQOVFIE_Pos (10U)\n#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */\n#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */\n\n/******************** Bit definition for ADC_CR register ********************/\n#define ADC_CR_ADEN_Pos (0U)\n#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */\n#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */\n#define ADC_CR_ADDIS_Pos (1U)\n#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */\n#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */\n#define ADC_CR_ADSTART_Pos (2U)\n#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */\n#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */\n#define ADC_CR_JADSTART_Pos (3U)\n#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */\n#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */\n#define ADC_CR_ADSTP_Pos (4U)\n#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */\n#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */\n#define ADC_CR_JADSTP_Pos (5U)\n#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */\n#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */\n#define ADC_CR_ADVREGEN_Pos (28U)\n#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */\n#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */\n#define ADC_CR_DEEPPWD_Pos (29U)\n#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */\n#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */\n#define ADC_CR_ADCALDIF_Pos (30U)\n#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */\n#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */\n#define ADC_CR_ADCAL_Pos (31U)\n#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */\n#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */\n\n/******************** Bit definition for ADC_CFGR register ******************/\n#define ADC_CFGR_DMAEN_Pos (0U)\n#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */\n#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */\n#define ADC_CFGR_DMACFG_Pos (1U)\n#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */\n#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */\n\n#define ADC_CFGR_RES_Pos (3U)\n#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */\n#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */\n#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */\n#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */\n\n#define ADC_CFGR_EXTSEL_Pos (5U)\n#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */\n#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */\n#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */\n#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */\n#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */\n#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */\n#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */\n\n#define ADC_CFGR_EXTEN_Pos (10U)\n#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */\n#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */\n#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */\n#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */\n\n#define ADC_CFGR_OVRMOD_Pos (12U)\n#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */\n#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */\n#define ADC_CFGR_CONT_Pos (13U)\n#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */\n#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */\n#define ADC_CFGR_AUTDLY_Pos (14U)\n#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */\n#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */\n#define ADC_CFGR_ALIGN_Pos (15U)\n#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */\n#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */\n#define ADC_CFGR_DISCEN_Pos (16U)\n#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */\n#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */\n\n#define ADC_CFGR_DISCNUM_Pos (17U)\n#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */\n#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */\n#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */\n#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */\n#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */\n\n#define ADC_CFGR_JDISCEN_Pos (20U)\n#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */\n#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */\n#define ADC_CFGR_JQM_Pos (21U)\n#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */\n#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */\n#define ADC_CFGR_AWD1SGL_Pos (22U)\n#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */\n#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\n#define ADC_CFGR_AWD1EN_Pos (23U)\n#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */\n#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */\n#define ADC_CFGR_JAWD1EN_Pos (24U)\n#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */\n#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */\n#define ADC_CFGR_JAUTO_Pos (25U)\n#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */\n#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */\n\n#define ADC_CFGR_AWD1CH_Pos (26U)\n#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */\n#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */\n#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */\n#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */\n#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */\n#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */\n#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */\n\n#define ADC_CFGR_JQDIS_Pos (31U)\n#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */\n#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */\n\n/******************** Bit definition for ADC_CFGR2 register *****************/\n#define ADC_CFGR2_ROVSE_Pos (0U)\n#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */\n#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */\n#define ADC_CFGR2_JOVSE_Pos (1U)\n#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */\n#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */\n\n#define ADC_CFGR2_OVSR_Pos (2U)\n#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */\n#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */\n#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */\n#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */\n#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */\n\n#define ADC_CFGR2_OVSS_Pos (5U)\n#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */\n#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */\n#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */\n#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */\n#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */\n#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */\n\n#define ADC_CFGR2_TROVS_Pos (9U)\n#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */\n#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */\n#define ADC_CFGR2_ROVSM_Pos (10U)\n#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */\n#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */\n\n#define ADC_CFGR2_GCOMP_Pos (16U)\n#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */\n#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */\n\n#define ADC_CFGR2_SWTRIG_Pos (25U)\n#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */\n#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */\n#define ADC_CFGR2_BULB_Pos (26U)\n#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */\n#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */\n#define ADC_CFGR2_SMPTRIG_Pos (27U)\n#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */\n#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */\n\n/******************** Bit definition for ADC_SMPR1 register *****************/\n#define ADC_SMPR1_SMP0_Pos (0U)\n#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */\n#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */\n#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */\n#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */\n#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */\n\n#define ADC_SMPR1_SMP1_Pos (3U)\n#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */\n#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */\n#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */\n#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */\n#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */\n\n#define ADC_SMPR1_SMP2_Pos (6U)\n#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */\n#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */\n#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */\n#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */\n\n#define ADC_SMPR1_SMP3_Pos (9U)\n#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */\n#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */\n#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */\n#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */\n\n#define ADC_SMPR1_SMP4_Pos (12U)\n#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */\n#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */\n#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */\n#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */\n#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */\n\n#define ADC_SMPR1_SMP5_Pos (15U)\n#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */\n#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */\n#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */\n#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */\n#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */\n\n#define ADC_SMPR1_SMP6_Pos (18U)\n#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */\n#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */\n#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */\n#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */\n\n#define ADC_SMPR1_SMP7_Pos (21U)\n#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */\n#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */\n#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */\n#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */\n\n#define ADC_SMPR1_SMP8_Pos (24U)\n#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */\n#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */\n#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */\n#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */\n#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */\n\n#define ADC_SMPR1_SMP9_Pos (27U)\n#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */\n#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */\n#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */\n#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */\n#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */\n\n#define ADC_SMPR1_SMPPLUS_Pos (31U)\n#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */\n#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */\n\n/******************** Bit definition for ADC_SMPR2 register *****************/\n#define ADC_SMPR2_SMP10_Pos (0U)\n#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */\n#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */\n#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */\n#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */\n#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */\n\n#define ADC_SMPR2_SMP11_Pos (3U)\n#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */\n#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */\n#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */\n#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */\n#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */\n\n#define ADC_SMPR2_SMP12_Pos (6U)\n#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */\n#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */\n#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */\n#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */\n\n#define ADC_SMPR2_SMP13_Pos (9U)\n#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */\n#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */\n#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */\n#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */\n\n#define ADC_SMPR2_SMP14_Pos (12U)\n#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */\n#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */\n#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */\n#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */\n#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */\n\n#define ADC_SMPR2_SMP15_Pos (15U)\n#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */\n#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */\n#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */\n#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */\n#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */\n\n#define ADC_SMPR2_SMP16_Pos (18U)\n#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */\n#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */\n#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */\n#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */\n\n#define ADC_SMPR2_SMP17_Pos (21U)\n#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */\n#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */\n#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */\n#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */\n\n#define ADC_SMPR2_SMP18_Pos (24U)\n#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */\n#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */\n#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */\n#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */\n#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */\n\n/******************** Bit definition for ADC_TR1 register *******************/\n#define ADC_TR1_LT1_Pos (0U)\n#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */\n#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */\n\n#define ADC_TR1_AWDFILT_Pos (12U)\n#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */\n#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */\n#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */\n#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */\n#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */\n\n#define ADC_TR1_HT1_Pos (16U)\n#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */\n#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */\n\n/******************** Bit definition for ADC_TR2 register *******************/\n#define ADC_TR2_LT2_Pos (0U)\n#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */\n#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */\n\n#define ADC_TR2_HT2_Pos (16U)\n#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */\n#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */\n\n/******************** Bit definition for ADC_TR3 register *******************/\n#define ADC_TR3_LT3_Pos (0U)\n#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */\n#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */\n\n#define ADC_TR3_HT3_Pos (16U)\n#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */\n#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */\n\n/******************** Bit definition for ADC_SQR1 register ******************/\n#define ADC_SQR1_L_Pos (0U)\n#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */\n#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */\n#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */\n#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */\n#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */\n#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */\n\n#define ADC_SQR1_SQ1_Pos (6U)\n#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */\n#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */\n#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */\n#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */\n#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */\n#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */\n#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR1_SQ2_Pos (12U)\n#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */\n#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */\n#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */\n#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */\n#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */\n#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */\n#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR1_SQ3_Pos (18U)\n#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */\n#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */\n#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */\n#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */\n#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */\n#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */\n#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR1_SQ4_Pos (24U)\n#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */\n#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */\n#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */\n#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */\n#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */\n#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */\n#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR2 register ******************/\n#define ADC_SQR2_SQ5_Pos (0U)\n#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */\n#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */\n#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */\n#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */\n#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */\n#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */\n#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR2_SQ6_Pos (6U)\n#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */\n#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */\n#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */\n#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */\n#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */\n#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */\n#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR2_SQ7_Pos (12U)\n#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */\n#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */\n#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */\n#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */\n#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */\n#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */\n#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR2_SQ8_Pos (18U)\n#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */\n#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */\n#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */\n#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */\n#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */\n#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */\n#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR2_SQ9_Pos (24U)\n#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */\n#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */\n#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */\n#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */\n#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */\n#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */\n#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR3 register ******************/\n#define ADC_SQR3_SQ10_Pos (0U)\n#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */\n#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */\n#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */\n#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */\n#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */\n#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */\n#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR3_SQ11_Pos (6U)\n#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */\n#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */\n#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */\n#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */\n#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */\n#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */\n#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR3_SQ12_Pos (12U)\n#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */\n#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */\n#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */\n#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */\n#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */\n#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */\n#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR3_SQ13_Pos (18U)\n#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */\n#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */\n#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */\n#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */\n#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */\n#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */\n#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR3_SQ14_Pos (24U)\n#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */\n#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */\n#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */\n#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */\n#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */\n#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */\n#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR4 register ******************/\n#define ADC_SQR4_SQ15_Pos (0U)\n#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */\n#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */\n#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */\n#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */\n#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */\n#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */\n#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR4_SQ16_Pos (6U)\n#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */\n#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */\n#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */\n#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */\n#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */\n#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */\n#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */\n\n/******************** Bit definition for ADC_DR register ********************/\n#define ADC_DR_RDATA_Pos (0U)\n#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */\n\n/******************** Bit definition for ADC_JSQR register ******************/\n#define ADC_JSQR_JL_Pos (0U)\n#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */\n#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */\n#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */\n#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */\n\n#define ADC_JSQR_JEXTSEL_Pos (2U)\n#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */\n#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */\n#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */\n#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */\n#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */\n#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */\n#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */\n\n#define ADC_JSQR_JEXTEN_Pos (7U)\n#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */\n#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */\n#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */\n#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */\n\n#define ADC_JSQR_JSQ1_Pos (9U)\n#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */\n#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */\n#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */\n#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */\n#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */\n#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */\n#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */\n\n#define ADC_JSQR_JSQ2_Pos (15U)\n#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */\n#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */\n#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */\n#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */\n#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */\n#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */\n#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */\n\n#define ADC_JSQR_JSQ3_Pos (21U)\n#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */\n#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */\n#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */\n#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */\n#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */\n#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */\n#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */\n\n#define ADC_JSQR_JSQ4_Pos (27U)\n#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */\n#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */\n#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */\n#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */\n#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */\n#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */\n#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */\n\n/******************** Bit definition for ADC_OFR1 register ******************/\n#define ADC_OFR1_OFFSET1_Pos (0U)\n#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */\n#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */\n\n#define ADC_OFR1_OFFSETPOS_Pos (24U)\n#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */\n#define ADC_OFR1_SATEN_Pos (25U)\n#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */\n\n#define ADC_OFR1_OFFSET1_CH_Pos (26U)\n#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */\n#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR1_OFFSET1_EN_Pos (31U)\n#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */\n\n/******************** Bit definition for ADC_OFR2 register ******************/\n#define ADC_OFR2_OFFSET2_Pos (0U)\n#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */\n#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */\n\n#define ADC_OFR2_OFFSETPOS_Pos (24U)\n#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */\n#define ADC_OFR2_SATEN_Pos (25U)\n#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */\n\n#define ADC_OFR2_OFFSET2_CH_Pos (26U)\n#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */\n#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR2_OFFSET2_EN_Pos (31U)\n#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */\n\n/******************** Bit definition for ADC_OFR3 register ******************/\n#define ADC_OFR3_OFFSET3_Pos (0U)\n#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */\n#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */\n\n#define ADC_OFR3_OFFSETPOS_Pos (24U)\n#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */\n#define ADC_OFR3_SATEN_Pos (25U)\n#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */\n\n#define ADC_OFR3_OFFSET3_CH_Pos (26U)\n#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */\n#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR3_OFFSET3_EN_Pos (31U)\n#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */\n\n/******************** Bit definition for ADC_OFR4 register ******************/\n#define ADC_OFR4_OFFSET4_Pos (0U)\n#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */\n#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */\n\n#define ADC_OFR4_OFFSETPOS_Pos (24U)\n#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */\n#define ADC_OFR4_SATEN_Pos (25U)\n#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */\n\n#define ADC_OFR4_OFFSET4_CH_Pos (26U)\n#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */\n#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR4_OFFSET4_EN_Pos (31U)\n#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */\n\n/******************** Bit definition for ADC_JDR1 register ******************/\n#define ADC_JDR1_JDATA_Pos (0U)\n#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */\n\n/******************** Bit definition for ADC_JDR2 register ******************/\n#define ADC_JDR2_JDATA_Pos (0U)\n#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */\n\n/******************** Bit definition for ADC_JDR3 register ******************/\n#define ADC_JDR3_JDATA_Pos (0U)\n#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */\n\n/******************** Bit definition for ADC_JDR4 register ******************/\n#define ADC_JDR4_JDATA_Pos (0U)\n#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */\n\n/******************** Bit definition for ADC_AWD2CR register ****************/\n#define ADC_AWD2CR_AWD2CH_Pos (0U)\n#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */\n#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */\n#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */\n#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */\n#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */\n#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */\n#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */\n#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */\n#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */\n#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */\n#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */\n#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */\n#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */\n#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */\n#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */\n#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */\n#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */\n#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */\n#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */\n#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */\n#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_AWD3CR register ****************/\n#define ADC_AWD3CR_AWD3CH_Pos (0U)\n#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */\n#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */\n#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */\n#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */\n#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */\n#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */\n#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */\n#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */\n#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */\n#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */\n#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */\n#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */\n#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */\n#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */\n#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */\n#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */\n#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */\n#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */\n#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */\n#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */\n#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_DIFSEL register ****************/\n#define ADC_DIFSEL_DIFSEL_Pos (0U)\n#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */\n#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */\n#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */\n#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */\n#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */\n#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */\n#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */\n#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */\n#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */\n#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */\n#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */\n#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */\n#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */\n#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */\n#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */\n#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */\n#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */\n#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */\n#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */\n#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */\n#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_CALFACT register ***************/\n#define ADC_CALFACT_CALFACT_S_Pos (0U)\n#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */\n#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */\n#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */\n#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */\n#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */\n#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */\n#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */\n#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */\n#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */\n\n#define ADC_CALFACT_CALFACT_D_Pos (16U)\n#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */\n#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */\n#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */\n#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */\n#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */\n#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */\n#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */\n#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */\n#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */\n\n/******************** Bit definition for ADC_GCOMP register *****************/\n#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)\n#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */\n#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */\n\n/************************* ADC Common registers *****************************/\n/******************** Bit definition for ADC_CSR register *******************/\n#define ADC_CSR_ADRDY_MST_Pos (0U)\n#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */\n#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */\n#define ADC_CSR_EOSMP_MST_Pos (1U)\n#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */\n#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */\n#define ADC_CSR_EOC_MST_Pos (2U)\n#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */\n#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */\n#define ADC_CSR_EOS_MST_Pos (3U)\n#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */\n#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */\n#define ADC_CSR_OVR_MST_Pos (4U)\n#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */\n#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */\n#define ADC_CSR_JEOC_MST_Pos (5U)\n#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */\n#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */\n#define ADC_CSR_JEOS_MST_Pos (6U)\n#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */\n#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */\n#define ADC_CSR_AWD1_MST_Pos (7U)\n#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */\n#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */\n#define ADC_CSR_AWD2_MST_Pos (8U)\n#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */\n#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */\n#define ADC_CSR_AWD3_MST_Pos (9U)\n#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */\n#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */\n#define ADC_CSR_JQOVF_MST_Pos (10U)\n#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */\n#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */\n\n#define ADC_CSR_ADRDY_SLV_Pos (16U)\n#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */\n#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */\n#define ADC_CSR_EOSMP_SLV_Pos (17U)\n#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */\n#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */\n#define ADC_CSR_EOC_SLV_Pos (18U)\n#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */\n#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */\n#define ADC_CSR_EOS_SLV_Pos (19U)\n#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */\n#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */\n#define ADC_CSR_OVR_SLV_Pos (20U)\n#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */\n#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */\n#define ADC_CSR_JEOC_SLV_Pos (21U)\n#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */\n#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */\n#define ADC_CSR_JEOS_SLV_Pos (22U)\n#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */\n#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */\n#define ADC_CSR_AWD1_SLV_Pos (23U)\n#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */\n#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */\n#define ADC_CSR_AWD2_SLV_Pos (24U)\n#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */\n#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */\n#define ADC_CSR_AWD3_SLV_Pos (25U)\n#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */\n#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */\n#define ADC_CSR_JQOVF_SLV_Pos (26U)\n#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */\n#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */\n\n/******************** Bit definition for ADC_CCR register *******************/\n#define ADC_CCR_DUAL_Pos (0U)\n#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */\n#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */\n#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */\n#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */\n#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */\n#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */\n#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */\n\n#define ADC_CCR_DELAY_Pos (8U)\n#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */\n#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */\n#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */\n\n#define ADC_CCR_DMACFG_Pos (13U)\n#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */\n#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */\n\n#define ADC_CCR_MDMA_Pos (14U)\n#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */\n#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */\n#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */\n#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */\n\n#define ADC_CCR_CKMODE_Pos (16U)\n#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */\n#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */\n#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */\n#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */\n\n#define ADC_CCR_PRESC_Pos (18U)\n#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */\n#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */\n#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */\n#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */\n#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */\n#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */\n\n#define ADC_CCR_VREFEN_Pos (22U)\n#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */\n#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */\n#define ADC_CCR_VSENSESEL_Pos (23U)\n#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */\n#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */\n#define ADC_CCR_VBATSEL_Pos (24U)\n#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */\n#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */\n\n/******************** Bit definition for ADC_CDR register *******************/\n#define ADC_CDR_RDATA_MST_Pos (0U)\n#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */\n#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */\n\n#define ADC_CDR_RDATA_SLV_Pos (16U)\n#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */\n#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */\n\n\n/******************************************************************************/\n/* */\n/* Analog Comparators (COMP) */\n/* */\n/******************************************************************************/\n/********************** Bit definition for COMP_CSR register ****************/\n#define COMP_CSR_EN_Pos (0U)\n#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */\n#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */\n\n#define COMP_CSR_INMSEL_Pos (4U)\n#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */\n#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */\n#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */\n#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */\n#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */\n#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */\n\n#define COMP_CSR_INPSEL_Pos (8U)\n#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */\n#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */\n\n#define COMP_CSR_POLARITY_Pos (15U)\n#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */\n#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */\n\n#define COMP_CSR_HYST_Pos (16U)\n#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */\n#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */\n#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */\n#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */\n#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */\n\n#define COMP_CSR_BLANKING_Pos (19U)\n#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */\n#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */\n#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */\n#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */\n#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */\n\n#define COMP_CSR_BRGEN_Pos (22U)\n#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */\n#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */\n\n#define COMP_CSR_SCALEN_Pos (23U)\n#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */\n#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */\n\n#define COMP_CSR_VALUE_Pos (30U)\n#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */\n#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */\n\n#define COMP_CSR_LOCK_Pos (31U)\n#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */\n#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */\n\n/******************************************************************************/\n/* */\n/* CORDIC calculation unit */\n/* */\n/******************************************************************************/\n/******************* Bit definition for CORDIC_CSR register *****************/\n#define CORDIC_CSR_FUNC_Pos (0U)\n#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */\n#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */\n#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */\n#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */\n#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */\n#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */\n#define CORDIC_CSR_PRECISION_Pos (4U)\n#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */\n#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */\n#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */\n#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */\n#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */\n#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */\n#define CORDIC_CSR_SCALE_Pos (8U)\n#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */\n#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */\n#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */\n#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */\n#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */\n#define CORDIC_CSR_IEN_Pos (16U)\n#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */\n#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */\n#define CORDIC_CSR_DMAREN_Pos (17U)\n#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */\n#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */\n#define CORDIC_CSR_DMAWEN_Pos (18U)\n#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */\n#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */\n#define CORDIC_CSR_NRES_Pos (19U)\n#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */\n#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */\n#define CORDIC_CSR_NARGS_Pos (20U)\n#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */\n#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */\n#define CORDIC_CSR_RESSIZE_Pos (21U)\n#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */\n#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */\n#define CORDIC_CSR_ARGSIZE_Pos (22U)\n#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */\n#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */\n#define CORDIC_CSR_RRDY_Pos (31U)\n#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */\n#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */\n\n/******************* Bit definition for CORDIC_WDATA register ***************/\n#define CORDIC_WDATA_ARG_Pos (0U)\n#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */\n#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */\n\n/******************* Bit definition for CORDIC_RDATA register ***************/\n#define CORDIC_RDATA_RES_Pos (0U)\n#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */\n#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */\n\n/******************************************************************************/\n/* */\n/* CRC calculation unit */\n/* */\n/******************************************************************************/\n/******************* Bit definition for CRC_DR register *********************/\n#define CRC_DR_DR_Pos (0U)\n#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\n#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\n\n/******************* Bit definition for CRC_IDR register ********************/\n#define CRC_IDR_IDR_Pos (0U)\n#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */\n#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */\n\n/******************** Bit definition for CRC_CR register ********************/\n#define CRC_CR_RESET_Pos (0U)\n#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */\n#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */\n#define CRC_CR_POLYSIZE_Pos (3U)\n#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */\n#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */\n#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */\n#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */\n#define CRC_CR_REV_IN_Pos (5U)\n#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */\n#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */\n#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */\n#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */\n#define CRC_CR_REV_OUT_Pos (7U)\n#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */\n#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */\n\n/******************* Bit definition for CRC_INIT register *******************/\n#define CRC_INIT_INIT_Pos (0U)\n#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */\n#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */\n\n/******************* Bit definition for CRC_POL register ********************/\n#define CRC_POL_POL_Pos (0U)\n#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */\n#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */\n\n/******************************************************************************/\n/* */\n/* CRS Clock Recovery System */\n/******************************************************************************/\n\n/******************* Bit definition for CRS_CR register *********************/\n#define CRS_CR_SYNCOKIE_Pos (0U)\n#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */\n#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */\n#define CRS_CR_SYNCWARNIE_Pos (1U)\n#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */\n#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */\n#define CRS_CR_ERRIE_Pos (2U)\n#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */\n#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */\n#define CRS_CR_ESYNCIE_Pos (3U)\n#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */\n#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */\n#define CRS_CR_CEN_Pos (5U)\n#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */\n#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */\n#define CRS_CR_AUTOTRIMEN_Pos (6U)\n#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */\n#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */\n#define CRS_CR_SWSYNC_Pos (7U)\n#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */\n#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */\n#define CRS_CR_TRIM_Pos (8U)\n#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */\n#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */\n\n/******************* Bit definition for CRS_CFGR register *********************/\n#define CRS_CFGR_RELOAD_Pos (0U)\n#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */\n#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */\n#define CRS_CFGR_FELIM_Pos (16U)\n#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */\n#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */\n\n#define CRS_CFGR_SYNCDIV_Pos (24U)\n#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */\n#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */\n#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */\n#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */\n#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */\n\n#define CRS_CFGR_SYNCSRC_Pos (28U)\n#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */\n#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */\n#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */\n#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */\n\n#define CRS_CFGR_SYNCPOL_Pos (31U)\n#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */\n#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */\n\n/******************* Bit definition for CRS_ISR register *********************/\n#define CRS_ISR_SYNCOKF_Pos (0U)\n#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */\n#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */\n#define CRS_ISR_SYNCWARNF_Pos (1U)\n#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */\n#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */\n#define CRS_ISR_ERRF_Pos (2U)\n#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */\n#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */\n#define CRS_ISR_ESYNCF_Pos (3U)\n#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */\n#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */\n#define CRS_ISR_SYNCERR_Pos (8U)\n#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */\n#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */\n#define CRS_ISR_SYNCMISS_Pos (9U)\n#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */\n#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */\n#define CRS_ISR_TRIMOVF_Pos (10U)\n#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */\n#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */\n#define CRS_ISR_FEDIR_Pos (15U)\n#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */\n#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */\n#define CRS_ISR_FECAP_Pos (16U)\n#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */\n#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */\n\n/******************* Bit definition for CRS_ICR register *********************/\n#define CRS_ICR_SYNCOKC_Pos (0U)\n#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */\n#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */\n#define CRS_ICR_SYNCWARNC_Pos (1U)\n#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */\n#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */\n#define CRS_ICR_ERRC_Pos (2U)\n#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */\n#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */\n#define CRS_ICR_ESYNCC_Pos (3U)\n#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */\n#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */\n\n/******************************************************************************/\n/* */\n/* Digital to Analog Converter */\n/* */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)\n */\n#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */\n\n/******************** Bit definition for DAC_CR register ********************/\n#define DAC_CR_EN1_Pos (0U)\n#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */\n#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/\n#define DAC_CR_CEN1_Pos (14U)\n#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */\n#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/\n\n#define DAC_CR_HFSEL_Pos (15U)\n#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */\n#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/\n\n#define DAC_CR_EN2_Pos (16U)\n#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\n#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/\n#define DAC_CR_CEN2_Pos (30U)\n#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */\n#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/\n\n/***************** Bit definition for DAC_SWTRIGR register ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!\n\n/** @addtogroup Peripheral_registers_structures\n * @{\n */\n\n/**\n * @brief Analog to Digital Converter\n */\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */\n __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */\n __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */\n __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */\n __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */\n __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */\n __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */\n uint32_t RESERVED1; /*!< Reserved, 0x1C */\n __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */\n __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */\n __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */\n uint32_t RESERVED2; /*!< Reserved, 0x2C */\n __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */\n __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */\n __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */\n __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */\n __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */\n uint32_t RESERVED3; /*!< Reserved, 0x44 */\n uint32_t RESERVED4; /*!< Reserved, 0x48 */\n __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */\n uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */\n __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */\n __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */\n __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */\n __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */\n uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */\n __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */\n __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */\n __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */\n __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */\n uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */\n __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */\n __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */\n uint32_t RESERVED8; /*!< Reserved, 0x0A8 */\n uint32_t RESERVED9; /*!< Reserved, 0x0AC */\n __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */\n __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */\n uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */\n __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */\n} ADC_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */\n uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */\n __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */\n __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */\n} ADC_Common_TypeDef;\n\n/**\n * @brief FD Controller Area Network\n */\n\ntypedef struct\n{\n __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */\n __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */\n uint32_t RESERVED1; /*!< Reserved, 0x008 */\n __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */\n __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */\n __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */\n __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */\n __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */\n __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */\n __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */\n __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */\n __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */\n uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */\n __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */\n __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */\n __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */\n uint32_t RESERVED3; /*!< Reserved, 0x04C */\n __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */\n __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */\n __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */\n __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */\n uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */\n __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */\n __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */\n __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */\n uint32_t RESERVED5; /*!< Reserved, 0x08C */\n __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */\n __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */\n __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */\n __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */\n uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */\n __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */\n __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */\n __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */\n __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */\n __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */\n __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */\n __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */\n __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */\n __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */\n __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */\n __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */\n} FDCAN_GlobalTypeDef;\n\n/**\n * @brief FD Controller Area Network Configuration\n */\n\ntypedef struct\n{\n __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */\n} FDCAN_Config_TypeDef;\n\n/**\n * @brief Comparator\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */\n} COMP_TypeDef;\n\n/**\n * @brief CRC calculation unit\n */\n\ntypedef struct\n{\n __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\n __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\n __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\n uint32_t RESERVED0; /*!< Reserved, 0x0C */\n __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\n __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\n} CRC_TypeDef;\n\n/**\n * @brief Clock Recovery System\n */\ntypedef struct\n{\n __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */\n __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */\n __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */\n __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */\n} CRS_TypeDef;\n\n/**\n * @brief Digital to Analog Converter\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\n __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\n __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\n __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\n __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\n __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\n __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\n __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\n __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\n __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\n __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\n __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\n __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */\n __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */\n __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */\n __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */\n __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */\n __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */\n __IO uint32_t RESERVED[2];\n __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */\n __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */\n __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */\n} DAC_TypeDef;\n\n/**\n * @brief Debug MCU\n */\n\ntypedef struct\n{\n __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\n __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\n __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */\n __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */\n __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */\n} DBGMCU_TypeDef;\n\n/**\n * @brief DMA Controller\n */\n\ntypedef struct\n{\n __IO uint32_t CCR; /*!< DMA channel x configuration register */\n __IO uint32_t CNDTR; /*!< DMA channel x number of data register */\n __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */\n __IO uint32_t CMAR; /*!< DMA channel x memory address register */\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */\n __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */\n} DMA_TypeDef;\n\n/**\n * @brief DMA Multiplexer\n */\n\ntypedef struct\n{\n __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */\n}DMAMUX_Channel_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */\n __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */\n}DMAMUX_ChannelStatus_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */\n}DMAMUX_RequestGen_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */\n __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */\n}DMAMUX_RequestGenStatus_TypeDef;\n\n/**\n * @brief External Interrupt/Event Controller\n */\n\ntypedef struct\n{\n __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */\n __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */\n __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */\n __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */\n __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */\n __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */\n uint32_t RESERVED1; /*!< Reserved, 0x18 */\n uint32_t RESERVED2; /*!< Reserved, 0x1C */\n __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */\n __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */\n __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */\n __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */\n __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */\n __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */\n} EXTI_TypeDef;\n\n/**\n * @brief FLASH Registers\n */\n\ntypedef struct\n{\n __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\n __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */\n __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */\n __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */\n __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */\n __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */\n __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */\n uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */\n __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */\n __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */\n __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */\n __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */\n __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */\n uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */\n __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */\n} FLASH_TypeDef;\n\n/**\n * @brief FMAC\n */\ntypedef struct\n{\n __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */\n __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */\n __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */\n __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */\n __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */\n __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */\n __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */\n __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */\n} FMAC_TypeDef;\n\n\n/**\n * @brief General Purpose I/O\n */\n\ntypedef struct\n{\n __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\n __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\n __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\n __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\n __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\n __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\n __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */\n __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\n __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\n __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */\n} GPIO_TypeDef;\n\n/**\n * @brief Inter-integrated Circuit Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\n __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\n __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\n __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\n __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\n __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\n __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\n __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\n __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\n __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */\n} I2C_TypeDef;\n\n/**\n * @brief Independent WATCHDOG\n */\n\ntypedef struct\n{\n __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\n __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\n __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\n __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\n __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\n} IWDG_TypeDef;\n\n/**\n * @brief LPTIMER\n */\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\n __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\n __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\n __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\n __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\n __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\n __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\n __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\n __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */\n} LPTIM_TypeDef;\n\n/**\n * @brief Operational Amplifier (OPAMP)\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */\n __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */\n __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */\n} OPAMP_TypeDef;\n\n/**\n * @brief Power Control\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */\n __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */\n __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */\n __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */\n __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */\n __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */\n uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */\n __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */\n __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */\n __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */\n __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */\n __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */\n __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */\n __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */\n __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */\n __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */\n __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */\n __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */\n __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */\n __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */\n __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */\n uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */\n __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */\n} PWR_TypeDef;\n\n\n/**\n * @brief Reset and Clock Control\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\n __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */\n __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\n __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */\n uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */\n uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */\n __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */\n __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */\n __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */\n uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */\n __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */\n __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */\n __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */\n uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */\n __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */\n __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */\n __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */\n uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */\n __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */\n __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */\n __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */\n uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */\n __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */\n __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */\n __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */\n uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */\n __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */\n __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */\n __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */\n uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */\n __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */\n __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */\n __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */\n uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */\n __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */\n uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */\n __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */\n __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */\n __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */\n __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */\n} RCC_TypeDef;\n\n/**\n * @brief Real-Time Clock\n */\n/*\n* @brief Specific device feature definitions\n*/\n#define RTC_TAMP_INT_6_SUPPORT\n#define RTC_TAMP_INT_NB 4u\n\n#define RTC_TAMP_NB 3u\n#define RTC_BACKUP_NB 16u\n\n\ntypedef struct\n{\n __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\n __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\n __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */\n __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */\n __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\n __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\n __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */\n uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */\n uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */\n __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\n __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */\n __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\n __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\n __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\n __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\n uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */\n __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */\n __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\n __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */\n __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */\n __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */\n __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */\n uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */\n __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */\n} RTC_TypeDef;\n\n/**\n * @brief Tamper and backup registers\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */\n uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */\n __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */\n uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */\n uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */\n __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */\n __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */\n __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */\n uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */\n __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */\n uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */\n __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */\n __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */\n __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */\n __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */\n __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */\n __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */\n __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */\n __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */\n __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */\n __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */\n __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */\n __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */\n __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */\n __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */\n __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */\n __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */\n} TAMP_TypeDef;\n\n/**\n * @brief Serial Audio Interface\n */\n\ntypedef struct\n{\n __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\n uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */\n __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */\n __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\n __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\n __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\n __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\n __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\n __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\n __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\n __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/**\n * @brief Serial Peripheral Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */\n __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */\n __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\n __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */\n __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */\n __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */\n __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\n __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n * @brief System configuration controller\n */\n\ntypedef struct\n{\n __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\n __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */\n __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */\n __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */\n __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */\n __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */\n} SYSCFG_TypeDef;\n\n/**\n * @brief TIM\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\n __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\n __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\n __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\n __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\n __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\n __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\n __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\n __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\n __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\n __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\n __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\n __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\n __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\n __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\n __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */\n __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */\n __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */\n __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */\n __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */\n __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */\n __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */\n __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */\n __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */\n uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */\n __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */\n __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */\n} TIM_TypeDef;\n\n/**\n * @brief Universal Synchronous Asynchronous Receiver Transmitter\n */\ntypedef struct\n{\n __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */\n __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\n __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */\n __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\n __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */\n __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\n __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\n __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\n __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\n __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\n __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */\n} USART_TypeDef;\n\n/**\n * @brief Universal Serial Bus Full Speed Device\n */\n\ntypedef struct\n{\n __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */\n __IO uint16_t RESERVED0; /*!< Reserved */\n __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */\n __IO uint16_t RESERVED1; /*!< Reserved */\n __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */\n __IO uint16_t RESERVED2; /*!< Reserved */\n __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */\n __IO uint16_t RESERVED3; /*!< Reserved */\n __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */\n __IO uint16_t RESERVED4; /*!< Reserved */\n __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */\n __IO uint16_t RESERVED5; /*!< Reserved */\n __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */\n __IO uint16_t RESERVED6; /*!< Reserved */\n __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */\n __IO uint16_t RESERVED7[17]; /*!< Reserved */\n __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */\n __IO uint16_t RESERVED8; /*!< Reserved */\n __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */\n __IO uint16_t RESERVED9; /*!< Reserved */\n __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */\n __IO uint16_t RESERVEDA; /*!< Reserved */\n __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */\n __IO uint16_t RESERVEDB; /*!< Reserved */\n __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */\n __IO uint16_t RESERVEDC; /*!< Reserved */\n __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */\n __IO uint16_t RESERVEDD; /*!< Reserved */\n __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */\n __IO uint16_t RESERVEDE; /*!< Reserved */\n} USB_TypeDef;\n\n/**\n * @brief VREFBUF\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */\n __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */\n} VREFBUF_TypeDef;\n\n/**\n * @brief Window WATCHDOG\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\n __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\n __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n * @brief AES hardware accelerator\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */\n __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */\n __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */\n __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */\n __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */\n __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */\n __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */\n __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */\n __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */\n __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */\n __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */\n __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */\n __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */\n __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */\n __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */\n __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */\n __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */\n __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */\n __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */\n __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */\n __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */\n __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */\n __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */\n __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */\n} AES_TypeDef;\n\n/**\n * @brief RNG\n */\ntypedef struct\n{\n __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\n __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\n __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n * @brief CORDIC\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */\n __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */\n __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */\n} CORDIC_TypeDef;\n\n/**\n * @brief UCPD\n */\n\ntypedef struct\n{\n __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */\n __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */\n __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */\n __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */\n __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */\n __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */\n __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */\n __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */\n __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */\n __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */\n __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */\n __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */\n __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */\n __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */\n __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */\n} UCPD_TypeDef;\n\n\n/**\n * @}\n */\n\n/** @addtogroup Peripheral_memory_map\n * @{\n */\n\n#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */\n#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */\n#define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */\n#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */\n#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */\n\n#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */\n#define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */\n#define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */\n#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */\n/* Legacy defines */\n#define SRAM_BASE SRAM1_BASE\n#define SRAM_BB_BASE SRAM1_BB_BASE\n\n#define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */\n#define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */\n#define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE PERIPH_BASE\n#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)\n\n\n/*!< APB1 peripherals */\n#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)\n#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)\n#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)\n#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)\n#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)\n#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)\n#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)\n#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)\n#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)\n#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */\n#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */\n#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)\n#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */\n#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)\n#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)\n#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)\n#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)\n#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)\n#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)\n\n/*!< APB2 peripherals */\n#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)\n#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)\n#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)\n#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)\n#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)\n#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)\n#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)\n#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)\n#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)\n#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)\n\n#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)\n#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)\n#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)\n#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)\n#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)\n#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)\n#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)\n#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)\n#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)\n#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)\n\n/*!< AHB1 peripherals */\n#define DMA1_BASE (AHB1PERIPH_BASE)\n#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)\n#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)\n#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)\n#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)\n#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)\n#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)\n#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)\n\n#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)\n#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)\n#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)\n#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)\n#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)\n#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)\n\n#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)\n#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)\n#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)\n#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)\n#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)\n#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)\n\n#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)\n#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)\n#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)\n#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)\n#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)\n#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)\n#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL)\n#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL)\n#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL)\n#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL)\n#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL)\n#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL)\n#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)\n#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)\n#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)\n#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)\n\n#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)\n#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)\n\n/*!< AHB2 peripherals */\n#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)\n\n#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)\n#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)\n#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)\n\n#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)\n#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)\n#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)\n#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL)\n\n#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)\n/* Debug MCU registers base address */\n#define DBGMCU_BASE (0xE0042000UL)\n\n#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */\n#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */\n/**\n * @}\n */\n\n/** @addtogroup Peripheral_declaration\n * @{\n */\n#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\n#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\n#define CRS ((CRS_TypeDef *) CRS_BASE)\n#define TAMP ((TAMP_TypeDef *) TAMP_BASE)\n#define RTC ((RTC_TypeDef *) RTC_BASE)\n#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\n#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\n#define USART2 ((USART_TypeDef *) USART2_BASE)\n#define USART3 ((USART_TypeDef *) USART3_BASE)\n#define UART4 ((USART_TypeDef *) UART4_BASE)\n#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\n#define USB ((USB_TypeDef *) USB_BASE)\n#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)\n#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)\n#define PWR ((PWR_TypeDef *) PWR_BASE)\n#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\n#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\n#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)\n#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)\n\n#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)\n#define COMP1 ((COMP_TypeDef *) COMP1_BASE)\n#define COMP2 ((COMP_TypeDef *) COMP2_BASE)\n#define COMP3 ((COMP_TypeDef *) COMP3_BASE)\n#define COMP4 ((COMP_TypeDef *) COMP4_BASE)\n\n#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)\n#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)\n#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)\n#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)\n\n#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\n#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\n#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\n#define USART1 ((USART_TypeDef *) USART1_BASE)\n#define TIM15 ((TIM_TypeDef *) TIM15_BASE)\n#define TIM16 ((TIM_TypeDef *) TIM16_BASE)\n#define TIM17 ((TIM_TypeDef *) TIM17_BASE)\n#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\n#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\n#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)\n#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)\n#define RCC ((RCC_TypeDef *) RCC_BASE)\n#define FMAC ((FMAC_TypeDef *) FMAC_BASE)\n#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\n#define CRC ((CRC_TypeDef *) CRC_BASE)\n\n#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\n#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\n#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)\n#define DAC ((DAC_TypeDef *) DAC_BASE)\n#define DAC1 ((DAC_TypeDef *) DAC1_BASE)\n#define DAC3 ((DAC_TypeDef *) DAC3_BASE)\n#define AES ((AES_TypeDef *) AES_BASE)\n#define RNG ((RNG_TypeDef *) RNG_BASE)\n\n#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\n#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\n#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\n#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\n#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\n#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\n\n#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\n#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\n#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\n#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\n#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\n#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)\n\n#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)\n#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)\n#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)\n#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)\n#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)\n#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)\n#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)\n#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)\n#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)\n#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)\n#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)\n#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)\n\n#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)\n#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)\n#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)\n#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)\n\n#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)\n#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)\n\n\n\n#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\n\n/**\n * @}\n */\n\n/** @addtogroup Exported_constants\n * @{\n */\n\n /** @addtogroup Hardware_Constant_Definition\n * @{\n */\n#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */\n\n /**\n * @}\n */\n\n/** @addtogroup Peripheral_Registers_Bits_Definition\n * @{\n */\n\n/******************************************************************************/\n/* Peripheral Registers_Bits_Definition */\n/******************************************************************************/\n\n/******************************************************************************/\n/* */\n/* Analog to Digital Converter */\n/* */\n/******************************************************************************/\n\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\n\n/******************** Bit definition for ADC_ISR register *******************/\n#define ADC_ISR_ADRDY_Pos (0U)\n#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */\n#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */\n#define ADC_ISR_EOSMP_Pos (1U)\n#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */\n#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */\n#define ADC_ISR_EOC_Pos (2U)\n#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */\n#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */\n#define ADC_ISR_EOS_Pos (3U)\n#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */\n#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */\n#define ADC_ISR_OVR_Pos (4U)\n#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */\n#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */\n#define ADC_ISR_JEOC_Pos (5U)\n#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */\n#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */\n#define ADC_ISR_JEOS_Pos (6U)\n#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */\n#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */\n#define ADC_ISR_AWD1_Pos (7U)\n#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */\n#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */\n#define ADC_ISR_AWD2_Pos (8U)\n#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */\n#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */\n#define ADC_ISR_AWD3_Pos (9U)\n#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */\n#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */\n#define ADC_ISR_JQOVF_Pos (10U)\n#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */\n#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */\n\n/******************** Bit definition for ADC_IER register *******************/\n#define ADC_IER_ADRDYIE_Pos (0U)\n#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */\n#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */\n#define ADC_IER_EOSMPIE_Pos (1U)\n#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */\n#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */\n#define ADC_IER_EOCIE_Pos (2U)\n#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */\n#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */\n#define ADC_IER_EOSIE_Pos (3U)\n#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */\n#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */\n#define ADC_IER_OVRIE_Pos (4U)\n#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */\n#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */\n#define ADC_IER_JEOCIE_Pos (5U)\n#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */\n#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */\n#define ADC_IER_JEOSIE_Pos (6U)\n#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */\n#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */\n#define ADC_IER_AWD1IE_Pos (7U)\n#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */\n#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */\n#define ADC_IER_AWD2IE_Pos (8U)\n#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */\n#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */\n#define ADC_IER_AWD3IE_Pos (9U)\n#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */\n#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */\n#define ADC_IER_JQOVFIE_Pos (10U)\n#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */\n#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */\n\n/******************** Bit definition for ADC_CR register ********************/\n#define ADC_CR_ADEN_Pos (0U)\n#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */\n#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */\n#define ADC_CR_ADDIS_Pos (1U)\n#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */\n#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */\n#define ADC_CR_ADSTART_Pos (2U)\n#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */\n#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */\n#define ADC_CR_JADSTART_Pos (3U)\n#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */\n#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */\n#define ADC_CR_ADSTP_Pos (4U)\n#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */\n#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */\n#define ADC_CR_JADSTP_Pos (5U)\n#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */\n#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */\n#define ADC_CR_ADVREGEN_Pos (28U)\n#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */\n#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */\n#define ADC_CR_DEEPPWD_Pos (29U)\n#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */\n#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */\n#define ADC_CR_ADCALDIF_Pos (30U)\n#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */\n#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */\n#define ADC_CR_ADCAL_Pos (31U)\n#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */\n#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */\n\n/******************** Bit definition for ADC_CFGR register ******************/\n#define ADC_CFGR_DMAEN_Pos (0U)\n#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */\n#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */\n#define ADC_CFGR_DMACFG_Pos (1U)\n#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */\n#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */\n\n#define ADC_CFGR_RES_Pos (3U)\n#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */\n#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */\n#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */\n#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */\n\n#define ADC_CFGR_EXTSEL_Pos (5U)\n#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */\n#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */\n#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */\n#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */\n#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */\n#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */\n#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */\n\n#define ADC_CFGR_EXTEN_Pos (10U)\n#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */\n#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */\n#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */\n#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */\n\n#define ADC_CFGR_OVRMOD_Pos (12U)\n#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */\n#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */\n#define ADC_CFGR_CONT_Pos (13U)\n#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */\n#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */\n#define ADC_CFGR_AUTDLY_Pos (14U)\n#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */\n#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */\n#define ADC_CFGR_ALIGN_Pos (15U)\n#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */\n#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */\n#define ADC_CFGR_DISCEN_Pos (16U)\n#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */\n#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */\n\n#define ADC_CFGR_DISCNUM_Pos (17U)\n#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */\n#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */\n#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */\n#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */\n#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */\n\n#define ADC_CFGR_JDISCEN_Pos (20U)\n#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */\n#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */\n#define ADC_CFGR_JQM_Pos (21U)\n#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */\n#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */\n#define ADC_CFGR_AWD1SGL_Pos (22U)\n#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */\n#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\n#define ADC_CFGR_AWD1EN_Pos (23U)\n#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */\n#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */\n#define ADC_CFGR_JAWD1EN_Pos (24U)\n#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */\n#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */\n#define ADC_CFGR_JAUTO_Pos (25U)\n#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */\n#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */\n\n#define ADC_CFGR_AWD1CH_Pos (26U)\n#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */\n#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */\n#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */\n#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */\n#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */\n#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */\n#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */\n\n#define ADC_CFGR_JQDIS_Pos (31U)\n#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */\n#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */\n\n/******************** Bit definition for ADC_CFGR2 register *****************/\n#define ADC_CFGR2_ROVSE_Pos (0U)\n#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */\n#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */\n#define ADC_CFGR2_JOVSE_Pos (1U)\n#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */\n#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */\n\n#define ADC_CFGR2_OVSR_Pos (2U)\n#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */\n#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */\n#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */\n#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */\n#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */\n\n#define ADC_CFGR2_OVSS_Pos (5U)\n#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */\n#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */\n#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */\n#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */\n#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */\n#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */\n\n#define ADC_CFGR2_TROVS_Pos (9U)\n#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */\n#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */\n#define ADC_CFGR2_ROVSM_Pos (10U)\n#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */\n#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */\n\n#define ADC_CFGR2_GCOMP_Pos (16U)\n#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */\n#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */\n\n#define ADC_CFGR2_SWTRIG_Pos (25U)\n#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */\n#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */\n#define ADC_CFGR2_BULB_Pos (26U)\n#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */\n#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */\n#define ADC_CFGR2_SMPTRIG_Pos (27U)\n#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */\n#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */\n\n/******************** Bit definition for ADC_SMPR1 register *****************/\n#define ADC_SMPR1_SMP0_Pos (0U)\n#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */\n#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */\n#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */\n#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */\n#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */\n\n#define ADC_SMPR1_SMP1_Pos (3U)\n#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */\n#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */\n#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */\n#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */\n#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */\n\n#define ADC_SMPR1_SMP2_Pos (6U)\n#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */\n#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */\n#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */\n#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */\n\n#define ADC_SMPR1_SMP3_Pos (9U)\n#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */\n#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */\n#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */\n#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */\n\n#define ADC_SMPR1_SMP4_Pos (12U)\n#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */\n#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */\n#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */\n#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */\n#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */\n\n#define ADC_SMPR1_SMP5_Pos (15U)\n#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */\n#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */\n#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */\n#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */\n#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */\n\n#define ADC_SMPR1_SMP6_Pos (18U)\n#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */\n#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */\n#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */\n#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */\n\n#define ADC_SMPR1_SMP7_Pos (21U)\n#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */\n#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */\n#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */\n#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */\n\n#define ADC_SMPR1_SMP8_Pos (24U)\n#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */\n#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */\n#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */\n#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */\n#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */\n\n#define ADC_SMPR1_SMP9_Pos (27U)\n#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */\n#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */\n#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */\n#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */\n#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */\n\n#define ADC_SMPR1_SMPPLUS_Pos (31U)\n#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */\n#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */\n\n/******************** Bit definition for ADC_SMPR2 register *****************/\n#define ADC_SMPR2_SMP10_Pos (0U)\n#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */\n#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */\n#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */\n#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */\n#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */\n\n#define ADC_SMPR2_SMP11_Pos (3U)\n#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */\n#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */\n#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */\n#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */\n#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */\n\n#define ADC_SMPR2_SMP12_Pos (6U)\n#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */\n#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */\n#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */\n#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */\n\n#define ADC_SMPR2_SMP13_Pos (9U)\n#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */\n#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */\n#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */\n#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */\n\n#define ADC_SMPR2_SMP14_Pos (12U)\n#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */\n#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */\n#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */\n#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */\n#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */\n\n#define ADC_SMPR2_SMP15_Pos (15U)\n#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */\n#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */\n#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */\n#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */\n#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */\n\n#define ADC_SMPR2_SMP16_Pos (18U)\n#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */\n#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */\n#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */\n#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */\n\n#define ADC_SMPR2_SMP17_Pos (21U)\n#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */\n#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */\n#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */\n#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */\n\n#define ADC_SMPR2_SMP18_Pos (24U)\n#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */\n#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */\n#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */\n#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */\n#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */\n\n/******************** Bit definition for ADC_TR1 register *******************/\n#define ADC_TR1_LT1_Pos (0U)\n#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */\n#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */\n\n#define ADC_TR1_AWDFILT_Pos (12U)\n#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */\n#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */\n#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */\n#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */\n#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */\n\n#define ADC_TR1_HT1_Pos (16U)\n#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */\n#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */\n\n/******************** Bit definition for ADC_TR2 register *******************/\n#define ADC_TR2_LT2_Pos (0U)\n#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */\n#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */\n\n#define ADC_TR2_HT2_Pos (16U)\n#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */\n#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */\n\n/******************** Bit definition for ADC_TR3 register *******************/\n#define ADC_TR3_LT3_Pos (0U)\n#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */\n#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */\n\n#define ADC_TR3_HT3_Pos (16U)\n#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */\n#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */\n\n/******************** Bit definition for ADC_SQR1 register ******************/\n#define ADC_SQR1_L_Pos (0U)\n#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */\n#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */\n#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */\n#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */\n#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */\n#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */\n\n#define ADC_SQR1_SQ1_Pos (6U)\n#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */\n#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */\n#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */\n#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */\n#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */\n#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */\n#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR1_SQ2_Pos (12U)\n#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */\n#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */\n#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */\n#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */\n#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */\n#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */\n#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR1_SQ3_Pos (18U)\n#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */\n#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */\n#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */\n#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */\n#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */\n#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */\n#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR1_SQ4_Pos (24U)\n#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */\n#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */\n#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */\n#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */\n#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */\n#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */\n#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR2 register ******************/\n#define ADC_SQR2_SQ5_Pos (0U)\n#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */\n#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */\n#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */\n#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */\n#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */\n#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */\n#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR2_SQ6_Pos (6U)\n#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */\n#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */\n#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */\n#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */\n#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */\n#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */\n#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR2_SQ7_Pos (12U)\n#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */\n#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */\n#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */\n#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */\n#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */\n#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */\n#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR2_SQ8_Pos (18U)\n#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */\n#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */\n#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */\n#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */\n#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */\n#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */\n#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR2_SQ9_Pos (24U)\n#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */\n#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */\n#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */\n#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */\n#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */\n#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */\n#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR3 register ******************/\n#define ADC_SQR3_SQ10_Pos (0U)\n#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */\n#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */\n#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */\n#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */\n#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */\n#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */\n#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR3_SQ11_Pos (6U)\n#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */\n#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */\n#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */\n#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */\n#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */\n#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */\n#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR3_SQ12_Pos (12U)\n#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */\n#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */\n#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */\n#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */\n#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */\n#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */\n#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR3_SQ13_Pos (18U)\n#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */\n#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */\n#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */\n#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */\n#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */\n#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */\n#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR3_SQ14_Pos (24U)\n#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */\n#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */\n#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */\n#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */\n#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */\n#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */\n#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR4 register ******************/\n#define ADC_SQR4_SQ15_Pos (0U)\n#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */\n#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */\n#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */\n#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */\n#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */\n#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */\n#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR4_SQ16_Pos (6U)\n#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */\n#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */\n#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */\n#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */\n#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */\n#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */\n#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */\n\n/******************** Bit definition for ADC_DR register ********************/\n#define ADC_DR_RDATA_Pos (0U)\n#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */\n\n/******************** Bit definition for ADC_JSQR register ******************/\n#define ADC_JSQR_JL_Pos (0U)\n#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */\n#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */\n#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */\n#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */\n\n#define ADC_JSQR_JEXTSEL_Pos (2U)\n#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */\n#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */\n#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */\n#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */\n#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */\n#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */\n#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */\n\n#define ADC_JSQR_JEXTEN_Pos (7U)\n#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */\n#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */\n#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */\n#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */\n\n#define ADC_JSQR_JSQ1_Pos (9U)\n#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */\n#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */\n#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */\n#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */\n#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */\n#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */\n#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */\n\n#define ADC_JSQR_JSQ2_Pos (15U)\n#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */\n#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */\n#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */\n#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */\n#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */\n#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */\n#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */\n\n#define ADC_JSQR_JSQ3_Pos (21U)\n#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */\n#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */\n#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */\n#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */\n#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */\n#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */\n#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */\n\n#define ADC_JSQR_JSQ4_Pos (27U)\n#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */\n#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */\n#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */\n#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */\n#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */\n#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */\n#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */\n\n/******************** Bit definition for ADC_OFR1 register ******************/\n#define ADC_OFR1_OFFSET1_Pos (0U)\n#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */\n#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */\n\n#define ADC_OFR1_OFFSETPOS_Pos (24U)\n#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */\n#define ADC_OFR1_SATEN_Pos (25U)\n#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */\n\n#define ADC_OFR1_OFFSET1_CH_Pos (26U)\n#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */\n#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR1_OFFSET1_EN_Pos (31U)\n#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */\n\n/******************** Bit definition for ADC_OFR2 register ******************/\n#define ADC_OFR2_OFFSET2_Pos (0U)\n#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */\n#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */\n\n#define ADC_OFR2_OFFSETPOS_Pos (24U)\n#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */\n#define ADC_OFR2_SATEN_Pos (25U)\n#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */\n\n#define ADC_OFR2_OFFSET2_CH_Pos (26U)\n#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */\n#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR2_OFFSET2_EN_Pos (31U)\n#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */\n\n/******************** Bit definition for ADC_OFR3 register ******************/\n#define ADC_OFR3_OFFSET3_Pos (0U)\n#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */\n#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */\n\n#define ADC_OFR3_OFFSETPOS_Pos (24U)\n#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */\n#define ADC_OFR3_SATEN_Pos (25U)\n#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */\n\n#define ADC_OFR3_OFFSET3_CH_Pos (26U)\n#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */\n#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR3_OFFSET3_EN_Pos (31U)\n#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */\n\n/******************** Bit definition for ADC_OFR4 register ******************/\n#define ADC_OFR4_OFFSET4_Pos (0U)\n#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */\n#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */\n\n#define ADC_OFR4_OFFSETPOS_Pos (24U)\n#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */\n#define ADC_OFR4_SATEN_Pos (25U)\n#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */\n\n#define ADC_OFR4_OFFSET4_CH_Pos (26U)\n#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */\n#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR4_OFFSET4_EN_Pos (31U)\n#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */\n\n/******************** Bit definition for ADC_JDR1 register ******************/\n#define ADC_JDR1_JDATA_Pos (0U)\n#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */\n\n/******************** Bit definition for ADC_JDR2 register ******************/\n#define ADC_JDR2_JDATA_Pos (0U)\n#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */\n\n/******************** Bit definition for ADC_JDR3 register ******************/\n#define ADC_JDR3_JDATA_Pos (0U)\n#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */\n\n/******************** Bit definition for ADC_JDR4 register ******************/\n#define ADC_JDR4_JDATA_Pos (0U)\n#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */\n\n/******************** Bit definition for ADC_AWD2CR register ****************/\n#define ADC_AWD2CR_AWD2CH_Pos (0U)\n#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */\n#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */\n#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */\n#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */\n#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */\n#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */\n#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */\n#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */\n#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */\n#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */\n#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */\n#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */\n#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */\n#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */\n#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */\n#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */\n#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */\n#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */\n#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */\n#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */\n#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_AWD3CR register ****************/\n#define ADC_AWD3CR_AWD3CH_Pos (0U)\n#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */\n#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */\n#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */\n#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */\n#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */\n#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */\n#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */\n#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */\n#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */\n#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */\n#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */\n#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */\n#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */\n#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */\n#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */\n#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */\n#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */\n#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */\n#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */\n#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */\n#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_DIFSEL register ****************/\n#define ADC_DIFSEL_DIFSEL_Pos (0U)\n#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */\n#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */\n#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */\n#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */\n#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */\n#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */\n#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */\n#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */\n#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */\n#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */\n#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */\n#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */\n#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */\n#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */\n#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */\n#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */\n#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */\n#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */\n#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */\n#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */\n#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_CALFACT register ***************/\n#define ADC_CALFACT_CALFACT_S_Pos (0U)\n#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */\n#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */\n#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */\n#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */\n#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */\n#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */\n#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */\n#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */\n#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */\n\n#define ADC_CALFACT_CALFACT_D_Pos (16U)\n#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */\n#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */\n#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */\n#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */\n#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */\n#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */\n#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */\n#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */\n#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */\n\n/******************** Bit definition for ADC_GCOMP register *****************/\n#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)\n#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */\n#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */\n\n/************************* ADC Common registers *****************************/\n/******************** Bit definition for ADC_CSR register *******************/\n#define ADC_CSR_ADRDY_MST_Pos (0U)\n#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */\n#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */\n#define ADC_CSR_EOSMP_MST_Pos (1U)\n#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */\n#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */\n#define ADC_CSR_EOC_MST_Pos (2U)\n#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */\n#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */\n#define ADC_CSR_EOS_MST_Pos (3U)\n#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */\n#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */\n#define ADC_CSR_OVR_MST_Pos (4U)\n#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */\n#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */\n#define ADC_CSR_JEOC_MST_Pos (5U)\n#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */\n#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */\n#define ADC_CSR_JEOS_MST_Pos (6U)\n#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */\n#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */\n#define ADC_CSR_AWD1_MST_Pos (7U)\n#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */\n#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */\n#define ADC_CSR_AWD2_MST_Pos (8U)\n#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */\n#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */\n#define ADC_CSR_AWD3_MST_Pos (9U)\n#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */\n#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */\n#define ADC_CSR_JQOVF_MST_Pos (10U)\n#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */\n#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */\n\n#define ADC_CSR_ADRDY_SLV_Pos (16U)\n#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */\n#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */\n#define ADC_CSR_EOSMP_SLV_Pos (17U)\n#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */\n#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */\n#define ADC_CSR_EOC_SLV_Pos (18U)\n#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */\n#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */\n#define ADC_CSR_EOS_SLV_Pos (19U)\n#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */\n#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */\n#define ADC_CSR_OVR_SLV_Pos (20U)\n#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */\n#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */\n#define ADC_CSR_JEOC_SLV_Pos (21U)\n#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */\n#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */\n#define ADC_CSR_JEOS_SLV_Pos (22U)\n#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */\n#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */\n#define ADC_CSR_AWD1_SLV_Pos (23U)\n#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */\n#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */\n#define ADC_CSR_AWD2_SLV_Pos (24U)\n#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */\n#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */\n#define ADC_CSR_AWD3_SLV_Pos (25U)\n#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */\n#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */\n#define ADC_CSR_JQOVF_SLV_Pos (26U)\n#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */\n#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */\n\n/******************** Bit definition for ADC_CCR register *******************/\n#define ADC_CCR_DUAL_Pos (0U)\n#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */\n#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */\n#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */\n#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */\n#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */\n#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */\n#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */\n\n#define ADC_CCR_DELAY_Pos (8U)\n#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */\n#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */\n#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */\n\n#define ADC_CCR_DMACFG_Pos (13U)\n#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */\n#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */\n\n#define ADC_CCR_MDMA_Pos (14U)\n#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */\n#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */\n#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */\n#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */\n\n#define ADC_CCR_CKMODE_Pos (16U)\n#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */\n#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */\n#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */\n#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */\n\n#define ADC_CCR_PRESC_Pos (18U)\n#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */\n#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */\n#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */\n#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */\n#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */\n#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */\n\n#define ADC_CCR_VREFEN_Pos (22U)\n#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */\n#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */\n#define ADC_CCR_VSENSESEL_Pos (23U)\n#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */\n#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */\n#define ADC_CCR_VBATSEL_Pos (24U)\n#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */\n#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */\n\n/******************** Bit definition for ADC_CDR register *******************/\n#define ADC_CDR_RDATA_MST_Pos (0U)\n#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */\n#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */\n\n#define ADC_CDR_RDATA_SLV_Pos (16U)\n#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */\n#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */\n\n/******************************************************************************/\n/* */\n/* Advanced Encryption Standard (AES) */\n/* */\n/******************************************************************************/\n/******************* Bit definition for AES_CR register *********************/\n#define AES_CR_EN_Pos (0U)\n#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */\n#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */\n#define AES_CR_DATATYPE_Pos (1U)\n#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */\n#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */\n#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */\n#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */\n\n#define AES_CR_MODE_Pos (3U)\n#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */\n#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */\n#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */\n#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */\n\n#define AES_CR_CHMOD_Pos (5U)\n#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */\n#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */\n#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */\n#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */\n#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */\n\n#define AES_CR_CCFC_Pos (7U)\n#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */\n#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */\n#define AES_CR_ERRC_Pos (8U)\n#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */\n#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */\n#define AES_CR_CCFIE_Pos (9U)\n#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */\n#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */\n#define AES_CR_ERRIE_Pos (10U)\n#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */\n#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */\n#define AES_CR_DMAINEN_Pos (11U)\n#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */\n#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */\n#define AES_CR_DMAOUTEN_Pos (12U)\n#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */\n#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */\n\n#define AES_CR_GCMPH_Pos (13U)\n#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */\n#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */\n#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */\n#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */\n\n#define AES_CR_KEYSIZE_Pos (18U)\n#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */\n#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */\n#define AES_CR_NPBLB_Pos (20U)\n#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */\n#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */\n#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */\n#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */\n#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */\n#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */\n\n/******************* Bit definition for AES_SR register *********************/\n#define AES_SR_CCF_Pos (0U)\n#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */\n#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */\n#define AES_SR_RDERR_Pos (1U)\n#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */\n#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */\n#define AES_SR_WRERR_Pos (2U)\n#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */\n#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */\n#define AES_SR_BUSY_Pos (3U)\n#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */\n#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */\n\n/******************* Bit definition for AES_DINR register *******************/\n#define AES_DINR_Pos (0U)\n#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */\n#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */\n\n/******************* Bit definition for AES_DOUTR register ******************/\n#define AES_DOUTR_Pos (0U)\n#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */\n#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */\n\n/******************* Bit definition for AES_KEYR0 register ******************/\n#define AES_KEYR0_Pos (0U)\n#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */\n\n/******************* Bit definition for AES_KEYR1 register ******************/\n#define AES_KEYR1_Pos (0U)\n#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */\n\n/******************* Bit definition for AES_KEYR2 register ******************/\n#define AES_KEYR2_Pos (0U)\n#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */\n\n/******************* Bit definition for AES_KEYR3 register ******************/\n#define AES_KEYR3_Pos (0U)\n#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */\n\n/******************* Bit definition for AES_KEYR4 register ******************/\n#define AES_KEYR4_Pos (0U)\n#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */\n\n/******************* Bit definition for AES_KEYR5 register ******************/\n#define AES_KEYR5_Pos (0U)\n#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */\n\n/******************* Bit definition for AES_KEYR6 register ******************/\n#define AES_KEYR6_Pos (0U)\n#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */\n\n/******************* Bit definition for AES_KEYR7 register ******************/\n#define AES_KEYR7_Pos (0U)\n#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */\n\n/******************* Bit definition for AES_IVR0 register ******************/\n#define AES_IVR0_Pos (0U)\n#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */\n#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */\n\n/******************* Bit definition for AES_IVR1 register ******************/\n#define AES_IVR1_Pos (0U)\n#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */\n#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */\n\n/******************* Bit definition for AES_IVR2 register ******************/\n#define AES_IVR2_Pos (0U)\n#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */\n#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */\n\n/******************* Bit definition for AES_IVR3 register ******************/\n#define AES_IVR3_Pos (0U)\n#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */\n#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */\n\n/******************* Bit definition for AES_SUSP0R register ******************/\n#define AES_SUSP0R_Pos (0U)\n#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */\n\n/******************* Bit definition for AES_SUSP1R register ******************/\n#define AES_SUSP1R_Pos (0U)\n#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */\n\n/******************* Bit definition for AES_SUSP2R register ******************/\n#define AES_SUSP2R_Pos (0U)\n#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */\n\n/******************* Bit definition for AES_SUSP3R register ******************/\n#define AES_SUSP3R_Pos (0U)\n#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */\n\n/******************* Bit definition for AES_SUSP4R register ******************/\n#define AES_SUSP4R_Pos (0U)\n#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */\n\n/******************* Bit definition for AES_SUSP5R register ******************/\n#define AES_SUSP5R_Pos (0U)\n#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */\n\n/******************* Bit definition for AES_SUSP6R register ******************/\n#define AES_SUSP6R_Pos (0U)\n#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */\n\n/******************* Bit definition for AES_SUSP7R register ******************/\n#define AES_SUSP7R_Pos (0U)\n#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */\n\n/******************************************************************************/\n/* */\n/* Analog Comparators (COMP) */\n/* */\n/******************************************************************************/\n/********************** Bit definition for COMP_CSR register ****************/\n#define COMP_CSR_EN_Pos (0U)\n#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */\n#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */\n\n#define COMP_CSR_INMSEL_Pos (4U)\n#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */\n#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */\n#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */\n#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */\n#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */\n#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */\n\n#define COMP_CSR_INPSEL_Pos (8U)\n#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */\n#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */\n\n#define COMP_CSR_POLARITY_Pos (15U)\n#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */\n#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */\n\n#define COMP_CSR_HYST_Pos (16U)\n#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */\n#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */\n#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */\n#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */\n#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */\n\n#define COMP_CSR_BLANKING_Pos (19U)\n#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */\n#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */\n#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */\n#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */\n#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */\n\n#define COMP_CSR_BRGEN_Pos (22U)\n#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */\n#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */\n\n#define COMP_CSR_SCALEN_Pos (23U)\n#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */\n#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */\n\n#define COMP_CSR_VALUE_Pos (30U)\n#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */\n#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */\n\n#define COMP_CSR_LOCK_Pos (31U)\n#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */\n#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */\n\n/******************************************************************************/\n/* */\n/* CORDIC calculation unit */\n/* */\n/******************************************************************************/\n/******************* Bit definition for CORDIC_CSR register *****************/\n#define CORDIC_CSR_FUNC_Pos (0U)\n#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */\n#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */\n#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */\n#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */\n#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */\n#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */\n#define CORDIC_CSR_PRECISION_Pos (4U)\n#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */\n#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */\n#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */\n#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */\n#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */\n#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */\n#define CORDIC_CSR_SCALE_Pos (8U)\n#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */\n#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */\n#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */\n#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */\n#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */\n#define CORDIC_CSR_IEN_Pos (16U)\n#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */\n#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */\n#define CORDIC_CSR_DMAREN_Pos (17U)\n#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */\n#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */\n#define CORDIC_CSR_DMAWEN_Pos (18U)\n#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */\n#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */\n#define CORDIC_CSR_NRES_Pos (19U)\n#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */\n#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */\n#define CORDIC_CSR_NARGS_Pos (20U)\n#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */\n#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */\n#define CORDIC_CSR_RESSIZE_Pos (21U)\n#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */\n#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */\n#define CORDIC_CSR_ARGSIZE_Pos (22U)\n#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */\n#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */\n#define CORDIC_CSR_RRDY_Pos (31U)\n#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */\n#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */\n\n/******************* Bit definition for CORDIC_WDATA register ***************/\n#define CORDIC_WDATA_ARG_Pos (0U)\n#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */\n#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */\n\n/******************* Bit definition for CORDIC_RDATA register ***************/\n#define CORDIC_RDATA_RES_Pos (0U)\n#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */\n#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */\n\n/******************************************************************************/\n/* */\n/* CRC calculation unit */\n/* */\n/******************************************************************************/\n/******************* Bit definition for CRC_DR register *********************/\n#define CRC_DR_DR_Pos (0U)\n#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\n#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\n\n/******************* Bit definition for CRC_IDR register ********************/\n#define CRC_IDR_IDR_Pos (0U)\n#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */\n#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */\n\n/******************** Bit definition for CRC_CR register ********************/\n#define CRC_CR_RESET_Pos (0U)\n#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */\n#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */\n#define CRC_CR_POLYSIZE_Pos (3U)\n#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */\n#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */\n#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */\n#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */\n#define CRC_CR_REV_IN_Pos (5U)\n#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */\n#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */\n#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */\n#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */\n#define CRC_CR_REV_OUT_Pos (7U)\n#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */\n#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */\n\n/******************* Bit definition for CRC_INIT register *******************/\n#define CRC_INIT_INIT_Pos (0U)\n#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */\n#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */\n\n/******************* Bit definition for CRC_POL register ********************/\n#define CRC_POL_POL_Pos (0U)\n#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */\n#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */\n\n/******************************************************************************/\n/* */\n/* CRS Clock Recovery System */\n/******************************************************************************/\n\n/******************* Bit definition for CRS_CR register *********************/\n#define CRS_CR_SYNCOKIE_Pos (0U)\n#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */\n#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */\n#define CRS_CR_SYNCWARNIE_Pos (1U)\n#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */\n#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */\n#define CRS_CR_ERRIE_Pos (2U)\n#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */\n#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */\n#define CRS_CR_ESYNCIE_Pos (3U)\n#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */\n#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */\n#define CRS_CR_CEN_Pos (5U)\n#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */\n#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */\n#define CRS_CR_AUTOTRIMEN_Pos (6U)\n#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */\n#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */\n#define CRS_CR_SWSYNC_Pos (7U)\n#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */\n#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */\n#define CRS_CR_TRIM_Pos (8U)\n#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */\n#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */\n\n/******************* Bit definition for CRS_CFGR register *********************/\n#define CRS_CFGR_RELOAD_Pos (0U)\n#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */\n#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */\n#define CRS_CFGR_FELIM_Pos (16U)\n#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */\n#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */\n\n#define CRS_CFGR_SYNCDIV_Pos (24U)\n#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */\n#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */\n#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */\n#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */\n#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */\n\n#define CRS_CFGR_SYNCSRC_Pos (28U)\n#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */\n#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */\n#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */\n#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */\n\n#define CRS_CFGR_SYNCPOL_Pos (31U)\n#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */\n#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */\n\n/******************* Bit definition for CRS_ISR register *********************/\n#define CRS_ISR_SYNCOKF_Pos (0U)\n#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */\n#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */\n#define CRS_ISR_SYNCWARNF_Pos (1U)\n#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */\n#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */\n#define CRS_ISR_ERRF_Pos (2U)\n#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */\n#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */\n#define CRS_ISR_ESYNCF_Pos (3U)\n#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */\n#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */\n#define CRS_ISR_SYNCERR_Pos (8U)\n#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */\n#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */\n#define CRS_ISR_SYNCMISS_Pos (9U)\n#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */\n#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */\n#define CRS_ISR_TRIMOVF_Pos (10U)\n#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */\n#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */\n#define CRS_ISR_FEDIR_Pos (15U)\n#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */\n#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */\n#define CRS_ISR_FECAP_Pos (16U)\n#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */\n#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */\n\n/******************* Bit definition for CRS_ICR register *********************/\n#define CRS_ICR_SYNCOKC_Pos (0U)\n#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */\n#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */\n#define CRS_ICR_SYNCWARNC_Pos (1U)\n#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */\n#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */\n#define CRS_ICR_ERRC_Pos (2U)\n#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */\n#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */\n#define CRS_ICR_ESYNCC_Pos (3U)\n#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */\n#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */\n\n/******************************************************************************/\n/* */\n/* Digital to Analog Converter */\n/* */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)\n */\n#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */\n\n/******************** Bit definition for DAC_CR register ********************/\n#define DAC_CR_EN1_Pos (0U)\n#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */\n#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/\n#define DAC_CR_CEN1_Pos (14U)\n#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */\n#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/\n\n#define DAC_CR_HFSEL_Pos (15U)\n#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */\n#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/\n\n#define DAC_CR_EN2_Pos (16U)\n#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\n#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/\n#define DAC_CR_CEN2_Pos (30U)\n#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */\n#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/\n\n/***************** Bit definition for DAC_SWTRIGR register ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!\n\n/** @addtogroup Peripheral_registers_structures\n * @{\n */\n\n/**\n * @brief Analog to Digital Converter\n */\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */\n __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */\n __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */\n __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */\n __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */\n __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */\n __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */\n uint32_t RESERVED1; /*!< Reserved, 0x1C */\n __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */\n __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */\n __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */\n uint32_t RESERVED2; /*!< Reserved, 0x2C */\n __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */\n __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */\n __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */\n __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */\n __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */\n uint32_t RESERVED3; /*!< Reserved, 0x44 */\n uint32_t RESERVED4; /*!< Reserved, 0x48 */\n __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */\n uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */\n __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */\n __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */\n __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */\n __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */\n uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */\n __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */\n __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */\n __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */\n __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */\n uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */\n __IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */\n __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */\n uint32_t RESERVED8; /*!< Reserved, 0x0A8 */\n uint32_t RESERVED9; /*!< Reserved, 0x0AC */\n __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */\n __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */\n uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */\n __IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */\n} ADC_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */\n uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */\n __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */\n __IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */\n} ADC_Common_TypeDef;\n\n/**\n * @brief FD Controller Area Network\n */\n\ntypedef struct\n{\n __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */\n __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */\n uint32_t RESERVED1; /*!< Reserved, 0x008 */\n __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */\n __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */\n __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */\n __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */\n __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */\n __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */\n __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */\n __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */\n __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */\n uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */\n __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */\n __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */\n __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */\n uint32_t RESERVED3; /*!< Reserved, 0x04C */\n __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */\n __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */\n __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */\n __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */\n uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */\n __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */\n __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */\n __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */\n uint32_t RESERVED5; /*!< Reserved, 0x08C */\n __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */\n __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */\n __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */\n __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */\n uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */\n __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */\n __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */\n __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */\n __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */\n __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */\n __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */\n __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */\n __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */\n __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */\n __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */\n __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */\n} FDCAN_GlobalTypeDef;\n\n/**\n * @brief FD Controller Area Network Configuration\n */\n\ntypedef struct\n{\n __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */\n} FDCAN_Config_TypeDef;\n\n/**\n * @brief Comparator\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */\n} COMP_TypeDef;\n\n/**\n * @brief CRC calculation unit\n */\n\ntypedef struct\n{\n __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\n __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\n __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\n uint32_t RESERVED0; /*!< Reserved, 0x0C */\n __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\n __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\n} CRC_TypeDef;\n\n/**\n * @brief Clock Recovery System\n */\ntypedef struct\n{\n __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */\n __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */\n __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */\n __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */\n} CRS_TypeDef;\n\n/**\n * @brief Digital to Analog Converter\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\n __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\n __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\n __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\n __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\n __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\n __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\n __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\n __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\n __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\n __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\n __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\n __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\n __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\n __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */\n __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */\n __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */\n __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */\n __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */\n __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */\n __IO uint32_t RESERVED[2];\n __IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */\n __IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */\n __IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */\n} DAC_TypeDef;\n\n/**\n * @brief Debug MCU\n */\n\ntypedef struct\n{\n __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\n __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\n __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */\n __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */\n __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */\n} DBGMCU_TypeDef;\n\n/**\n * @brief DMA Controller\n */\n\ntypedef struct\n{\n __IO uint32_t CCR; /*!< DMA channel x configuration register */\n __IO uint32_t CNDTR; /*!< DMA channel x number of data register */\n __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */\n __IO uint32_t CMAR; /*!< DMA channel x memory address register */\n} DMA_Channel_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */\n __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */\n} DMA_TypeDef;\n\n/**\n * @brief DMA Multiplexer\n */\n\ntypedef struct\n{\n __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */\n}DMAMUX_Channel_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */\n __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */\n}DMAMUX_ChannelStatus_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */\n}DMAMUX_RequestGen_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */\n __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */\n}DMAMUX_RequestGenStatus_TypeDef;\n\n/**\n * @brief External Interrupt/Event Controller\n */\n\ntypedef struct\n{\n __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */\n __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */\n __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */\n __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */\n __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */\n __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */\n uint32_t RESERVED1; /*!< Reserved, 0x18 */\n uint32_t RESERVED2; /*!< Reserved, 0x1C */\n __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */\n __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */\n __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */\n __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */\n __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */\n __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */\n} EXTI_TypeDef;\n\n/**\n * @brief FLASH Registers\n */\n\ntypedef struct\n{\n __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\n __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */\n __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */\n __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */\n __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */\n __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */\n __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */\n uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */\n __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */\n __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */\n __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */\n __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */\n __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */\n uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */\n __IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */\n} FLASH_TypeDef;\n\n/**\n * @brief FMAC\n */\ntypedef struct\n{\n __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */\n __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */\n __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */\n __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */\n __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */\n __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */\n __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */\n __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */\n} FMAC_TypeDef;\n\n\n/**\n * @brief General Purpose I/O\n */\n\ntypedef struct\n{\n __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\n __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\n __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\n __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\n __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\n __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\n __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */\n __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\n __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\n __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */\n} GPIO_TypeDef;\n\n/**\n * @brief Inter-integrated Circuit Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\n __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\n __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\n __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\n __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\n __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\n __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\n __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\n __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\n __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */\n} I2C_TypeDef;\n\n/**\n * @brief Independent WATCHDOG\n */\n\ntypedef struct\n{\n __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\n __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\n __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\n __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\n __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\n} IWDG_TypeDef;\n\n/**\n * @brief LPTIMER\n */\n\ntypedef struct\n{\n __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\n __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\n __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\n __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\n __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\n __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\n __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\n __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\n __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */\n} LPTIM_TypeDef;\n\n/**\n * @brief Operational Amplifier (OPAMP)\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */\n __IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */\n __IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */\n} OPAMP_TypeDef;\n\n/**\n * @brief Power Control\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */\n __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */\n __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */\n __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */\n __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */\n __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */\n uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */\n __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */\n __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */\n __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */\n __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */\n __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */\n __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */\n __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */\n __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */\n __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */\n __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */\n __IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */\n __IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */\n __IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */\n __IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */\n uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */\n __IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */\n} PWR_TypeDef;\n\n/**\n * @brief QUAD Serial Peripheral Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */\n __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */\n __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */\n __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */\n __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */\n __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */\n __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */\n __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */\n __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */\n __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */\n __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */\n __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */\n __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */\n} QUADSPI_TypeDef;\n\n/**\n * @brief Reset and Clock Control\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\n __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */\n __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\n __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */\n uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */\n uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */\n __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */\n __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */\n __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */\n uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */\n __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */\n __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */\n __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */\n uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */\n __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */\n __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */\n __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */\n uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */\n __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */\n __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */\n __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */\n uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */\n __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */\n __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */\n __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */\n uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */\n __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */\n __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */\n __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */\n uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */\n __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */\n __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */\n __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */\n uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */\n __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */\n uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */\n __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */\n __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */\n __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */\n __IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */\n} RCC_TypeDef;\n\n/**\n * @brief Real-Time Clock\n */\n/*\n* @brief Specific device feature definitions\n*/\n#define RTC_TAMP_INT_6_SUPPORT\n#define RTC_TAMP_INT_NB 4u\n\n#define RTC_TAMP_NB 3u\n#define RTC_BACKUP_NB 32u\n\n\ntypedef struct\n{\n __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\n __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\n __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */\n __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */\n __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\n __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\n __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */\n uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */\n uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */\n __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\n __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */\n __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\n __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\n __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\n __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\n uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */\n __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */\n __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\n __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */\n __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */\n __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */\n __IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */\n uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */\n __IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */\n} RTC_TypeDef;\n\n/**\n * @brief Tamper and backup registers\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */\n uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */\n __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */\n uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */\n uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */\n __IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */\n __IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */\n __IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */\n uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */\n __IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */\n uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */\n __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */\n __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */\n __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */\n __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */\n __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */\n __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */\n __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */\n __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */\n __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */\n __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */\n __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */\n __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */\n __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */\n __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */\n __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */\n __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */\n __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */\n __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */\n __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */\n __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */\n __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */\n __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */\n __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */\n __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */\n __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */\n __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */\n __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */\n __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */\n __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */\n __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */\n __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */\n __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */\n} TAMP_TypeDef;\n\n/**\n * @brief Serial Audio Interface\n */\n\ntypedef struct\n{\n __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\n uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */\n __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */\n __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */\n} SAI_TypeDef;\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\n __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\n __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\n __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\n __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\n __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\n __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\n __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\n} SAI_Block_TypeDef;\n\n/**\n * @brief Serial Peripheral Interface\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */\n __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */\n __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\n __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */\n __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */\n __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */\n __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\n __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\n} SPI_TypeDef;\n\n/**\n * @brief System configuration controller\n */\n\ntypedef struct\n{\n __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\n __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */\n __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\n __IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */\n __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */\n __IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */\n __IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */\n} SYSCFG_TypeDef;\n\n/**\n * @brief TIM\n */\n\ntypedef struct\n{\n __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\n __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\n __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\n __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\n __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\n __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\n __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\n __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\n __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\n __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\n __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\n __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\n __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\n __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\n __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\n __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\n __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\n __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */\n __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */\n __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */\n __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */\n __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */\n __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */\n __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */\n __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */\n __IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */\n uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */\n __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */\n __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */\n} TIM_TypeDef;\n\n/**\n * @brief Universal Synchronous Asynchronous Receiver Transmitter\n */\ntypedef struct\n{\n __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */\n __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */\n __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\n __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */\n __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\n __IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */\n __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\n __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\n __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\n __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\n __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\n __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */\n} USART_TypeDef;\n\n/**\n * @brief Universal Serial Bus Full Speed Device\n */\n\ntypedef struct\n{\n __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */\n __IO uint16_t RESERVED0; /*!< Reserved */\n __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */\n __IO uint16_t RESERVED1; /*!< Reserved */\n __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */\n __IO uint16_t RESERVED2; /*!< Reserved */\n __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */\n __IO uint16_t RESERVED3; /*!< Reserved */\n __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */\n __IO uint16_t RESERVED4; /*!< Reserved */\n __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */\n __IO uint16_t RESERVED5; /*!< Reserved */\n __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */\n __IO uint16_t RESERVED6; /*!< Reserved */\n __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */\n __IO uint16_t RESERVED7[17]; /*!< Reserved */\n __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */\n __IO uint16_t RESERVED8; /*!< Reserved */\n __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */\n __IO uint16_t RESERVED9; /*!< Reserved */\n __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */\n __IO uint16_t RESERVEDA; /*!< Reserved */\n __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */\n __IO uint16_t RESERVEDB; /*!< Reserved */\n __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */\n __IO uint16_t RESERVEDC; /*!< Reserved */\n __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */\n __IO uint16_t RESERVEDD; /*!< Reserved */\n __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */\n __IO uint16_t RESERVEDE; /*!< Reserved */\n} USB_TypeDef;\n\n/**\n * @brief VREFBUF\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */\n __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */\n} VREFBUF_TypeDef;\n\n/**\n * @brief Window WATCHDOG\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\n __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\n __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\n} WWDG_TypeDef;\n\n/**\n * @brief AES hardware accelerator\n */\n\ntypedef struct\n{\n __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */\n __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */\n __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */\n __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */\n __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */\n __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */\n __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */\n __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */\n __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */\n __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */\n __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */\n __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */\n __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */\n __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */\n __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */\n __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */\n __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */\n __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */\n __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */\n __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */\n __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */\n __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */\n __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */\n __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */\n} AES_TypeDef;\n\n/**\n * @brief RNG\n */\ntypedef struct\n{\n __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\n __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\n __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\n} RNG_TypeDef;\n\n/**\n * @brief CORDIC\n */\n\ntypedef struct\n{\n __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */\n __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */\n __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */\n} CORDIC_TypeDef;\n\n/**\n * @brief UCPD\n */\n\ntypedef struct\n{\n __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */\n __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */\n __IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */\n __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */\n __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */\n __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */\n __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */\n __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */\n __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */\n __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */\n __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */\n __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */\n __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */\n __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */\n __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */\n} UCPD_TypeDef;\n\n\n/**\n * @}\n */\n\n/** @addtogroup Peripheral_memory_map\n * @{\n */\n\n#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */\n#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */\n#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */\n#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */\n#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */\n#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */\n\n#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */\n#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */\n#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */\n#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */\n#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */\n/* Legacy defines */\n#define SRAM_BASE SRAM1_BASE\n#define SRAM_BB_BASE SRAM1_BB_BASE\n\n#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */\n#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */\n#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */\n\n/*!< Peripheral memory map */\n#define APB1PERIPH_BASE PERIPH_BASE\n#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\n#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)\n#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)\n\n\n/*!< APB1 peripherals */\n#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)\n#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)\n#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)\n#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)\n#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)\n#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)\n#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)\n#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)\n#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)\n#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)\n#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)\n#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)\n#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)\n#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)\n#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)\n#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)\n#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)\n#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)\n#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */\n#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */\n#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)\n#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */\n#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)\n#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)\n#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)\n#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)\n#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)\n#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)\n#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)\n\n/*!< APB2 peripherals */\n#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)\n#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)\n#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)\n#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)\n#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)\n#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)\n#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)\n#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)\n#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)\n#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)\n#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)\n\n#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)\n#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)\n#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)\n#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)\n#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)\n#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)\n#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)\n#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)\n#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)\n#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)\n#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)\n#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)\n\n/*!< AHB1 peripherals */\n#define DMA1_BASE (AHB1PERIPH_BASE)\n#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)\n#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)\n#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)\n#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)\n#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)\n#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)\n#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)\n\n#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)\n#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)\n#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)\n#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)\n#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)\n#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)\n#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)\n#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)\n\n#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)\n#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)\n#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)\n#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)\n#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)\n#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)\n#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)\n#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)\n\n#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)\n#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)\n#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)\n#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)\n#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)\n#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)\n#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)\n#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)\n#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)\n#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)\n#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)\n#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)\n#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)\n#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)\n#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)\n#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)\n#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)\n#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)\n#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)\n#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)\n\n#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)\n#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)\n\n/*!< AHB2 peripherals */\n#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)\n#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)\n#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)\n#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)\n#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)\n#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)\n#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)\n\n#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)\n#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)\n#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)\n#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)\n#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)\n\n#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)\n#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)\n#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)\n#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL)\n\n#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)\n/* Debug MCU registers base address */\n#define DBGMCU_BASE (0xE0042000UL)\n\n#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */\n#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */\n#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */\n/**\n * @}\n */\n\n/** @addtogroup Peripheral_declaration\n * @{\n */\n#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\n#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\n#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\n#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\n#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\n#define CRS ((CRS_TypeDef *) CRS_BASE)\n#define TAMP ((TAMP_TypeDef *) TAMP_BASE)\n#define RTC ((RTC_TypeDef *) RTC_BASE)\n#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\n#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\n#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\n#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\n#define USART2 ((USART_TypeDef *) USART2_BASE)\n#define USART3 ((USART_TypeDef *) USART3_BASE)\n#define UART4 ((USART_TypeDef *) UART4_BASE)\n#define UART5 ((USART_TypeDef *) UART5_BASE)\n#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\n#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\n#define USB ((USB_TypeDef *) USB_BASE)\n#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)\n#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)\n#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)\n#define PWR ((PWR_TypeDef *) PWR_BASE)\n#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\n#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\n#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)\n#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)\n\n#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\n#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)\n#define COMP1 ((COMP_TypeDef *) COMP1_BASE)\n#define COMP2 ((COMP_TypeDef *) COMP2_BASE)\n#define COMP3 ((COMP_TypeDef *) COMP3_BASE)\n#define COMP4 ((COMP_TypeDef *) COMP4_BASE)\n\n#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)\n#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)\n#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)\n#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)\n#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)\n\n#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\n#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\n#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\n#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\n#define USART1 ((USART_TypeDef *) USART1_BASE)\n#define TIM15 ((TIM_TypeDef *) TIM15_BASE)\n#define TIM16 ((TIM_TypeDef *) TIM16_BASE)\n#define TIM17 ((TIM_TypeDef *) TIM17_BASE)\n#define TIM20 ((TIM_TypeDef *) TIM20_BASE)\n#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\n#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\n#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\n#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\n#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\n#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)\n#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)\n#define RCC ((RCC_TypeDef *) RCC_BASE)\n#define FMAC ((FMAC_TypeDef *) FMAC_BASE)\n#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\n#define CRC ((CRC_TypeDef *) CRC_BASE)\n\n#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\n#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\n#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\n#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\n#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\n#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\n#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\n#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\n#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\n#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)\n#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\n#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)\n#define DAC ((DAC_TypeDef *) DAC_BASE)\n#define DAC1 ((DAC_TypeDef *) DAC1_BASE)\n#define DAC3 ((DAC_TypeDef *) DAC3_BASE)\n#define AES ((AES_TypeDef *) AES_BASE)\n#define RNG ((RNG_TypeDef *) RNG_BASE)\n\n#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)\n#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)\n#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)\n#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)\n#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)\n#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)\n#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)\n#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)\n\n#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)\n#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)\n#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)\n#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)\n#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)\n#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)\n#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)\n#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)\n\n#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)\n#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)\n#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)\n#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)\n#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)\n#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)\n#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)\n#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)\n#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)\n#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)\n#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)\n#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)\n#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)\n#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)\n#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)\n#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)\n\n#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)\n#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)\n#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)\n#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)\n\n#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)\n#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)\n\n\n#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)\n\n#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\n\n/**\n * @}\n */\n\n/** @addtogroup Exported_constants\n * @{\n */\n\n /** @addtogroup Hardware_Constant_Definition\n * @{\n */\n#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */\n\n /**\n * @}\n */\n\n/** @addtogroup Peripheral_Registers_Bits_Definition\n * @{\n */\n\n/******************************************************************************/\n/* Peripheral Registers_Bits_Definition */\n/******************************************************************************/\n\n/******************************************************************************/\n/* */\n/* Analog to Digital Converter */\n/* */\n/******************************************************************************/\n\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)\n */\n#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */\n\n/******************** Bit definition for ADC_ISR register *******************/\n#define ADC_ISR_ADRDY_Pos (0U)\n#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */\n#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */\n#define ADC_ISR_EOSMP_Pos (1U)\n#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */\n#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */\n#define ADC_ISR_EOC_Pos (2U)\n#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */\n#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */\n#define ADC_ISR_EOS_Pos (3U)\n#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */\n#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */\n#define ADC_ISR_OVR_Pos (4U)\n#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */\n#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */\n#define ADC_ISR_JEOC_Pos (5U)\n#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */\n#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */\n#define ADC_ISR_JEOS_Pos (6U)\n#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */\n#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */\n#define ADC_ISR_AWD1_Pos (7U)\n#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */\n#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */\n#define ADC_ISR_AWD2_Pos (8U)\n#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */\n#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */\n#define ADC_ISR_AWD3_Pos (9U)\n#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */\n#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */\n#define ADC_ISR_JQOVF_Pos (10U)\n#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */\n#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */\n\n/******************** Bit definition for ADC_IER register *******************/\n#define ADC_IER_ADRDYIE_Pos (0U)\n#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */\n#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */\n#define ADC_IER_EOSMPIE_Pos (1U)\n#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */\n#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */\n#define ADC_IER_EOCIE_Pos (2U)\n#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */\n#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */\n#define ADC_IER_EOSIE_Pos (3U)\n#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */\n#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */\n#define ADC_IER_OVRIE_Pos (4U)\n#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */\n#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */\n#define ADC_IER_JEOCIE_Pos (5U)\n#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */\n#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */\n#define ADC_IER_JEOSIE_Pos (6U)\n#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */\n#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */\n#define ADC_IER_AWD1IE_Pos (7U)\n#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */\n#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */\n#define ADC_IER_AWD2IE_Pos (8U)\n#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */\n#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */\n#define ADC_IER_AWD3IE_Pos (9U)\n#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */\n#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */\n#define ADC_IER_JQOVFIE_Pos (10U)\n#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */\n#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */\n\n/******************** Bit definition for ADC_CR register ********************/\n#define ADC_CR_ADEN_Pos (0U)\n#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */\n#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */\n#define ADC_CR_ADDIS_Pos (1U)\n#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */\n#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */\n#define ADC_CR_ADSTART_Pos (2U)\n#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */\n#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */\n#define ADC_CR_JADSTART_Pos (3U)\n#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */\n#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */\n#define ADC_CR_ADSTP_Pos (4U)\n#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */\n#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */\n#define ADC_CR_JADSTP_Pos (5U)\n#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */\n#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */\n#define ADC_CR_ADVREGEN_Pos (28U)\n#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */\n#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */\n#define ADC_CR_DEEPPWD_Pos (29U)\n#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */\n#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */\n#define ADC_CR_ADCALDIF_Pos (30U)\n#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */\n#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */\n#define ADC_CR_ADCAL_Pos (31U)\n#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */\n#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */\n\n/******************** Bit definition for ADC_CFGR register ******************/\n#define ADC_CFGR_DMAEN_Pos (0U)\n#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */\n#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */\n#define ADC_CFGR_DMACFG_Pos (1U)\n#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */\n#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */\n\n#define ADC_CFGR_RES_Pos (3U)\n#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */\n#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */\n#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */\n#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */\n\n#define ADC_CFGR_EXTSEL_Pos (5U)\n#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */\n#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */\n#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */\n#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */\n#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */\n#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */\n#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */\n\n#define ADC_CFGR_EXTEN_Pos (10U)\n#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */\n#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */\n#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */\n#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */\n\n#define ADC_CFGR_OVRMOD_Pos (12U)\n#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */\n#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */\n#define ADC_CFGR_CONT_Pos (13U)\n#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */\n#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */\n#define ADC_CFGR_AUTDLY_Pos (14U)\n#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */\n#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */\n#define ADC_CFGR_ALIGN_Pos (15U)\n#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */\n#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */\n#define ADC_CFGR_DISCEN_Pos (16U)\n#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */\n#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */\n\n#define ADC_CFGR_DISCNUM_Pos (17U)\n#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */\n#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */\n#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */\n#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */\n#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */\n\n#define ADC_CFGR_JDISCEN_Pos (20U)\n#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */\n#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */\n#define ADC_CFGR_JQM_Pos (21U)\n#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */\n#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */\n#define ADC_CFGR_AWD1SGL_Pos (22U)\n#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */\n#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */\n#define ADC_CFGR_AWD1EN_Pos (23U)\n#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */\n#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */\n#define ADC_CFGR_JAWD1EN_Pos (24U)\n#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */\n#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */\n#define ADC_CFGR_JAUTO_Pos (25U)\n#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */\n#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */\n\n#define ADC_CFGR_AWD1CH_Pos (26U)\n#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */\n#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */\n#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */\n#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */\n#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */\n#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */\n#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */\n\n#define ADC_CFGR_JQDIS_Pos (31U)\n#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */\n#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */\n\n/******************** Bit definition for ADC_CFGR2 register *****************/\n#define ADC_CFGR2_ROVSE_Pos (0U)\n#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */\n#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */\n#define ADC_CFGR2_JOVSE_Pos (1U)\n#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */\n#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */\n\n#define ADC_CFGR2_OVSR_Pos (2U)\n#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */\n#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */\n#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */\n#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */\n#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */\n\n#define ADC_CFGR2_OVSS_Pos (5U)\n#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */\n#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */\n#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */\n#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */\n#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */\n#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */\n\n#define ADC_CFGR2_TROVS_Pos (9U)\n#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */\n#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */\n#define ADC_CFGR2_ROVSM_Pos (10U)\n#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */\n#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */\n\n#define ADC_CFGR2_GCOMP_Pos (16U)\n#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */\n#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */\n\n#define ADC_CFGR2_SWTRIG_Pos (25U)\n#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */\n#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */\n#define ADC_CFGR2_BULB_Pos (26U)\n#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */\n#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */\n#define ADC_CFGR2_SMPTRIG_Pos (27U)\n#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */\n#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */\n\n/******************** Bit definition for ADC_SMPR1 register *****************/\n#define ADC_SMPR1_SMP0_Pos (0U)\n#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */\n#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */\n#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */\n#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */\n#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */\n\n#define ADC_SMPR1_SMP1_Pos (3U)\n#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */\n#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */\n#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */\n#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */\n#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */\n\n#define ADC_SMPR1_SMP2_Pos (6U)\n#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */\n#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */\n#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */\n#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */\n#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */\n\n#define ADC_SMPR1_SMP3_Pos (9U)\n#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */\n#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */\n#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */\n#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */\n#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */\n\n#define ADC_SMPR1_SMP4_Pos (12U)\n#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */\n#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */\n#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */\n#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */\n#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */\n\n#define ADC_SMPR1_SMP5_Pos (15U)\n#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */\n#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */\n#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */\n#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */\n#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */\n\n#define ADC_SMPR1_SMP6_Pos (18U)\n#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */\n#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */\n#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */\n#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */\n#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */\n\n#define ADC_SMPR1_SMP7_Pos (21U)\n#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */\n#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */\n#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */\n#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */\n#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */\n\n#define ADC_SMPR1_SMP8_Pos (24U)\n#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */\n#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */\n#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */\n#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */\n#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */\n\n#define ADC_SMPR1_SMP9_Pos (27U)\n#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */\n#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */\n#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */\n#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */\n#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */\n\n#define ADC_SMPR1_SMPPLUS_Pos (31U)\n#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */\n#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */\n\n/******************** Bit definition for ADC_SMPR2 register *****************/\n#define ADC_SMPR2_SMP10_Pos (0U)\n#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */\n#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */\n#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */\n#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */\n#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */\n\n#define ADC_SMPR2_SMP11_Pos (3U)\n#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */\n#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */\n#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */\n#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */\n#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */\n\n#define ADC_SMPR2_SMP12_Pos (6U)\n#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */\n#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */\n#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */\n#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */\n#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */\n\n#define ADC_SMPR2_SMP13_Pos (9U)\n#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */\n#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */\n#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */\n#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */\n#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */\n\n#define ADC_SMPR2_SMP14_Pos (12U)\n#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */\n#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */\n#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */\n#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */\n#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */\n\n#define ADC_SMPR2_SMP15_Pos (15U)\n#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */\n#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */\n#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */\n#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */\n#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */\n\n#define ADC_SMPR2_SMP16_Pos (18U)\n#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */\n#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */\n#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */\n#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */\n#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */\n\n#define ADC_SMPR2_SMP17_Pos (21U)\n#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */\n#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */\n#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */\n#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */\n#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */\n\n#define ADC_SMPR2_SMP18_Pos (24U)\n#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */\n#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */\n#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */\n#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */\n#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */\n\n/******************** Bit definition for ADC_TR1 register *******************/\n#define ADC_TR1_LT1_Pos (0U)\n#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */\n#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */\n\n#define ADC_TR1_AWDFILT_Pos (12U)\n#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */\n#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */\n#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */\n#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */\n#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */\n\n#define ADC_TR1_HT1_Pos (16U)\n#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */\n#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */\n\n/******************** Bit definition for ADC_TR2 register *******************/\n#define ADC_TR2_LT2_Pos (0U)\n#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */\n#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */\n\n#define ADC_TR2_HT2_Pos (16U)\n#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */\n#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */\n\n/******************** Bit definition for ADC_TR3 register *******************/\n#define ADC_TR3_LT3_Pos (0U)\n#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */\n#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */\n\n#define ADC_TR3_HT3_Pos (16U)\n#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */\n#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */\n\n/******************** Bit definition for ADC_SQR1 register ******************/\n#define ADC_SQR1_L_Pos (0U)\n#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */\n#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */\n#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */\n#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */\n#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */\n#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */\n\n#define ADC_SQR1_SQ1_Pos (6U)\n#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */\n#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */\n#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */\n#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */\n#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */\n#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */\n#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR1_SQ2_Pos (12U)\n#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */\n#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */\n#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */\n#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */\n#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */\n#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */\n#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR1_SQ3_Pos (18U)\n#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */\n#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */\n#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */\n#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */\n#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */\n#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */\n#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR1_SQ4_Pos (24U)\n#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */\n#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */\n#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */\n#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */\n#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */\n#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */\n#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR2 register ******************/\n#define ADC_SQR2_SQ5_Pos (0U)\n#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */\n#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */\n#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */\n#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */\n#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */\n#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */\n#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR2_SQ6_Pos (6U)\n#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */\n#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */\n#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */\n#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */\n#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */\n#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */\n#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR2_SQ7_Pos (12U)\n#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */\n#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */\n#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */\n#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */\n#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */\n#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */\n#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR2_SQ8_Pos (18U)\n#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */\n#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */\n#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */\n#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */\n#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */\n#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */\n#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR2_SQ9_Pos (24U)\n#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */\n#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */\n#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */\n#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */\n#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */\n#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */\n#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR3 register ******************/\n#define ADC_SQR3_SQ10_Pos (0U)\n#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */\n#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */\n#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */\n#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */\n#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */\n#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */\n#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR3_SQ11_Pos (6U)\n#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */\n#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */\n#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */\n#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */\n#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */\n#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */\n#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */\n\n#define ADC_SQR3_SQ12_Pos (12U)\n#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */\n#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */\n#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */\n#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */\n#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */\n#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */\n#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */\n\n#define ADC_SQR3_SQ13_Pos (18U)\n#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */\n#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */\n#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */\n#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */\n#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */\n#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */\n#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */\n\n#define ADC_SQR3_SQ14_Pos (24U)\n#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */\n#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */\n#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */\n#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */\n#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */\n#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */\n#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */\n\n/******************** Bit definition for ADC_SQR4 register ******************/\n#define ADC_SQR4_SQ15_Pos (0U)\n#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */\n#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */\n#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */\n#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */\n#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */\n#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */\n#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */\n\n#define ADC_SQR4_SQ16_Pos (6U)\n#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */\n#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */\n#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */\n#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */\n#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */\n#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */\n#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */\n\n/******************** Bit definition for ADC_DR register ********************/\n#define ADC_DR_RDATA_Pos (0U)\n#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */\n\n/******************** Bit definition for ADC_JSQR register ******************/\n#define ADC_JSQR_JL_Pos (0U)\n#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */\n#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */\n#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */\n#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */\n\n#define ADC_JSQR_JEXTSEL_Pos (2U)\n#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */\n#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */\n#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */\n#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */\n#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */\n#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */\n#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */\n\n#define ADC_JSQR_JEXTEN_Pos (7U)\n#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */\n#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */\n#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */\n#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */\n\n#define ADC_JSQR_JSQ1_Pos (9U)\n#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */\n#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */\n#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */\n#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */\n#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */\n#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */\n#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */\n\n#define ADC_JSQR_JSQ2_Pos (15U)\n#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */\n#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */\n#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */\n#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */\n#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */\n#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */\n#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */\n\n#define ADC_JSQR_JSQ3_Pos (21U)\n#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */\n#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */\n#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */\n#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */\n#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */\n#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */\n#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */\n\n#define ADC_JSQR_JSQ4_Pos (27U)\n#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */\n#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */\n#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */\n#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */\n#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */\n#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */\n#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */\n\n/******************** Bit definition for ADC_OFR1 register ******************/\n#define ADC_OFR1_OFFSET1_Pos (0U)\n#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */\n#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */\n\n#define ADC_OFR1_OFFSETPOS_Pos (24U)\n#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */\n#define ADC_OFR1_SATEN_Pos (25U)\n#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */\n\n#define ADC_OFR1_OFFSET1_CH_Pos (26U)\n#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */\n#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR1_OFFSET1_EN_Pos (31U)\n#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */\n\n/******************** Bit definition for ADC_OFR2 register ******************/\n#define ADC_OFR2_OFFSET2_Pos (0U)\n#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */\n#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */\n\n#define ADC_OFR2_OFFSETPOS_Pos (24U)\n#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */\n#define ADC_OFR2_SATEN_Pos (25U)\n#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */\n\n#define ADC_OFR2_OFFSET2_CH_Pos (26U)\n#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */\n#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR2_OFFSET2_EN_Pos (31U)\n#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */\n\n/******************** Bit definition for ADC_OFR3 register ******************/\n#define ADC_OFR3_OFFSET3_Pos (0U)\n#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */\n#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */\n\n#define ADC_OFR3_OFFSETPOS_Pos (24U)\n#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */\n#define ADC_OFR3_SATEN_Pos (25U)\n#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */\n\n#define ADC_OFR3_OFFSET3_CH_Pos (26U)\n#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */\n#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR3_OFFSET3_EN_Pos (31U)\n#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */\n\n/******************** Bit definition for ADC_OFR4 register ******************/\n#define ADC_OFR4_OFFSET4_Pos (0U)\n#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */\n#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */\n\n#define ADC_OFR4_OFFSETPOS_Pos (24U)\n#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */\n#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */\n#define ADC_OFR4_SATEN_Pos (25U)\n#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */\n#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */\n\n#define ADC_OFR4_OFFSET4_CH_Pos (26U)\n#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */\n#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */\n#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */\n#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */\n#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */\n#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */\n#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */\n\n#define ADC_OFR4_OFFSET4_EN_Pos (31U)\n#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */\n#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */\n\n/******************** Bit definition for ADC_JDR1 register ******************/\n#define ADC_JDR1_JDATA_Pos (0U)\n#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */\n\n/******************** Bit definition for ADC_JDR2 register ******************/\n#define ADC_JDR2_JDATA_Pos (0U)\n#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */\n\n/******************** Bit definition for ADC_JDR3 register ******************/\n#define ADC_JDR3_JDATA_Pos (0U)\n#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */\n\n/******************** Bit definition for ADC_JDR4 register ******************/\n#define ADC_JDR4_JDATA_Pos (0U)\n#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */\n#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */\n\n/******************** Bit definition for ADC_AWD2CR register ****************/\n#define ADC_AWD2CR_AWD2CH_Pos (0U)\n#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */\n#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */\n#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */\n#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */\n#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */\n#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */\n#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */\n#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */\n#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */\n#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */\n#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */\n#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */\n#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */\n#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */\n#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */\n#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */\n#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */\n#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */\n#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */\n#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */\n#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_AWD3CR register ****************/\n#define ADC_AWD3CR_AWD3CH_Pos (0U)\n#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */\n#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */\n#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */\n#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */\n#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */\n#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */\n#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */\n#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */\n#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */\n#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */\n#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */\n#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */\n#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */\n#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */\n#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */\n#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */\n#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */\n#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */\n#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */\n#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */\n#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_DIFSEL register ****************/\n#define ADC_DIFSEL_DIFSEL_Pos (0U)\n#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */\n#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */\n#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */\n#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */\n#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */\n#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */\n#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */\n#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */\n#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */\n#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */\n#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */\n#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */\n#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */\n#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */\n#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */\n#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */\n#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */\n#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */\n#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */\n#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */\n#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */\n\n/******************** Bit definition for ADC_CALFACT register ***************/\n#define ADC_CALFACT_CALFACT_S_Pos (0U)\n#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */\n#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */\n#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */\n#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */\n#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */\n#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */\n#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */\n#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */\n#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */\n\n#define ADC_CALFACT_CALFACT_D_Pos (16U)\n#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */\n#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */\n#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */\n#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */\n#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */\n#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */\n#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */\n#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */\n#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */\n\n/******************** Bit definition for ADC_GCOMP register *****************/\n#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)\n#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */\n#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */\n\n/************************* ADC Common registers *****************************/\n/******************** Bit definition for ADC_CSR register *******************/\n#define ADC_CSR_ADRDY_MST_Pos (0U)\n#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */\n#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */\n#define ADC_CSR_EOSMP_MST_Pos (1U)\n#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */\n#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */\n#define ADC_CSR_EOC_MST_Pos (2U)\n#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */\n#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */\n#define ADC_CSR_EOS_MST_Pos (3U)\n#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */\n#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */\n#define ADC_CSR_OVR_MST_Pos (4U)\n#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */\n#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */\n#define ADC_CSR_JEOC_MST_Pos (5U)\n#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */\n#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */\n#define ADC_CSR_JEOS_MST_Pos (6U)\n#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */\n#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */\n#define ADC_CSR_AWD1_MST_Pos (7U)\n#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */\n#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */\n#define ADC_CSR_AWD2_MST_Pos (8U)\n#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */\n#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */\n#define ADC_CSR_AWD3_MST_Pos (9U)\n#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */\n#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */\n#define ADC_CSR_JQOVF_MST_Pos (10U)\n#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */\n#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */\n\n#define ADC_CSR_ADRDY_SLV_Pos (16U)\n#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */\n#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */\n#define ADC_CSR_EOSMP_SLV_Pos (17U)\n#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */\n#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */\n#define ADC_CSR_EOC_SLV_Pos (18U)\n#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */\n#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */\n#define ADC_CSR_EOS_SLV_Pos (19U)\n#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */\n#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */\n#define ADC_CSR_OVR_SLV_Pos (20U)\n#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */\n#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */\n#define ADC_CSR_JEOC_SLV_Pos (21U)\n#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */\n#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */\n#define ADC_CSR_JEOS_SLV_Pos (22U)\n#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */\n#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */\n#define ADC_CSR_AWD1_SLV_Pos (23U)\n#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */\n#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */\n#define ADC_CSR_AWD2_SLV_Pos (24U)\n#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */\n#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */\n#define ADC_CSR_AWD3_SLV_Pos (25U)\n#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */\n#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */\n#define ADC_CSR_JQOVF_SLV_Pos (26U)\n#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */\n#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */\n\n/******************** Bit definition for ADC_CCR register *******************/\n#define ADC_CCR_DUAL_Pos (0U)\n#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */\n#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */\n#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */\n#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */\n#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */\n#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */\n#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */\n\n#define ADC_CCR_DELAY_Pos (8U)\n#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */\n#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */\n#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */\n#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */\n#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */\n#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */\n\n#define ADC_CCR_DMACFG_Pos (13U)\n#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */\n#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */\n\n#define ADC_CCR_MDMA_Pos (14U)\n#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */\n#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */\n#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */\n#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */\n\n#define ADC_CCR_CKMODE_Pos (16U)\n#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */\n#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */\n#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */\n#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */\n\n#define ADC_CCR_PRESC_Pos (18U)\n#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */\n#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */\n#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */\n#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */\n#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */\n#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */\n\n#define ADC_CCR_VREFEN_Pos (22U)\n#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */\n#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */\n#define ADC_CCR_VSENSESEL_Pos (23U)\n#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */\n#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */\n#define ADC_CCR_VBATSEL_Pos (24U)\n#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */\n#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */\n\n/******************** Bit definition for ADC_CDR register *******************/\n#define ADC_CDR_RDATA_MST_Pos (0U)\n#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */\n#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */\n\n#define ADC_CDR_RDATA_SLV_Pos (16U)\n#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */\n#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */\n\n/******************************************************************************/\n/* */\n/* Advanced Encryption Standard (AES) */\n/* */\n/******************************************************************************/\n/******************* Bit definition for AES_CR register *********************/\n#define AES_CR_EN_Pos (0U)\n#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */\n#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */\n#define AES_CR_DATATYPE_Pos (1U)\n#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */\n#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */\n#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */\n#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */\n\n#define AES_CR_MODE_Pos (3U)\n#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */\n#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */\n#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */\n#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */\n\n#define AES_CR_CHMOD_Pos (5U)\n#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */\n#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */\n#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */\n#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */\n#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */\n\n#define AES_CR_CCFC_Pos (7U)\n#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */\n#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */\n#define AES_CR_ERRC_Pos (8U)\n#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */\n#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */\n#define AES_CR_CCFIE_Pos (9U)\n#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */\n#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */\n#define AES_CR_ERRIE_Pos (10U)\n#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */\n#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */\n#define AES_CR_DMAINEN_Pos (11U)\n#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */\n#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */\n#define AES_CR_DMAOUTEN_Pos (12U)\n#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */\n#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */\n\n#define AES_CR_GCMPH_Pos (13U)\n#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */\n#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */\n#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */\n#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */\n\n#define AES_CR_KEYSIZE_Pos (18U)\n#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */\n#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */\n#define AES_CR_NPBLB_Pos (20U)\n#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */\n#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */\n#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */\n#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */\n#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */\n#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */\n\n/******************* Bit definition for AES_SR register *********************/\n#define AES_SR_CCF_Pos (0U)\n#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */\n#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */\n#define AES_SR_RDERR_Pos (1U)\n#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */\n#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */\n#define AES_SR_WRERR_Pos (2U)\n#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */\n#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */\n#define AES_SR_BUSY_Pos (3U)\n#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */\n#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */\n\n/******************* Bit definition for AES_DINR register *******************/\n#define AES_DINR_Pos (0U)\n#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */\n#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */\n\n/******************* Bit definition for AES_DOUTR register ******************/\n#define AES_DOUTR_Pos (0U)\n#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */\n#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */\n\n/******************* Bit definition for AES_KEYR0 register ******************/\n#define AES_KEYR0_Pos (0U)\n#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */\n\n/******************* Bit definition for AES_KEYR1 register ******************/\n#define AES_KEYR1_Pos (0U)\n#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */\n\n/******************* Bit definition for AES_KEYR2 register ******************/\n#define AES_KEYR2_Pos (0U)\n#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */\n\n/******************* Bit definition for AES_KEYR3 register ******************/\n#define AES_KEYR3_Pos (0U)\n#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */\n\n/******************* Bit definition for AES_KEYR4 register ******************/\n#define AES_KEYR4_Pos (0U)\n#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */\n\n/******************* Bit definition for AES_KEYR5 register ******************/\n#define AES_KEYR5_Pos (0U)\n#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */\n\n/******************* Bit definition for AES_KEYR6 register ******************/\n#define AES_KEYR6_Pos (0U)\n#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */\n\n/******************* Bit definition for AES_KEYR7 register ******************/\n#define AES_KEYR7_Pos (0U)\n#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */\n#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */\n\n/******************* Bit definition for AES_IVR0 register ******************/\n#define AES_IVR0_Pos (0U)\n#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */\n#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */\n\n/******************* Bit definition for AES_IVR1 register ******************/\n#define AES_IVR1_Pos (0U)\n#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */\n#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */\n\n/******************* Bit definition for AES_IVR2 register ******************/\n#define AES_IVR2_Pos (0U)\n#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */\n#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */\n\n/******************* Bit definition for AES_IVR3 register ******************/\n#define AES_IVR3_Pos (0U)\n#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */\n#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */\n\n/******************* Bit definition for AES_SUSP0R register ******************/\n#define AES_SUSP0R_Pos (0U)\n#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */\n\n/******************* Bit definition for AES_SUSP1R register ******************/\n#define AES_SUSP1R_Pos (0U)\n#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */\n\n/******************* Bit definition for AES_SUSP2R register ******************/\n#define AES_SUSP2R_Pos (0U)\n#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */\n\n/******************* Bit definition for AES_SUSP3R register ******************/\n#define AES_SUSP3R_Pos (0U)\n#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */\n\n/******************* Bit definition for AES_SUSP4R register ******************/\n#define AES_SUSP4R_Pos (0U)\n#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */\n\n/******************* Bit definition for AES_SUSP5R register ******************/\n#define AES_SUSP5R_Pos (0U)\n#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */\n\n/******************* Bit definition for AES_SUSP6R register ******************/\n#define AES_SUSP6R_Pos (0U)\n#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */\n\n/******************* Bit definition for AES_SUSP7R register ******************/\n#define AES_SUSP7R_Pos (0U)\n#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */\n#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */\n\n/******************************************************************************/\n/* */\n/* Analog Comparators (COMP) */\n/* */\n/******************************************************************************/\n/********************** Bit definition for COMP_CSR register ****************/\n#define COMP_CSR_EN_Pos (0U)\n#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */\n#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */\n\n#define COMP_CSR_INMSEL_Pos (4U)\n#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */\n#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */\n#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */\n#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */\n#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */\n#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */\n\n#define COMP_CSR_INPSEL_Pos (8U)\n#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */\n#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */\n\n#define COMP_CSR_POLARITY_Pos (15U)\n#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */\n#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */\n\n#define COMP_CSR_HYST_Pos (16U)\n#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */\n#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */\n#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */\n#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */\n#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */\n\n#define COMP_CSR_BLANKING_Pos (19U)\n#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */\n#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */\n#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */\n#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */\n#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */\n\n#define COMP_CSR_BRGEN_Pos (22U)\n#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */\n#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */\n\n#define COMP_CSR_SCALEN_Pos (23U)\n#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */\n#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */\n\n#define COMP_CSR_VALUE_Pos (30U)\n#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */\n#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */\n\n#define COMP_CSR_LOCK_Pos (31U)\n#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */\n#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */\n\n/******************************************************************************/\n/* */\n/* CORDIC calculation unit */\n/* */\n/******************************************************************************/\n/******************* Bit definition for CORDIC_CSR register *****************/\n#define CORDIC_CSR_FUNC_Pos (0U)\n#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */\n#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */\n#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */\n#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */\n#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */\n#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */\n#define CORDIC_CSR_PRECISION_Pos (4U)\n#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */\n#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */\n#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */\n#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */\n#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */\n#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */\n#define CORDIC_CSR_SCALE_Pos (8U)\n#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */\n#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */\n#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */\n#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */\n#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */\n#define CORDIC_CSR_IEN_Pos (16U)\n#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */\n#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */\n#define CORDIC_CSR_DMAREN_Pos (17U)\n#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */\n#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */\n#define CORDIC_CSR_DMAWEN_Pos (18U)\n#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */\n#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */\n#define CORDIC_CSR_NRES_Pos (19U)\n#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */\n#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */\n#define CORDIC_CSR_NARGS_Pos (20U)\n#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */\n#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */\n#define CORDIC_CSR_RESSIZE_Pos (21U)\n#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */\n#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */\n#define CORDIC_CSR_ARGSIZE_Pos (22U)\n#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */\n#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */\n#define CORDIC_CSR_RRDY_Pos (31U)\n#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */\n#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */\n\n/******************* Bit definition for CORDIC_WDATA register ***************/\n#define CORDIC_WDATA_ARG_Pos (0U)\n#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */\n#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */\n\n/******************* Bit definition for CORDIC_RDATA register ***************/\n#define CORDIC_RDATA_RES_Pos (0U)\n#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */\n#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */\n\n/******************************************************************************/\n/* */\n/* CRC calculation unit */\n/* */\n/******************************************************************************/\n/******************* Bit definition for CRC_DR register *********************/\n#define CRC_DR_DR_Pos (0U)\n#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\n#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\n\n/******************* Bit definition for CRC_IDR register ********************/\n#define CRC_IDR_IDR_Pos (0U)\n#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */\n#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */\n\n/******************** Bit definition for CRC_CR register ********************/\n#define CRC_CR_RESET_Pos (0U)\n#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */\n#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */\n#define CRC_CR_POLYSIZE_Pos (3U)\n#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */\n#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */\n#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */\n#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */\n#define CRC_CR_REV_IN_Pos (5U)\n#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */\n#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */\n#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */\n#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */\n#define CRC_CR_REV_OUT_Pos (7U)\n#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */\n#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */\n\n/******************* Bit definition for CRC_INIT register *******************/\n#define CRC_INIT_INIT_Pos (0U)\n#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */\n#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */\n\n/******************* Bit definition for CRC_POL register ********************/\n#define CRC_POL_POL_Pos (0U)\n#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */\n#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */\n\n/******************************************************************************/\n/* */\n/* CRS Clock Recovery System */\n/******************************************************************************/\n\n/******************* Bit definition for CRS_CR register *********************/\n#define CRS_CR_SYNCOKIE_Pos (0U)\n#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */\n#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */\n#define CRS_CR_SYNCWARNIE_Pos (1U)\n#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */\n#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */\n#define CRS_CR_ERRIE_Pos (2U)\n#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */\n#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */\n#define CRS_CR_ESYNCIE_Pos (3U)\n#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */\n#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */\n#define CRS_CR_CEN_Pos (5U)\n#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */\n#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */\n#define CRS_CR_AUTOTRIMEN_Pos (6U)\n#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */\n#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */\n#define CRS_CR_SWSYNC_Pos (7U)\n#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */\n#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */\n#define CRS_CR_TRIM_Pos (8U)\n#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */\n#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */\n\n/******************* Bit definition for CRS_CFGR register *********************/\n#define CRS_CFGR_RELOAD_Pos (0U)\n#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */\n#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */\n#define CRS_CFGR_FELIM_Pos (16U)\n#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */\n#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */\n\n#define CRS_CFGR_SYNCDIV_Pos (24U)\n#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */\n#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */\n#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */\n#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */\n#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */\n\n#define CRS_CFGR_SYNCSRC_Pos (28U)\n#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */\n#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */\n#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */\n#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */\n\n#define CRS_CFGR_SYNCPOL_Pos (31U)\n#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */\n#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */\n\n/******************* Bit definition for CRS_ISR register *********************/\n#define CRS_ISR_SYNCOKF_Pos (0U)\n#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */\n#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */\n#define CRS_ISR_SYNCWARNF_Pos (1U)\n#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */\n#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */\n#define CRS_ISR_ERRF_Pos (2U)\n#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */\n#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */\n#define CRS_ISR_ESYNCF_Pos (3U)\n#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */\n#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */\n#define CRS_ISR_SYNCERR_Pos (8U)\n#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */\n#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */\n#define CRS_ISR_SYNCMISS_Pos (9U)\n#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */\n#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */\n#define CRS_ISR_TRIMOVF_Pos (10U)\n#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */\n#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */\n#define CRS_ISR_FEDIR_Pos (15U)\n#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */\n#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */\n#define CRS_ISR_FECAP_Pos (16U)\n#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */\n#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */\n\n/******************* Bit definition for CRS_ICR register *********************/\n#define CRS_ICR_SYNCOKC_Pos (0U)\n#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */\n#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */\n#define CRS_ICR_SYNCWARNC_Pos (1U)\n#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */\n#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */\n#define CRS_ICR_ERRC_Pos (2U)\n#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */\n#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */\n#define CRS_ICR_ESYNCC_Pos (3U)\n#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */\n#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */\n\n/******************************************************************************/\n/* */\n/* Digital to Analog Converter */\n/* */\n/******************************************************************************/\n/*\n * @brief Specific device feature definitions (not present on all devices in the STM32G4 series)\n */\n#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */\n\n/******************** Bit definition for DAC_CR register ********************/\n#define DAC_CR_EN1_Pos (0U)\n#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */\n#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/\n#define DAC_CR_CEN1_Pos (14U)\n#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */\n#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/\n\n#define DAC_CR_HFSEL_Pos (15U)\n#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */\n#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!*/\n\n#define DAC_CR_EN2_Pos (16U)\n#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\n#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/\n#define DAC_CR_CEN2_Pos (30U)\n#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */\n#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/\n\n/***************** Bit definition for DAC_SWTRIGR register ******************/\n#define DAC_SWTRIGR_SWTRIG1_Pos (0U)\n#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\n#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!
file_path
stringlengths 20
207
| content
stringlengths 5
3.85M
| size
int64 5
3.85M
| lang
stringclasses 9
values | avg_line_length
float64 1.33
100
| max_line_length
int64 4
993
| alphanum_fraction
float64 0.26
0.93
|
|---|---|---|---|---|---|---|
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp.h | /**
******************************************************************************
* @file stm32g4xx_hal_cryp.h
* @author MCD Application Team
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_CRYP_H
#define STM32G4xx_HAL_CRYP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
#if defined(AES)
/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRYP_Exported_Types CRYP Exported Types
* @{
*/
/**
* @brief CRYP Init Structure definition
*/
typedef struct
{
uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
This parameter can be a value of @ref CRYP_Data_Type */
uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.
128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */
uint32_t *pKey; /*!< The key used for encryption/decryption */
uint32_t *pInitVect; /*!< The initialization vector used also as initialization
counter in CTR mode */
uint32_t Algorithm; /*!< DES/ TDES Algorithm ECB/CBC
AES Algorithm ECB/CBC/CTR/GCM or CCM
This parameter can be a value of @ref CRYP_Algorithm_Mode */
uint32_t *Header; /*!< used only in AES GCM and CCM Algorithm for authentication,
GCM : also known as Additional Authentication Data
CCM : named B1 composed of the associated data length and Associated Data. */
uint32_t HeaderSize; /*!< The size of header buffer */
uint32_t *B0; /*!< B0 is first authentication block used only in AES CCM mode */
uint32_t DataWidthUnit; /*!< Payload Data Width Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
uint32_t HeaderWidthUnit; /*!< Header Width Unit, this parameter can be value of @ref CRYP_Header_Width_Unit*/
uint32_t KeyIVConfigSkip; /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
Vector only once and to skip configuration for consecutive processings.
This parameter can be a value of @ref CRYP_Configuration_Skip */
} CRYP_ConfigTypeDef;
/**
* @brief CRYP State Structure definition
*/
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP BUSY, internal processing is ongoing */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
HAL_CRYP_STATE_SUSPENDED = 0x03U, /*!< CRYP suspended */
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
} HAL_CRYP_STATETypeDef;
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
/**
* @brief HAL CRYP mode suspend definitions
*/
typedef enum
{
HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */
HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */
}HAL_SuspendTypeDef;
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
/**
* @brief CRYP handle Structure definition
*/
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
typedef struct __CRYP_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
{
AES_TypeDef *Instance; /*!< AES Register base address */
CRYP_ConfigTypeDef Init; /*!< CRYP required parameters */
FunctionalState AutoKeyDerivation; /*!< Used only in TinyAES to allow to bypass or not key write-up before decryption.
This parameter can be a value of ENABLE/DISABLE */
uint32_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
uint32_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
__IO uint16_t CrypHeaderCount; /*!< Counter of header data in words */
__IO uint16_t CrypInCount; /*!< Counter of input data in words */
__IO uint16_t CrypOutCount; /*!< Counter of output data in words */
uint16_t Size; /*!< Length of input data */
uint32_t Phase; /*!< CRYP peripheral phase */
DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */
DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */
HAL_LockTypeDef Lock; /*!< CRYP locking object */
__IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */
__IO uint32_t ErrorCode; /*!< CRYP peripheral error code */
uint32_t KeyIVConfig; /*!< CRYP peripheral Key and IV configuration flag, used when
configuration can be skipped */
uint32_t SizesSum; /*!< Sum of successive payloads lengths (in bytes), stored
for a single signature computation after several
messages processing */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Input FIFO transfer completed callback */
void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Output FIFO transfer completed callback */
void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Error callback */
void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp Init callback */
void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp); /*!< CRYP Msp DeInit callback */
#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
__IO HAL_SuspendTypeDef SuspendRequest; /*!< CRYP peripheral suspension request flag */
CRYP_ConfigTypeDef Init_saved; /*!< copy of CRYP required parameters when processing is suspended */
uint32_t *pCrypInBuffPtr_saved; /*!< copy of CRYP input pointer when processing is suspended */
uint32_t *pCrypOutBuffPtr_saved; /*!< copy of CRYP output pointer when processing is suspended */
uint32_t CrypInCount_saved; /*!< copy of CRYP input data counter when processing is suspended */
uint32_t CrypOutCount_saved; /*!< copy of CRYP output data counter when processing is suspended */
uint32_t Phase_saved; /*!< copy of CRYP authentication phase when processing is suspended */
__IO HAL_CRYP_STATETypeDef State_saved; /*!< copy of CRYP peripheral state when processing is suspended */
uint32_t IV_saved[4]; /*!< copy of Initialisation Vector registers */
uint32_t SUSPxR_saved[8]; /*!< copy of suspension registers */
uint32_t CR_saved; /*!< copy of CRYP control register when processing is suspended*/
uint32_t Key_saved[8]; /*!< copy of key registers */
uint16_t Size_saved; /*!< copy of input buffer size */
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
#endif /* USE_HAL_CRYP_SUSPEND_RESUME */
} CRYP_HandleTypeDef;
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition
* @brief HAL CRYP Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_CRYP_MSPINIT_CB_ID = 0x00U, /*!< CRYP MspInit callback ID */
HAL_CRYP_MSPDEINIT_CB_ID = 0x01U, /*!< CRYP MspDeInit callback ID */
HAL_CRYP_INPUT_COMPLETE_CB_ID = 0x02U, /*!< CRYP Input FIFO transfer completed callback ID */
HAL_CRYP_OUTPUT_COMPLETE_CB_ID = 0x03U, /*!< CRYP Output FIFO transfer completed callback ID */
HAL_CRYP_ERROR_CB_ID = 0x04U, /*!< CRYP Error callback ID */
} HAL_CRYP_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition
* @brief HAL CRYP Callback pointer definition
* @{
*/
typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< pointer to a common CRYP callback function */
/**
* @}
*/
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
* @{
*/
/** @defgroup CRYP_Error_Definition CRYP Error Definition
* @{
*/
#define HAL_CRYP_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_CRYP_ERROR_WRITE 0x00000001U /*!< Write error */
#define HAL_CRYP_ERROR_READ 0x00000002U /*!< Read error */
#define HAL_CRYP_ERROR_DMA 0x00000004U /*!< DMA error */
#define HAL_CRYP_ERROR_BUSY 0x00000008U /*!< Busy flag error */
#define HAL_CRYP_ERROR_TIMEOUT 0x00000010U /*!< Timeout error */
#define HAL_CRYP_ERROR_NOT_SUPPORTED 0x00000020U /*!< Not supported mode */
#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U /*!< Sequence are not respected only for GCM or CCM */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
#define HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit
* @{
*/
#define CRYP_DATAWIDTHUNIT_WORD 0x00000000U /*!< By default, size unit is word */
#define CRYP_DATAWIDTHUNIT_BYTE 0x00000001U /*!< By default, size unit is byte */
/**
* @}
*/
/** @defgroup CRYP_Header_Width_Unit CRYP Header Width Unit
* @{
*/
#define CRYP_HEADERWIDTHUNIT_WORD 0x00000000U /*!< By default, header size unit is word */
#define CRYP_HEADERWIDTHUNIT_BYTE 0x00000001U /*!< By default, header size unit is byte */
/**
* @}
*/
/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode
* @{
*/
#define CRYP_AES_ECB 0x00000000U /*!< Electronic codebook chaining algorithm */
#define CRYP_AES_CBC AES_CR_CHMOD_0 /*!< Cipher block chaining algorithm */
#define CRYP_AES_CTR AES_CR_CHMOD_1 /*!< Counter mode chaining algorithm */
#define CRYP_AES_GCM_GMAC (AES_CR_CHMOD_0 | AES_CR_CHMOD_1) /*!< Galois counter mode - Galois message authentication code */
#define CRYP_AES_CCM AES_CR_CHMOD_2 /*!< Counter with Cipher Mode */
/**
* @}
*/
/** @defgroup CRYP_Key_Size CRYP Key Size
* @{
*/
#define CRYP_KEYSIZE_128B 0x00000000U /*!< 128-bit long key */
#define CRYP_KEYSIZE_256B AES_CR_KEYSIZE /*!< 256-bit long key */
/**
* @}
*/
/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
#define CRYP_DATATYPE_32B 0x00000000U /*!< 32-bit data type (no swapping) */
#define CRYP_DATATYPE_16B AES_CR_DATATYPE_0 /*!< 16-bit data type (half-word swapping) */
#define CRYP_DATATYPE_8B AES_CR_DATATYPE_1 /*!< 8-bit data type (byte swapping) */
#define CRYP_DATATYPE_1B AES_CR_DATATYPE /*!< 1-bit data type (bit swapping) */
/**
* @}
*/
/** @defgroup CRYP_Interrupt CRYP Interrupt
* @{
*/
#define CRYP_IT_CCFIE AES_CR_CCFIE /*!< Computation Complete interrupt enable */
#define CRYP_IT_ERRIE AES_CR_ERRIE /*!< Error interrupt enable */
#define CRYP_IT_WRERR AES_SR_WRERR /*!< Write Error */
#define CRYP_IT_RDERR AES_SR_RDERR /*!< Read Error */
#define CRYP_IT_CCF AES_SR_CCF /*!< Computation completed */
/**
* @}
*/
/** @defgroup CRYP_Flags CRYP Flags
* @{
*/
/* status flags */
#define CRYP_FLAG_BUSY AES_SR_BUSY /*!< GCM process suspension forbidden */
#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error */
#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read error */
#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation completed */
/* clearing flags */
#define CRYP_CCF_CLEAR AES_CR_CCFC /*!< Computation Complete Flag Clear */
#define CRYP_ERR_CLEAR AES_CR_ERRC /*!< Error Flag Clear */
/**
* @}
*/
/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
* @{
*/
#define CRYP_KEYIVCONFIG_ALWAYS 0x00000000U /*!< Peripheral Key and IV configuration to do systematically */
#define CRYP_KEYIVCONFIG_ONCE 0x00000001U /*!< Peripheral Key and IV configuration to do only once */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
* @{
*/
/** @brief Reset CRYP handle state
* @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_CRYP_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL;\
(__HANDLE__)->MspDeInitCallback = NULL;\
}while(0U)
#else
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
/**
* @brief Enable/Disable the CRYP peripheral.
* @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= AES_CR_EN)
#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~AES_CR_EN)
/** @brief Check whether the specified CRYP status flag is set or not.
* @param __HANDLE__ specifies the CRYP handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
* @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
* or a key preparation (for AES decryption).
* @arg CRYP_FLAG_IFEM: Input FIFO is empty
* @arg CRYP_FLAG_IFNF: Input FIFO is not full
* @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_FLAG_OFNE: Output FIFO is not empty
* @arg CRYP_FLAG_OFFU: Output FIFO is full
* @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define CRYP_FLAG_MASK 0x0000001FU
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the CRYP pending status flag.
* @param __HANDLE__ specifies the CRYP handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
* @retval None
*/
#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__))
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
* @param __HANDLE__ specifies the CRYP handle.
* @param __INTERRUPT__ CRYP interrupt source to check
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* @retval State of interruption (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Check whether the specified CRYP interrupt is set or not.
* @param __HANDLE__ specifies the CRYP handle.
* @param __INTERRUPT__ specifies the interrupt to check.
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
* @arg @ref CRYP_IT_CCF Computation Complete
* This parameter can be one of the following values for CRYP:
* @arg CRYP_IT_INI: Input FIFO service masked interrupt status
* @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status
* @retval The state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Enable the CRYP interrupt.
* @param __HANDLE__ specifies the CRYP handle.
* @param __INTERRUPT__ CRYP Interrupt.
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
* @retval None
*/
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
* @param __HANDLE__ specifies the CRYP handle.
* @param __INTERRUPT__ CRYP Interrupt.
* This parameter can be one of the following values for TinyAES:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
* This parameter can be one of the following values for CRYP:
* @ CRYP_IT_INI : Input FIFO service interrupt mask.
* @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.
* @retval None
*/
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/**
* @}
*/
/* Include CRYP HAL Extended module */
#include "stm32g4xx_hal_cryp_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
* @{
*/
/** @addtogroup CRYP_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
#if (USE_HAL_CRYP_SUSPEND_RESUME == 1U)
void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp);
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp);
#endif /* defined (USE_HAL_CRYP_SUSPEND_RESUME) */
/**
* @}
*/
/** @addtogroup CRYP_Exported_Functions_Group2
* @{
*/
/* encryption/decryption ***********************************/
HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);
/**
* @}
*/
/** @addtogroup CRYP_Exported_Functions_Group3
* @{
*/
/* Interrupt Handler functions **********************************************/
void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRYP_Private_Macros CRYP Private Macros
* @{
*/
/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters
* @{
*/
#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_AES_ECB) || \
((ALGORITHM) == CRYP_AES_CBC) || \
((ALGORITHM) == CRYP_AES_CTR) || \
((ALGORITHM) == CRYP_AES_GCM_GMAC)|| \
((ALGORITHM) == CRYP_AES_CCM))
#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B) || \
((KEYSIZE) == CRYP_KEYSIZE_256B))
#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B) || \
((DATATYPE) == CRYP_DATATYPE_16B) || \
((DATATYPE) == CRYP_DATATYPE_8B) || \
((DATATYPE) == CRYP_DATATYPE_1B))
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
(((((ALGO) == CRYP_AES_CTR)) && \
((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
(((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
(((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \
((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Constants CRYP Private Constants
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup CRYP_Private_Defines CRYP Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Variables CRYP Private Variables
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYP_Private_Functions CRYP Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
#endif /* AES */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_CRYP_H */
| 25,987 | C | 39.229102 | 143 | 0.563436 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sram.h | /**
******************************************************************************
* @file stm32g4xx_hal_sram.h
* @author MCD Application Team
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SRAM_H
#define STM32G4xx_HAL_SRAM_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FMC_BANK1)
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_ll_fmc.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SRAM
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup SRAM_Exported_Types SRAM Exported Types
* @{
*/
/**
* @brief HAL SRAM State structures definition
*/
typedef enum
{
HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */
HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */
HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */
HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */
HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */
} HAL_SRAM_StateTypeDef;
/**
* @brief SRAM handle Structure definition
*/
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
typedef struct __SRAM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
{
FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */
HAL_LockTypeDef Lock; /*!< SRAM locking object */
__IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */
DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */
void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */
void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */
void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
} SRAM_HandleTypeDef;
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SRAM Callback ID enumeration definition
*/
typedef enum
{
HAL_SRAM_MSP_INIT_CB_ID = 0x00U, /*!< SRAM MspInit Callback ID */
HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */
HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */
HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */
} HAL_SRAM_CallbackIDTypeDef;
/**
* @brief HAL SRAM Callback pointer definition
*/
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
* @{
*/
/** @brief Reset SRAM handle state
* @param __HANDLE__ SRAM handle
* @retval None
*/
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
* @{
*/
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing,
FMC_NORSRAM_TimingTypeDef *ExtTiming);
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
uint32_t BufferSize);
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
uint32_t BufferSize);
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
/* SRAM callback registering/unregistering */
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
pSRAM_DmaCallbackTypeDef pCallback);
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
* @{
*/
/* SRAM Control functions ****************************************************/
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* SRAM State functions ******************************************************/
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SRAM_H */
| 8,633 | C | 36.055794 | 121 | 0.555195 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma.h | /**
******************************************************************************
* @file stm32g4xx_hal_dma.h
* @author MCD Application Team
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_HAL_DMA_H
#define __STM32G4xx_HAL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup DMA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMA_Exported_Types DMA Exported Types
* @{
*/
/**
* @brief DMA Configuration Structure definition
*/
typedef struct
{
uint32_t Request; /*!< Specifies the request selected for the specified channel.
This parameter can be a value of @ref DMA_request */
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_Data_transfer_direction */
uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
This parameter can be a value of @ref DMA_Memory_incremented_mode */
uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_Peripheral_data_size */
uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
This parameter can be a value of @ref DMA_Memory_data_size */
uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_mode
@note The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_Priority_level */
} DMA_InitTypeDef;
/**
* @brief HAL DMA State structures definition
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
} HAL_DMA_StateTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */
} HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Callback ID structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */
} HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
typedef struct __DMA_HandleTypeDef
{
DMA_Channel_TypeDef *Instance; /*!< Register base address */
DMA_InitTypeDef Init; /*!< DMA communication parameters */
HAL_LockTypeDef Lock; /*!< DMA locking object */
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA Half transfer complete callback */
void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */
uint32_t ChannelIndex; /*!< DMA Channel Index */
DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */
DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */
uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */
DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */
DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */
uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */
} DMA_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_Error_Code DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
#define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
#define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */
#define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */
/**
* @}
*/
/** @defgroup DMA_request DMA request
* @{
*/
#define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */
#define DMA_REQUEST_GENERATOR0 1U
#define DMA_REQUEST_GENERATOR1 2U
#define DMA_REQUEST_GENERATOR2 3U
#define DMA_REQUEST_GENERATOR3 4U
#define DMA_REQUEST_ADC1 5U
#define DMA_REQUEST_DAC1_CHANNEL1 6U
#define DMA_REQUEST_DAC1_CHANNEL2 7U
#define DMA_REQUEST_TIM6_UP 8U
#define DMA_REQUEST_TIM7_UP 9U
#define DMA_REQUEST_SPI1_RX 10U
#define DMA_REQUEST_SPI1_TX 11U
#define DMA_REQUEST_SPI2_RX 12U
#define DMA_REQUEST_SPI2_TX 13U
#define DMA_REQUEST_SPI3_RX 14U
#define DMA_REQUEST_SPI3_TX 15U
#define DMA_REQUEST_I2C1_RX 16U
#define DMA_REQUEST_I2C1_TX 17U
#define DMA_REQUEST_I2C2_RX 18U
#define DMA_REQUEST_I2C2_TX 19U
#define DMA_REQUEST_I2C3_RX 20U
#define DMA_REQUEST_I2C3_TX 21U
#if defined (I2C4)
#define DMA_REQUEST_I2C4_RX 22U
#define DMA_REQUEST_I2C4_TX 23U
#endif /* I2C4 */
#define DMA_REQUEST_USART1_RX 24U
#define DMA_REQUEST_USART1_TX 25U
#define DMA_REQUEST_USART2_RX 26U
#define DMA_REQUEST_USART2_TX 27U
#define DMA_REQUEST_USART3_RX 28U
#define DMA_REQUEST_USART3_TX 29U
#define DMA_REQUEST_UART4_RX 30U
#define DMA_REQUEST_UART4_TX 31U
#if defined (UART5)
#define DMA_REQUEST_UART5_RX 32U
#define DMA_REQUEST_UART5_TX 33U
#endif /* UART5 */
#define DMA_REQUEST_LPUART1_RX 34U
#define DMA_REQUEST_LPUART1_TX 35U
#define DMA_REQUEST_ADC2 36U
#if defined (ADC3)
#define DMA_REQUEST_ADC3 37U
#endif /* ADC3 */
#if defined (ADC4)
#define DMA_REQUEST_ADC4 38U
#endif /* ADC4 */
#if defined (ADC5)
#define DMA_REQUEST_ADC5 39U
#endif /* ADC5 */
#if defined (QUADSPI)
#define DMA_REQUEST_QUADSPI 40U
#endif /* QUADSPI */
#if defined (DAC2)
#define DMA_REQUEST_DAC2_CHANNEL1 41U
#endif /* DAC2 */
#define DMA_REQUEST_TIM1_CH1 42U
#define DMA_REQUEST_TIM1_CH2 43U
#define DMA_REQUEST_TIM1_CH3 44U
#define DMA_REQUEST_TIM1_CH4 45U
#define DMA_REQUEST_TIM1_UP 46U
#define DMA_REQUEST_TIM1_TRIG 47U
#define DMA_REQUEST_TIM1_COM 48U
#define DMA_REQUEST_TIM8_CH1 49U
#define DMA_REQUEST_TIM8_CH2 50U
#define DMA_REQUEST_TIM8_CH3 51U
#define DMA_REQUEST_TIM8_CH4 52U
#define DMA_REQUEST_TIM8_UP 53U
#define DMA_REQUEST_TIM8_TRIG 54U
#define DMA_REQUEST_TIM8_COM 55U
#define DMA_REQUEST_TIM2_CH1 56U
#define DMA_REQUEST_TIM2_CH2 57U
#define DMA_REQUEST_TIM2_CH3 58U
#define DMA_REQUEST_TIM2_CH4 59U
#define DMA_REQUEST_TIM2_UP 60U
#define DMA_REQUEST_TIM3_CH1 61U
#define DMA_REQUEST_TIM3_CH2 62U
#define DMA_REQUEST_TIM3_CH3 63U
#define DMA_REQUEST_TIM3_CH4 64U
#define DMA_REQUEST_TIM3_UP 65U
#define DMA_REQUEST_TIM3_TRIG 66U
#define DMA_REQUEST_TIM4_CH1 67U
#define DMA_REQUEST_TIM4_CH2 68U
#define DMA_REQUEST_TIM4_CH3 69U
#define DMA_REQUEST_TIM4_CH4 70U
#define DMA_REQUEST_TIM4_UP 71U
#if defined (TIM5)
#define DMA_REQUEST_TIM5_CH1 72U
#define DMA_REQUEST_TIM5_CH2 73U
#define DMA_REQUEST_TIM5_CH3 74U
#define DMA_REQUEST_TIM5_CH4 75U
#define DMA_REQUEST_TIM5_UP 76U
#define DMA_REQUEST_TIM5_TRIG 77U
#endif /* TIM5 */
#define DMA_REQUEST_TIM15_CH1 78U
#define DMA_REQUEST_TIM15_UP 79U
#define DMA_REQUEST_TIM15_TRIG 80U
#define DMA_REQUEST_TIM15_COM 81U
#define DMA_REQUEST_TIM16_CH1 82U
#define DMA_REQUEST_TIM16_UP 83U
#define DMA_REQUEST_TIM17_CH1 84U
#define DMA_REQUEST_TIM17_UP 85U
#if defined (TIM20)
#define DMA_REQUEST_TIM20_CH1 86U
#define DMA_REQUEST_TIM20_CH2 87U
#define DMA_REQUEST_TIM20_CH3 88U
#define DMA_REQUEST_TIM20_CH4 89U
#define DMA_REQUEST_TIM20_UP 90U
#endif /* TIM20 */
#define DMA_REQUEST_AES_IN 91U
#define DMA_REQUEST_AES_OUT 92U
#if defined (TIM20)
#define DMA_REQUEST_TIM20_TRIG 93U
#define DMA_REQUEST_TIM20_COM 94U
#endif /* TIM20 */
#if defined (HRTIM1)
#define DMA_REQUEST_HRTIM1_M 95U
#define DMA_REQUEST_HRTIM1_A 96U
#define DMA_REQUEST_HRTIM1_B 97U
#define DMA_REQUEST_HRTIM1_C 98U
#define DMA_REQUEST_HRTIM1_D 99U
#define DMA_REQUEST_HRTIM1_E 100U
#define DMA_REQUEST_HRTIM1_F 101U
#endif /* HRTIM1 */
#define DMA_REQUEST_DAC3_CHANNEL1 102U
#define DMA_REQUEST_DAC3_CHANNEL2 103U
#if defined (DAC4)
#define DMA_REQUEST_DAC4_CHANNEL1 104U
#define DMA_REQUEST_DAC4_CHANNEL2 105U
#endif /* DAC4 */
#if defined (SPI4)
#define DMA_REQUEST_SPI4_RX 106U
#define DMA_REQUEST_SPI4_TX 107U
#endif /* SPI4 */
#define DMA_REQUEST_SAI1_A 108U
#define DMA_REQUEST_SAI1_B 109U
#define DMA_REQUEST_FMAC_READ 110U
#define DMA_REQUEST_FMAC_WRITE 111U
#define DMA_REQUEST_CORDIC_READ 112U
#define DMA_REQUEST_CORDIC_WRITE 113U
#define DMA_REQUEST_UCPD1_RX 114U
#define DMA_REQUEST_UCPD1_TX 115U
/**
* @}
*/
/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */
#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */
#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
#define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
#define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
#define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
#define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_mode DMA mode
* @{
*/
#define DMA_NORMAL 0x00000000U /*!< Normal mode */
#define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */
/**
* @}
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @{
*/
#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
#define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
#define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */
/**
* @}
*/
/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
* @{
*/
#define DMA_IT_TC DMA_CCR_TCIE
#define DMA_IT_HT DMA_CCR_HTIE
#define DMA_IT_TE DMA_CCR_TEIE
/**
* @}
*/
/** @defgroup DMA_flag_definitions DMA flag definitions
* @{
*/
#define DMA_FLAG_GL1 0x00000001U
#define DMA_FLAG_TC1 0x00000002U
#define DMA_FLAG_HT1 0x00000004U
#define DMA_FLAG_TE1 0x00000008U
#define DMA_FLAG_GL2 0x00000010U
#define DMA_FLAG_TC2 0x00000020U
#define DMA_FLAG_HT2 0x00000040U
#define DMA_FLAG_TE2 0x00000080U
#define DMA_FLAG_GL3 0x00000100U
#define DMA_FLAG_TC3 0x00000200U
#define DMA_FLAG_HT3 0x00000400U
#define DMA_FLAG_TE3 0x00000800U
#define DMA_FLAG_GL4 0x00001000U
#define DMA_FLAG_TC4 0x00002000U
#define DMA_FLAG_HT4 0x00004000U
#define DMA_FLAG_TE4 0x00008000U
#define DMA_FLAG_GL5 0x00010000U
#define DMA_FLAG_TC5 0x00020000U
#define DMA_FLAG_HT5 0x00040000U
#define DMA_FLAG_TE5 0x00080000U
#define DMA_FLAG_GL6 0x00100000U
#define DMA_FLAG_TC6 0x00200000U
#define DMA_FLAG_HT6 0x00400000U
#define DMA_FLAG_TE6 0x00800000U
#if defined (DMA1_Channel7)
#define DMA_FLAG_GL7 0x01000000U
#define DMA_FLAG_TC7 0x02000000U
#define DMA_FLAG_HT7 0x04000000U
#define DMA_FLAG_TE7 0x08000000U
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
#define DMA_FLAG_GL8 0x10000000U
#define DMA_FLAG_TC8 0x20000000U
#define DMA_FLAG_HT8 0x40000000U
#define DMA_FLAG_TE8 0x80000000U
#endif /* DMA1_Channel8 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DMA_Exported_Macros DMA Exported Macros
* @{
*/
/** @brief Reset DMA handle state.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Enable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
/**
* @brief Disable the specified DMA Channel.
* @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
/* Interrupt & Flag management */
/**
* @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TC7 :\
DMA_FLAG_TC8)
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
DMA_FLAG_TC6)
#endif /* DMA1_Channel8 */
/**
* @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_HT7 :\
DMA_FLAG_HT8)
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
DMA_FLAG_HT6)
#endif /* DMA1_Channel8 */
/**
* @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_FLAG_TE7 :\
DMA_FLAG_TE8)
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
DMA_FLAG_TE6)
#endif /* DMA1_Channel8 */
/**
* @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_ISR_GIF7 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel7))? DMA_ISR_GIF7 :\
DMA_ISR_GIF8)
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
DMA_ISR_GIF6)
#endif /* DMA1_Channel8 */
/**
* @brief Get the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx Transfer complete flag
* @arg DMA_FLAG_HTx Half transfer complete flag
* @arg DMA_FLAG_TEx Transfer error flag
* @arg DMA_FLAG_GLx Global interrupt flag
* Where x can be from 1 to 8 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET).
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
#elif defined (DMA1_Channel6)
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
#endif /* DMA1_Channel8 */
/**
* @brief Clear the DMA Channel pending flags.
* @param __HANDLE__ DMA handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCx Transfer complete flag
* @arg DMA_FLAG_HTx Half transfer complete flag
* @arg DMA_FLAG_TEx Transfer error flag
* @arg DMA_FLAG_GLx Global interrupt flag
* Where x can be from 1 to 8 to select the DMA Channel x flag.
* @retval None
*/
#if defined (DMA1_Channel8)
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel8))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
#else
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel6))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
#endif /* DMA1_Channel8 */
/**
* @brief Enable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC Transfer complete interrupt mask
* @arg DMA_IT_HT Half transfer complete interrupt mask
* @arg DMA_IT_TE Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
/**
* @brief Disable the specified DMA Channel interrupts.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC Transfer complete interrupt mask
* @arg DMA_IT_HT Half transfer complete interrupt mask
* @arg DMA_IT_TE Transfer error interrupt mask
* @retval None
*/
#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified DMA Channel interrupt is enabled or not.
* @param __HANDLE__ DMA handle
* @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC Transfer complete interrupt mask
* @arg DMA_IT_HT Half transfer complete interrupt mask
* @arg DMA_IT_TE Transfer error interrupt mask
* @retval The state of DMA_IT (SET or RESET).
*/
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/**
* @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__ DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer.
*/
#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
/**
* @}
*/
/* Include DMA HAL Extension module */
#include "stm32g4xx_hal_dma_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMA_Exported_Functions
* @{
*/
/** @addtogroup DMA_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel,
uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup DMA_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA_Private_Macros DMA Private Macros
* @{
*/
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x40000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
((STATE) == DMA_MINC_DISABLE))
#define IS_DMA_ALL_REQUEST(REQUEST) ((REQUEST) <= DMA_REQUEST_UCPD1_TX)
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
((SIZE) == DMA_PDATAALIGN_WORD))
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
((SIZE) == DMA_MDATAALIGN_WORD ))
#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
((MODE) == DMA_CIRCULAR))
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
((PRIORITY) == DMA_PRIORITY_HIGH) || \
((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_HAL_DMA_H */
| 36,647 | C | 41.963658 | 152 | 0.556417 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cortex.h | /**
******************************************************************************
* @file stm32g4xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_HAL_CORTEX_H
#define __STM32G4xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @brief CORTEX HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @brief MPU Region initialization structure
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the number of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint8_t Size; /*!< Specifies the size of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Size */
uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint8_t TypeExtField; /*!< Specifies the TEX field level.
This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */
uint8_t AccessPermission; /*!< Specifies the region access permission type.
This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected.
This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */
uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */
}MPU_Region_InitTypeDef;
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bit for pre-emption priority,
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bit for pre-emption priority,
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority,
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority,
1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority,
0 bit for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
#define SYSTICK_CLKSOURCE_HCLK 0x00000004U
/**
* @}
*/
#if (__MPU_PRESENT == 1)
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
#define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk)
#define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk)
#define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
/**
* @}
*/
/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define MPU_TEX_LEVEL4 ((uint8_t)0x04)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and Configuration functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
* @brief Cortex control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
#if (__MPU_PRESENT == 1)
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if (__MPU_PRESENT == 1)
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
((STATE) == MPU_ACCESS_NOT_CACHEABLE))
#define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
((TYPE) == MPU_TEX_LEVEL1) || \
((TYPE) == MPU_TEX_LEVEL2) || \
((TYPE) == MPU_TEX_LEVEL4))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_PRIV_RW_URO) || \
((TYPE) == MPU_REGION_FULL_ACCESS) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_PRIV_RO_URO))
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
((SIZE) == MPU_REGION_SIZE_64B) || \
((SIZE) == MPU_REGION_SIZE_128B) || \
((SIZE) == MPU_REGION_SIZE_256B) || \
((SIZE) == MPU_REGION_SIZE_512B) || \
((SIZE) == MPU_REGION_SIZE_1KB) || \
((SIZE) == MPU_REGION_SIZE_2KB) || \
((SIZE) == MPU_REGION_SIZE_4KB) || \
((SIZE) == MPU_REGION_SIZE_8KB) || \
((SIZE) == MPU_REGION_SIZE_16KB) || \
((SIZE) == MPU_REGION_SIZE_32KB) || \
((SIZE) == MPU_REGION_SIZE_64KB) || \
((SIZE) == MPU_REGION_SIZE_128KB) || \
((SIZE) == MPU_REGION_SIZE_256KB) || \
((SIZE) == MPU_REGION_SIZE_512KB) || \
((SIZE) == MPU_REGION_SIZE_1MB) || \
((SIZE) == MPU_REGION_SIZE_2MB) || \
((SIZE) == MPU_REGION_SIZE_4MB) || \
((SIZE) == MPU_REGION_SIZE_8MB) || \
((SIZE) == MPU_REGION_SIZE_16MB) || \
((SIZE) == MPU_REGION_SIZE_32MB) || \
((SIZE) == MPU_REGION_SIZE_64MB) || \
((SIZE) == MPU_REGION_SIZE_128MB) || \
((SIZE) == MPU_REGION_SIZE_256MB) || \
((SIZE) == MPU_REGION_SIZE_512MB) || \
((SIZE) == MPU_REGION_SIZE_1GB) || \
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_HAL_CORTEX_H */
| 17,395 | C | 40.419048 | 134 | 0.488704 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pwr.h | /**
******************************************************************************
* @file stm32g4xx_hal_pwr.h
* @author MCD Application Team
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_PWR_H
#define STM32G4xx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
This parameter can be a value of @ref PWR_PVD_detection_level. */
uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode. */
}PWR_PVDTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
* @{
*/
#define PWR_PVDLEVEL_0 PWR_CR2_PLS_LEV0 /*!< PVD threshold around 2.0 V */
#define PWR_PVDLEVEL_1 PWR_CR2_PLS_LEV1 /*!< PVD threshold around 2.2 V */
#define PWR_PVDLEVEL_2 PWR_CR2_PLS_LEV2 /*!< PVD threshold around 2.4 V */
#define PWR_PVDLEVEL_3 PWR_CR2_PLS_LEV3 /*!< PVD threshold around 2.5 V */
#define PWR_PVDLEVEL_4 PWR_CR2_PLS_LEV4 /*!< PVD threshold around 2.6 V */
#define PWR_PVDLEVEL_5 PWR_CR2_PLS_LEV5 /*!< PVD threshold around 2.8 V */
#define PWR_PVDLEVEL_6 PWR_CR2_PLS_LEV6 /*!< PVD threshold around 2.9 V */
#define PWR_PVDLEVEL_7 PWR_CR2_PLS_LEV7 /*!< External input analog voltage (compared internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode PWR PVD interrupt and event mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< Basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR regulator mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) /*!< Regulator in main mode */
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPR /*!< Regulator in low-power mode */
/**
* @}
*/
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Sleep mode */
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Sleep mode */
/**
* @}
*/
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01) /*!< Wait For Interruption instruction to enter Stop mode */
#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /*!< Wait For Event instruction to enter Stop mode */
/**
* @}
*/
/** @defgroup PWR_PVD_EXTI_LINE PWR PVD external interrupt line
* @{
*/
#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @}
*/
/** @defgroup PWR_PVD_EVENT_LINE PWR PVD event line
* @{
*/
#define PWR_EVENT_LINE_PVD ((uint32_t)0x00010000) /*!< Event line 16 Connected to the PVD Event Line */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros
* @{
*/
/** @brief Check whether or not a specific PWR flag is set.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
* was received from the WKUP pin 1.
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
* was received from the WKUP pin 2.
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
* was received from the WKUP pin 3.
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
* was received from the WKUP pin 4.
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
* was received from the WKUP pin 5.
* @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
* entered StandBy mode.
* @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
* the internal wakeup line.
* @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the
* low-power regulator is ready.
* @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the
* regulator is ready in main mode or is in low-power mode.
* @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready
* in the selected voltage range or is still changing to the required voltage level.
* @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
* below or above the selected PVD threshold.
@if PWR_CR2_PVME1
* @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
* is below or above PVM1 threshold (applicable when USB feature is supported).
@endif
@if PWR_CR2_PVME2
* @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
* is below or above PVM2 threshold (applicable when VDDIO2 is present on device).
@endif
* @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
* is below or above PVM3 threshold.
* @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
* is below or above PVM4 threshold.
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_PWR_GET_FLAG(__FLAG__) ( ((((uint8_t)(__FLAG__)) >> 5U) == 1) ?\
(PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
(PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
/** @brief Clear a specific PWR flag.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
* was received from the WKUP pin 1.
* @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
* was received from the WKUP pin 2.
* @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
* was received from the WKUP pin 3.
* @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
* was received from the WKUP pin 4.
* @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
* was received from the WKUP pin 5.
* @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
* @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
* entered Standby mode.
* @retval None
*/
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
(PWR->SCR = (__FLAG__)) :\
(PWR->SCR = (1U << ((__FLAG__) & 31U))) )
/**
* @brief Enable the PVD Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Event Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
/**
* @brief Disable the PVD Event Line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/**
* @brief Check whether or not the PVD EXTI interrupt flag is set.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR1 & PWR_EXTI_LINE_PVD)
/**
* @brief Clear the PVD EXTI interrupt flag.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup PWR_Private_Macros PWR Private Macros
* @{
*/
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_NORMAL) ||\
((MODE) == PWR_PVD_MODE_IT_RISING) ||\
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
/**
* @}
*/
/* Include PWR HAL Extended module */
#include "stm32g4xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions PWR Exported Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
/* WakeUp pins configuration functions ****************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low Power modes configuration functions ************************************/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
void HAL_PWR_PVDCallback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_PWR_H */
| 15,118 | C | 35.696602 | 143 | 0.562839 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi.h | /**
******************************************************************************
* @file stm32g4xx_hal_spi.h
* @author MCD Application Team
* @brief Header file of SPI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SPI_H
#define STM32G4xx_HAL_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SPI_Exported_Types SPI Exported Types
* @{
*/
/**
* @brief SPI Configuration Structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_Mode */
uint32_t Direction; /*!< Specifies the SPI bidirectional mode state.
This parameter can be a value of @ref SPI_Direction */
uint32_t DataSize; /*!< Specifies the SPI data size.
This parameter can be a value of @ref SPI_Data_Size */
uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
This parameter can be a value of @ref SPI_TI_mode */
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_CRC_Calculation */
uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */
uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation.
CRC Length is only used with Data8 and Data16, not other data size
This parameter can be a value of @ref SPI_CRC_length */
uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not .
This parameter can be a value of @ref SPI_NSSP_Mode
This mode is activated by the NSSP bit in the SPIx_CR2 register and
it takes effect only if the SPI interface is configured as Motorola SPI
master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
CPOL setting is ignored).. */
} SPI_InitTypeDef;
/**
* @brief HAL SPI State structure definition
*/
typedef enum
{
HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */
HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */
HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */
} HAL_SPI_StateTypeDef;
/**
* @brief SPI handle Structure definition
*/
typedef struct __SPI_HandleTypeDef
{
SPI_TypeDef *Instance; /*!< SPI registers base address */
SPI_InitTypeDef Init; /*!< SPI communication parameters */
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
__IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */
uint16_t RxXferSize; /*!< SPI Rx Transfer size */
__IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */
uint32_t CRCSize; /*!< SPI CRC size used for the transfer */
void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */
void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */
DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */
__IO uint32_t ErrorCode; /*!< SPI Error code */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */
void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */
void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */
void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */
void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */
void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */
void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */
void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */
void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
} SPI_HandleTypeDef;
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
/**
* @brief HAL SPI Callback ID enumeration definition
*/
typedef enum
{
HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */
HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */
HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */
HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */
HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */
HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */
HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */
HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */
HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */
HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */
} HAL_SPI_CallbackIDTypeDef;
/**
* @brief HAL SPI Callback pointer definition
*/
typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_Error_Code SPI Error Code
* @{
*/
#define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */
#define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */
#define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */
#define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */
#define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
#define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SPI_Mode SPI Mode
* @{
*/
#define SPI_MODE_SLAVE (0x00000000U)
#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
/**
* @}
*/
/** @defgroup SPI_Direction SPI Direction Mode
* @{
*/
#define SPI_DIRECTION_2LINES (0x00000000U)
#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
/**
* @}
*/
/** @defgroup SPI_Data_Size SPI Data Size
* @{
*/
#define SPI_DATASIZE_4BIT (0x00000300U)
#define SPI_DATASIZE_5BIT (0x00000400U)
#define SPI_DATASIZE_6BIT (0x00000500U)
#define SPI_DATASIZE_7BIT (0x00000600U)
#define SPI_DATASIZE_8BIT (0x00000700U)
#define SPI_DATASIZE_9BIT (0x00000800U)
#define SPI_DATASIZE_10BIT (0x00000900U)
#define SPI_DATASIZE_11BIT (0x00000A00U)
#define SPI_DATASIZE_12BIT (0x00000B00U)
#define SPI_DATASIZE_13BIT (0x00000C00U)
#define SPI_DATASIZE_14BIT (0x00000D00U)
#define SPI_DATASIZE_15BIT (0x00000E00U)
#define SPI_DATASIZE_16BIT (0x00000F00U)
/**
* @}
*/
/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
* @{
*/
#define SPI_POLARITY_LOW (0x00000000U)
#define SPI_POLARITY_HIGH SPI_CR1_CPOL
/**
* @}
*/
/** @defgroup SPI_Clock_Phase SPI Clock Phase
* @{
*/
#define SPI_PHASE_1EDGE (0x00000000U)
#define SPI_PHASE_2EDGE SPI_CR1_CPHA
/**
* @}
*/
/** @defgroup SPI_Slave_Select_management SPI Slave Select Management
* @{
*/
#define SPI_NSS_SOFT SPI_CR1_SSM
#define SPI_NSS_HARD_INPUT (0x00000000U)
#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
/**
* @}
*/
/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
* @{
*/
#define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP
#define SPI_NSS_PULSE_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
* @{
*/
#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
/**
* @}
*/
/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
* @{
*/
#define SPI_FIRSTBIT_MSB (0x00000000U)
#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
/**
* @}
*/
/** @defgroup SPI_TI_mode SPI TI Mode
* @{
*/
#define SPI_TIMODE_DISABLE (0x00000000U)
#define SPI_TIMODE_ENABLE SPI_CR2_FRF
/**
* @}
*/
/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
* @{
*/
#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
/**
* @}
*/
/** @defgroup SPI_CRC_length SPI CRC Length
* @{
* This parameter can be one of the following values:
* SPI_CRC_LENGTH_DATASIZE: aligned with the data size
* SPI_CRC_LENGTH_8BIT : CRC 8bit
* SPI_CRC_LENGTH_16BIT : CRC 16bit
*/
#define SPI_CRC_LENGTH_DATASIZE (0x00000000U)
#define SPI_CRC_LENGTH_8BIT (0x00000001U)
#define SPI_CRC_LENGTH_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
* @{
* This parameter can be one of the following values:
* SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
* RXNE event is generated if the FIFO
* level is greater or equal to 1/4(8-bits).
* SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
* level is greater or equal to 1/2(16 bits). */
#define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH
#define SPI_RXFIFO_THRESHOLD_HF (0x00000000U)
/**
* @}
*/
/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
* @{
*/
#define SPI_IT_TXE SPI_CR2_TXEIE
#define SPI_IT_RXNE SPI_CR2_RXNEIE
#define SPI_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
/** @defgroup SPI_Flags_definition SPI Flags Definition
* @{
*/
#define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */
#define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */
#define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */
#define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */
#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
| SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
/**
* @}
*/
/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
* @{
*/
#define SPI_FTLVL_EMPTY (0x00000000U)
#define SPI_FTLVL_QUARTER_FULL (0x00000800U)
#define SPI_FTLVL_HALF_FULL (0x00001000U)
#define SPI_FTLVL_FULL (0x00001800U)
/**
* @}
*/
/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
* @{
*/
#define SPI_FRLVL_EMPTY (0x00000000U)
#define SPI_FRLVL_QUARTER_FULL (0x00000200U)
#define SPI_FRLVL_HALF_FULL (0x00000400U)
#define SPI_FRLVL_FULL (0x00000600U)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SPI_Exported_Macros SPI Exported Macros
* @{
*/
/** @brief Reset SPI handle state.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Disable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI handle.
* This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
/** @brief Check whether the specified SPI interrupt source is enabled or not.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
* @arg SPI_FLAG_CRCERR: CRC error flag
* @arg SPI_FLAG_MODF: Mode fault flag
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
* @arg SPI_FLAG_FRE: Frame format error flag
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the SPI CRCERR pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
/** @brief Clear the SPI MODF pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg_modf = 0x00U; \
tmpreg_modf = (__HANDLE__)->Instance->SR; \
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
UNUSED(tmpreg_modf); \
} while(0U)
/** @brief Clear the SPI OVR pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg_ovr = 0x00U; \
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
} while(0U)
/** @brief Clear the SPI FRE pending flag.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg_fre = 0x00U; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \
}while(0U)
/** @brief Enable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/** @brief Disable the SPI peripheral.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SPI_Private_Macros SPI Private Macros
* @{
*/
/** @brief Set the SPI transmit-only mode.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Set the SPI receive-only mode.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
/** @brief Reset the CRC calculation of the SPI.
* @param __HANDLE__ specifies the SPI Handle.
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
* @retval None
*/
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of SPI SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SPI_FLAG_RXNE: Receive buffer not empty flag
* @arg SPI_FLAG_TXE: Transmit buffer empty flag
* @arg SPI_FLAG_CRCERR: CRC error flag
* @arg SPI_FLAG_MODF: Mode fault flag
* @arg SPI_FLAG_OVR: Overrun flag
* @arg SPI_FLAG_BSY: Busy flag
* @arg SPI_FLAG_FRE: Frame format error flag
* @arg SPI_FLAG_FTLVL: SPI fifo transmission level
* @arg SPI_FLAG_FRLVL: SPI fifo reception level
* @retval SET or RESET.
*/
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of SPI CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg SPI_IT_TXE: Tx buffer empty interrupt enable
* @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
* @arg SPI_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
(__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if SPI Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Mode.
* This parameter can be a value of @ref SPI_Mode
* @retval None
*/
#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
((__MODE__) == SPI_MODE_MASTER))
/** @brief Checks if SPI Direction Mode parameter is in allowed range.
* @param __MODE__ specifies the SPI Direction Mode.
* This parameter can be a value of @ref SPI_Direction
* @retval None
*/
#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
((__MODE__) == SPI_DIRECTION_1LINE))
/** @brief Checks if SPI Direction Mode parameter is 2 lines.
* @param __MODE__ specifies the SPI Direction Mode.
* @retval None
*/
#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines.
* @param __MODE__ specifies the SPI Direction Mode.
* @retval None
*/
#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
((__MODE__) == SPI_DIRECTION_1LINE))
/** @brief Checks if SPI Data Size parameter is in allowed range.
* @param __DATASIZE__ specifies the SPI Data Size.
* This parameter can be a value of @ref SPI_Data_Size
* @retval None
*/
#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
((__DATASIZE__) == SPI_DATASIZE_15BIT) || \
((__DATASIZE__) == SPI_DATASIZE_14BIT) || \
((__DATASIZE__) == SPI_DATASIZE_13BIT) || \
((__DATASIZE__) == SPI_DATASIZE_12BIT) || \
((__DATASIZE__) == SPI_DATASIZE_11BIT) || \
((__DATASIZE__) == SPI_DATASIZE_10BIT) || \
((__DATASIZE__) == SPI_DATASIZE_9BIT) || \
((__DATASIZE__) == SPI_DATASIZE_8BIT) || \
((__DATASIZE__) == SPI_DATASIZE_7BIT) || \
((__DATASIZE__) == SPI_DATASIZE_6BIT) || \
((__DATASIZE__) == SPI_DATASIZE_5BIT) || \
((__DATASIZE__) == SPI_DATASIZE_4BIT))
/** @brief Checks if SPI Serial clock steady state parameter is in allowed range.
* @param __CPOL__ specifies the SPI serial clock steady state.
* This parameter can be a value of @ref SPI_Clock_Polarity
* @retval None
*/
#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
((__CPOL__) == SPI_POLARITY_HIGH))
/** @brief Checks if SPI Clock Phase parameter is in allowed range.
* @param __CPHA__ specifies the SPI Clock Phase.
* This parameter can be a value of @ref SPI_Clock_Phase
* @retval None
*/
#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
((__CPHA__) == SPI_PHASE_2EDGE))
/** @brief Checks if SPI Slave Select parameter is in allowed range.
* @param __NSS__ specifies the SPI Slave Select management parameter.
* This parameter can be a value of @ref SPI_Slave_Select_management
* @retval None
*/
#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
((__NSS__) == SPI_NSS_HARD_INPUT) || \
((__NSS__) == SPI_NSS_HARD_OUTPUT))
/** @brief Checks if SPI NSS Pulse parameter is in allowed range.
* @param __NSSP__ specifies the SPI NSS Pulse Mode parameter.
* This parameter can be a value of @ref SPI_NSSP_Mode
* @retval None
*/
#define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \
((__NSSP__) == SPI_NSS_PULSE_DISABLE))
/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range.
* @param __PRESCALER__ specifies the SPI Baudrate prescaler.
* This parameter can be a value of @ref SPI_BaudRate_Prescaler
* @retval None
*/
#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range.
* @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit).
* This parameter can be a value of @ref SPI_MSB_LSB_transmission
* @retval None
*/
#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
((__BIT__) == SPI_FIRSTBIT_LSB))
/** @brief Checks if SPI TI mode parameter is in allowed range.
* @param __MODE__ specifies the SPI TI mode.
* This parameter can be a value of @ref SPI_TI_mode
* @retval None
*/
#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
((__MODE__) == SPI_TIMODE_ENABLE))
/** @brief Checks if SPI CRC calculation enabled state is in allowed range.
* @param __CALCULATION__ specifies the SPI CRC calculation enable state.
* This parameter can be a value of @ref SPI_CRC_Calculation
* @retval None
*/
#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
/** @brief Checks if SPI CRC length is in allowed range.
* @param __LENGTH__ specifies the SPI CRC length.
* This parameter can be a value of @ref SPI_CRC_length
* @retval None
*/
#define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) || \
((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \
((__LENGTH__) == SPI_CRC_LENGTH_16BIT))
/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range.
* @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation.
* This parameter must be a number between Min_Data = 0 and Max_Data = 65535
* @retval None
*/
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
((__POLYNOMIAL__) <= 0xFFFFU) && \
(((__POLYNOMIAL__)&0x1U) != 0U))
/** @brief Checks if DMA handle is valid.
* @param __HANDLE__ specifies a DMA Handle.
* @retval None
*/
#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
/**
* @}
*/
/* Include SPI HAL Extended module */
#include "stm32g4xx_hal_spi_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
/** @addtogroup SPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
pSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/** @addtogroup SPI_Exported_Functions_Group3
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SPI_H */
| 37,848 | C | 43.423709 | 118 | 0.542274 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_qspi.h | /**
******************************************************************************
* @file stm32g4xx_hal_qspi.h
* @author MCD Application Team
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_QSPI_H
#define STM32G4xx_HAL_QSPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(QUADSPI)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup QSPI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup QSPI_Exported_Types QSPI Exported Types
* @{
*/
/**
* @brief QSPI Init structure definition
*/
typedef struct
{
uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
This parameter can be a number between 0 and 255 */
uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
This parameter can be a value between 1 and 16 */
uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
This parameter can be a value of @ref QSPI_SampleShifting */
uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
required to address the flash memory. The flash capacity can be up to 4GB
(addressed using 32 bits) in indirect mode, but the addressable space in
memory-mapped mode is limited to 256MB
This parameter can be a number between 0 and 31 */
uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
of clock cycles which the chip select must remain high between commands.
This parameter can be a value of @ref QSPI_ChipSelectHighTime */
uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
This parameter can be a value of @ref QSPI_ClockMode */
uint32_t FlashID; /* Specifies the Flash which will be used,
This parameter can be a value of @ref QSPI_Flash_Select */
uint32_t DualFlash; /* Specifies the Dual Flash Mode State
This parameter can be a value of @ref QSPI_DualFlash_Mode */
}QSPI_InitTypeDef;
/**
* @brief HAL QSPI State structures definition
*/
typedef enum
{
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
}HAL_QSPI_StateTypeDef;
/**
* @brief QSPI Handle Structure definition
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
typedef struct __QSPI_HandleTypeDef
#else
typedef struct
#endif
{
QUADSPI_TypeDef *Instance; /* QSPI registers base address */
QSPI_InitTypeDef Init; /* QSPI communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
__IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
__IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
__IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
__IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
__IO HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
__IO uint32_t ErrorCode; /* QSPI Error code */
uint32_t Timeout; /* Timeout for the QSPI memory access */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);
void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi);
#endif
}QSPI_HandleTypeDef;
/**
* @brief QSPI Command structure definition
*/
typedef struct
{
uint32_t Instruction; /* Specifies the Instruction to be sent
This parameter can be a value (8-bit) between 0x00 and 0xFF */
uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
uint32_t AddressSize; /* Specifies the Address Size
This parameter can be a value of @ref QSPI_AddressSize */
uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
This parameter can be a value of @ref QSPI_AlternateBytesSize */
uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
This parameter can be a number between 0 and 31 */
uint32_t InstructionMode; /* Specifies the Instruction Mode
This parameter can be a value of @ref QSPI_InstructionMode */
uint32_t AddressMode; /* Specifies the Address Mode
This parameter can be a value of @ref QSPI_AddressMode */
uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
This parameter can be a value of @ref QSPI_AlternateBytesMode */
uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
This parameter can be a value of @ref QSPI_DataMode */
uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
until end of memory)*/
uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
This parameter can be a value of @ref QSPI_DdrMode */
uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data
output by one quarter of QUADSPI output clock in DDR mode.
This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
uint32_t SIOOMode; /* Specifies the send instruction only once mode
This parameter can be a value of @ref QSPI_SIOOMode */
}QSPI_CommandTypeDef;
/**
* @brief QSPI Auto Polling mode configuration structure definition
*/
typedef struct
{
uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
This parameter can be any value between 0 and 0xFFFFFFFF */
uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
This parameter can be any value between 0 and 0xFFFF */
uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
This parameter can be any value between 1 and 4 */
uint32_t MatchMode; /* Specifies the method used for determining a match.
This parameter can be a value of @ref QSPI_MatchMode */
uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
This parameter can be a value of @ref QSPI_AutomaticStop */
}QSPI_AutoPollingTypeDef;
/**
* @brief QSPI Memory Mapped mode configuration structure definition
*/
typedef struct
{
uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
This parameter can be any value between 0 and 0xFFFF */
uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
This parameter can be a value of @ref QSPI_TimeOutActivation */
}QSPI_MemoryMappedTypeDef;
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/**
* @brief HAL QSPI Callback ID enumeration definition
*/
typedef enum
{
HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */
HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */
HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */
HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */
HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */
HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */
HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */
HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */
HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */
HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */
HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */
HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */
}HAL_QSPI_CallbackIDTypeDef;
/**
* @brief HAL QSPI Callback pointer definition
*/
typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
#endif
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
* @{
*/
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
#define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */
#endif
/**
* @}
*/
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
#define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
*/
/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
* @{
*/
#define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
/**
* @}
*/
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
#define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
*/
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
#define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
/**
* @}
*/
/** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
#define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/
/**
* @}
*/
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
#define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
/**
* @}
*/
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
#define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
/**
* @}
*/
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
#define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
/**
* @}
*/
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
#define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
/**
* @}
*/
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
#define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
/**
* @}
*/
/** @defgroup QSPI_DataMode QSPI Data Mode
* @{
*/
#define QSPI_DATA_NONE 0x00000000U /*!<No data*/
#define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
#define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
#define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
/**
* @}
*/
/** @defgroup QSPI_DdrMode QSPI DDR Mode
* @{
*/
#define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
*/
/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
* @{
*/
#define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one quarter of QUADSPI output clock in DDR mode*/
/**
* @}
*/
/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
* @{
*/
#define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
*/
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
#define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
*/
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
#define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
*/
/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
* @{
*/
#define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
*/
/** @defgroup QSPI_Flags QSPI Flags
* @{
*/
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
/**
* @}
*/
/** @defgroup QSPI_Interrupts QSPI Interrupts
* @{
*/
#define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
#define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
#define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
#define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
#define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
/**
* @}
*/
/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
* @brief QSPI Timeout definition
* @{
*/
#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
* @{
*/
/** @brief Reset QSPI handle state.
* @param __HANDLE__ : QSPI handle.
* @retval None
*/
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_QSPI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
#endif
/** @brief Enable the QSPI peripheral.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Disable the QSPI peripheral.
* @param __HANDLE__ : specifies the QSPI Handle.
* @retval None
*/
#define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
/** @brief Enable the specified QSPI interrupt.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to enable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval None
*/
#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Disable the specified QSPI interrupt.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to disable.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval None
*/
#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
/** @brief Check whether the specified QSPI interrupt source is enabled or not.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __INTERRUPT__ : specifies the QSPI interrupt source to check.
* This parameter can be one of the following values:
* @arg QSPI_IT_TO: QSPI Timeout interrupt
* @arg QSPI_IT_SM: QSPI Status match interrupt
* @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
* @arg QSPI_IT_TC: QSPI Transfer complete interrupt
* @arg QSPI_IT_TE: QSPI Transfer error interrupt
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Check whether the selected QSPI flag is set or not.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __FLAG__ : specifies the QSPI flag to check.
* This parameter can be one of the following values:
* @arg QSPI_FLAG_BUSY: QSPI Busy flag
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)
/** @brief Clears the specified QSPI's flag status.
* @param __HANDLE__ : specifies the QSPI Handle.
* @param __FLAG__ : specifies the QSPI clear register flag that needs to be set
* This parameter can be one of the following values:
* @arg QSPI_FLAG_TO: QSPI Timeout flag
* @arg QSPI_FLAG_SM: QSPI Status match flag
* @arg QSPI_FLAG_TC: QSPI Transfer complete flag
* @arg QSPI_FLAG_TE: QSPI Transfer error flag
* @retval None
*/
#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup QSPI_Exported_Functions
* @{
*/
/** @addtogroup QSPI_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
/* QSPI IRQ handler method */
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
/* QSPI indirect mode */
HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
/* QSPI status flag polling mode */
HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
/* QSPI memory-mapped mode */
HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
/* Callback functions in non-blocking modes ***********************************/
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
/* QSPI indirect mode */
void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI status flag polling mode */
void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
/* QSPI memory-mapped mode */
void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)
/* QSPI callback registering/unregistering */
HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);
#endif
/**
* @}
*/
/** @addtogroup QSPI_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup QSPI_Private_Macros QSPI Private Macros
* @{
*/
#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)
#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U))
#define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
#define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U))
#define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
#define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
((CLKMODE) == QSPI_CLOCK_MODE_3))
#define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \
((FLASH_ID) == QSPI_FLASH_ID_2))
#define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
((MODE) == QSPI_DUALFLASH_DISABLE))
#define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU)
#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
#define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U)
#define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
((MODE) == QSPI_INSTRUCTION_1_LINE) || \
((MODE) == QSPI_INSTRUCTION_2_LINES) || \
((MODE) == QSPI_INSTRUCTION_4_LINES))
#define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
((MODE) == QSPI_ADDRESS_1_LINE) || \
((MODE) == QSPI_ADDRESS_2_LINES) || \
((MODE) == QSPI_ADDRESS_4_LINES))
#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
((MODE) == QSPI_DATA_1_LINE) || \
((MODE) == QSPI_DATA_2_LINES) || \
((MODE) == QSPI_DATA_4_LINES))
#define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
#define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
#define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
#define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
#define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U))
#define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
((MODE) == QSPI_MATCH_MODE_OR))
#define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
#define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU)
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(QUADSPI) */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_QSPI_H */
| 36,916 | C | 48.157124 | 165 | 0.568236 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32_assert_template.h | /**
******************************************************************************
* @file stm32_assert.h
* @author MCD Application Team
* @brief STM32 assert template file.
* This file should be copied to the application folder and renamed
* to stm32_assert.h.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32_ASSERT_H
#define STM32_ASSERT_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Includes ------------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32_ASSERT_H */
| 1,978 | C | 34.339285 | 93 | 0.469161 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2s.h | /**
******************************************************************************
* @file stm32g4xx_hal_i2s.h
* @author MCD Application Team
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_I2S_H
#define STM32G4xx_HAL_I2S_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(SPI_I2S_SUPPORT)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup I2S
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2S_Exported_Types I2S Exported Types
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint32_t CPOL; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
} I2S_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
} HAL_I2S_StateTypeDef;
/**
* @brief I2S handle Structure definition
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1)
typedef struct __I2S_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
{
SPI_TypeDef *Instance; /*!< I2S registers base address */
I2S_InitTypeDef Init; /*!< I2S communication parameters */
uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */
__IO uint16_t TxXferSize; /*!< I2S Tx transfer size */
__IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */
uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */
__IO uint16_t RxXferSize; /*!< I2S Rx transfer size */
__IO uint16_t RxXferCount; /*!< I2S Rx transfer counter
(This field is initialized at the
same value as transfer size at the
beginning of the transfer and
decremented when a sample is received
NbSamplesReceived = RxBufferSize-RxBufferCount) */
DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */
__IO HAL_LockTypeDef Lock; /*!< I2S locking object */
__IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */
__IO uint32_t ErrorCode; /*!< I2S Error code
This parameter can be a value of @ref I2S_Error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */
void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */
void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */
void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */
void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */
void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */
void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
} I2S_HandleTypeDef;
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
/**
* @brief HAL I2S Callback ID enumeration definition
*/
typedef enum
{
HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */
HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */
HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */
HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */
HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */
HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */
HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */
} HAL_I2S_CallbackIDTypeDef;
/**
* @brief HAL I2S Callback pointer definition
*/
typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_Exported_Constants I2S Exported Constants
* @{
*/
/** @defgroup I2S_Error I2S Error
* @{
*/
#define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */
#define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */
#define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
#define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */
/**
* @}
*/
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX (0x00000000U)
#define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
#define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
#define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1))
/**
* @}
*/
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS (0x00000000U)
#define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
#define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
#define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1))
#define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC))
/**
* @}
*/
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B (0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
#define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
#define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
/**
* @}
*/
/** @defgroup I2S_MCLK_Output I2S MCLK Output
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K (192000U)
#define I2S_AUDIOFREQ_96K (96000U)
#define I2S_AUDIOFREQ_48K (48000U)
#define I2S_AUDIOFREQ_44K (44100U)
#define I2S_AUDIOFREQ_32K (32000U)
#define I2S_AUDIOFREQ_22K (22050U)
#define I2S_AUDIOFREQ_16K (16000U)
#define I2S_AUDIOFREQ_11K (11025U)
#define I2S_AUDIOFREQ_8K (8000U)
#define I2S_AUDIOFREQ_DEFAULT (2U)
/**
* @}
*/
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW (0x00000000U)
#define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL)
/**
* @}
*/
/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition
* @{
*/
#define I2S_IT_TXE SPI_CR2_TXEIE
#define I2S_IT_RXNE SPI_CR2_RXNEIE
#define I2S_IT_ERR SPI_CR2_ERRIE
/**
* @}
*/
/** @defgroup I2S_Flags_Definition I2S Flags Definition
* @{
*/
#define I2S_FLAG_TXE SPI_SR_TXE
#define I2S_FLAG_RXNE SPI_SR_RXNE
#define I2S_FLAG_UDR SPI_SR_UDR
#define I2S_FLAG_OVR SPI_SR_OVR
#define I2S_FLAG_FRE SPI_SR_FRE
#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
#define I2S_FLAG_BSY SPI_SR_BSY
#define I2S_FLAG_MASK (SPI_SR_RXNE\
| SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY)
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2S_Exported_macros I2S Exported Macros
* @{
*/
/** @brief Reset I2S handle state
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2S_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
/** @brief Disable the specified SPI peripheral (in I2S mode).
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
/** @brief Enable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Disable the specified I2S interrupts.
* @param __HANDLE__ specifies the I2S Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval None
*/
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
* @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
* @param __HANDLE__ specifies the I2S Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_FRE: Frame error flag
* @arg I2S_FLAG_CHSIDE: Channel Side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2S OVR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
__IO uint32_t tmpreg_ovr = 0x00U; \
tmpreg_ovr = (__HANDLE__)->Instance->DR; \
tmpreg_ovr = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2S UDR pending flag.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\
__IO uint32_t tmpreg_udr = 0x00U;\
tmpreg_udr = ((__HANDLE__)->Instance->SR);\
UNUSED(tmpreg_udr); \
}while(0U)
/** @brief Flush the I2S DR Register.
* @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\
__IO uint32_t tmpreg_dr = 0x00U;\
tmpreg_dr = ((__HANDLE__)->Instance->DR);\
UNUSED(tmpreg_dr); \
}while(0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2S_Exported_Functions
* @{
*/
/** @addtogroup I2S_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)
HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID,
pI2S_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ***************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/** @addtogroup I2S_Exported_Functions_Group3
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2S_Private_Macros I2S Private Macros
* @{
*/
/** @brief Check whether the specified SPI flag is set or not.
* @param __SR__ copy of I2S SR register.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
* @arg I2S_FLAG_UDR: Underrun error flag
* @arg I2S_FLAG_OVR: Overrun flag
* @arg I2S_FLAG_CHSIDE: Channel side flag
* @arg I2S_FLAG_BSY: Busy flag
* @retval SET or RESET.
*/
#define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\
& ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)
/** @brief Check whether the specified SPI Interrupt is set or not.
* @param __CR2__ copy of I2S CR2 register.
* @param __INTERRUPT__ specifies the SPI interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
* @arg I2S_IT_ERR: Error interrupt enable
* @retval SET or RESET.
*/
#define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if I2S Mode parameter is in allowed range.
* @param __MODE__ specifies the I2S Mode.
* This parameter can be a value of @ref I2S_Mode
* @retval None
*/
#define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \
((__MODE__) == I2S_MODE_SLAVE_RX) || \
((__MODE__) == I2S_MODE_MASTER_TX) || \
((__MODE__) == I2S_MODE_MASTER_RX))
#define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \
((__STANDARD__) == I2S_STANDARD_MSB) || \
((__STANDARD__) == I2S_STANDARD_LSB) || \
((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
((__STANDARD__) == I2S_STANDARD_PCM_LONG))
#define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \
((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \
((__FORMAT__) == I2S_DATAFORMAT_24B) || \
((__FORMAT__) == I2S_DATAFORMAT_32B))
#define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \
((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
#define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \
((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \
((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))
/** @brief Checks if I2S Serial clock steady state parameter is in allowed range.
* @param __CPOL__ specifies the I2S serial clock steady state.
* This parameter can be a value of @ref I2S_Clock_Polarity
* @retval None
*/
#define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \
((__CPOL__) == I2S_CPOL_HIGH))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* SPI_I2S_SUPPORT */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_I2S_H */
| 23,275 | C | 40.938739 | 131 | 0.523008 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard.h | /**
******************************************************************************
* @file stm32g4xx_hal_smartcard.h
* @author MCD Application Team
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SMARTCARD_H
#define STM32G4xx_HAL_SMARTCARD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SMARTCARD
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
* @{
*/
/**
* @brief SMARTCARD Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< Configures the SmartCard communication baud rate.
The baud rate register is computed using the following formula:
Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))
where usart_ker_ckpres is the USART input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter @ref SMARTCARD_Word_Length can only be
set to 9 (8 data + 1 parity bits). */
uint32_t StopBits; /*!< Specifies the number of stop bits.
This parameter can be a value of @ref SMARTCARD_Stop_Bits. */
uint16_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref SMARTCARD_Parity
@note The parity is enabled by default (PCE is forced to 1).
Since the WordLength is forced to 8 bits + parity, M is
forced to 1 and the parity bit is the 9th bit. */
uint16_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref SMARTCARD_Mode */
uint16_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
uint16_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref SMARTCARD_Clock_Phase */
uint16_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref SMARTCARD_Last_Bit */
uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote
is selected. Selecting the single sample method increases
the receiver tolerance to clock deviations. This parameter can be a value
of @ref SMARTCARD_OneBit_Sampling. */
uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler.
This parameter can be any value from 0x01 to 0x1F. Prescaler value is
multiplied by 2 to give the division factor of the source clock frequency */
uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */
uint16_t NACKEnable; /*!< Specifies whether the SmartCard NACK transmission is enabled
in case of parity error.
This parameter can be a value of @ref SMARTCARD_NACK_Enable */
uint32_t TimeOutEnable; /*!< Specifies whether the receiver timeout is enabled.
This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/
uint32_t TimeOutValue; /*!< Specifies the receiver time out value in number of baud blocks:
it is used to implement the Character Wait Time (CWT) and
Block Wait Time (BWT). It is coded over 24 bits. */
uint8_t BlockLength; /*!< Specifies the SmartCard Block Length in T=1 Reception mode.
This parameter can be any value from 0x0 to 0xFF */
uint8_t AutoRetryCount; /*!< Specifies the SmartCard auto-retry count (number of retries in
receive and transmit mode). When set to 0, retransmission is
disabled. Otherwise, its maximum value is 7 (before signalling
an error) */
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source.
This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */
} SMARTCARD_InitTypeDef;
/**
* @brief SMARTCARD advanced features initialization structure definition
*/
typedef struct
{
uint32_t AdvFeatureInit; /*!< Specifies which advanced SMARTCARD features is initialized. Several
advanced features may be initialized at the same time. This parameter
can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */
uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
This parameter can be a value of @ref SMARTCARD_Tx_Inv */
uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
This parameter can be a value of @ref SMARTCARD_Rx_Inv */
uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
vs negative/inverted logic).
This parameter can be a value of @ref SMARTCARD_Data_Inv */
uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */
uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
This parameter can be a value of @ref SMARTCARD_Overrun_Disable */
uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */
uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
This parameter can be a value of @ref SMARTCARD_MSB_First */
uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when
relevant flag is available) or once guard time period has elapsed.
This parameter can be a value
of @ref SMARTCARDEx_Transmission_Completion_Indication. */
} SMARTCARD_AdvFeatureInitTypeDef;
/**
* @brief HAL SMARTCARD State definition
* @note HAL SMARTCARD State value is a combination of 2 different substates:
* gState and RxState (see @ref SMARTCARD_State_Definition).
* - gState contains SMARTCARD state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized. HAL SMARTCARD Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef uint32_t HAL_SMARTCARD_StateTypeDef;
/**
* @brief SMARTCARD handle Structure definition
*/
typedef struct __SMARTCARD_HandleTypeDef
{
USART_TypeDef *Instance; /*!< USART registers base address */
SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */
SMARTCARD_AdvFeatureInitTypeDef AdvancedInit; /*!< SmartCard advanced features initialization parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */
uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */
__IO uint16_t TxXferCount; /*!< SmartCard Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to SmartCard Rx transfer Buffer */
uint16_t RxXferSize; /*!< SmartCard Rx Transfer size */
__IO uint16_t RxXferCount; /*!< SmartCard Rx Transfer Counter */
uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used.
This parameter can be a value of
@ref SMARTCARDEx_FIFO_mode. */
void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
DMA_HandleTypeDef *hdmatx; /*!< SmartCard Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SmartCard Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global
Handle management and also related to Tx operations.
This parameter can be a value
of @ref HAL_SMARTCARD_StateTypeDef */
__IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations.
This parameter can be a value
of @ref HAL_SMARTCARD_StateTypeDef */
__IO uint32_t ErrorCode; /*!< SmartCard Error code */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Complete Callback */
void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Complete Callback */
void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Error Callback */
void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Receive Complete Callback */
void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Tx Fifo Empty Callback */
void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp Init callback */
void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Msp DeInit callback */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
} SMARTCARD_HandleTypeDef;
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SMARTCARD Callback ID enumeration definition
*/
typedef enum
{
HAL_SMARTCARD_TX_COMPLETE_CB_ID = 0x00U, /*!< SMARTCARD Tx Complete Callback ID */
HAL_SMARTCARD_RX_COMPLETE_CB_ID = 0x01U, /*!< SMARTCARD Rx Complete Callback ID */
HAL_SMARTCARD_ERROR_CB_ID = 0x02U, /*!< SMARTCARD Error Callback ID */
HAL_SMARTCARD_ABORT_COMPLETE_CB_ID = 0x03U, /*!< SMARTCARD Abort Complete Callback ID */
HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U, /*!< SMARTCARD Abort Transmit Complete Callback ID */
HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID = 0x05U, /*!< SMARTCARD Abort Receive Complete Callback ID */
HAL_SMARTCARD_RX_FIFO_FULL_CB_ID = 0x06U, /*!< SMARTCARD Rx Fifo Full Callback ID */
HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID = 0x07U, /*!< SMARTCARD Tx Fifo Empty Callback ID */
HAL_SMARTCARD_MSPINIT_CB_ID = 0x08U, /*!< SMARTCARD MspInit callback ID */
HAL_SMARTCARD_MSPDEINIT_CB_ID = 0x09U /*!< SMARTCARD MspDeInit callback ID */
} HAL_SMARTCARD_CallbackIDTypeDef;
/**
* @brief HAL SMARTCARD Callback pointer definition
*/
typedef void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard); /*!< pointer to an SMARTCARD callback function */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @brief SMARTCARD clock sources
*/
typedef enum
{
SMARTCARD_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
SMARTCARD_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
SMARTCARD_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
SMARTCARD_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
SMARTCARD_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U /*!< undefined clock source */
} SMARTCARD_ClockSourceTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants
* @{
*/
/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition
* @{
*/
#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value
is allowed for gState and RxState */
#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for
use. Value is allowed for gState
and RxState */
#define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing
Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception
process is ongoing Not to be used for
neither gState nor RxState.
Value is result of combination (Or)
between gState and RxState values */
#define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error
Value is allowed for gState only */
/**
* @}
*/
/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition
* @{
*/
#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */
#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
* @{
*/
#define SMARTCARD_WORDLENGTH_9B USART_CR1_M0 /*!< SMARTCARD frame length */
/**
* @}
*/
/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
* @{
*/
#define SMARTCARD_STOPBITS_0_5 USART_CR2_STOP_0 /*!< SMARTCARD frame with 0.5 stop bit */
#define SMARTCARD_STOPBITS_1_5 USART_CR2_STOP /*!< SMARTCARD frame with 1.5 stop bits */
/**
* @}
*/
/** @defgroup SMARTCARD_Parity SMARTCARD Parity
* @{
*/
#define SMARTCARD_PARITY_EVEN USART_CR1_PCE /*!< SMARTCARD frame even parity */
#define SMARTCARD_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< SMARTCARD frame odd parity */
/**
* @}
*/
/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode
* @{
*/
#define SMARTCARD_MODE_RX USART_CR1_RE /*!< SMARTCARD RX mode */
#define SMARTCARD_MODE_TX USART_CR1_TE /*!< SMARTCARD TX mode */
#define SMARTCARD_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< SMARTCARD RX and TX mode */
/**
* @}
*/
/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity
* @{
*/
#define SMARTCARD_POLARITY_LOW 0x00000000U /*!< SMARTCARD frame low polarity */
#define SMARTCARD_POLARITY_HIGH USART_CR2_CPOL /*!< SMARTCARD frame high polarity */
/**
* @}
*/
/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
* @{
*/
#define SMARTCARD_PHASE_1EDGE 0x00000000U /*!< SMARTCARD frame phase on first clock transition */
#define SMARTCARD_PHASE_2EDGE USART_CR2_CPHA /*!< SMARTCARD frame phase on second clock transition */
/**
* @}
*/
/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit
* @{
*/
#define SMARTCARD_LASTBIT_DISABLE 0x00000000U /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */
#define SMARTCARD_LASTBIT_ENABLE USART_CR2_LBCL /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method
* @{
*/
#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< SMARTCARD frame one-bit sample disabled */
#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< SMARTCARD frame one-bit sample enabled */
/**
* @}
*/
/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable
* @{
*/
#define SMARTCARD_NACK_DISABLE 0x00000000U /*!< SMARTCARD NACK transmission disabled */
#define SMARTCARD_NACK_ENABLE USART_CR3_NACK /*!< SMARTCARD NACK transmission enabled */
/**
* @}
*/
/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable
* @{
*/
#define SMARTCARD_TIMEOUT_DISABLE 0x00000000U /*!< SMARTCARD receiver timeout disabled */
#define SMARTCARD_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< SMARTCARD receiver timeout enabled */
/**
* @}
*/
/** @defgroup SMARTCARD_ClockPrescaler SMARTCARD Clock Prescaler
* @{
*/
#define SMARTCARD_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
#define SMARTCARD_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
#define SMARTCARD_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
#define SMARTCARD_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
#define SMARTCARD_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
#define SMARTCARD_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
#define SMARTCARD_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
#define SMARTCARD_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
#define SMARTCARD_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
#define SMARTCARD_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
#define SMARTCARD_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
#define SMARTCARD_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
/**
* @}
*/
/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion
* @{
*/
#define SMARTCARD_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */
#define SMARTCARD_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */
/**
* @}
*/
/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion
* @{
*/
#define SMARTCARD_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */
#define SMARTCARD_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */
/**
* @}
*/
/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion
* @{
*/
#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */
#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */
/**
* @}
*/
/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap
* @{
*/
#define SMARTCARD_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */
#define SMARTCARD_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */
/**
* @}
*/
/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable
* @{
*/
#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */
#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */
/**
* @}
*/
/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error
* @{
*/
#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */
#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */
/**
* @}
*/
/** @defgroup SMARTCARD_MSB_First SMARTCARD advanced feature MSB first
* @{
*/
#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received first disable */
#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received first enable */
/**
* @}
*/
/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters
* @{
*/
#define SMARTCARD_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive data flush request */
#define SMARTCARD_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush request */
/**
* @}
*/
/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask
* @{
*/
#define SMARTCARD_IT_MASK 0x001FU /*!< SMARTCARD interruptions flags mask */
#define SMARTCARD_CR_MASK 0x00E0U /*!< SMARTCARD control register mask */
#define SMARTCARD_CR_POS 5U /*!< SMARTCARD control register position */
#define SMARTCARD_ISR_MASK 0x1F00U /*!< SMARTCARD ISR register mask */
#define SMARTCARD_ISR_POS 8U /*!< SMARTCARD ISR register position */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
* @{
*/
/** @brief Reset SMARTCARD handle states.
* @param __HANDLE__ SMARTCARD handle.
* @retval None
*/
#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET; \
(__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/** @brief Flush the Smartcard Data registers.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified SMARTCARD pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
* @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
* @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
* @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
* @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detected clear flag
* @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
* @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag
* @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
* @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the SMARTCARD PE pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
/** @brief Clear the SMARTCARD FE pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
/** @brief Clear the SMARTCARD NE pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
/** @brief Clear the SMARTCARD ORE pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
/** @brief Clear the SMARTCARD IDLE pending flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
/** @brief Check whether the specified Smartcard flag is set or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)
* @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag
* @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref SMARTCARD_FLAG_BUSY Busy flag
* @arg @ref SMARTCARD_FLAG_EOBF End of block flag
* @arg @ref SMARTCARD_FLAG_RTOF Receiver timeout flag
* @arg @ref SMARTCARD_FLAG_TXE Transmit data register empty flag
* @arg @ref SMARTCARD_FLAG_TC Transmission complete flag
* @arg @ref SMARTCARD_FLAG_RXNE Receive data register not empty flag
* @arg @ref SMARTCARD_FLAG_IDLE Idle line detection flag
* @arg @ref SMARTCARD_FLAG_ORE Overrun error flag
* @arg @ref SMARTCARD_FLAG_NE Noise error flag
* @arg @ref SMARTCARD_FLAG_FE Framing error flag
* @arg @ref SMARTCARD_FLAG_PE Parity error flag
* @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag
* @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag
* @arg @ref SMARTCARD_FLAG_TXFE TXFIFO Empty flag
* @arg @ref SMARTCARD_FLAG_RXFF RXFIFO Full flag
* @arg @ref SMARTCARD_FLAG_RXFT SMARTCARD RXFIFO threshold flag
* @arg @ref SMARTCARD_FLAG_TXFT SMARTCARD TXFIFO threshold flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Enable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_IT_EOB End of block interrupt
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before
* guard time interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
* @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
* @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
* @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
* @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))):\
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1UL <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disable the specified SmartCard interrupt.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to disable.
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_IT_EOB End of block interrupt
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard
* time interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
* @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
* @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
* @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
* @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Check whether the specified SmartCard interrupt has occurred or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __INTERRUPT__ specifies the SMARTCARD interrupt to check.
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_IT_EOB End of block interrupt
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
* interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
* @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
* @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
* @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
* @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\
(((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\
& SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\
? SET : RESET)
/** @brief Check whether the specified SmartCard interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_IT_EOB End of block interrupt
* @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt
* @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt
* @arg @ref SMARTCARD_IT_TC Transmission complete interrupt
* @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time
* interrupt (when interruption available)
* @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt
* @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt
* @arg @ref SMARTCARD_IT_PE Parity error interrupt
* @arg @ref SMARTCARD_IT_ERR Error interrupt(frame error, noise error, overrun error)
* @arg @ref SMARTCARD_IT_TXFNF TX FIFO not full interruption
* @arg @ref SMARTCARD_IT_RXFNE RXFIFO not empty interruption
* @arg @ref SMARTCARD_IT_RXFF RXFIFO full interruption
* @arg @ref SMARTCARD_IT_TXFE TXFIFO empty interruption
* @arg @ref SMARTCARD_IT_RXFT RXFIFO threshold reached interruption
* @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 0x01U)?\
(__HANDLE__)->Instance->CR1 : \
(((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\
SMARTCARD_CR_POS) == 0x02U)?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) &\
(0x01UL << (((uint16_t)(__INTERRUPT__))\
& SMARTCARD_IT_MASK))) != 0U)\
? SET : RESET)
/** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt.
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
* @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
* @arg @ref SMARTCARD_CLEAR_NEF Noise detected clear flag
* @arg @ref SMARTCARD_CLEAR_OREF OverRun error clear flag
* @arg @ref SMARTCARD_CLEAR_IDLEF Idle line detection clear flag
* @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag
* @arg @ref SMARTCARD_CLEAR_TCF Transmission complete clear flag
* @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)
* @arg @ref SMARTCARD_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref SMARTCARD_CLEAR_EOBF End of block clear flag
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific SMARTCARD request flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
* @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request
* @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the SMARTCARD one bit sample method.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the SMARTCARD one bit sample method.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable the USART associated to the SMARTCARD Handle.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Private macros -------------------------------------------------------------*/
/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros
* @{
*/
/** @brief Report the SMARTCARD clock source.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
*/
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
/** @brief Check the Baud rate range.
* @note The maximum Baud Rate is derived from the maximum clock on G4 (150 MHz)
* divided by the oversampling used on the SMARTCARD (i.e. 16).
* @param __BAUDRATE__ Baud rate set by the configuration function.
* @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 9375001U)
/** @brief Check the block length range.
* @note The maximum SMARTCARD block length is 0xFF.
* @param __LENGTH__ block length.
* @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)
/** @brief Check the receiver timeout value.
* @note The maximum SMARTCARD receiver timeout value is 0xFFFFFF.
* @param __TIMEOUTVALUE__ receiver timeout value.
* @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
/** @brief Check the SMARTCARD autoretry counter value.
* @note The maximum number of retransmissions is 0x7.
* @param __COUNT__ number of retransmissions.
* @retval Test result (TRUE or FALSE)
*/
#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__) ((__COUNT__) <= 0x7U)
/** @brief Ensure that SMARTCARD frame length is valid.
* @param __LENGTH__ SMARTCARD frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)
/** @brief Ensure that SMARTCARD frame number of stop bits is valid.
* @param __STOPBITS__ SMARTCARD frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\
((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))
/** @brief Ensure that SMARTCARD frame parity is valid.
* @param __PARITY__ SMARTCARD frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
*/
#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \
((__PARITY__) == SMARTCARD_PARITY_ODD))
/** @brief Ensure that SMARTCARD communication mode is valid.
* @param __MODE__ SMARTCARD communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/** @brief Ensure that SMARTCARD frame polarity is valid.
* @param __CPOL__ SMARTCARD frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
*/
#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
|| ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
/** @brief Ensure that SMARTCARD frame phase is valid.
* @param __CPHA__ SMARTCARD frame phase.
* @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
*/
#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))
/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.
* @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.
* @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
*/
#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \
((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))
/** @brief Ensure that SMARTCARD frame sampling is valid.
* @param __ONEBIT__ SMARTCARD frame sampling.
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
*/
#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \
((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))
/** @brief Ensure that SMARTCARD NACK transmission setting is valid.
* @param __NACK__ SMARTCARD NACK transmission setting.
* @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)
*/
#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \
((__NACK__) == SMARTCARD_NACK_DISABLE))
/** @brief Ensure that SMARTCARD receiver timeout setting is valid.
* @param __TIMEOUT__ SMARTCARD receiver timeout setting.
* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
*/
#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \
((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))
/** @brief Ensure that SMARTCARD clock Prescaler is valid.
* @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
*/
#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
/** @brief Ensure that SMARTCARD advanced features initialization is valid.
* @param __INIT__ SMARTCARD advanced features initialization.
* @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT | \
SMARTCARD_ADVFEATURE_TXINVERT_INIT | \
SMARTCARD_ADVFEATURE_RXINVERT_INIT | \
SMARTCARD_ADVFEATURE_DATAINVERT_INIT | \
SMARTCARD_ADVFEATURE_SWAP_INIT | \
SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT | \
SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \
SMARTCARD_ADVFEATURE_MSBFIRST_INIT))
/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.
* @param __TXINV__ SMARTCARD frame TX inversion setting.
* @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \
((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))
/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.
* @param __RXINV__ SMARTCARD frame RX inversion setting.
* @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \
((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))
/** @brief Ensure that SMARTCARD frame data inversion setting is valid.
* @param __DATAINV__ SMARTCARD frame data inversion setting.
* @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \
((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))
/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.
* @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.
* @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \
((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))
/** @brief Ensure that SMARTCARD frame overrun setting is valid.
* @param __OVERRUN__ SMARTCARD frame overrun setting.
* @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
*/
#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \
((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))
/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.
* @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.
* @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \
((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))
/** @brief Ensure that SMARTCARD frame MSB first setting is valid.
* @param __MSBFIRST__ SMARTCARD frame MSB first setting.
* @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
*/
#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \
((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))
/** @brief Ensure that SMARTCARD request parameter is valid.
* @param __PARAM__ SMARTCARD request parameter.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
/* Include SMARTCARD HAL Extended module */
#include "stm32g4xx_hal_smartcard_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARD_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @addtogroup SMARTCARD_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID,
pSMARTCARD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup SMARTCARD_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @addtogroup SMARTCARD_Exported_Functions_Group4
* @{
*/
HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);
uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SMARTCARD_H */
| 66,639 | C | 53.93817 | 148 | 0.52909 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_tim.h | /**
******************************************************************************
* @file stm32g4xx_ll_tim.h
* @author MCD Application Team
* @brief Header file of TIM LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_TIM_H
#define __STM32G4xx_LL_TIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM20)
/** @defgroup TIM_LL TIM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Variables TIM Private Variables
* @{
*/
static const uint8_t OFFSET_TAB_CCMRx[] =
{
0x00U, /* 0: TIMx_CH1 */
0x00U, /* 1: TIMx_CH1N */
0x00U, /* 2: TIMx_CH2 */
0x00U, /* 3: TIMx_CH2N */
0x04U, /* 4: TIMx_CH3 */
0x04U, /* 5: TIMx_CH3N */
0x04U, /* 6: TIMx_CH4 */
0x04U, /* 7: TIMx_CH4N */
0x38U, /* 8: TIMx_CH5 */
0x38U /* 9: TIMx_CH6 */
};
static const uint8_t SHIFT_TAB_OCxx[] =
{
0U, /* 0: OC1M, OC1FE, OC1PE */
0U, /* 1: - NA */
8U, /* 2: OC2M, OC2FE, OC2PE */
0U, /* 3: - NA */
0U, /* 4: OC3M, OC3FE, OC3PE */
0U, /* 5: - NA */
8U, /* 6: OC4M, OC4FE, OC4PE */
0U, /* 7: - NA */
0U, /* 8: OC5M, OC5FE, OC5PE */
8U /* 9: OC6M, OC6FE, OC6PE */
};
static const uint8_t SHIFT_TAB_ICxx[] =
{
0U, /* 0: CC1S, IC1PSC, IC1F */
0U, /* 1: - NA */
8U, /* 2: CC2S, IC2PSC, IC2F */
0U, /* 3: - NA */
0U, /* 4: CC3S, IC3PSC, IC3F */
0U, /* 5: - NA */
8U, /* 6: CC4S, IC4PSC, IC4F */
0U, /* 7: - NA */
0U, /* 8: - NA */
0U /* 9: - NA */
};
static const uint8_t SHIFT_TAB_CCxP[] =
{
0U, /* 0: CC1P */
2U, /* 1: CC1NP */
4U, /* 2: CC2P */
6U, /* 3: CC2NP */
8U, /* 4: CC3P */
10U, /* 5: CC3NP */
12U, /* 6: CC4P */
14U, /* 7: CC4NP */
16U, /* 8: CC5P */
20U /* 9: CC6P */
};
static const uint8_t SHIFT_TAB_OISx[] =
{
0U, /* 0: OIS1 */
1U, /* 1: OIS1N */
2U, /* 2: OIS2 */
3U, /* 3: OIS2N */
4U, /* 4: OIS3 */
5U, /* 5: OIS3N */
6U, /* 6: OIS4 */
7U, /* 7: OIS4N */
8U, /* 8: OIS5 */
10U /* 9: OIS6 */
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Constants TIM Private Constants
* @{
*/
/* Defines used for the bit position in the register and perform offsets */
#define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FUL)
/* Generic bit definitions for TIMx_AF1 register */
#define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
#define TIMx_AF1_ETRSEL TIM1_AF1_ETRSEL /*!< TIMx ETR source selection */
/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
#define DT_DELAY_1 ((uint8_t)0x7F)
#define DT_DELAY_2 ((uint8_t)0x3F)
#define DT_DELAY_3 ((uint8_t)0x1F)
#define DT_DELAY_4 ((uint8_t)0x1F)
/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
#define DT_RANGE_1 ((uint8_t)0x00)
#define DT_RANGE_2 ((uint8_t)0x80)
#define DT_RANGE_3 ((uint8_t)0xC0)
#define DT_RANGE_4 ((uint8_t)0xE0)
/** Legacy definitions for compatibility purpose
@cond 0
*/
/**
@endcond
*/
#define OCREF_CLEAR_SELECT_Pos (28U)
#define OCREF_CLEAR_SELECT_Msk (0x1U << OCREF_CLEAR_SELECT_Pos) /*!< 0x10000000 */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup TIM_LL_Private_Macros TIM Private Macros
* @{
*/
/** @brief Convert channel id into channel index.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval none
*/
#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
(((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
/** @brief Calculate the deadtime sampling period(in ps).
* @param __TIMCLK__ timer input clock frequency (in Hz).
* @param __CKD__ This parameter can be one of the following values:
* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
* @retval none
*/
#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
(((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
* @{
*/
/**
* @brief TIM Time Base configuration structure definition.
*/
typedef struct
{
uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetPrescaler().*/
uint32_t CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetCounterMode().*/
uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
Some timer instances may support 32 bits counters. In that case this parameter must
be a number between 0x0000 and 0xFFFFFFFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetAutoReload().*/
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetClockDivision().*/
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
GP timers: this parameter must be a number between Min_Data = 0x00 and
Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetRepetitionCounter().*/
} LL_TIM_InitTypeDef;
/**
* @brief TIM Output Compare configuration structure definition.
*/
typedef struct
{
uint32_t OCMode; /*!< Specifies the output mode.
This parameter can be a value of @ref TIM_LL_EC_OCMODE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetMode().*/
uint32_t OCState; /*!< Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
This feature can be modified afterwards using unitary functions
@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
This feature can be modified afterwards using unitary functions
@ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
This feature can be modified afterwards using unitary function
LL_TIM_OC_SetCompareCHx (x=1..6).*/
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetPolarity().*/
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetPolarity().*/
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetIdleState().*/
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetIdleState().*/
} LL_TIM_OC_InitTypeDef;
/**
* @brief TIM Input Capture configuration structure definition.
*/
typedef struct
{
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPolarity().*/
uint32_t ICActiveInput; /*!< Specifies the input.
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetActiveInput().*/
uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPrescaler().*/
uint32_t ICFilter; /*!< Specifies the input capture filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetFilter().*/
} LL_TIM_IC_InitTypeDef;
/**
* @brief TIM Encoder interface configuration structure definition.
*/
typedef struct
{
uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetEncoderMode().*/
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPolarity().*/
uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetActiveInput().*/
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetFilter().*/
uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPolarity().*/
uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetActiveInput().*/
uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetFilter().*/
} LL_TIM_ENCODER_InitTypeDef;
/**
* @brief TIM Hall sensor interface configuration structure definition.
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPolarity().*/
uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
Prescaler must be set to get a maximum counter period longer than the
time interval between 2 consecutive changes on the Hall inputs.
This parameter can be a value of @ref TIM_LL_EC_ICPSC.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetPrescaler().*/
uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
This parameter can be a value of
@ref TIM_LL_EC_IC_FILTER.
This feature can be modified afterwards using unitary function
@ref LL_TIM_IC_SetFilter().*/
uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
A positive pulse (TRGO event) is generated with a programmable delay every time
a change occurs on the Hall inputs.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetCompareCH2().*/
} LL_TIM_HALLSENSOR_InitTypeDef;
/**
* @brief BDTR (Break and Dead Time) structure definition
*/
typedef struct
{
uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
This parameter can be a value of @ref TIM_LL_EC_OSSR
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetOffStates()
@note This bit-field cannot be modified as long as LOCK level 2 has been
programmed. */
uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
This parameter can be a value of @ref TIM_LL_EC_OSSI
This feature can be modified afterwards using unitary function
@ref LL_TIM_SetOffStates()
@note This bit-field cannot be modified as long as LOCK level 2 has been
programmed. */
uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
@note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
register has been written, their content is frozen until the next reset.*/
uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
This feature can be modified afterwards using unitary function
@ref LL_TIM_OC_SetDeadTime()
@note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
programmed. */
uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
This feature can be modified afterwards using unitary function
@ref LL_TIM_ConfigBRK()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
This feature can be modified afterwards using unitary function
@ref LL_TIM_ConfigBRK()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.
This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_ConfigBRK()
@note Bidirectional break input is only supported by advanced timers instances.
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
This feature can be modified afterwards using unitary function
@ref LL_TIM_ConfigBRK2()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
This feature can be modified afterwards using unitary function
@ref LL_TIM_ConfigBRK2()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.
This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_ConfigBRK2()
@note Bidirectional break input is only supported by advanced timers instances.
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
This feature can be modified afterwards using unitary functions
@ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
@note This bit-field can not be modified as long as LOCK level 1 has been
programmed. */
} LL_TIM_BDTR_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
* @{
*/
/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_TIM_ReadReg function.
* @{
*/
#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
#define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
#define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
#define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
#define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
#define LL_TIM_SR_IDXF TIM_SR_IDXF /*!< Index interrupt flag */
#define LL_TIM_SR_DIRF TIM_SR_DIRF /*!< Direction Change interrupt flag */
#define LL_TIM_SR_IERRF TIM_SR_IERRF /*!< Index Error flag */
#define LL_TIM_SR_TERRF TIM_SR_TERRF /*!< Transition Error flag */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
* @{
*/
#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
* @{
*/
#define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
#define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
/**
* @}
*/
/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
* @{
*/
#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup TIM_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
* @{
*/
#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
#define LL_TIM_DIER_IDXIE TIM_DIER_IDXIE /*!< Index interrupt enable */
#define LL_TIM_DIER_DIRIE TIM_DIER_DIRIE /*!< Direction Change interrupt enable */
#define LL_TIM_DIER_IERRIE TIM_DIER_IERRIE /*!< Index Error interrupt enable */
#define LL_TIM_DIER_TERRIE TIM_DIER_TERRIE /*!< Transition Error interrupt enable */
/**
* @}
*/
/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
* @{
*/
#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
* @{
*/
#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
* @{
*/
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
* @{
*/
#define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
#define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
#define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
/**
* @}
*/
/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
* @{
*/
#define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
#define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
* @{
*/
#define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
* @{
*/
#define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
#define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
/**
* @}
*/
/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
* @{
*/
#define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
#define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
#define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
#define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CHANNEL Channel
* @{
*/
#define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
#define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
#define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
#define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
#define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
#define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
#define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
#define LL_TIM_CHANNEL_CH4N TIM_CCER_CC4NE /*!< Timer complementary output channel 4 */
#define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
#define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
* @{
*/
#define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
#define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
* @{
*/
#define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
#define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
#define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
#define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
#define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
#define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
#define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
#define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
#define LL_TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!<Pulse on Compare mode */
#define LL_TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
/**
* @}
*/
/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
* @{
*/
#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
/**
* @}
*/
/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
* @{
*/
#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
#define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
/**
* @}
*/
/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
* @{
*/
#define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
* @{
*/
#define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
#define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
#define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
* @{
*/
#define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
#define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
#define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
#define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
/**
* @}
*/
/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
* @{
*/
#define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
#define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
#define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
#define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
#define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
#define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
#define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
* @{
*/
#define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
#define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
#define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
/**
* @}
*/
/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
* @{
*/
#define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
#define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/
#define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
* @{
*/
#define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
#define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
#define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction - x2 mode */
#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
#define LL_TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
#define LL_TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TRGO Trigger Output
* @{
*/
#define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
#define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
#define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
#define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
#define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
#define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
#define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
#define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
#define LL_TIM_TRGO_ENCODERCLK TIM_CR2_MMS_3 /*!< Encoder clock signal is used as trigger output */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
* @{
*/
#define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
#define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
#define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
#define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
#define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
#define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
* @{
*/
#define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
#define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
#define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
#define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
the counter are controlled. */
/**
* @}
*/
/** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
* @{
*/
#define LL_TIM_SMSPS_TIMUPDATE 0x00000000U /*!< The SMS preload transfer is triggered by the Timer's Update event */
#define LL_TIM_SMSPS_INDEX TIM_SMCR_SMSPS /*!< The SMS preload transfer is triggered by the Index event */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TS Trigger Selection
* @{
*/
#define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
#define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
#define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
#define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
#define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
#define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
#define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
#define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
#define LL_TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR4) is used as trigger input */
#define LL_TIM_TS_ITR5 (TIM_SMCR_TS_3 | TIM_SMCR_TS_0) /*!< Internal Trigger 5 (ITR5) is used as trigger input */
#define LL_TIM_TS_ITR6 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1) /*!< Internal Trigger 6 (ITR6) is used as trigger input */
#define LL_TIM_TS_ITR7 (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 7 (ITR7) is used as trigger input */
#define LL_TIM_TS_ITR8 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2) /*!< Internal Trigger 8 (ITR8) is used as trigger input */
#define LL_TIM_TS_ITR9 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Internal Trigger 9 (ITR9) is used as trigger input */
#define LL_TIM_TS_ITR10 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Internal Trigger 10 (ITR10) is used as trigger input */
#define LL_TIM_TS_ITR11 (TIM_SMCR_TS_3 | TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
* @{
*/
#define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
#define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
* @{
*/
#define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
#define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
#define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
#define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
* @{
*/
#define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
#define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
#define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
#define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
#define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
* @{
*/
#define LL_TIM_TIM1_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM1_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM1_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM1_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
#define LL_TIM_TIM1_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM1_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM1_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM1_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC1 analog watchdog 1 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC1 analog watchdog 2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC1 analog watchdog 3 */
#if defined(ADC4)
#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 1 */
#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC4 analog watchdog 2 */
#define LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC4 analog watchdog 3 */
#endif /* ADC4 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
* @{
*/
#define LL_TIM_TIM2_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM2_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM2_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM2_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
#define LL_TIM_TIM2_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM2_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM2_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM2_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
#if defined(TIM5)
#define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to TIM5 ETR */
#endif /* TIM5 */
#define LL_TIM_TIM2_ETRSOURCE_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to LSE */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
* @{
*/
#define LL_TIM_TIM3_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM3_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM3_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM3_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
#define LL_TIM_TIM3_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM3_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM3_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM3_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM4 ETR */
#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 1 */
#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC2 analog watchdog 2 */
#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 3 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
* @{
*/
#define LL_TIM_TIM4_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM4_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM4_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM4_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
#define LL_TIM_TIM4_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM4_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM4_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM4_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM3 ETR */
#if defined(TIM5)
#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
#endif /* TIM5 */
/**
* @}
*/
#if defined(TIM5)
/** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
* @{
*/
#define LL_TIM_TIM5_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM5_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM5_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM5_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
#define LL_TIM_TIM5_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM5_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM5_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM5_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< ETR input is connected to TIM2 ETR */
#define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM3 ETR */
/**
* @}
*/
#endif /* TIM5 */
/** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
* @{
*/
#define LL_TIM_TIM8_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM8_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM8_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM8_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
#define LL_TIM_TIM8_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM8_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM8_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM8_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC2 analog watchdog 1 */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC2 analog watchdog 2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC2 analog watchdog 3 */
#if defined(ADC3)
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 1 */
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC3 analog watchdog 2 */
#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 3 */
#endif /* ADC3 */
/**
* @}
*/
#if defined(TIM20)
/** @defgroup TIM_LL_EC_TIM20_ETRSOURCE External Trigger Source TIM20
* @{
*/
#define LL_TIM_TIM20_ETRSOURCE_GPIO 0x00000000U /*!< ETR input is connected to GPIO */
#define LL_TIM_TIM20_ETRSOURCE_COMP1 TIM1_AF1_ETRSEL_0 /*!< ETR input is connected to COMP1_OUT */
#define LL_TIM_TIM20_ETRSOURCE_COMP2 TIM1_AF1_ETRSEL_1 /*!< ETR input is connected to COMP2_OUT */
#define LL_TIM_TIM20_ETRSOURCE_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP3_OUT */
#define LL_TIM_TIM20_ETRSOURCE_COMP4 TIM1_AF1_ETRSEL_2 /*!< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM20_ETRSOURCE_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM20_ETRSOURCE_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM20_ETRSOURCE_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#if defined(ADC3)
#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /*!< ADC3 analog watchdog 1 */
#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
#define LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< ADC3 analog watchdog 3 */
#endif /* ADC3 */
#if defined(ADC5)
#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 1 */
#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< ADC5 analog watchdog 2 */
#define LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ADC5 analog watchdog 3 */
#endif /* ADC5 */
/**
* @}
*/
#endif /* TIM20 */
/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
* @{
*/
#define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
#define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
* @{
*/
#define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
#define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
#define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
#define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
* @{
*/
#define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
#define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
* @{
*/
#define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
#define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
#define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
#define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
#define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
#define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
#define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
#define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_OSSI OSSI
* @{
*/
#define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
#define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
/**
* @}
*/
/** @defgroup TIM_LL_EC_OSSR OSSR
* @{
*/
#define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
#define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
* @{
*/
#define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
#define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
* @{
*/
#define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
#define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_AF1_BKCMP1E /*!< internal signal: COMP1 output */
#define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_AF1_BKCMP2E /*!< internal signal: COMP2 output */
#define LL_TIM_BKIN_SOURCE_BKCOMP3 TIM1_AF1_BKCMP3E /*!< internal signal: COMP3 output */
#define LL_TIM_BKIN_SOURCE_BKCOMP4 TIM1_AF1_BKCMP4E /*!< internal signal: COMP4 output */
#if defined(COMP5)
#define LL_TIM_BKIN_SOURCE_BKCOMP5 TIM1_AF1_BKCMP5E /*!< internal signal: COMP5 output */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_BKIN_SOURCE_BKCOMP6 TIM1_AF1_BKCMP6E /*!< internal signal: COMP6 output */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_BKIN_SOURCE_BKCOMP7 TIM1_AF1_BKCMP7E /*!< internal signal: COMP7 output */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
* @{
*/
#define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
#define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
* @{
*/
#define LL_TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
/**
* @}
*/
/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
* @{
*/
#define LL_TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
/**
* @}
*/
/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
* @{
*/
#define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_DTR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_ECR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_ECR register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_TISEL (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_TISEL register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
#define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_OR register is the DMA base address for DMA burst */
/**
* @}
*/
/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
* @{
*/
#define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_19TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1) /*!< Transfer is done to 19 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_20TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 20 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_21TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2) /*!< Transfer is done to 21 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_22TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 22 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_23TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 23 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_24TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_25TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3) /*!< Transfer is done to 25 registers starting from the DMA burst base address */
#define LL_TIM_DMABURST_LENGTH_26TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 26 registers starting from the DMA burst base address */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM1_TI1_RMP_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
#define LL_TIM_TIM1_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
#define LL_TIM_TIM1_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
#define LL_TIM_TIM1_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
#define LL_TIM_TIM1_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_TI1_RMP TIM2 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM2_TI1_RMP_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
#define LL_TIM_TIM2_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
#define LL_TIM_TIM2_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
#define LL_TIM_TIM2_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
#define LL_TIM_TIM2_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM2_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_TI2_RMP TIM2 Timer Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM2_TI2_RMP_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
#define LL_TIM_TIM2_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
#define LL_TIM_TIM2_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
#define LL_TIM_TIM2_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
#define LL_TIM_TIM2_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
#if defined(COMP6)
#define LL_TIM_TIM2_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_TI3_RMP TIM2 Timer Input Ch3 Remap
* @{
*/
#define LL_TIM_TIM2_TI3_RMP_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
#define LL_TIM_TIM2_TI3_RMP_COMP4 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 Timer Input Ch4 Remap
* @{
*/
#define LL_TIM_TIM2_TI4_RMP_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
#define LL_TIM_TIM2_TI4_RMP_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
#define LL_TIM_TIM2_TI4_RMP_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM3_TI1_RMP_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
#define LL_TIM_TIM3_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
#define LL_TIM_TIM3_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
#define LL_TIM_TIM3_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
#define LL_TIM_TIM3_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM3_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM3_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM3_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM3_TI2_RMP TIM3 Timer Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM3_TI2_RMP_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
#define LL_TIM_TIM3_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
#define LL_TIM_TIM3_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
#define LL_TIM_TIM3_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
#define LL_TIM_TIM3_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM3_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM3_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM3_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM3_TI3_RMP TIM3 Timer Input Ch3 Remap
* @{
*/
#define LL_TIM_TIM3_TI3_RMP_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
#define LL_TIM_TIM3_TI3_RMP_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM4_TI1_RMP TIM4 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM4_TI1_RMP_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
#define LL_TIM_TIM4_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
#define LL_TIM_TIM4_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
#define LL_TIM_TIM4_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
#define LL_TIM_TIM4_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM4_TI1_RMP_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM4_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM4_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM4_TI2_RMP TIM4 Timer Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM4_TI2_RMP_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
#define LL_TIM_TIM4_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
#define LL_TIM_TIM4_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
#define LL_TIM_TIM4_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
#define LL_TIM_TIM4_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM4_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM4_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM4_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM4_TI3_RMP TIM4 Timer Input Ch3 Remap
* @{
*/
#define LL_TIM_TIM4_TI3_RMP_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
#if defined(COMP5)
#define LL_TIM_TIM4_TI3_RMP_COMP5 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
#endif /* COMP5 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM4_TI4_RMP TIM4 Timer Input Ch4 Remap
* @{
*/
#define LL_TIM_TIM4_TI4_RMP_GPIO 0x00000000U /*!< TIM4 input 4 is connected to GPIO */
#if defined(COMP6)
#define LL_TIM_TIM4_TI4_RMP_COMP6 TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
#endif /* COMP6 */
/**
* @}
*/
#if defined(TIM5)
/** @defgroup TIM_LL_EC_TIM5_TI1_RMP TIM5 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM5_TI1_RMP_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
#define LL_TIM_TIM5_TI1_RMP_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
#define LL_TIM_TIM5_TI1_RMP_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
#define LL_TIM_TIM5_TI1_RMP_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
#define LL_TIM_TIM5_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
#define LL_TIM_TIM5_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
#define LL_TIM_TIM5_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
#define LL_TIM_TIM5_TI1_RMP_COMP4 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM5_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM5_TI1_RMP_COMP6 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM5_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM5_TI2_RMP TIM5 Timer Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM5_TI2_RMP_GPIO 0x00000000U /*!< TIM5 input 2 is connected to GPIO */
#define LL_TIM_TIM5_TI2_RMP_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
#define LL_TIM_TIM5_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
#define LL_TIM_TIM5_TI2_RMP_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
#define LL_TIM_TIM5_TI2_RMP_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_TIM5_TI2_RMP_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_TIM5_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM5_TI2_RMP_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
#endif /* TIM5 */
/** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM8_TI1_RMP_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
#define LL_TIM_TIM8_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
#define LL_TIM_TIM8_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
#define LL_TIM_TIM8_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
#define LL_TIM_TIM8_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM15_TI1_RMP_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
#define LL_TIM_TIM15_TI1_RMP_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
#define LL_TIM_TIM15_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
#define LL_TIM_TIM15_TI1_RMP_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
#if defined(COMP5)
#define LL_TIM_TIM15_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP7)
#define LL_TIM_TIM15_TI1_RMP_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM15_TI2_RMP TIM15 Timer Input Ch2 Remap
* @{
*/
#define LL_TIM_TIM15_TI2_RMP_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
#define LL_TIM_TIM15_TI2_RMP_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
#define LL_TIM_TIM15_TI2_RMP_COMP3 TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
#if defined(COMP6)
#define LL_TIM_TIM15_TI2_RMP_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_TIM15_TI2_RMP_COMP7 TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM16_TI1_RMP_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
#if defined(COMP6)
#define LL_TIM_TIM16_TI1_RMP_COMP6 TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
#endif /* COMP6 */
#define LL_TIM_TIM16_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
#define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
#define LL_TIM_TIM16_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
#define LL_TIM_TIM16_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
#define LL_TIM_TIM16_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
/**
* @}
*/
/** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM17_TI1_RMP_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
#if defined(COMP5)
#define LL_TIM_TIM17_TI1_RMP_COMP5 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#define LL_TIM_TIM17_TI1_RMP_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
#define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
#define LL_TIM_TIM17_TI1_RMP_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
#define LL_TIM_TIM17_TI1_RMP_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
#define LL_TIM_TIM17_TI1_RMP_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
/**
* @}
*/
#if defined(TIM20)
/** @defgroup TIM_LL_EC_TIM20_TI1_RMP TIM20 Timer Input Ch1 Remap
* @{
*/
#define LL_TIM_TIM20_TI1_RMP_GPIO 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
#define LL_TIM_TIM20_TI1_RMP_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
#define LL_TIM_TIM20_TI1_RMP_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
#define LL_TIM_TIM20_TI1_RMP_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
#define LL_TIM_TIM20_TI1_RMP_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
/**
* @}
*/
#endif /* TIM20 */
/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
* @{
*/
#define LL_TIM_OCREF_CLR_INT_ETR OCREF_CLEAR_SELECT_Msk /*!< OCREF_CLR_INT is connected to ETRF */
#define LL_TIM_OCREF_CLR_INT_COMP1 0x00000000U /*!< OCREF clear input is connected to COMP1_OUT */
#define LL_TIM_OCREF_CLR_INT_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF clear input is connected to COMP2_OUT */
#define LL_TIM_OCREF_CLR_INT_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF clear input is connected to COMP3_OUT */
#define LL_TIM_OCREF_CLR_INT_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP4_OUT */
#if defined(COMP5)
#define LL_TIM_OCREF_CLR_INT_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF clear input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define LL_TIM_OCREF_CLR_INT_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF clear input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define LL_TIM_OCREF_CLR_INT_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF clear input is connected to COMP7_OUT */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
* @{
*/
#define LL_TIM_INDEX_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
#define LL_TIM_INDEX_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
#define LL_TIM_INDEX_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
/**
* @}
*/
/** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
* @{
*/
#define LL_TIM_INDEX_POSITION_DOWN_DOWN 0x00000000U /*!< Index resets the counter when AB = 00 */
#define LL_TIM_INDEX_POSITION_DOWN_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when AB = 01 */
#define LL_TIM_INDEX_POSITION_UP_DOWN TIM_ECR_IPOS_1 /*!< Index resets the counter when AB = 10 */
#define LL_TIM_INDEX_POSITION_UP_UP (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Index resets the counter when AB = 11 */
#define LL_TIM_INDEX_POSITION_DOWN 0x00000000U /*!< Index resets the counter when clock is 0 */
#define LL_TIM_INDEX_POSITION_UP TIM_ECR_IPOS_0 /*!< Index resets the counter when clock is 1 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
* @{
*/
#define LL_TIM_INDEX_ALL 0x00000000U /*!< Index is always active */
#define LL_TIM_INDEX_FIRST_ONLY TIM_ECR_FIDX /*!< The first Index only resets the counter */
/**
* @}
*/
/** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
* @{
*/
#define LL_TIM_PWPRSC_X1 0x00000000U /*!< Pulse on compare pulse width prescaler 1 */
#define LL_TIM_PWPRSC_X2 TIM_ECR_PWPRSC_0 /*!< Pulse on compare pulse width prescaler 2 */
#define LL_TIM_PWPRSC_X4 TIM_ECR_PWPRSC_1 /*!< Pulse on compare pulse width prescaler 4 */
#define LL_TIM_PWPRSC_X8 (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 8 */
#define LL_TIM_PWPRSC_X16 TIM_ECR_PWPRSC_2 /*!< Pulse on compare pulse width prescaler 16 */
#define LL_TIM_PWPRSC_X32 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 32 */
#define LL_TIM_PWPRSC_X64 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1) /*!< Pulse on compare pulse width prescaler 64 */
#define LL_TIM_PWPRSC_X128 (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
/**
* @}
*/
/** @defgroup TIM_LL_EC_HSE_32_REQUEST Clock HSE/32 request
* @{
*/
#define LL_TIM_HSE_32_NOT_REQUEST 0x00000000U /*!< Clock HSE/32 not requested */
#define LL_TIM_HSE_32_REQUEST TIM_OR_HSE32EN /*!< Clock HSE/32 requested for TIM16/17 TI1SEL remap */
/**
* @}
*/
/** Legacy definitions for compatibility purpose
@cond 0
*/
#define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK
/**
@endcond
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
* @{
*/
/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in TIM register.
* @param __INSTANCE__ TIM Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in TIM register.
* @param __INSTANCE__ TIM Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
* @{
*/
/**
* @brief HELPER macro retrieving the UIFCPY flag from the counter value.
* @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
* @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
* to TIMx_CNT register bit 31)
* @param __CNT__ Counter value
* @retval UIF status bit
*/
#define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
(READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
/**
* @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
* @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __CKD__ This parameter can be one of the following values:
* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
* @param __DT__ deadtime duration (in ns)
* @retval DTG[0:7]
*/
#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
(uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
(((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
(uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
(__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
(((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
(uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
(__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
(((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \
(uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \
(__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
0U)
/**
* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
* @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __CNTCLK__ counter clock frequency (in Hz)
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
(((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
* @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __FREQ__ output signal frequency (in Hz)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
/**
* @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
* output signal frequency.
* @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __FREQ__ output signal frequency (in Hz)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
(uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare
* active/inactive delay.
* @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
* output compare active/inactive delay.
* @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
* (when the timer operates in one pulse mode).
* @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @param __PULSE__ pulse duration (in us)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
* pulse duration (when the timer operates in one pulse mode).
* @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @param __PULSE__ pulse duration (in us)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro retrieving the ratio of the input capture prescaler
* @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
* @param __ICPSC__ This parameter can be one of the following values:
* @arg @ref LL_TIM_ICPSC_DIV1
* @arg @ref LL_TIM_ICPSC_DIV2
* @arg @ref LL_TIM_ICPSC_DIV4
* @arg @ref LL_TIM_ICPSC_DIV8
* @retval Input capture prescaler ratio (1, 2, 4 or 8)
*/
#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
* @{
*/
/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
* @{
*/
/**
* @brief Enable timer counter.
* @rmtoll CR1 CEN LL_TIM_EnableCounter
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_CEN);
}
/**
* @brief Disable timer counter.
* @rmtoll CR1 CEN LL_TIM_DisableCounter
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
}
/**
* @brief Indicates whether the timer counter is enabled.
* @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
}
/**
* @brief Enable update event generation.
* @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
* @brief Disable update event generation.
* @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
* @brief Indicates whether update event generation is enabled.
* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
* @param TIMx Timer instance
* @retval Inverted state of bit (0 or 1).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
}
/**
* @brief Set update event source
* @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
* generate an update interrupt or DMA request if enabled:
* - Counter overflow/underflow
* - Setting the UG bit
* - Update generation through the slave mode controller
* @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
* overflow/underflow generates an update interrupt or DMA request if enabled.
* @rmtoll CR1 URS LL_TIM_SetUpdateSource
* @param TIMx Timer instance
* @param UpdateSource This parameter can be one of the following values:
* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
{
MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
}
/**
* @brief Get actual event update source
* @rmtoll CR1 URS LL_TIM_GetUpdateSource
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_UPDATESOURCE_REGULAR
* @arg @ref LL_TIM_UPDATESOURCE_COUNTER
*/
__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
}
/**
* @brief Set one pulse mode (one shot v.s. repetitive).
* @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
* @param TIMx Timer instance
* @param OnePulseMode This parameter can be one of the following values:
* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
{
MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
}
/**
* @brief Get actual one pulse mode.
* @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
* @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
*/
__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
}
/**
* @brief Set the timer counter counting mode.
* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
* requires a timer reset to avoid unexpected direction
* due to DIR bit readonly in center aligned mode.
* @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
* CR1 CMS LL_TIM_SetCounterMode
* @param TIMx Timer instance
* @param CounterMode This parameter can be one of the following values:
* @arg @ref LL_TIM_COUNTERMODE_UP
* @arg @ref LL_TIM_COUNTERMODE_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
{
MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
}
/**
* @brief Get actual counter mode.
* @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
* check whether or not the counter mode selection feature is supported
* by a timer instance.
* @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
* CR1 CMS LL_TIM_GetCounterMode
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_COUNTERMODE_UP
* @arg @ref LL_TIM_COUNTERMODE_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
* @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
* @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
{
uint32_t counter_mode;
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
if (counter_mode == 0U)
{
counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
}
return counter_mode;
}
/**
* @brief Enable auto-reload (ARR) preload.
* @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
}
/**
* @brief Disable auto-reload (ARR) preload.
* @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
}
/**
* @brief Indicates whether auto-reload (ARR) preload is enabled.
* @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
}
/**
* @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators
* (when supported) and the digital filters.
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_SetClockDivision
* @param TIMx Timer instance
* @param ClockDivision This parameter can be one of the following values:
* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
{
MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
}
/**
* @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time
* generators (when supported) and the digital filters.
* @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
* whether or not the clock division feature is supported by the timer
* instance.
* @rmtoll CR1 CKD LL_TIM_GetClockDivision
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_CLOCKDIVISION_DIV1
* @arg @ref LL_TIM_CLOCKDIVISION_DIV2
* @arg @ref LL_TIM_CLOCKDIVISION_DIV4
*/
__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
}
/**
* @brief Set the counter value.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the Counter value interpretation
* @rmtoll CNT CNT LL_TIM_SetCounter
* @param TIMx Timer instance
* @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
{
WRITE_REG(TIMx->CNT, Counter);
}
/**
* @brief Get the counter value.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the Counter value interpretation
* @rmtoll CNT CNT LL_TIM_GetCounter
* @param TIMx Timer instance
* @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
*/
__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CNT));
}
/**
* @brief Get the current direction of the counter
* @rmtoll CR1 DIR LL_TIM_GetDirection
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_COUNTERDIRECTION_UP
* @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
*/
__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
}
/**
* @brief Set the prescaler value.
* @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
* @note The prescaler can be changed on the fly as this control register is buffered. The new
* prescaler ratio is taken into account at the next update event.
* @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
* @rmtoll PSC PSC LL_TIM_SetPrescaler
* @param TIMx Timer instance
* @param Prescaler between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
{
WRITE_REG(TIMx->PSC, Prescaler);
}
/**
* @brief Get the prescaler value.
* @rmtoll PSC PSC LL_TIM_GetPrescaler
* @param TIMx Timer instance
* @retval Prescaler value between Min_Data=0 and Max_Data=65535
*/
__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->PSC));
}
/**
* @brief Set the auto-reload value.
* @note The counter is blocked while the auto-reload value is null.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
* In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
* parameter.
* @rmtoll ARR ARR LL_TIM_SetAutoReload
* @param TIMx Timer instance
* @param AutoReload between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
{
WRITE_REG(TIMx->ARR, AutoReload);
}
/**
* @brief Get the auto-reload value.
* @rmtoll ARR ARR LL_TIM_GetAutoReload
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note If dithering is activated, pay attention to the returned value interpretation
* @param TIMx Timer instance
* @retval Auto-reload value
*/
__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->ARR));
}
/**
* @brief Set the repetition counter value.
* @note For advanced timer instances RepetitionCounter can be up to 65535.
* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_SetRepetitionCounter
* @param TIMx Timer instance
* @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
{
WRITE_REG(TIMx->RCR, RepetitionCounter);
}
/**
* @brief Get the repetition counter value.
* @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a repetition counter.
* @rmtoll RCR REP LL_TIM_GetRepetitionCounter
* @param TIMx Timer instance
* @retval Repetition counter value
*/
__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->RCR));
}
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
* in an atomic way.
* @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
}
/**
* @brief Disable update interrupt flag (UIF) remapping.
* @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
}
/**
* @brief Indicate whether update interrupt flag (UIF) copy is set.
* @param Counter Counter value
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)
{
return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
}
/**
* @brief Enable dithering.
* @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides dithering.
* @rmtoll CR1 DITHEN LL_TIM_EnableDithering
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
}
/**
* @brief Disable dithering.
* @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides dithering.
* @rmtoll CR1 DITHEN LL_TIM_DisableDithering
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
}
/**
* @brief Indicates whether dithering is activated.
* @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides dithering.
* @rmtoll CR1 DITHEN LL_TIM_IsEnabledDithering
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
* @{
*/
/**
* @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
* @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
* they are updated only when a commutation event (COM) occurs.
* @note Only on channels that have a complementary output.
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
}
/**
* @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
}
/**
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
* whether or not a timer instance is able to generate a commutation event.
* @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
* @param TIMx Timer instance
* @param CCUpdateSource This parameter can be one of the following values:
* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
* @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
{
MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
}
/**
* @brief Set the trigger of the capture/compare DMA request.
* @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
* @param TIMx Timer instance
* @param DMAReqTrigger This parameter can be one of the following values:
* @arg @ref LL_TIM_CCDMAREQUEST_CC
* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
{
MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
}
/**
* @brief Get actual trigger of the capture/compare DMA request.
* @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_CCDMAREQUEST_CC
* @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
*/
__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
}
/**
* @brief Set the lock level to freeze the
* configuration of several capture/compare parameters.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* the lock mechanism is supported by a timer instance.
* @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
* @param TIMx Timer instance
* @param LockLevel This parameter can be one of the following values:
* @arg @ref LL_TIM_LOCKLEVEL_OFF
* @arg @ref LL_TIM_LOCKLEVEL_1
* @arg @ref LL_TIM_LOCKLEVEL_2
* @arg @ref LL_TIM_LOCKLEVEL_3
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
}
/**
* @brief Enable capture/compare channels.
* @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
* CCER CC1NE LL_TIM_CC_EnableChannel\n
* CCER CC2E LL_TIM_CC_EnableChannel\n
* CCER CC2NE LL_TIM_CC_EnableChannel\n
* CCER CC3E LL_TIM_CC_EnableChannel\n
* CCER CC3NE LL_TIM_CC_EnableChannel\n
* CCER CC4E LL_TIM_CC_EnableChannel\n
* CCER CC4NE LL_TIM_CC_EnableChannel\n
* CCER CC5E LL_TIM_CC_EnableChannel\n
* CCER CC6E LL_TIM_CC_EnableChannel
* @param TIMx Timer instance
* @param Channels This parameter can be a combination of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
SET_BIT(TIMx->CCER, Channels);
}
/**
* @brief Disable capture/compare channels.
* @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
* CCER CC1NE LL_TIM_CC_DisableChannel\n
* CCER CC2E LL_TIM_CC_DisableChannel\n
* CCER CC2NE LL_TIM_CC_DisableChannel\n
* CCER CC3E LL_TIM_CC_DisableChannel\n
* CCER CC3NE LL_TIM_CC_DisableChannel\n
* CCER CC4E LL_TIM_CC_DisableChannel\n
* CCER CC4NE LL_TIM_CC_DisableChannel\n
* CCER CC5E LL_TIM_CC_DisableChannel\n
* CCER CC6E LL_TIM_CC_DisableChannel
* @param TIMx Timer instance
* @param Channels This parameter can be a combination of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
CLEAR_BIT(TIMx->CCER, Channels);
}
/**
* @brief Indicate whether channel(s) is(are) enabled.
* @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
* CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
* CCER CC2E LL_TIM_CC_IsEnabledChannel\n
* CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
* CCER CC3E LL_TIM_CC_IsEnabledChannel\n
* CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
* CCER CC4E LL_TIM_CC_IsEnabledChannel\n
* CCER CC4NE LL_TIM_CC_IsEnabledChannel\n
* CCER CC5E LL_TIM_CC_IsEnabledChannel\n
* CCER CC6E LL_TIM_CC_IsEnabledChannel
* @param TIMx Timer instance
* @param Channels This parameter can be a combination of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
{
return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
* @{
*/
/**
* @brief Configure an output channel.
* @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
* CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
* CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
* CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
* CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
* CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
* CCER CC1P LL_TIM_OC_ConfigOutput\n
* CCER CC2P LL_TIM_OC_ConfigOutput\n
* CCER CC3P LL_TIM_OC_ConfigOutput\n
* CCER CC4P LL_TIM_OC_ConfigOutput\n
* CCER CC5P LL_TIM_OC_ConfigOutput\n
* CCER CC6P LL_TIM_OC_ConfigOutput\n
* CR2 OIS1 LL_TIM_OC_ConfigOutput\n
* CR2 OIS2 LL_TIM_OC_ConfigOutput\n
* CR2 OIS3 LL_TIM_OC_ConfigOutput\n
* CR2 OIS4 LL_TIM_OC_ConfigOutput\n
* CR2 OIS5 LL_TIM_OC_ConfigOutput\n
* CR2 OIS6 LL_TIM_OC_ConfigOutput
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
* @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
(Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
(Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
}
/**
* @brief Define the behavior of the output reference signal OCxREF from which
* OCx and OCxN (when relevant) are derived.
* @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
* CCMR1 OC2M LL_TIM_OC_SetMode\n
* CCMR2 OC3M LL_TIM_OC_SetMode\n
* CCMR2 OC4M LL_TIM_OC_SetMode\n
* CCMR3 OC5M LL_TIM_OC_SetMode\n
* CCMR3 OC6M LL_TIM_OC_SetMode
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_TIM_OCMODE_FROZEN
* @arg @ref LL_TIM_OCMODE_ACTIVE
* @arg @ref LL_TIM_OCMODE_INACTIVE
* @arg @ref LL_TIM_OCMODE_TOGGLE
* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
* @arg @ref LL_TIM_OCMODE_PWM1
* @arg @ref LL_TIM_OCMODE_PWM2
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
* @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
* @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
}
/**
* @brief Get the output compare mode of an output channel.
* @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
* CCMR1 OC2M LL_TIM_OC_GetMode\n
* CCMR2 OC3M LL_TIM_OC_GetMode\n
* CCMR2 OC4M LL_TIM_OC_GetMode\n
* CCMR3 OC5M LL_TIM_OC_GetMode\n
* CCMR3 OC6M LL_TIM_OC_GetMode
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_OCMODE_FROZEN
* @arg @ref LL_TIM_OCMODE_ACTIVE
* @arg @ref LL_TIM_OCMODE_INACTIVE
* @arg @ref LL_TIM_OCMODE_TOGGLE
* @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
* @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
* @arg @ref LL_TIM_OCMODE_PWM1
* @arg @ref LL_TIM_OCMODE_PWM2
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
* @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE (for channel 3 or channel 4 only)
* @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT (for channel 3 or channel 4 only)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
}
/**
* @brief Set the polarity of an output channel.
* @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
* CCER CC1NP LL_TIM_OC_SetPolarity\n
* CCER CC2P LL_TIM_OC_SetPolarity\n
* CCER CC2NP LL_TIM_OC_SetPolarity\n
* CCER CC3P LL_TIM_OC_SetPolarity\n
* CCER CC3NP LL_TIM_OC_SetPolarity\n
* CCER CC4P LL_TIM_OC_SetPolarity\n
* CCER CC4NP LL_TIM_OC_SetPolarity\n
* CCER CC5P LL_TIM_OC_SetPolarity\n
* CCER CC6P LL_TIM_OC_SetPolarity
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_TIM_OCPOLARITY_HIGH
* @arg @ref LL_TIM_OCPOLARITY_LOW
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Get the polarity of an output channel.
* @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
* CCER CC1NP LL_TIM_OC_GetPolarity\n
* CCER CC2P LL_TIM_OC_GetPolarity\n
* CCER CC2NP LL_TIM_OC_GetPolarity\n
* CCER CC3P LL_TIM_OC_GetPolarity\n
* CCER CC3NP LL_TIM_OC_GetPolarity\n
* CCER CC4P LL_TIM_OC_GetPolarity\n
* CCER CC4NP LL_TIM_OC_GetPolarity\n
* CCER CC5P LL_TIM_OC_GetPolarity\n
* CCER CC6P LL_TIM_OC_GetPolarity
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_OCPOLARITY_HIGH
* @arg @ref LL_TIM_OCPOLARITY_LOW
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Set the IDLE state of an output channel
* @note This function is significant only for the timer instances
* supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
* can be used to check whether or not a timer instance provides
* a break input.
* @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
* CR2 OIS2N LL_TIM_OC_SetIdleState\n
* CR2 OIS2 LL_TIM_OC_SetIdleState\n
* CR2 OIS2N LL_TIM_OC_SetIdleState\n
* CR2 OIS3 LL_TIM_OC_SetIdleState\n
* CR2 OIS3N LL_TIM_OC_SetIdleState\n
* CR2 OIS4 LL_TIM_OC_SetIdleState\n
* CR2 OIS4N LL_TIM_OC_SetIdleState\n
* CR2 OIS5 LL_TIM_OC_SetIdleState\n
* CR2 OIS6 LL_TIM_OC_SetIdleState
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @param IdleState This parameter can be one of the following values:
* @arg @ref LL_TIM_OCIDLESTATE_LOW
* @arg @ref LL_TIM_OCIDLESTATE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
}
/**
* @brief Get the IDLE state of an output channel
* @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
* CR2 OIS2N LL_TIM_OC_GetIdleState\n
* CR2 OIS2 LL_TIM_OC_GetIdleState\n
* CR2 OIS2N LL_TIM_OC_GetIdleState\n
* CR2 OIS3 LL_TIM_OC_GetIdleState\n
* CR2 OIS3N LL_TIM_OC_GetIdleState\n
* CR2 OIS4 LL_TIM_OC_GetIdleState\n
* CR2 OIS4N LL_TIM_OC_GetIdleState\n
* CR2 OIS5 LL_TIM_OC_GetIdleState\n
* CR2 OIS6 LL_TIM_OC_GetIdleState
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH1N
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH2N
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH3N
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH4N
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_OCIDLESTATE_LOW
* @arg @ref LL_TIM_OCIDLESTATE_HIGH
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
}
/**
* @brief Enable fast mode for the output channel.
* @note Acts only if the channel is configured in PWM1 or PWM2 mode.
* @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
* CCMR1 OC2FE LL_TIM_OC_EnableFast\n
* CCMR2 OC3FE LL_TIM_OC_EnableFast\n
* CCMR2 OC4FE LL_TIM_OC_EnableFast\n
* CCMR3 OC5FE LL_TIM_OC_EnableFast\n
* CCMR3 OC6FE LL_TIM_OC_EnableFast
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Disable fast mode for the output channel.
* @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
* CCMR1 OC2FE LL_TIM_OC_DisableFast\n
* CCMR2 OC3FE LL_TIM_OC_DisableFast\n
* CCMR2 OC4FE LL_TIM_OC_DisableFast\n
* CCMR3 OC5FE LL_TIM_OC_DisableFast\n
* CCMR3 OC6FE LL_TIM_OC_DisableFast
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Indicates whether fast mode is enabled for the output channel.
* @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
* CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
* CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
* CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
* CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
* CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Enable compare register (TIMx_CCRx) preload for the output channel.
* @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
* CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
* CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
* CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
* CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
* CCMR3 OC6PE LL_TIM_OC_EnablePreload
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Disable compare register (TIMx_CCRx) preload for the output channel.
* @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
* CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
* CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
* CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
* CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
* CCMR3 OC6PE LL_TIM_OC_DisablePreload
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
* @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
* CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
* CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
* CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
* CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
* CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Enable clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
* CCMR1 OC2CE LL_TIM_OC_EnableClear\n
* CCMR2 OC3CE LL_TIM_OC_EnableClear\n
* CCMR2 OC4CE LL_TIM_OC_EnableClear\n
* CCMR3 OC5CE LL_TIM_OC_EnableClear\n
* CCMR3 OC6CE LL_TIM_OC_EnableClear
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Disable clearing the output channel on an external event.
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
* CCMR1 OC2CE LL_TIM_OC_DisableClear\n
* CCMR2 OC3CE LL_TIM_OC_DisableClear\n
* CCMR2 OC4CE LL_TIM_OC_DisableClear\n
* CCMR3 OC5CE LL_TIM_OC_DisableClear\n
* CCMR3 OC6CE LL_TIM_OC_DisableClear
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
}
/**
* @brief Indicates clearing the output channel on an external event is enabled for the output channel.
* @note This function enables clearing the output channel on an external event.
* @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
* @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can clear the OCxREF signal on an external event.
* @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
* CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
* CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
* CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
* CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
* CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @arg @ref LL_TIM_CHANNEL_CH5
* @arg @ref LL_TIM_CHANNEL_CH6
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
}
/**
* @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
* the Ocx and OCxN signals).
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
* @param TIMx Timer instance
* @param DeadTime between Min_Data=0 and Max_Data=255
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
}
/**
* @brief Set compare value for output channel 1 (TIMx_CCR1).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR1, CompareValue);
}
/**
* @brief Set compare value for output channel 2 (TIMx_CCR2).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR2, CompareValue);
}
/**
* @brief Set compare value for output channel 3 (TIMx_CCR3).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR3, CompareValue);
}
/**
* @brief Set compare value for output channel 4 (TIMx_CCR4).
* @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR4, CompareValue);
}
/**
* @brief Set compare value for output channel 5 (TIMx_CCR5).
* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
}
/**
* @brief Set compare value for output channel 6 (TIMx_CCR6).
* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
* @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
* @param TIMx Timer instance
* @param CompareValue between Min_Data=0 and Max_Data=65535
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
{
WRITE_REG(TIMx->CCR6, CompareValue);
}
/**
* @brief Get compare value (TIMx_CCR1) set for output channel 1.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* output channel 1 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR1));
}
/**
* @brief Get compare value (TIMx_CCR2) set for output channel 2.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* output channel 2 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR2));
}
/**
* @brief Get compare value (TIMx_CCR3) set for output channel 3.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* output channel 3 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR3));
}
/**
* @brief Get compare value (TIMx_CCR4) set for output channel 4.
* @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* output channel 4 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR4));
}
/**
* @brief Get compare value (TIMx_CCR5) set for output channel 5.
* @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
* output channel 5 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
}
/**
* @brief Get compare value (TIMx_CCR6) set for output channel 6.
* @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
* output channel 6 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
* @param TIMx Timer instance
* @retval CompareValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR6));
}
/**
* @brief Select on which reference signal the OC5REF is combined to.
* @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the combined 3-phase PWM mode.
* @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
* CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
* @param TIMx Timer instance
* @param GroupCH5 This parameter can be a combination of the following values:
* @arg @ref LL_TIM_GROUPCH5_NONE
* @arg @ref LL_TIM_GROUPCH5_OC1REFC
* @arg @ref LL_TIM_GROUPCH5_OC2REFC
* @arg @ref LL_TIM_GROUPCH5_OC3REFC
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
{
MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
}
/**
* @brief Set the pulse on compare pulse width prescaler.
* @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PWPRSC LL_TIM_OC_SetPulseWidthPrescaler
* @param TIMx Timer instance
* @param PulseWidthPrescaler This parameter can be one of the following values:
* @arg @ref LL_TIM_PWPRSC_X1
* @arg @ref LL_TIM_PWPRSC_X2
* @arg @ref LL_TIM_PWPRSC_X4
* @arg @ref LL_TIM_PWPRSC_X8
* @arg @ref LL_TIM_PWPRSC_X16
* @arg @ref LL_TIM_PWPRSC_X32
* @arg @ref LL_TIM_PWPRSC_X64
* @arg @ref LL_TIM_PWPRSC_X128
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
}
/**
* @brief Get the pulse on compare pulse width prescaler.
* @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PWPRSC LL_TIM_OC_GetPulseWidthPrescaler
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_PWPRSC_X1
* @arg @ref LL_TIM_PWPRSC_X2
* @arg @ref LL_TIM_PWPRSC_X4
* @arg @ref LL_TIM_PWPRSC_X8
* @arg @ref LL_TIM_PWPRSC_X16
* @arg @ref LL_TIM_PWPRSC_X32
* @arg @ref LL_TIM_PWPRSC_X64
* @arg @ref LL_TIM_PWPRSC_X128
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
}
/**
* @brief Set the pulse on compare pulse width duration.
* @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PW LL_TIM_OC_SetPulseWidth
* @param TIMx Timer instance
* @param PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
* @retval None
*/
__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
}
/**
* @brief Get the pulse on compare pulse width duration.
* @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
* whether or not the pulse on compare feature is supported by the timer
* instance.
* @rmtoll ECR PW LL_TIM_OC_GetPulseWidth
* @param TIMx Timer instance
* @retval Returned value can be between Min_Data=0 and Max_Data=255:
*/
__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
* @{
*/
/**
* @brief Configure input channel.
* @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
* CCMR1 IC1PSC LL_TIM_IC_Config\n
* CCMR1 IC1F LL_TIM_IC_Config\n
* CCMR1 CC2S LL_TIM_IC_Config\n
* CCMR1 IC2PSC LL_TIM_IC_Config\n
* CCMR1 IC2F LL_TIM_IC_Config\n
* CCMR2 CC3S LL_TIM_IC_Config\n
* CCMR2 IC3PSC LL_TIM_IC_Config\n
* CCMR2 IC3F LL_TIM_IC_Config\n
* CCMR2 CC4S LL_TIM_IC_Config\n
* CCMR2 IC4PSC LL_TIM_IC_Config\n
* CCMR2 IC4F LL_TIM_IC_Config\n
* CCER CC1P LL_TIM_IC_Config\n
* CCER CC1NP LL_TIM_IC_Config\n
* CCER CC2P LL_TIM_IC_Config\n
* CCER CC2NP LL_TIM_IC_Config\n
* CCER CC3P LL_TIM_IC_Config\n
* CCER CC3NP LL_TIM_IC_Config\n
* CCER CC4P LL_TIM_IC_Config\n
* CCER CC4NP LL_TIM_IC_Config
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
* @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
* @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
* @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \
<< SHIFT_TAB_ICxx[iChannel]);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
(Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Set the active input.
* @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
* CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
* CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
* CCMR2 CC4S LL_TIM_IC_SetActiveInput
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param ICActiveInput This parameter can be one of the following values:
* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_TRC
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
/**
* @brief Get the current active input.
* @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
* CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
* CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
* CCMR2 CC4S LL_TIM_IC_GetActiveInput
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
* @arg @ref LL_TIM_ACTIVEINPUT_TRC
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
/**
* @brief Set the prescaler of input channel.
* @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
* CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
* CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
* CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param ICPrescaler This parameter can be one of the following values:
* @arg @ref LL_TIM_ICPSC_DIV1
* @arg @ref LL_TIM_ICPSC_DIV2
* @arg @ref LL_TIM_ICPSC_DIV4
* @arg @ref LL_TIM_ICPSC_DIV8
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
/**
* @brief Get the current prescaler value acting on an input channel.
* @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
* CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
* CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
* CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_ICPSC_DIV1
* @arg @ref LL_TIM_ICPSC_DIV2
* @arg @ref LL_TIM_ICPSC_DIV4
* @arg @ref LL_TIM_ICPSC_DIV8
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
/**
* @brief Set the input filter duration.
* @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
* CCMR1 IC2F LL_TIM_IC_SetFilter\n
* CCMR2 IC3F LL_TIM_IC_SetFilter\n
* CCMR2 IC4F LL_TIM_IC_SetFilter
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param ICFilter This parameter can be one of the following values:
* @arg @ref LL_TIM_IC_FILTER_FDIV1
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
}
/**
* @brief Get the input filter duration.
* @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
* CCMR1 IC2F LL_TIM_IC_GetFilter\n
* CCMR2 IC3F LL_TIM_IC_GetFilter\n
* CCMR2 IC4F LL_TIM_IC_GetFilter
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_IC_FILTER_FDIV1
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
* @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
* @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
}
/**
* @brief Set the input channel polarity.
* @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
* CCER CC1NP LL_TIM_IC_SetPolarity\n
* CCER CC2P LL_TIM_IC_SetPolarity\n
* CCER CC2NP LL_TIM_IC_SetPolarity\n
* CCER CC3P LL_TIM_IC_SetPolarity\n
* CCER CC3NP LL_TIM_IC_SetPolarity\n
* CCER CC4P LL_TIM_IC_SetPolarity\n
* CCER CC4NP LL_TIM_IC_SetPolarity
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @param ICPolarity This parameter can be one of the following values:
* @arg @ref LL_TIM_IC_POLARITY_RISING
* @arg @ref LL_TIM_IC_POLARITY_FALLING
* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
ICPolarity << SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Get the current input channel polarity.
* @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
* CCER CC1NP LL_TIM_IC_GetPolarity\n
* CCER CC2P LL_TIM_IC_GetPolarity\n
* CCER CC2NP LL_TIM_IC_GetPolarity\n
* CCER CC3P LL_TIM_IC_GetPolarity\n
* CCER CC3NP LL_TIM_IC_GetPolarity\n
* CCER CC4P LL_TIM_IC_GetPolarity\n
* CCER CC4NP LL_TIM_IC_GetPolarity
* @param TIMx Timer instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_TIM_CHANNEL_CH1
* @arg @ref LL_TIM_CHANNEL_CH2
* @arg @ref LL_TIM_CHANNEL_CH3
* @arg @ref LL_TIM_CHANNEL_CH4
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_IC_POLARITY_RISING
* @arg @ref LL_TIM_IC_POLARITY_FALLING
* @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
{
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
SHIFT_TAB_CCxP[iChannel]);
}
/**
* @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
}
/**
* @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
}
/**
* @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
* @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an XOR input.
* @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
}
/**
* @brief Get captured value for input channel 1.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
* input channel 1 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR1));
}
/**
* @brief Get captured value for input channel 2.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
* input channel 2 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR2));
}
/**
* @brief Get captured value for input channel 3.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
* input channel 3 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR3));
}
/**
* @brief Get captured value for input channel 4.
* @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
* @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports a 32 bits counter.
* @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
* input channel 4 is supported by a timer instance.
* @note If dithering is activated, pay attention to the returned value interpretation.
* @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
* @param TIMx Timer instance
* @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
*/
__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_REG(TIMx->CCR4));
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
* @{
*/
/**
* @brief Enable external clock mode 2.
* @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_EnableExternalClock
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
}
/**
* @brief Disable external clock mode 2.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_DisableExternalClock
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
}
/**
* @brief Indicate whether external clock mode 2 is enabled.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
}
/**
* @brief Set the clock source of the counter clock.
* @note when selected clock source is external clock mode 1, the timer input
* the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
* function. This timer input must be configured by calling
* the @ref LL_TIM_IC_Config() function.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode1.
* @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports external clock mode2.
* @rmtoll SMCR SMS LL_TIM_SetClockSource\n
* SMCR ECE LL_TIM_SetClockSource
* @param TIMx Timer instance
* @param ClockSource This parameter can be one of the following values:
* @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
* @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
}
/**
* @brief Set the encoder interface mode.
* @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the encoder mode.
* @rmtoll SMCR SMS LL_TIM_SetEncoderMode
* @param TIMx Timer instance
* @param EncoderMode This parameter can be one of the following values:
* @arg @ref LL_TIM_ENCODERMODE_X2_TI1
* @arg @ref LL_TIM_ENCODERMODE_X2_TI2
* @arg @ref LL_TIM_ENCODERMODE_X4_TI12
* @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
* @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
* @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
* @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
* @arg @ref LL_TIM_ENCODERMODE_X1_TI1
* @arg @ref LL_TIM_ENCODERMODE_X1_TI2
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
* @{
*/
/**
* @brief Set the trigger output (TRGO) used for timer synchronization .
* @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can operate as a master timer.
* @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
* @param TIMx Timer instance
* @param TimerSynchronization This parameter can be one of the following values:
* @arg @ref LL_TIM_TRGO_RESET
* @arg @ref LL_TIM_TRGO_ENABLE
* @arg @ref LL_TIM_TRGO_UPDATE
* @arg @ref LL_TIM_TRGO_CC1IF
* @arg @ref LL_TIM_TRGO_OC1REF
* @arg @ref LL_TIM_TRGO_OC2REF
* @arg @ref LL_TIM_TRGO_OC3REF
* @arg @ref LL_TIM_TRGO_OC4REF
* @arg @ref LL_TIM_TRGO_ENCODERCLK
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
{
MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
}
/**
* @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
* @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
* whether or not a timer instance can be used for ADC synchronization.
* @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
* @param TIMx Timer Instance
* @param ADCSynchronization This parameter can be one of the following values:
* @arg @ref LL_TIM_TRGO2_RESET
* @arg @ref LL_TIM_TRGO2_ENABLE
* @arg @ref LL_TIM_TRGO2_UPDATE
* @arg @ref LL_TIM_TRGO2_CC1F
* @arg @ref LL_TIM_TRGO2_OC1
* @arg @ref LL_TIM_TRGO2_OC2
* @arg @ref LL_TIM_TRGO2_OC3
* @arg @ref LL_TIM_TRGO2_OC4
* @arg @ref LL_TIM_TRGO2_OC5
* @arg @ref LL_TIM_TRGO2_OC6
* @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
* @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
* @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
* @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
{
MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
}
/**
* @brief Set the synchronization mode of a slave timer.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR SMS LL_TIM_SetSlaveMode
* @param TIMx Timer instance
* @param SlaveMode This parameter can be one of the following values:
* @arg @ref LL_TIM_SLAVEMODE_DISABLED
* @arg @ref LL_TIM_SLAVEMODE_RESET
* @arg @ref LL_TIM_SLAVEMODE_GATED
* @arg @ref LL_TIM_SLAVEMODE_TRIGGER
* @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
* @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
}
/**
* @brief Set the selects the trigger input to be used to synchronize the counter.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR TS LL_TIM_SetTriggerInput
* @param TIMx Timer instance
* @param TriggerInput This parameter can be one of the following values:
* @arg @ref LL_TIM_TS_ITR0
* @arg @ref LL_TIM_TS_ITR1
* @arg @ref LL_TIM_TS_ITR2
* @arg @ref LL_TIM_TS_ITR3
* @arg @ref LL_TIM_TS_TI1F_ED
* @arg @ref LL_TIM_TS_TI1FP1
* @arg @ref LL_TIM_TS_TI2FP2
* @arg @ref LL_TIM_TS_ETRF
* @arg @ref LL_TIM_TS_ITR4
* @arg @ref LL_TIM_TS_ITR5
* @arg @ref LL_TIM_TS_ITR6
* @arg @ref LL_TIM_TS_ITR7
* @arg @ref LL_TIM_TS_ITR8
* @arg @ref LL_TIM_TS_ITR9
* @arg @ref LL_TIM_TS_ITR10
* @arg @ref LL_TIM_TS_ITR11
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
}
/**
* @brief Enable the Master/Slave mode.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
}
/**
* @brief Disable the Master/Slave mode.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
}
/**
* @brief Indicates whether the Master/Slave mode is enabled.
* @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
* a timer instance can operate as a slave timer.
* @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
}
/**
* @brief Configure the external trigger (ETR) input.
* @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an external trigger input.
* @rmtoll SMCR ETP LL_TIM_ConfigETR\n
* SMCR ETPS LL_TIM_ConfigETR\n
* SMCR ETF LL_TIM_ConfigETR
* @param TIMx Timer instance
* @param ETRPolarity This parameter can be one of the following values:
* @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
* @arg @ref LL_TIM_ETR_POLARITY_INVERTED
* @param ETRPrescaler This parameter can be one of the following values:
* @arg @ref LL_TIM_ETR_PRESCALER_DIV1
* @arg @ref LL_TIM_ETR_PRESCALER_DIV2
* @arg @ref LL_TIM_ETR_PRESCALER_DIV4
* @arg @ref LL_TIM_ETR_PRESCALER_DIV8
* @param ETRFilter This parameter can be one of the following values:
* @arg @ref LL_TIM_ETR_FILTER_FDIV1
* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
* @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
* @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
uint32_t ETRFilter)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
}
/**
* @brief Select the external trigger (ETR) input source.
* @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports ETR source selection.
* @rmtoll AF1 ETRSEL LL_TIM_SetETRSource
* @param TIMx Timer instance
* @param ETRSource This parameter can be one of the following values:
*
* TIM1: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP3
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP4
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP5 (*)
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP6 (*)
* @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP7 (*)
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD1 (*)
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD2 (*)
* @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC4_AWD3 (*)
*
* TIM2: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP3
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP4
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP5 (*)
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP6 (*)
* @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP7 (*)
* @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
* @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR
* @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR (*)
* @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
*
* TIM3: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP3
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP4
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP5 (*)
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP6 (*)
* @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP7 (*)
* @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
* @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR
* @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1
* @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2
* @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3
*
* TIM4: any combination of ETR_RMP where
*
* @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP3
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP4
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP5 (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP6 (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP7 (*)
* @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
* @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR (*)
*
* TIM5: any combination of ETR_RMP where (**)
*
* @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1 (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2 (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP3 (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP4 (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP5 (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP6 (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP7 (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR (*)
* @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR (*)
*
* TIM8: any combination of ETR_RMP where
*
* . . ETR_RMP can be one of the following values
* @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP3
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP4
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP5 (*)
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP6 (*)
* @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP7 (*)
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1 (*)
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2 (*)
* @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3 (*)
*
* TIM20: any combination of ETR_RMP where (**)
*
* . . ETR_RMP can be one of the following values
* @arg @ref LL_TIM_TIM20_ETRSOURCE_GPIO (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP1 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP2 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP3 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP4 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP5 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP6 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_COMP7 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD1 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD2 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC3_AWD3 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD1 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD2 (*)
* @arg @ref LL_TIM_TIM20_ETRSOURCE_ADC5_AWD3 (*)
*
* (*) Value not defined in all devices. \n
* (**) Register not available in all devices.
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
{
MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
}
/**
* @brief Enable SMS preload.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_EnableSMSPreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
}
/**
* @brief Disable SMS preload.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_DisableSMSPreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
}
/**
* @brief Indicate whether SMS preload is enabled.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPE LL_TIM_IsEnabledSMSPreload
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
}
/**
* @brief Set the preload source of SMS.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPS LL_TIM_SetSMSPreloadSource\n
* @param TIMx Timer instance
* @param PreloadSource This parameter can be one of the following values:
* @arg @ref LL_TIM_SMSPS_TIMUPDATE
* @arg @ref LL_TIM_SMSPS_INDEX
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
}
/**
* @brief Get the preload source of SMS.
* @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
* whether or not a timer instance supports the preload of SMS field in SMCR register.
* @rmtoll SMCR SMSPS LL_TIM_GetSMSPreloadSource\n
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_SMSPS_TIMUPDATE
* @arg @ref LL_TIM_SMSPS_INDEX
*/
__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Break_Function Break function configuration
* @{
*/
/**
* @brief Enable the break function.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR BKE LL_TIM_EnableBRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
}
/**
* @brief Disable the break function.
* @rmtoll BDTR BKE LL_TIM_DisableBRK
* @param TIMx Timer instance
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
}
/**
* @brief Configure the break input.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @note Bidirectional mode is only supported by advanced timer instances.
* Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
* a timer instance is an advanced-control timer.
* @note In bidirectional mode (BKBID bit set), the Break input is configured both
* in input mode and in open drain output mode. Any active Break event will
* assert a low logic level on the Break input to indicate an internal break
* event to external devices.
* @note When bidirectional mode isn't supported, BreakAFMode must be set to
* LL_TIM_BREAK_AFMODE_INPUT.
* @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
* BDTR BKF LL_TIM_ConfigBRK\n
* BDTR BKBID LL_TIM_ConfigBRK
* @param TIMx Timer instance
* @param BreakPolarity This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_POLARITY_LOW
* @arg @ref LL_TIM_BREAK_POLARITY_HIGH
* @param BreakFilter This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_FILTER_FDIV1
* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
* @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
* @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
* @param BreakAFMode This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_AFMODE_INPUT
* @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
uint32_t BreakAFMode)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
}
/**
* @brief Disarm the break input (when it operates in bidirectional mode).
* @note The break input can be disarmed only when it is configured in
* bidirectional mode and when when MOE is reset.
* @note Purpose is to be able to have the input voltage back to high-state,
* whatever the time constant on the output .
* @rmtoll BDTR BKDSRM LL_TIM_DisarmBRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
}
/**
* @brief Re-arm the break input (when it operates in bidirectional mode).
* @note The Break input is automatically armed as soon as MOE bit is set.
* @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
}
/**
* @brief Enable the break 2 function.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_EnableBRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
}
/**
* @brief Disable the break 2 function.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @rmtoll BDTR BK2E LL_TIM_DisableBRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
}
/**
* @brief Configure the break 2 input.
* @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a second break input.
* @note Bidirectional mode is only supported by advanced timer instances.
* Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
* a timer instance is an advanced-control timer.
* @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
* in input mode and in open drain output mode. Any active Break event will
* assert a low logic level on the Break 2 input to indicate an internal break
* event to external devices.
* @note When bidirectional mode isn't supported, Break2AFMode must be set to
* LL_TIM_BREAK2_AFMODE_INPUT.
* @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
* BDTR BK2F LL_TIM_ConfigBRK2\n
* BDTR BK2BID LL_TIM_ConfigBRK2
* @param TIMx Timer instance
* @param Break2Polarity This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK2_POLARITY_LOW
* @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
* @param Break2Filter This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
* @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
* @param Break2AFMode This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
* @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
uint32_t Break2AFMode)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
}
/**
* @brief Disarm the break 2 input (when it operates in bidirectional mode).
* @note The break 2 input can be disarmed only when it is configured in
* bidirectional mode and when when MOE is reset.
* @note Purpose is to be able to have the input voltage back to high-state,
* whatever the time constant on the output.
* @rmtoll BDTR BK2DSRM LL_TIM_DisarmBRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
}
/**
* @brief Re-arm the break 2 input (when it operates in bidirectional mode).
* @note The Break 2 input is automatically armed as soon as MOE bit is set.
* @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
}
/**
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
* BDTR OSSR LL_TIM_SetOffStates
* @param TIMx Timer instance
* @param OffStateIdle This parameter can be one of the following values:
* @arg @ref LL_TIM_OSSI_DISABLE
* @arg @ref LL_TIM_OSSI_ENABLE
* @param OffStateRun This parameter can be one of the following values:
* @arg @ref LL_TIM_OSSR_DISABLE
* @arg @ref LL_TIM_OSSR_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
{
MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
}
/**
* @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
}
/**
* @brief Disable automatic output (MOE can be set only by software).
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
}
/**
* @brief Indicate whether automatic output is enabled.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
}
/**
* @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
}
/**
* @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
* @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
* software and is reset in case of break or break2 event.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
}
/**
* @brief Indicates whether outputs are enabled.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides a break input.
* @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
}
/**
* @brief Enable the signals connected to the designated timer break input.
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP1E LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP2E LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP3E LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP4E LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP5E LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP6E LL_TIM_EnableBreakInputSource\n
* AF1 BKCMP7E LL_TIM_EnableBreakInputSource\n
* AF2 BK2NE LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP1E LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP2E LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP3E LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP4E LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP5E LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP6E LL_TIM_EnableBreakInputSource\n
* AF2 BK2CMP7E LL_TIM_EnableBreakInputSource
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN
* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
* @param Source This parameter can be one of the following values:
* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
*
* (*) Value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
SET_BIT(*pReg, Source);
}
/**
* @brief Disable the signals connected to the designated timer break input.
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP1E LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP2E LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP3E LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP4E LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP5E LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP6E LL_TIM_DisableBreakInputSource\n
* AF1 BKCMP7E LL_TIM_DisableBreakInputSource\n
* AF2 BKINE LL_TIM_DisableBreakInputSource\n
* AF2 BKCMP1E LL_TIM_DisableBreakInputSource\n
* AF2 BKCMP2E LL_TIM_DisableBreakInputSource\n
* AF2 BKCMP3E LL_TIM_DisableBreakInputSource\n
* AF2 BKCMP4E LL_TIM_DisableBreakInputSource\n
* AF2 BKCMP5E LL_TIM_DisableBreakInputSource\n
* AF2 BKCMP6E LL_TIM_DisableBreakInputSource\n
* AF2 BKCMP7E LL_TIM_DisableBreakInputSource
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN
* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
* @param Source This parameter can be one of the following values:
* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP5 (*)
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP6 (*)
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP7 (*)
*
* (*) Value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
CLEAR_BIT(*pReg, Source);
}
/**
* @brief Set the polarity of the break signal for the timer break input.
* @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
* or not a timer instance allows for break input selection.
* @rmtoll AF1 BKINP LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKCMP3P LL_TIM_SetBreakInputSourcePolarity\n
* AF1 BKCMP4P LL_TIM_SetBreakInputSourcePolarity\n
* AF2 BK2INP LL_TIM_SetBreakInputSourcePolarity\n
* AF2 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n
* AF2 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity\n
* AF2 BK2CMP3P LL_TIM_SetBreakInputSourcePolarity\n
* AF2 BK2CMP4P LL_TIM_SetBreakInputSourcePolarity
* @param TIMx Timer instance
* @param BreakInput This parameter can be one of the following values:
* @arg @ref LL_TIM_BREAK_INPUT_BKIN
* @arg @ref LL_TIM_BREAK_INPUT_BKIN2
* @param Source This parameter can be one of the following values:
* @arg @ref LL_TIM_BKIN_SOURCE_BKIN
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP3
* @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP4
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_TIM_BKIN_POLARITY_LOW
* @arg @ref LL_TIM_BKIN_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
uint32_t Polarity)
{
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
}
/**
* @brief Enable asymmetrical deadtime.
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides asymmetrical deadtime.
* @rmtoll DTR2 DTAE LL_TIM_EnableAsymmetricalDeadTime
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
}
/**
* @brief Disable asymmetrical dead-time.
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides asymmetrical deadtime.
* @rmtoll DTR2 DTAE LL_TIM_DisableAsymmetricalDeadTime
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
}
/**
* @brief Indicates whether asymmetrical deadtime is activated.
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides asymmetrical deadtime.
* @rmtoll DTR2 DTAE LL_TIM_IsEnabledAsymmetricalDeadTime
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
}
/**
* @brief Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
* rising edge of OCxN signals).
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* asymmetrical dead-time insertion feature is supported by a timer instance.
* @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
* @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
* (LOCK bits in TIMx_BDTR register).
* @rmtoll DTR2 DTGF LL_TIM_SetFallingDeadTime
* @param TIMx Timer instance
* @param DeadTime between Min_Data=0 and Max_Data=255
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
{
MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
}
/**
* @brief Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
* the rising edge of OCxN signals).
* @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
* asymmetrical dead-time insertion feature is supported by a timer instance.
* @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
* (LOCK bits in TIMx_BDTR register).
* @rmtoll DTR2 DTGF LL_TIM_GetFallingDeadTime
* @param TIMx Timer instance
* @retval Returned value can be between Min_Data=0 and Max_Data=255:
*/
__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
}
/**
* @brief Enable deadtime preload.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides deadtime preload.
* @rmtoll DTR2 DTPE LL_TIM_EnableDeadTimePreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
}
/**
* @brief Disable dead-time preload.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides deadtime preload.
* @rmtoll DTR2 DTPE LL_TIM_DisableDeadTimePreload
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
}
/**
* @brief Indicates whether deadtime preload is activated.
* @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides deadtime preload.
* @rmtoll DTR2 DTPE LL_TIM_IsEnabledDeadTimePreload
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
* @{
*/
/**
* @brief Configures the timer DMA burst feature.
* @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
* not a timer instance supports the DMA burst mode.
* @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
* DCR DBA LL_TIM_ConfigDMABurst
* @param TIMx Timer instance
* @param DMABurstBaseAddress This parameter can be one of the following values:
* @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
* @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
* @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
* @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
* @arg @ref LL_TIM_DMABURST_BASEADDR_SR
* @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
* @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
* @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
* @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
* @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
* @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
* @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
* @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
* @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
* @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
* @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
* @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
* @arg @ref LL_TIM_DMABURST_BASEADDR_OR
* @param DMABurstLength This parameter can be one of the following values:
* @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
* @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
* @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
{
MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Encoder Encoder configuration
* @{
*/
/**
* @brief Enable encoder index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_EnableEncoderIndex
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->ECR, TIM_ECR_IE);
}
/**
* @brief Disable encoder index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_DisableEncoderIndex
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
}
/**
* @brief Indicate whether encoder index is enabled.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IE LL_TIM_IsEnabledEncoderIndex
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
}
/**
* @brief Set index direction
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_SetIndexDirection
* @param TIMx Timer instance
* @param IndexDirection This parameter can be one of the following values:
* @arg @ref LL_TIM_INDEX_UP_DOWN
* @arg @ref LL_TIM_INDEX_UP
* @arg @ref LL_TIM_INDEX_DOWN
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
}
/**
* @brief Get actual index direction
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_GetIndexDirection
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_INDEX_UP_DOWN
* @arg @ref LL_TIM_INDEX_UP
* @arg @ref LL_TIM_INDEX_DOWN
*/
__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
}
/**
* @brief Enable first index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_EnableFirstIndex
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
}
/**
* @brief Disable first index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_DisableFirstIndex
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
}
/**
* @brief Indicates whether first index is enabled.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR FIDX LL_TIM_IsEnabledFirstIndex
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
}
/**
* @brief Set index positioning
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IPOS LL_TIM_SetIndexPositionning
* @param TIMx Timer instance
* @param IndexPositionning This parameter can be one of the following values:
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
* @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_UP_UP
* @arg @ref LL_TIM_INDEX_POSITION_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_UP
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
}
/**
* @brief Get actual index positioning
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IPOS LL_TIM_GetIndexPositionning
* @param TIMx Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
* @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_UP_UP
* @arg @ref LL_TIM_INDEX_POSITION_DOWN
* @arg @ref LL_TIM_INDEX_POSITION_UP
*/
__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(TIM_TypeDef *TIMx)
{
return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
}
/**
* @brief Configure encoder index.
* @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides an index input.
* @rmtoll ECR IDIR LL_TIM_ConfigIDX\n
* ECR FIDX LL_TIM_ConfigIDX\n
* ECR IPOS LL_TIM_ConfigIDX
* @param TIMx Timer instance
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
* @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
* @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
* @retval None
*/
__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
{
MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
* @{
*/
/**
* @brief Remap TIM inputs (input channel, internal/external triggers).
* @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
* a some timer inputs can be remapped.
* @rmtoll TIM1_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM2_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM2_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM2_TISEL TI3SEL LL_TIM_SetRemap\n
* TIM2_TISEL TI4SEL LL_TIM_SetRemap\n
* TIM3_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM3_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM3_TISEL TI3SEL LL_TIM_SetRemap\n
* TIM4_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM4_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM4_TISEL TI3SEL LL_TIM_SetRemap\n
* TIM4_TISEL TI4SEL LL_TIM_SetRemap\n
* TIM5_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM5_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM8_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM15_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM15_TISEL TI2SEL LL_TIM_SetRemap\n
* TIM16_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM17_TISEL TI1SEL LL_TIM_SetRemap\n
* TIM20_TISEL TI1SEL LL_TIM_SetRemap
* @param TIMx Timer instance
* @param Remap Remap param depends on the TIMx. Description available only
* in CHM version of the User Manual (not in .pdf).
* Otherwise see Reference Manual description of TISEL registers.
*
* Below description summarizes "Timer Instance" and "Remap" param combinations:
*
* TIM1: one of the following values
*
* @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO
* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1
* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP2
* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP3
* @arg @ref LL_TIM_TIM1_TI1_RMP_COMP4
*
* TIM2: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
*
* . . TI1_RMP can be one of the following values
* @arg @ref LL_TIM_TIM2_TI1_RMP_GPIO
* @arg @ref LL_TIM_TIM2_TI1_RMP_COMP1
* @arg @ref LL_TIM_TIM2_TI1_RMP_COMP2
* @arg @ref LL_TIM_TIM2_TI1_RMP_COMP3
* @arg @ref LL_TIM_TIM2_TI1_RMP_COMP4
* @arg @ref LL_TIM_TIM2_TI1_RMP_COMP5 (*)
*
* . . TI2_RMP can be one of the following values
* @arg @ref LL_TIM_TIM2_TI2_RMP_GPIO
* @arg @ref LL_TIM_TIM2_TI2_RMP_COMP1
* @arg @ref LL_TIM_TIM2_TI2_RMP_COMP2
* @arg @ref LL_TIM_TIM2_TI2_RMP_COMP3
* @arg @ref LL_TIM_TIM2_TI2_RMP_COMP4
* @arg @ref LL_TIM_TIM2_TI2_RMP_COMP6 (*)
*
* . . TI3_RMP can be one of the following values
* @arg @ref LL_TIM_TIM2_TI3_RMP_GPIO
* @arg @ref LL_TIM_TIM2_TI3_RMP_COMP4
*
* . . TI4_RMP can be one of the following values
* @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO
* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1
* @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2
*
* TIM3: any combination of TI1_RMP and TI2_RMP where
*
* . . TI1_RMP can be one of the following values
* @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO
* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1
* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2
* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP3
* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP4
* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP5 (*)
* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP6 (*)
* @arg @ref LL_TIM_TIM3_TI1_RMP_COMP7 (*)
*
* . . TI2_RMP can be one of the following values
* @arg @ref LL_TIM_TIM3_TI2_RMP_GPIO
* @arg @ref LL_TIM_TIM3_TI2_RMP_COMP1
* @arg @ref LL_TIM_TIM3_TI2_RMP_COMP2
* @arg @ref LL_TIM_TIM3_TI2_RMP_COMP3
* @arg @ref LL_TIM_TIM3_TI2_RMP_COMP4
* @arg @ref LL_TIM_TIM3_TI2_RMP_COMP5 (*)
* @arg @ref LL_TIM_TIM3_TI2_RMP_COMP6 (*)
* @arg @ref LL_TIM_TIM3_TI2_RMP_COMP7 (*)
*
* . . TI3_RMP can be one of the following values
* @arg @ref LL_TIM_TIM3_TI3_RMP_GPIO
* @arg @ref LL_TIM_TIM3_TI3_RMP_COMP3
*
* TIM4: any combination of TI1_RMP, TI2_RMP, TI3_RMP and TI4_RMP where
*
* . . TI1_RMP can be one of the following values
* @arg @ref LL_TIM_TIM4_TI1_RMP_GPIO
* @arg @ref LL_TIM_TIM4_TI1_RMP_COMP1
* @arg @ref LL_TIM_TIM4_TI1_RMP_COMP2
* @arg @ref LL_TIM_TIM4_TI1_RMP_COMP3
* @arg @ref LL_TIM_TIM4_TI1_RMP_COMP4
* @arg @ref LL_TIM_TIM4_TI1_RMP_COMP5 (*)
* @arg @ref LL_TIM_TIM4_TI1_RMP_COMP6 (*)
* @arg @ref LL_TIM_TIM4_TI1_RMP_COMP7 (*)
*
* . . TI2_RMP can be one of the following values
* @arg @ref LL_TIM_TIM4_TI2_RMP_GPIO
* @arg @ref LL_TIM_TIM4_TI2_RMP_COMP1
* @arg @ref LL_TIM_TIM4_TI2_RMP_COMP2
* @arg @ref LL_TIM_TIM4_TI2_RMP_COMP3
* @arg @ref LL_TIM_TIM4_TI2_RMP_COMP4
* @arg @ref LL_TIM_TIM4_TI2_RMP_COMP5 (*)
* @arg @ref LL_TIM_TIM4_TI2_RMP_COMP6 (*)
* @arg @ref LL_TIM_TIM4_TI2_RMP_COMP7 (*)
*
* . . TI3_RMP can be one of the following values
* @arg @ref LL_TIM_TIM4_TI3_RMP_GPIO
* @arg @ref LL_TIM_TIM4_TI3_RMP_COMP5 (*)
*
* . . TI4_RMP can be one of the following values
* @arg @ref LL_TIM_TIM4_TI4_RMP_GPIO
* @arg @ref LL_TIM_TIM4_TI4_RMP_COMP6 (*)
*
* TIM5: any combination of TI1_RMP and TI2_RMP where (**)
*
* . . TI1_RMP can be one of the following values
* @arg @ref LL_TIM_TIM5_TI1_RMP_GPIO (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_LSI (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_LSE (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_RTC_WK (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_COMP1 (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_COMP2 (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_COMP3 (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_COMP4 (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_COMP5 (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_COMP6 (*)
* @arg @ref LL_TIM_TIM5_TI1_RMP_COMP7 (*)
*
* . . TI2_RMP can be one of the following values
* @arg @ref LL_TIM_TIM5_TI2_RMP_GPIO (*)
* @arg @ref LL_TIM_TIM5_TI2_RMP_COMP1 (*)
* @arg @ref LL_TIM_TIM5_TI2_RMP_COMP2 (*)
* @arg @ref LL_TIM_TIM5_TI2_RMP_COMP3 (*)
* @arg @ref LL_TIM_TIM5_TI2_RMP_COMP4 (*)
* @arg @ref LL_TIM_TIM5_TI2_RMP_COMP5 (*)
* @arg @ref LL_TIM_TIM5_TI2_RMP_COMP6 (*)
* @arg @ref LL_TIM_TIM5_TI2_RMP_COMP7 (*)
*
* TIM8: one of the following values
*
* @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO
* @arg @ref LL_TIM_TIM8_TI1_RMP_COMP1
* @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2
* @arg @ref LL_TIM_TIM8_TI1_RMP_COMP3
* @arg @ref LL_TIM_TIM8_TI1_RMP_COMP4
*
* TIM15: any combination of TI1_RMP and TI2_RMP where
*
* . . TI1_RMP can be one of the following values
* @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO
* @arg @ref LL_TIM_TIM15_TI1_RMP_LSE
* @arg @ref LL_TIM_TIM15_TI1_RMP_COMP1
* @arg @ref LL_TIM_TIM15_TI1_RMP_COMP2
* @arg @ref LL_TIM_TIM15_TI1_RMP_COMP5 (*)
* @arg @ref LL_TIM_TIM15_TI1_RMP_COMP7 (*)
*
* . . TI2_RMP can be one of the following values
* @arg @ref LL_TIM_TIM15_TI2_RMP_GPIO
* @arg @ref LL_TIM_TIM15_TI2_RMP_COMP2
* @arg @ref LL_TIM_TIM15_TI2_RMP_COMP3
* @arg @ref LL_TIM_TIM15_TI2_RMP_COMP6 (*)
* @arg @ref LL_TIM_TIM15_TI2_RMP_COMP7 (*)
*
* TIM16: one of the following values
*
* @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO
* @arg @ref LL_TIM_TIM16_TI1_RMP_COMP6 (*)
* @arg @ref LL_TIM_TIM16_TI1_RMP_MCO
* @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32
* @arg @ref LL_TIM_TIM16_TI1_RMP_RTC_WK
* @arg @ref LL_TIM_TIM16_TI1_RMP_LSE
* @arg @ref LL_TIM_TIM16_TI1_RMP_LSI
*
* TIM17: one of the following values
*
* @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO
* @arg @ref LL_TIM_TIM17_TI1_RMP_COMP5 (*)
* @arg @ref LL_TIM_TIM17_TI1_RMP_MCO
* @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32
* @arg @ref LL_TIM_TIM17_TI1_RMP_RTC_WK
* @arg @ref LL_TIM_TIM17_TI1_RMP_LSE
* @arg @ref LL_TIM_TIM17_TI1_RMP_LSI
*
* TIM20: one of the following values (**)
*
* @arg @ref LL_TIM_TIM20_TI1_RMP_GPIO (*)
* @arg @ref LL_TIM_TIM20_TI1_RMP_COMP1 (*)
* @arg @ref LL_TIM_TIM20_TI1_RMP_COMP2 (*)
* @arg @ref LL_TIM_TIM20_TI1_RMP_COMP3 (*)
* @arg @ref LL_TIM_TIM20_TI1_RMP_COMP4 (*)
*
* (*) Value not defined in all devices. \n
* (**) Register not available in all devices.
*
*
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
{
MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
}
/**
* @brief Enable request for HSE/32 clock used for TISEL remap.
* @note Only TIM16 and TIM17 support HSE/32 remap
* @rmtoll OR HSE32EN LL_TIM_EnableHSE32
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableHSE32(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->OR, TIM_OR_HSE32EN);
}
/**
* @brief Disable request for HSE/32 clock used for TISEL remap.
* @note Only TIM16 and TIM17 support HSE/32 remap
* @rmtoll OR HSE32EN LL_TIM_DisableHSE32
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableHSE32(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->OR, TIM_OR_HSE32EN);
}
/**
* @brief Indicate whether request for HSE/32 clock is enabled.
* @note Only TIM16 and TIM17 support HSE/32 remap
* @rmtoll OR HSE32EN LL_TIM_IsEnabledHSE32
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledHSE32(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->OR, TIM_OR_HSE32EN) == (TIM_OR_HSE32EN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
* @{
*/
/**
* @brief Set the OCREF clear input source
* @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
* @note This function can only be used in Output compare and PWM modes.
* @note Macro IS_TIM_OCCS_INSTANCE(TIMx) can be used to check whether
* or not a timer instance can configure OCREF clear input source.
* @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource
* @rmtoll AF2 OCRSEL LL_TIM_SetOCRefClearInputSource
* @param TIMx Timer instance
* @param OCRefClearInputSource This parameter can be one of the following values:
* @arg @ref LL_TIM_OCREF_CLR_INT_ETR
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP1
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP2
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP3
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP4
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP5 (*)
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP6 (*)
* @arg @ref LL_TIM_OCREF_CLR_INT_COMP7 (*)
*
* (*) Value not defined in all devices. \n
* @retval None
*/
__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
{
MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
((OCRefClearInputSource & OCREF_CLEAR_SELECT_Msk) >> OCREF_CLEAR_SELECT_Pos) << TIM_SMCR_OCCS_Pos);
MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
* @{
*/
/**
* @brief Clear the update interrupt flag (UIF).
* @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
}
/**
* @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
* @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
* @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
}
/**
* @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
* @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
* @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
}
/**
* @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
* @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
* @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
}
/**
* @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
* @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
* @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
}
/**
* @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
* @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
* @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
}
/**
* @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
* @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
* @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
}
/**
* @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
* @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the commutation interrupt flag (COMIF).
* @rmtoll SR COMIF LL_TIM_ClearFlag_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
}
/**
* @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
* @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the trigger interrupt flag (TIF).
* @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
}
/**
* @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
* @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the break interrupt flag (BIF).
* @rmtoll SR BIF LL_TIM_ClearFlag_BRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
}
/**
* @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
* @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the break 2 interrupt flag (B2IF).
* @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
}
/**
* @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
* @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
* @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
}
/**
* @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
* (Capture/Compare 1 interrupt is pending).
* @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
* @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
}
/**
* @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
* (Capture/Compare 2 over-capture interrupt is pending).
* @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
* @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
}
/**
* @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
* (Capture/Compare 3 over-capture interrupt is pending).
* @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
}
/**
* @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
* @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
}
/**
* @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
* (Capture/Compare 4 over-capture interrupt is pending).
* @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
}
/**
* @brief Clear the system break interrupt flag (SBIF).
* @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
}
/**
* @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
* @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
}
/**
* @brief Clear the transition error interrupt flag (TERRF).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR TERRF LL_TIM_ClearFlag_TERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
}
/**
* @brief Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR TERRF LL_TIM_IsActiveFlag_TERR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear the index error interrupt flag (IERRF).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR IERRF LL_TIM_ClearFlag_IERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
}
/**
* @brief Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll SR IERRF LL_TIM_IsActiveFlag_IERR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear the direction change interrupt flag (DIRF).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll SR DIRF LL_TIM_ClearFlag_DIR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
}
/**
* @brief Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll SR DIRF LL_TIM_IsActiveFlag_DIR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
}
/**
* @brief Clear the index interrupt flag (IDXF).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll SR IDXF LL_TIM_ClearFlag_IDX
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
{
WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
}
/**
* @brief Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll SR IDXF LL_TIM_IsActiveFlag_IDX
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_IT_Management IT-Management
* @{
*/
/**
* @brief Enable update interrupt (UIE).
* @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_UIE);
}
/**
* @brief Disable update interrupt (UIE).
* @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
}
/**
* @brief Indicates whether the update interrupt (UIE) is enabled.
* @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 1 interrupt (CC1IE).
* @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
}
/**
* @brief Disable capture/compare 1 interrupt (CC1IE).
* @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
}
/**
* @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
* @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 2 interrupt (CC2IE).
* @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
}
/**
* @brief Disable capture/compare 2 interrupt (CC2IE).
* @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
}
/**
* @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
* @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 3 interrupt (CC3IE).
* @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
}
/**
* @brief Disable capture/compare 3 interrupt (CC3IE).
* @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
}
/**
* @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
* @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 4 interrupt (CC4IE).
* @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
}
/**
* @brief Disable capture/compare 4 interrupt (CC4IE).
* @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
}
/**
* @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
* @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
}
/**
* @brief Enable commutation interrupt (COMIE).
* @rmtoll DIER COMIE LL_TIM_EnableIT_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
}
/**
* @brief Disable commutation interrupt (COMIE).
* @rmtoll DIER COMIE LL_TIM_DisableIT_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
}
/**
* @brief Indicates whether the commutation interrupt (COMIE) is enabled.
* @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
}
/**
* @brief Enable trigger interrupt (TIE).
* @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_TIE);
}
/**
* @brief Disable trigger interrupt (TIE).
* @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
}
/**
* @brief Indicates whether the trigger interrupt (TIE) is enabled.
* @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
}
/**
* @brief Enable break interrupt (BIE).
* @rmtoll DIER BIE LL_TIM_EnableIT_BRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_BIE);
}
/**
* @brief Disable break interrupt (BIE).
* @rmtoll DIER BIE LL_TIM_DisableIT_BRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
}
/**
* @brief Indicates whether the break interrupt (BIE) is enabled.
* @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
}
/**
* @brief Enable transition error interrupt (TERRIE).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_EnableIT_TERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
}
/**
* @brief Disable transition error interrupt (TERRIE).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_DisableIT_TERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
}
/**
* @brief Indicates whether the transition error interrupt (TERRIE) is enabled.
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER TERRIE LL_TIM_IsEnabledIT_TERR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable index error interrupt (IERRIE).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_EnableIT_IERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
}
/**
* @brief Disable index error interrupt (IERRIE).
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_DisableIT_IERR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
}
/**
* @brief Indicates whether the index error interrupt (IERRIE) is enabled.
* @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder error management.
* @rmtoll DIER IERRIE LL_TIM_IsEnabledIT_IERR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable direction change interrupt (DIRIE).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER DIRIE LL_TIM_EnableIT_DIR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
}
/**
* @brief Disable direction change interrupt (DIRIE).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER DIRIE LL_TIM_DisableIT_DIR
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
}
/**
* @brief Indicates whether the direction change interrupt (DIRIE) is enabled.
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER DIRIE LL_TIM_IsEnabledIT_DIR
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable index interrupt (IDXIE).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER IDXIE LL_TIM_EnableIT_IDX
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
}
/**
* @brief Disable index interrupt (IDXIE).
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER IDXIE LL_TIM_DisableIT_IDX
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
}
/**
* @brief Indicates whether the index interrupt (IDXIE) is enabled.
* @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
* a timer instance provides encoder interrupt management.
* @rmtoll DIER IDXIE LL_TIM_IsEnabledIT_IDX
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable update DMA request (UDE).
* @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_UDE);
}
/**
* @brief Disable update DMA request (UDE).
* @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
}
/**
* @brief Indicates whether the update DMA request (UDE) is enabled.
* @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 1 DMA request (CC1DE).
* @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
}
/**
* @brief Disable capture/compare 1 DMA request (CC1DE).
* @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
}
/**
* @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
* @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 2 DMA request (CC2DE).
* @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
}
/**
* @brief Disable capture/compare 2 DMA request (CC2DE).
* @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
}
/**
* @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
* @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 3 DMA request (CC3DE).
* @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
}
/**
* @brief Disable capture/compare 3 DMA request (CC3DE).
* @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
}
/**
* @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
* @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
}
/**
* @brief Enable capture/compare 4 DMA request (CC4DE).
* @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
}
/**
* @brief Disable capture/compare 4 DMA request (CC4DE).
* @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
}
/**
* @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
* @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
}
/**
* @brief Enable commutation DMA request (COMDE).
* @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
}
/**
* @brief Disable commutation DMA request (COMDE).
* @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
}
/**
* @brief Indicates whether the commutation DMA request (COMDE) is enabled.
* @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
}
/**
* @brief Enable trigger interrupt (TDE).
* @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->DIER, TIM_DIER_TDE);
}
/**
* @brief Disable trigger interrupt (TDE).
* @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
{
CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
}
/**
* @brief Indicates whether the trigger interrupt (TDE) is enabled.
* @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
* @param TIMx Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
{
return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
* @{
*/
/**
* @brief Generate an update event.
* @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_UG);
}
/**
* @brief Generate Capture/Compare 1 event.
* @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
}
/**
* @brief Generate Capture/Compare 2 event.
* @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
}
/**
* @brief Generate Capture/Compare 3 event.
* @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
}
/**
* @brief Generate Capture/Compare 4 event.
* @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
}
/**
* @brief Generate commutation event.
* @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_COMG);
}
/**
* @brief Generate trigger event.
* @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_TG);
}
/**
* @brief Generate break event.
* @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_BG);
}
/**
* @brief Generate break 2 event.
* @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
* @param TIMx Timer instance
* @retval None
*/
__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
{
SET_BIT(TIMx->EGR, TIM_EGR_B2G);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
* @{
*/
ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM15 || TIM16 || TIM17 || TIM20 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_TIM_H */
| 307,874 | C | 44.835194 | 274 | 0.595377 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c.h | /**
******************************************************************************
* @file stm32g4xx_hal_i2c.h
* @author MCD Application Team
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_I2C_H
#define STM32G4xx_HAL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup I2C
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
* @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
This parameter calculated by referring to I2C initialization section
in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing
mode is selected.
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
} I2C_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :\n
* b7-b6 Error information\n
* 00 : No Error\n
* 01 : Abort (Abort user request on going)\n
* 10 : Timeout\n
* 11 : Error\n
* b5 Peripheral initialization status\n
* 0 : Reset (peripheral not initialized)\n
* 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n
* b4 (not used)\n
* x : Should be set to 0\n
* b3\n
* 0 : Ready or Busy (No Listen mode ongoing)\n
* 1 : Listen (peripheral in Address Listen Mode)\n
* b2 Intrinsic process state\n
* 0 : Ready\n
* 1 : Busy (peripheral busy with some configuration or internal operations)\n
* b1 Rx state\n
* 0 : Ready (no Rx operation ongoing)\n
* 1 : Busy (Rx operation ongoing)\n
* b0 Tx state\n
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
} HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :\n
* b7 (not used)\n
* x : Should be set to 0\n
* b6\n
* 0 : None\n
* 1 : Memory (HAL I2C communication is in Memory Mode)\n
* b5\n
* 0 : None\n
* 1 : Slave (HAL I2C communication is in Slave Mode)\n
* b4\n
* 0 : None\n
* 1 : Master (HAL I2C communication is in Master Mode)\n
* b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
} HAL_I2C_ModeTypeDef;
/**
* @}
*/
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
/*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Listen Complete callback */
void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Tx Transfer completed callback */
void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Memory Rx Transfer completed callback */
void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Error callback */
void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Abort callback */
void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< I2C Slave Address Match callback */
void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp Init callback */
void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);
/*!< I2C Msp DeInit callback */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
} I2C_HandleTypeDef;
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
/**
* @brief HAL I2C Callback ID enumeration definition
*/
typedef enum
{
HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */
HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */
HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */
HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */
HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */
HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */
HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */
HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */
HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */
HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */
HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */
} HAL_I2C_CallbackIDTypeDef;
/**
* @brief HAL I2C Callback pointer definition
*/
typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c);
/*!< pointer to an I2C callback function */
typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an I2C Address Match callback function */
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define I2C_OTHER_FRAME (0x000000AAU)
#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U)
/**
* @}
*/
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT (0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE (0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE (0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE (0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT (0x00000001U)
#define I2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
#define I2C_DIRECTION_TRANSMIT (0x00000000U)
#define I2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
* @brief I2C Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define I2C_IT_ERRI I2C_CR1_ERRIE
#define I2C_IT_TCI I2C_CR1_TCIE
#define I2C_IT_STOPI I2C_CR1_STOPIE
#define I2C_IT_NACKI I2C_CR1_NACKIE
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
/** @defgroup I2C_Flag_definition I2C Flag definition
* @{
*/
#define I2C_FLAG_TXE I2C_ISR_TXE
#define I2C_FLAG_TXIS I2C_ISR_TXIS
#define I2C_FLAG_RXNE I2C_ISR_RXNE
#define I2C_FLAG_ADDR I2C_ISR_ADDR
#define I2C_FLAG_AF I2C_ISR_NACKF
#define I2C_FLAG_STOPF I2C_ISR_STOPF
#define I2C_FLAG_TC I2C_ISR_TC
#define I2C_FLAG_TCR I2C_ISR_TCR
#define I2C_FLAG_BERR I2C_ISR_BERR
#define I2C_FLAG_ARLO I2C_ISR_ARLO
#define I2C_FLAG_OVR I2C_ISR_OVR
#define I2C_FLAG_PECERR I2C_ISR_PECERR
#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define I2C_FLAG_ALERT I2C_ISR_ALERT
#define I2C_FLAG_BUSY I2C_ISR_BUSY
#define I2C_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup I2C_Exported_Macros I2C Exported Macros
* @{
*/
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_I2C_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \
(__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define I2C_FLAG_MASK (0x0001FFFFU)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \
(__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Include I2C HAL Extended module */
#include "stm32g4xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2C_Exported_Functions
* @{
*/
/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID,
pI2C_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions ****************************************************/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData,
uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
/**
* @}
*/
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
* @{
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \
IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \
((REQUEST) == I2C_OTHER_AND_LAST_FRAME))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \
>> 16U))
#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \
>> 16U))
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \
(uint16_t)(0xFF00U))) >> 8U)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
(~I2C_CR2_RD_WRN)))
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
* @{
*/
/* Private functions are defined in stm32g4xx_hal_i2c.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_I2C_H */
| 38,780 | C | 45.388756 | 120 | 0.538834 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc.h | /**
******************************************************************************
* @file stm32g4xx_hal_crc.h
* @author MCD Application Team
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_CRC_H
#define STM32G4xx_HAL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup CRC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CRC_Exported_Types CRC Exported Types
* @{
*/
/**
* @brief CRC HAL State Structure definition
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
} HAL_CRC_StateTypeDef;
/**
* @brief CRC Init Structure definition
*/
typedef struct
{
uint8_t DefaultPolynomialUse; /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.
If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default
X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 +
X^4 + X^2+ X +1.
In that case, there is no need to set GeneratingPolynomial field.
If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and
CRCLength fields must be set. */
uint8_t DefaultInitValueUse; /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.
If set to DEFAULT_INIT_VALUE_ENABLE, resort to default
0xFFFFFFFF value. In that case, there is no need to set InitValue field. If
otherwise set to DEFAULT_INIT_VALUE_DISABLE, InitValue field must be set. */
uint32_t GeneratingPolynomial; /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree
respectively equal to 7, 8, 16 or 32. This field is written in normal,
representation e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1
is written 0x65. No need to specify it if DefaultPolynomialUse is set to
DEFAULT_POLYNOMIAL_ENABLE. */
uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.
Value can be either one of
@arg @ref CRC_POLYLENGTH_32B (32-bit CRC),
@arg @ref CRC_POLYLENGTH_16B (16-bit CRC),
@arg @ref CRC_POLYLENGTH_8B (8-bit CRC),
@arg @ref CRC_POLYLENGTH_7B (7-bit CRC). */
uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse
is set to DEFAULT_INIT_VALUE_ENABLE. */
uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.
Can be either one of the following values
@arg @ref CRC_INPUTDATA_INVERSION_NONE no input data inversion
@arg @ref CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D
becomes 0x58D43CB2
@arg @ref CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion,
0x1A2B3C4D becomes 0xD458B23C
@arg @ref CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D
becomes 0xB23CD458 */
uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.
Can be either
@arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion,
@arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted
into 0x22CC4488 */
} CRC_InitTypeDef;
/**
* @brief CRC Handle Structure definition
*/
typedef struct
{
CRC_TypeDef *Instance; /*!< Register base address */
CRC_InitTypeDef Init; /*!< CRC configuration parameters */
HAL_LockTypeDef Lock; /*!< CRC Locking object */
__IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */
uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.
Can be either
@arg @ref CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes
(8-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS input data is a stream of
half-words (16-bit data)
@arg @ref CRC_INPUTDATA_FORMAT_WORDS input data is a stream of words
(32-bit data)
Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization
error must occur if InputBufferFormat is not one of the three values listed
above */
} CRC_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7U /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U) /*!< Enable default generating polynomial 0x04C11DB7 */
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U) /*!< Disable default generating polynomial 0x04C11DB7 */
/**
* @}
*/
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U) /*!< Enable initial CRC default value */
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U) /*!< Disable initial CRC default value */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral
* @{
*/
#define CRC_POLYLENGTH_32B 0x00000000U /*!< Resort to a 32-bit long generating polynomial */
#define CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< Resort to a 16-bit long generating polynomial */
#define CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< Resort to a 8-bit long generating polynomial */
#define CRC_POLYLENGTH_7B CRC_CR_POLYSIZE /*!< Resort to a 7-bit long generating polynomial */
/**
* @}
*/
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32U /*!< 32-bit long CRC */
#define HAL_CRC_LENGTH_16B 16U /*!< 16-bit long CRC */
#define HAL_CRC_LENGTH_8B 8U /*!< 8-bit long CRC */
#define HAL_CRC_LENGTH_7B 7U /*!< 7-bit long CRC */
/**
* @}
*/
/** @defgroup CRC_Input_Buffer_Format Input Buffer Format
* @{
*/
/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED 0x00000000U /*!< Undefined input data format */
#define CRC_INPUTDATA_FORMAT_BYTES 0x00000001U /*!< Input data in byte format */
#define CRC_INPUTDATA_FORMAT_HALFWORDS 0x00000002U /*!< Input data in half-word format */
#define CRC_INPUTDATA_FORMAT_WORDS 0x00000003U /*!< Input data in word format */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CRC_Exported_Macros CRC Exported Macros
* @{
*/
/** @brief Reset CRC handle state.
* @param __HANDLE__ CRC handle.
* @retval None
*/
#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
/**
* @brief Reset CRC Data Register.
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
/**
* @brief Set CRC INIT non-default value
* @param __HANDLE__ CRC handle
* @param __INIT__ 32-bit initial value
* @retval None
*/
#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))
/**
* @brief Store data in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @param __VALUE__ Value to be stored in the ID register
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval None
*/
#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
/**
* @brief Return the data stored in the Independent Data (ID) register.
* @param __HANDLE__ CRC handle
* @note Refer to the Reference Manual to get the authorized __VALUE__ length in bits
* @retval Value of the ID register
*/
#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRC_Private_Macros CRC Private Macros
* @{
*/
#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \
((LENGTH) == CRC_POLYLENGTH_16B) || \
((LENGTH) == CRC_POLYLENGTH_8B) || \
((LENGTH) == CRC_POLYLENGTH_7B))
#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \
((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))
/**
* @}
*/
/* Include CRC HAL Extended module */
#include "stm32g4xx_hal_crc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_Exported_Functions CRC Exported Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/* Peripheral Control functions ***********************************************/
/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
/**
* @}
*/
/* Peripheral State and Error functions ***************************************/
/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_CRC_H */
| 14,202 | C | 40.408163 | 157 | 0.523588 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim.h | /**
******************************************************************************
* @file stm32g4xx_hal_tim.h
* @author MCD Application Team
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_TIM_H
#define STM32G4xx_HAL_TIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup TIM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIM_Exported_Types TIM Exported Types
* @{
*/
/**
* @brief TIM Time base Configuration Structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */
uint32_t CounterMode; /*!< Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint32_t Period; /*!< Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
(or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(),
__HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(),
__HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */
uint32_t ClockDivision; /*!< Specifies the clock division.
This parameter can be a value of @ref TIM_ClockDivision */
uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
GP timers: this parameter must be a number between Min_Data = 0x00 and
Max_Data = 0xFF.
Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
Max_Data = 0xFFFF. */
uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
This parameter can be a value of @ref TIM_AutoReloadPreload */
} TIM_Base_InitTypeDef;
/**
* @brief TIM Output Compare Configuration Structure definition
*/
typedef struct
{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
(or 0xFFEF if dithering is activated)
Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
Pulse value */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCFastMode; /*!< Specifies the Fast mode state.
This parameter can be a value of @ref TIM_Output_Fast_State
@note This parameter is valid only in PWM1 and PWM2 mode. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for timer instances supporting break feature. */
} TIM_OC_InitTypeDef;
/**
* @brief TIM One Pulse Mode Configuration Structure definition
*/
typedef struct
{
uint32_t OCMode; /*!< Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF
(or 0xFFEF if dithering is activated)
Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate
Pulse value */
uint32_t OCPolarity; /*!< Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for timer instances supporting break feature. */
uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for timer instances supporting break feature. */
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t ICSelection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint32_t ICFilter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_OnePulse_InitTypeDef;
/**
* @brief TIM Input Capture Configuration Structure definition
*/
typedef struct
{
uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t ICSelection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t ICFilter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_IC_InitTypeDef;
/**
* @brief TIM Encoder Configuration Structure definition
*/
typedef struct
{
uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC2Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_Encoder_InitTypeDef;
/**
* @brief Clock Configuration Handle Structure definition
*/
typedef struct
{
uint32_t ClockSource; /*!< TIM clock sources
This parameter can be a value of @ref TIM_Clock_Source */
uint32_t ClockPolarity; /*!< TIM clock polarity
This parameter can be a value of @ref TIM_Clock_Polarity */
uint32_t ClockPrescaler; /*!< TIM clock prescaler
This parameter can be a value of @ref TIM_Clock_Prescaler */
uint32_t ClockFilter; /*!< TIM clock filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClockConfigTypeDef;
/**
* @brief TIM Clear Input Configuration Handle Structure definition
*/
typedef struct
{
uint32_t ClearInputState; /*!< TIM clear Input state
This parameter can be ENABLE or DISABLE */
uint32_t ClearInputSource; /*!< TIM clear Input sources
This parameter can be a value of @ref TIM_ClearInput_Source */
uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
This parameter can be a value of @ref TIM_ClearInput_Polarity */
uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
This parameter must be 0: When OCRef clear feature is used with ETR source,
ETR prescaler must be off */
uint32_t ClearInputFilter; /*!< TIM Clear Input filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_ClearInputConfigTypeDef;
/**
* @brief TIM Master configuration Structure definition
* @note Advanced timers provide TRGO2 internal line which is redirected
* to the ADC
*/
typedef struct
{
uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection */
uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode
@note When the Master/slave mode is enabled, the effect of
an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its
slaves (through TRGO). It is not mandatory in case of timer
synchronization mode. */
} TIM_MasterConfigTypeDef;
/**
* @brief TIM Slave configuration Structure definition
*/
typedef struct
{
uint32_t SlaveMode; /*!< Slave mode selection
This parameter can be a value of @ref TIM_Slave_Mode */
uint32_t InputTrigger; /*!< Input Trigger source
This parameter can be a value of @ref TIM_Trigger_Selection */
uint32_t TriggerPolarity; /*!< Input Trigger polarity
This parameter can be a value of @ref TIM_Trigger_Polarity */
uint32_t TriggerPrescaler; /*!< Input trigger prescaler
This parameter can be a value of @ref TIM_Trigger_Prescaler */
uint32_t TriggerFilter; /*!< Input trigger filter
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
} TIM_SlaveConfigTypeDef;
/**
* @brief TIM Break input(s) and Dead time configuration Structure definition
* @note 2 break inputs can be configured (BKIN and BKIN2) with configurable
* filter and polarity.
*/
typedef struct
{
uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */
uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */
uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */
uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */
uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */
uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */
uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */
uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BreakDeadTimeConfigTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
} HAL_TIM_StateTypeDef;
/**
* @brief TIM Channel States definition
*/
typedef enum
{
HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */
HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */
HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */
} HAL_TIM_ChannelStateTypeDef;
/**
* @brief DMA Burst States definition
*/
typedef enum
{
HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */
HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */
HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */
} HAL_TIM_DMABurstStateTypeDef;
/**
* @brief HAL Active channel structures definition
*/
typedef enum
{
HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */
HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */
HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
} HAL_TIM_ActiveChannel;
/**
* @brief TIM Time Base Handle Structure definition
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
typedef struct __TIM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
{
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
HAL_TIM_ActiveChannel Channel; /*!< Active channel */
DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */
__IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */
void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */
void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */
void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */
void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */
void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
} TIM_HandleTypeDef;
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL TIM Callback ID enumeration definition
*/
typedef enum
{
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
, HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */
, HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */
, HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */
, HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */
, HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */
, HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */
, HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */
} HAL_TIM_CallbackIDTypeDef;
/**
* @brief HAL TIM Callback pointer definition
*/
typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIM_Exported_Constants TIM Exported Constants
* @{
*/
/** @defgroup TIM_ClearInput_Source TIM Clear Input Source
* @{
*/
#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */
#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */
#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */
#define TIM_CLEARINPUTSOURCE_COMP3 TIM1_AF2_OCRSEL_1 /*!< OCREF_CLR_INT is connected to COMP3 output */
#define TIM_CLEARINPUTSOURCE_COMP4 (TIM1_AF2_OCRSEL_1 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP4 output */
#if defined (COMP5)
#define TIM_CLEARINPUTSOURCE_COMP5 TIM1_AF2_OCRSEL_2 /*!< OCREF_CLR_INT is connected to COMP5 output */
#endif /* COMP5 */
#if defined (COMP6)
#define TIM_CLEARINPUTSOURCE_COMP6 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_0) /*!< OCREF_CLR_INT is connected to COMP6 output */
#endif /* COMP6 */
#if defined (COMP7)
#define TIM_CLEARINPUTSOURCE_COMP7 (TIM1_AF2_OCRSEL_2 | TIM1_AF2_OCRSEL_1) /*!< OCREF_CLR_INT is connected to COMP7 output */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
* @{
*/
#define TIM_DMABASE_CR1 0x00000000U
#define TIM_DMABASE_CR2 0x00000001U
#define TIM_DMABASE_SMCR 0x00000002U
#define TIM_DMABASE_DIER 0x00000003U
#define TIM_DMABASE_SR 0x00000004U
#define TIM_DMABASE_EGR 0x00000005U
#define TIM_DMABASE_CCMR1 0x00000006U
#define TIM_DMABASE_CCMR2 0x00000007U
#define TIM_DMABASE_CCER 0x00000008U
#define TIM_DMABASE_CNT 0x00000009U
#define TIM_DMABASE_PSC 0x0000000AU
#define TIM_DMABASE_ARR 0x0000000BU
#define TIM_DMABASE_RCR 0x0000000CU
#define TIM_DMABASE_CCR1 0x0000000DU
#define TIM_DMABASE_CCR2 0x0000000EU
#define TIM_DMABASE_CCR3 0x0000000FU
#define TIM_DMABASE_CCR4 0x00000010U
#define TIM_DMABASE_BDTR 0x00000011U
#define TIM_DMABASE_CCR5 0x00000012U
#define TIM_DMABASE_CCR6 0x00000013U
#define TIM_DMABASE_CCMR3 0x00000014U
#define TIM_DMABASE_DTR2 0x00000015U
#define TIM_DMABASE_ECR 0x00000016U
#define TIM_DMABASE_TISEL 0x00000017U
#define TIM_DMABASE_AF1 0x00000018U
#define TIM_DMABASE_AF2 0x00000019U
#define TIM_DMABASE_OR 0x0000001AU
/**
* @}
*/
/** @defgroup TIM_Event_Source TIM Event Source
* @{
*/
#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */
#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */
#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */
/**
* @}
*/
/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
* @{
*/
#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
/**
* @}
*/
/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
* @{
*/
#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
/**
* @}
*/
/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
* @{
*/
#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
/**
* @}
*/
/** @defgroup TIM_Counter_Mode TIM Counter Mode
* @{
*/
#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
/**
* @}
*/
/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
* @{
*/
#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */
#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */
/**
* @}
*/
/** @defgroup TIM_ClockDivision TIM Clock Division
* @{
*/
#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
/**
* @}
*/
/** @defgroup TIM_Output_Compare_State TIM Output Compare State
* @{
*/
#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
/**
* @}
*/
/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
* @{
*/
#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
/**
* @}
*/
/** @defgroup TIM_Output_Fast_State TIM Output Fast State
* @{
*/
#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
/**
* @}
*/
/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
* @{
*/
#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
/**
* @}
*/
/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
* @{
*/
#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
/**
* @}
*/
/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
* @{
*/
#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */
#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */
/**
* @}
*/
/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
* @{
*/
#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */
#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */
/**
* @}
*/
/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
* @{
*/
#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */
#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
* @{
*/
#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
/**
* @}
*/
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
* @{
*/
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{
*/
#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */
#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
* @{
*/
#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
/**
* @}
*/
/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
* @{
*/
#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
/**
* @}
*/
/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
* @{
*/
#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */
#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */
#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
#define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
#define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
/**
* @}
*/
/** @defgroup TIM_Interrupt_definition TIM interrupt Definition
* @{
*/
#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */
#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */
#define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */
#define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */
#define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */
#define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */
/**
* @}
*/
/** @defgroup TIM_Commutation_Source TIM Commutation Source
* @{
*/
#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */
#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */
/**
* @}
*/
/** @defgroup TIM_DMA_sources TIM DMA Sources
* @{
*/
#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */
#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
/**
* @}
*/
/** @defgroup TIM_Flag_definition TIM Flag Definition
* @{
*/
#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */
#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */
#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */
#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */
#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */
#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */
#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
#define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */
#define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */
#define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */
#define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */
/**
* @}
*/
/** @defgroup TIM_Channel TIM Channel
* @{
*/
#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */
#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */
#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
/**
* @}
*/
/** @defgroup TIM_Clock_Source TIM Clock Source
* @{
*/
#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
#if defined (TIM5)
#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */
#endif /* TIM5 */
#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */
#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */
#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */
#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */
#if defined (TIM20)
#define TIM_CLOCKSOURCE_ITR9 TIM_TS_ITR9 /*!< External clock source mode 1 (ITR9) */
#endif /* TIM20 */
#define TIM_CLOCKSOURCE_ITR10 TIM_TS_ITR10 /*!< External clock source mode 1 (ITR10) */
#define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */
/**
* @}
*/
/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
* @{
*/
#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
/**
* @}
*/
/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
* @{
*/
#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
/**
* @}
*/
/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
* @{
*/
#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
/**
* @}
*/
/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
* @{
*/
#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
/**
* @}
*/
/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
* @{
*/
#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/
/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
* @{
*/
#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */
#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */
/**
* @}
*/
/** @defgroup TIM_Lock_level TIM Lock level
* @{
*/
#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */
#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
/**
* @}
*/
/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable
* @{
*/
#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */
#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */
/**
* @}
*/
/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
* @{
*/
#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
/**
* @}
*/
/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode
* @{
*/
#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */
#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */
/**
* @}
*/
/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable
* @{
*/
#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */
#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */
/**
* @}
*/
/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity
* @{
*/
#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
/**
* @}
*/
/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode
* @{
*/
#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */
#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */
/**
* @}
*/
/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
* @{
*/
#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */
/**
* @}
*/
/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3
* @{
*/
#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
/**
* @}
*/
/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
* @{
*/
#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
#define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */
/**
* @}
*/
/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)
* @{
*/
#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */
#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */
#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */
#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */
#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */
#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */
#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */
#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */
#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */
#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */
#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */
#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */
#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */
#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */
#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */
/**
* @}
*/
/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
* @{
*/
#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
/**
* @}
*/
/** @defgroup TIM_Slave_Mode TIM Slave mode
* @{
*/
#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */
#define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */
/**
* @}
*/
/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
* @{
*/
#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
#define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */
#define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */
/**
* @}
*/
/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
* @{
*/
#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
#if defined (TIM5)
#define TIM_TS_ITR4 TIM_SMCR_TS_3 /*!< Internal Trigger 4 (ITR9) */
#endif /* TIM5 */
#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */
#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */
#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */
#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */
#if defined (TIM20)
#define TIM_TS_ITR9 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 9 (ITR9) */
#endif /* TIM20 */
#define TIM_TS_ITR10 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 10 (ITR10) */
#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */
#define TIM_TS_NONE 0xFFFFFFFFU /*!< No trigger selected */
/**
* @}
*/
/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
* @{
*/
#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
/**
* @}
*/
/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
* @{
*/
#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
/**
* @}
*/
/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
* @{
*/
#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
/**
* @}
*/
/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
* @{
*/
#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */
/**
* @}
*/
/** @defgroup DMA_Handle_index TIM DMA Handle Index
* @{
*/
#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */
#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
/**
* @}
*/
/** @defgroup Channel_CC_State TIM Capture/Compare Channel State
* @{
*/
#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */
#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */
/**
* @}
*/
/** @defgroup TIM_Break_System TIM Break System
* @{
*/
#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */
#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */
#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */
#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup TIM_Exported_Macros TIM Exported Macros
* @{
*/
/** @brief Reset TIM handle state.
* @param __HANDLE__ TIM handle.
* @retval None
*/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
(__HANDLE__)->Base_MspInitCallback = NULL; \
(__HANDLE__)->Base_MspDeInitCallback = NULL; \
(__HANDLE__)->IC_MspInitCallback = NULL; \
(__HANDLE__)->IC_MspDeInitCallback = NULL; \
(__HANDLE__)->OC_MspInitCallback = NULL; \
(__HANDLE__)->OC_MspDeInitCallback = NULL; \
(__HANDLE__)->PWM_MspInitCallback = NULL; \
(__HANDLE__)->PWM_MspDeInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspInitCallback = NULL; \
(__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
(__HANDLE__)->Encoder_MspInitCallback = NULL; \
(__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspInitCallback = NULL; \
(__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_TIM_STATE_RESET; \
(__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
(__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
} while(0)
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @brief Enable the TIM peripheral.
* @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
/**
* @brief Enable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
/**
* @brief Disable the TIM peripheral.
* @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \
} \
} while(0)
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been
* disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \
} \
} while(0)
/**
* @brief Disable the TIM main Output.
* @param __HANDLE__ TIM handle
* @retval None
* @note The Main Output Enable of a timer instance is disabled unconditionally
*/
#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
/** @brief Enable the specified TIM interrupt.
* @param __HANDLE__ specifies the TIM Handle.
* @param __INTERRUPT__ specifies the TIM interrupt source to enable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @arg TIM_IT_IDX: Index interrupt
* @arg TIM_IT_DIR: Direction change interrupt
* @arg TIM_IT_IERR: Index error interrupt
* @arg TIM_IT_TERR: Transition error interrupt
* @retval None
*/
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
/** @brief Disable the specified TIM interrupt.
* @param __HANDLE__ specifies the TIM Handle.
* @param __INTERRUPT__ specifies the TIM interrupt source to disable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @arg TIM_IT_IDX: Index interrupt
* @arg TIM_IT_DIR: Direction change interrupt
* @arg TIM_IT_IERR: Index error interrupt
* @arg TIM_IT_TERR: Transition error interrupt
* @retval None
*/
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
/** @brief Enable the specified DMA request.
* @param __HANDLE__ specifies the TIM Handle.
* @param __DMA__ specifies the TIM DMA request to enable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
* @arg TIM_DMA_COM: Commutation DMA request
* @arg TIM_DMA_TRIGGER: Trigger DMA request
* @retval None
*/
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
/** @brief Disable the specified DMA request.
* @param __HANDLE__ specifies the TIM Handle.
* @param __DMA__ specifies the TIM DMA request to disable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
* @arg TIM_DMA_COM: Commutation DMA request
* @arg TIM_DMA_TRIGGER: Trigger DMA request
* @retval None
*/
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
/** @brief Check whether the specified TIM interrupt flag is set or not.
* @param __HANDLE__ specifies the TIM Handle.
* @param __FLAG__ specifies the TIM interrupt flag to check.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
* @arg TIM_FLAG_IDX: Index interrupt flag
* @arg TIM_FLAG_DIR: Direction change interrupt flag
* @arg TIM_FLAG_IERR: Index error interrupt flag
* @arg TIM_FLAG_TERR: Transition error interrupt flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
/** @brief Clear the specified TIM interrupt flag.
* @param __HANDLE__ specifies the TIM Handle.
* @param __FLAG__ specifies the TIM interrupt flag to clear.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
* @arg TIM_FLAG_CC5: Compare 5 interrupt flag
* @arg TIM_FLAG_CC6: Compare 6 interrupt flag
* @arg TIM_FLAG_COM: Commutation interrupt flag
* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
* @arg TIM_FLAG_BREAK: Break interrupt flag
* @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
* @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag
* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
* @arg TIM_FLAG_IDX: Index interrupt flag
* @arg TIM_FLAG_DIR: Direction change interrupt flag
* @arg TIM_FLAG_IERR: Index error interrupt flag
* @arg TIM_FLAG_TERR: Transition error interrupt flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/**
* @brief Check whether the specified TIM interrupt source is enabled or not.
* @param __HANDLE__ TIM handle
* @param __INTERRUPT__ specifies the TIM interrupt source to check.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @arg TIM_IT_IDX: Index interrupt
* @arg TIM_IT_DIR: Direction change interrupt
* @arg TIM_IT_IERR: Index error interrupt
* @arg TIM_IT_TERR: Transition error interrupt
* @retval The state of TIM_IT (SET or RESET).
*/
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
== (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
* @arg TIM_IT_COM: Commutation interrupt
* @arg TIM_IT_TRIGGER: Trigger interrupt
* @arg TIM_IT_BREAK: Break interrupt
* @arg TIM_IT_IDX: Index interrupt
* @arg TIM_IT_DIR: Direction change interrupt
* @arg TIM_IT_IERR: Index error interrupt
* @arg TIM_IT_TERR: Transition error interrupt
* @retval None
*/
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
/**
* @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
* @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
* in an atomic way.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
*/
#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
/**
* @brief Disable update interrupt flag (UIF) remapping.
* @param __HANDLE__ TIM handle.
* @retval None
mode.
*/
#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
/**
* @brief Get update interrupt flag (UIF) copy status.
* @param __COUNTER__ Counter value.
* @retval The state of UIFCPY (TRUE or FALSE).
mode.
*/
#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
* @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode
* or Encoder mode.
*/
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
/**
* @brief Set the TIM Prescaler on runtime.
* @param __HANDLE__ TIM handle.
* @param __PRESC__ specifies the Prescaler new value.
* @retval None
*/
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
/**
* @brief Set the TIM Counter Register value on runtime.
* Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in
* case of 32 bits counter TIM instance.
* Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
* @param __HANDLE__ TIM handle.
* @param __COUNTER__ specifies the Counter register new value.
* @retval None
*/
#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
/**
* @brief Get the TIM Counter Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __AUTORELOAD__ specifies the Counter register new value.
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
/**
* @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
* @param __HANDLE__ TIM handle.
* @param __CKD__ specifies the clock division value.
* This parameter can be one of the following value:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
* @retval None
*/
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \
(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
/**
* @brief Get the TIM Clock Division value on runtime.
* @param __HANDLE__ TIM handle.
* @retval The clock division can be one of the following values:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel()
* function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param __ICPSC__ specifies the Input Capture4 prescaler new value.
* This parameter can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
* @retval None
*/
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0)
/**
* @brief Get the TIM Input Capture prescaler on runtime.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
* @retval The input capture prescaler can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
/**
* @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @param __COMPARE__ specifies the Capture Compare register new value.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
/**
* @brief Get the TIM Capture Compare Register value on runtime.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channel associated with the capture compare register
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get capture/compare 1 register value
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
* @arg TIM_CHANNEL_3: get capture/compare 3 register value
* @arg TIM_CHANNEL_4: get capture/compare 4 register value
* @arg TIM_CHANNEL_5: get capture/compare 5 register value
* @arg TIM_CHANNEL_6: get capture/compare 6 register value
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
((__HANDLE__)->Instance->CCR6))
/**
* @brief Set the TIM Output compare preload.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
/**
* @brief Reset the TIM Output compare preload.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
/**
* @brief Enable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @note When fast mode is enabled an active edge on the trigger input acts
* like a compare match on CCx output. Delay to sample the trigger
* input and to activate CCx output is reduced to 3 clock cycles.
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
/**
* @brief Disable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @note When fast mode is disabled CCx output behaves normally depending
* on counter and CCRx values even when the trigger is ON. The minimum
* delay to activate CCx output when an active edge occurs on the
* trigger input is 5 clock cycles.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
* @param __HANDLE__ TIM handle.
* @note When the URS bit of the TIMx_CR1 register is set, only counter
* overflow/underflow generates an update interrupt or DMA request (if
* enabled)
* @retval None
*/
#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
* @param __HANDLE__ TIM handle.
* @note When the URS bit of the TIMx_CR1 register is reset, any of the
* following events generate an update interrupt or DMA request (if
* enabled):
* _ Counter overflow underflow
* _ Setting the UG bit
* _ Update generation through the slave mode controller
* @retval None
*/
#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/**
* @brief Set the TIM Capture x input polarity on runtime.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @param __POLARITY__ Polarity for TIx source
* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
* @retval None
*/
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0)
/**
* @}
*/
/* End of exported macros ----------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup TIM_Private_Constants TIM Private Constants
* @{
*/
/* The counter of a timer instance is disabled only if all the CCx and CCxN
channels have been disabled */
#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE))
/**
* @}
*/
/* End of private constants --------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup TIM_Private_Macros TIM Private Macros
* @{
*/
#if defined(COMP5) && defined(COMP6) && defined(COMP7)
#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP5) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP6) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP7) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
#else /* COMP5 && COMP6 && COMP7 */
#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP3) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_COMP4) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_NONE))
#endif /* COMP5 && COMP6 && COMP7 */
#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
((__BASE__) == TIM_DMABASE_CR2) || \
((__BASE__) == TIM_DMABASE_SMCR) || \
((__BASE__) == TIM_DMABASE_DIER) || \
((__BASE__) == TIM_DMABASE_SR) || \
((__BASE__) == TIM_DMABASE_EGR) || \
((__BASE__) == TIM_DMABASE_CCMR1) || \
((__BASE__) == TIM_DMABASE_CCMR2) || \
((__BASE__) == TIM_DMABASE_CCER) || \
((__BASE__) == TIM_DMABASE_CNT) || \
((__BASE__) == TIM_DMABASE_PSC) || \
((__BASE__) == TIM_DMABASE_ARR) || \
((__BASE__) == TIM_DMABASE_RCR) || \
((__BASE__) == TIM_DMABASE_CCR1) || \
((__BASE__) == TIM_DMABASE_CCR2) || \
((__BASE__) == TIM_DMABASE_CCR3) || \
((__BASE__) == TIM_DMABASE_CCR4) || \
((__BASE__) == TIM_DMABASE_BDTR) || \
((__BASE__) == TIM_DMABASE_CCMR3) || \
((__BASE__) == TIM_DMABASE_CCR5) || \
((__BASE__) == TIM_DMABASE_CCR6) || \
((__BASE__) == TIM_DMABASE_AF1) || \
((__BASE__) == TIM_DMABASE_AF2) || \
((__BASE__) == TIM_DMABASE_TISEL) || \
((__BASE__) == TIM_DMABASE_DTR2) || \
((__BASE__) == TIM_DMABASE_ECR) || \
((__BASE__) == TIM_DMABASE_OR))
#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
((__MODE__) == TIM_COUNTERMODE_DOWN) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
((__MODE__) == TIM_UIFREMAP_ENALE))
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
((__STATE__) == TIM_OCFAST_ENABLE))
#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
((__POLARITY__) == TIM_OCPOLARITY_LOW))
#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
((__POLARITY__) == TIM_OCNPOLARITY_LOW))
#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
((__STATE__) == TIM_OCIDLESTATE_RESET))
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
((__SELECTION__) == TIM_ICSELECTION_TRC))
#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
((__PRESCALER__) == TIM_ICPSC_DIV2) || \
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
((__PRESCALER__) == TIM_ICPSC_DIV8))
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
((__MODE__) == TIM_OPMODE_REPETITIVE))
#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
((__MODE__) == TIM_ENCODERMODE_TI2) || \
((__MODE__) == TIM_ENCODERMODE_TI12) || \
((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \
((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \
((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \
((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \
((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \
((__MODE__) == TIM_ENCODERMODE_X1_TI2))
#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3) || \
((__CHANNEL__) == TIM_CHANNEL_4) || \
((__CHANNEL__) == TIM_CHANNEL_5) || \
((__CHANNEL__) == TIM_CHANNEL_6) || \
((__CHANNEL__) == TIM_CHANNEL_ALL))
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3) || \
((__CHANNEL__) == TIM_CHANNEL_4))
#if defined(TIM5) && defined(TIM20)
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
#elif defined(TIM5)
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
#elif defined(TIM20)
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
#else
#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))
#endif /* TIM5 && TIM20 */
#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
((__STATE__) == TIM_OSSR_DISABLE))
#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
((__STATE__) == TIM_OSSI_DISABLE))
#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
((__LEVEL__) == TIM_LOCKLEVEL_1) || \
((__LEVEL__) == TIM_LOCKLEVEL_2) || \
((__LEVEL__) == TIM_LOCKLEVEL_3))
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \
((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL))
#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \
((__STATE__) == TIM_BREAK2_DISABLE))
#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \
((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL))
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
((__SOURCE__) == TIM_TRGO_ENABLE) || \
((__SOURCE__) == TIM_TRGO_UPDATE) || \
((__SOURCE__) == TIM_TRGO_OC1) || \
((__SOURCE__) == TIM_TRGO_OC1REF) || \
((__SOURCE__) == TIM_TRGO_OC2REF) || \
((__SOURCE__) == TIM_TRGO_OC3REF) || \
((__SOURCE__) == TIM_TRGO_OC4REF) || \
((__SOURCE__) == TIM_TRGO_ENCODER_CLK))
#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \
((__SOURCE__) == TIM_TRGO2_ENABLE) || \
((__SOURCE__) == TIM_TRGO2_UPDATE) || \
((__SOURCE__) == TIM_TRGO2_OC1) || \
((__SOURCE__) == TIM_TRGO2_OC1REF) || \
((__SOURCE__) == TIM_TRGO2_OC2REF) || \
((__SOURCE__) == TIM_TRGO2_OC3REF) || \
((__SOURCE__) == TIM_TRGO2_OC3REF) || \
((__SOURCE__) == TIM_TRGO2_OC4REF) || \
((__SOURCE__) == TIM_TRGO2_OC5REF) || \
((__SOURCE__) == TIM_TRGO2_OC6REF) || \
((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \
((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \
((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \
((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))
#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
((__MODE__) == TIM_SLAVEMODE_RESET) || \
((__MODE__) == TIM_SLAVEMODE_GATED) || \
((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \
((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET))
#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
((__MODE__) == TIM_OCMODE_PWM2) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
((__MODE__) == TIM_OCMODE_ACTIVE) || \
((__MODE__) == TIM_OCMODE_INACTIVE) || \
((__MODE__) == TIM_OCMODE_TOGGLE) || \
((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \
((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \
((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE))
#if defined (TIM5) && defined(TIM20)
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))
#elif defined (TIM5)
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))
#elif defined (TIM20)
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))
#else
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))
#endif /* TIM5 && TIM20 */
#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS))
#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \
((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelState[0] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[1] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[2] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[3] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[4] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[5] = \
(__CHANNEL_STATE__); \
} while(0)
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
(__HANDLE__)->ChannelNState[0] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[1] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[2] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[3] = \
(__CHANNEL_STATE__); \
} while(0)
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/* Include TIM HAL Extended module */
#include "stm32g4xx_hal_tim_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIM_Exported_Functions TIM Exported Functions
* @{
*/
/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
* @brief Time Base functions
* @{
*/
/* Time Base functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
* @brief TIM Output Compare functions
* @{
*/
/* Timer Output Compare functions *********************************************/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
* @brief TIM PWM functions
* @{
*/
/* Timer PWM functions ********************************************************/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
* @brief TIM Input Capture functions
* @{
*/
/* Timer Input Capture functions **********************************************/
HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
* @brief TIM One Pulse functions
* @{
*/
/* Timer One Pulse functions **************************************************/
HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
* @brief TIM Encoder functions
* @{
*/
/* Timer Encoder functions ****************************************************/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief IRQ handler management
* @{
*/
/* Interrupt Handler functions ***********************************************/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Control functions *********************************************************/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
uint32_t BurstLength, uint32_t DataLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions
* @{
*/
/* Callback in non blocking modes (Interrupt and DMA) *************************/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
* @brief Peripheral State functions
* @{
*/
/* Peripheral State functions ************************************************/
HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Peripheral Channel state functions ************************************************/
HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
* @{
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_DMAError(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_TIM_H */
| 163,223 | C | 61.015198 | 250 | 0.507018 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_sai_ex.h
* @author MCD Application Team
* @brief Header file of SAI HAL extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SAI_EX_H
#define STM32G4xx_HAL_SAI_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SAIEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SAIEx_Exported_Types SAIEx Exported Types
* @{
*/
/**
* @brief PDM microphone delay structure definition
*/
typedef struct
{
uint32_t MicPair; /*!< Specifies which pair of microphones is selected.
This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
uint32_t LeftDelay; /*!< Specifies the delay in PDM clock unit to apply on left microphone.
This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
uint32_t RightDelay; /*!< Specifies the delay in PDM clock unit to apply on right microphone.
This parameter must be a number between Min_Data = 0 and Max_Data = 7. */
} SAIEx_PdmMicDelayParamTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions
* @{
*/
/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros
* @{
*/
#define IS_SAI_PDM_MIC_DELAY(VALUE) ((VALUE) <= 7U)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SAI_EX_H */
| 2,822 | C | 26.144231 | 115 | 0.491495 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_rcc_ex.h
* @author MCD Application Team
* @brief Header file of RCC HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_RCC_EX_H
#define STM32G4xx_HAL_RCC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup RCCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
* @{
*/
/**
* @brief RCC extended clocks structure definition
*/
typedef struct
{
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source.
This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source.
This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
#if defined(UART4)
uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source.
This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
#endif /* UART4 */
#if defined(UART5)
uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source.
This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
#endif /* UART5 */
uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source.
This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
#if defined(I2C4)
uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source.
This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
#endif /* I2C4 */
uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
uint32_t I2sClockSelection; /*!< Specifies I2S clock source.
This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
#if defined(FDCAN1)
uint32_t FdcanClockSelection; /*!< Specifies FDCAN clock source.
This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source */
#endif /* FDCAN1 */
#if defined(USB)
uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG).
This parameter can be a value of @ref RCCEx_USB_Clock_Source */
#endif /* USB */
uint32_t RngClockSelection; /*!< Specifies RNG clock source (warning: same source for USB).
This parameter can be a value of @ref RCCEx_RNG_Clock_Source */
uint32_t Adc12ClockSelection; /*!< Specifies ADC12 interface clock source.
This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
#if defined(ADC345_COMMON)
uint32_t Adc345ClockSelection; /*!< Specifies ADC345 interface clock source.
This parameter can be a value of @ref RCCEx_ADC345_Clock_Source */
#endif /* ADC345_COMMON */
#if defined(QUADSPI)
uint32_t QspiClockSelection; /*!< Specifies QuadSPI clock source.
This parameter can be a value of @ref RCCEx_QSPI_Clock_Source */
#endif
uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
This parameter can be a value of @ref RCC_RTC_Clock_Source */
}RCC_PeriphCLKInitTypeDef;
/**
* @brief RCC_CRS Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
uint32_t Source; /*!< Specifies the SYNC signal source.
This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)
This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
This parameter must be a number between 0 and 0x7F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
}RCC_CRSInitTypeDef;
/**
* @brief RCC_CRS Synchronization structure definition
*/
typedef struct
{
uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
This parameter must be a number between 0 and 0xFFFF */
uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
This parameter must be a number between 0 and 0x7F */
uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
value latched in the time of the last SYNC event.
This parameter must be a number between 0 and 0xFFFF */
uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
frequency error counter latched in the time of the last SYNC event.
It shows whether the actual frequency is below or above the target.
This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
}RCC_CRSSynchroInfoTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
* @{
*/
/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
* @{
*/
#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */
#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
/**
* @}
*/
/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
* @{
*/
#define RCC_PERIPHCLK_USART1 0x00000001U
#define RCC_PERIPHCLK_USART2 0x00000002U
#define RCC_PERIPHCLK_USART3 0x00000004U
#if defined(UART4)
#define RCC_PERIPHCLK_UART4 0x00000008U
#endif /* UART4 */
#if defined(UART5)
#define RCC_PERIPHCLK_UART5 0x00000010U
#endif /* UART5 */
#define RCC_PERIPHCLK_LPUART1 0x00000020U
#define RCC_PERIPHCLK_I2C1 0x00000040U
#define RCC_PERIPHCLK_I2C2 0x00000080U
#define RCC_PERIPHCLK_I2C3 0x00000100U
#define RCC_PERIPHCLK_LPTIM1 0x00000200U
#define RCC_PERIPHCLK_SAI1 0x00000400U
#define RCC_PERIPHCLK_I2S 0x00000800U
#if defined(FDCAN1)
#define RCC_PERIPHCLK_FDCAN 0x00001000U
#endif /* FDCAN1 */
#define RCC_PERIPHCLK_USB 0x00002000U
#define RCC_PERIPHCLK_RNG 0x00004000U
#define RCC_PERIPHCLK_ADC12 0x00008000U
#if defined(ADC345_COMMON)
#define RCC_PERIPHCLK_ADC345 0x00010000U
#endif /* ADC345_COMMON */
#if defined(I2C4)
#define RCC_PERIPHCLK_I2C4 0x00020000U
#endif /* I2C4 */
#if defined(QUADSPI)
#define RCC_PERIPHCLK_QSPI 0x00040000U
#endif /* QUADSPI */
#define RCC_PERIPHCLK_RTC 0x00080000U
/**
* @}
*/
/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
* @{
*/
#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U
#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
/**
* @}
*/
/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source
* @{
*/
#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U
#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
/**
* @}
*/
/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source
* @{
*/
#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U
#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR_USART3SEL_0
#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR_USART3SEL_1
#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR_USART3SEL_0 | RCC_CCIPR_USART3SEL_1)
/**
* @}
*/
#if defined(UART4)
/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source
* @{
*/
#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U
#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR_UART4SEL_0
#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR_UART4SEL_1
#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR_UART4SEL_0 | RCC_CCIPR_UART4SEL_1)
/**
* @}
*/
#endif /* UART4 */
#if defined(UART5)
/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source
* @{
*/
#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U
#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR_UART5SEL_0
#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR_UART5SEL_1
#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR_UART5SEL_0 | RCC_CCIPR_UART5SEL_1)
/**
* @}
*/
#endif /* UART5 */
/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
* @{
*/
#define RCC_LPUART1CLKSOURCE_PCLK1 0x00000000U
#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
/**
* @}
*/
/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
* @{
*/
#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U
#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
/**
* @}
*/
/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source
* @{
*/
#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U
#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR_I2C2SEL_0
#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR_I2C2SEL_1
/**
* @}
*/
/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
* @{
*/
#define RCC_I2C3CLKSOURCE_PCLK1 0x00000000U
#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
/**
* @}
*/
/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
* @{
*/
#define RCC_LPTIM1CLKSOURCE_PCLK1 0x00000000U
#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
/**
* @}
*/
/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
* @{
*/
#define RCC_SAI1CLKSOURCE_SYSCLK 0x00000000U
#define RCC_SAI1CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0
#define RCC_SAI1CLKSOURCE_EXT RCC_CCIPR_SAI1SEL_1
#define RCC_SAI1CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_1 | RCC_CCIPR_SAI1SEL_0)
/**
* @}
*/
/** @defgroup RCCEx_I2S_Clock_Source I2S Clock Source
* @{
*/
#define RCC_I2SCLKSOURCE_SYSCLK 0x00000000U
#define RCC_I2SCLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0
#define RCC_I2SCLKSOURCE_EXT RCC_CCIPR_I2S23SEL_1
#define RCC_I2SCLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_1 | RCC_CCIPR_I2S23SEL_0)
/**
* @}
*/
#if defined(FDCAN1)
/** @defgroup RCCEx_FDCAN_Clock_Source FDCAN Clock Source
* @{
*/
#define RCC_FDCANCLKSOURCE_HSE 0x00000000U
#define RCC_FDCANCLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0
#define RCC_FDCANCLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1
/**
* @}
*/
#endif /* FDCAN1 */
/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
* @{
*/
#define RCC_RNGCLKSOURCE_HSI48 0x00000000U
#define RCC_RNGCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
/**
* @}
*/
/** @defgroup RCCEx_USB_Clock_Source USB Clock Source
* @{
*/
#define RCC_USBCLKSOURCE_HSI48 0x00000000U
#define RCC_USBCLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1
/**
* @}
*/
/** @defgroup RCCEx_ADC12_Clock_Source ADC12 Clock Source
* @{
*/
#define RCC_ADC12CLKSOURCE_NONE 0x00000000U
#define RCC_ADC12CLKSOURCE_PLL RCC_CCIPR_ADC12SEL_0
#define RCC_ADC12CLKSOURCE_SYSCLK RCC_CCIPR_ADC12SEL_1
/**
* @}
*/
#if defined(ADC345_COMMON)
/** @defgroup RCCEx_ADC345_Clock_Source ADC345 Clock Source
* @{
*/
#define RCC_ADC345CLKSOURCE_NONE 0x00000000U
#define RCC_ADC345CLKSOURCE_PLL RCC_CCIPR_ADC345SEL_0
#define RCC_ADC345CLKSOURCE_SYSCLK RCC_CCIPR_ADC345SEL_1
/**
* @}
*/
#endif /* ADC345_COMMON */
#if defined(I2C4)
/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source
* @{
*/
#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U
#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR2_I2C4SEL_0
#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR2_I2C4SEL_1
/**
* @}
*/
#endif /* I2C4 */
#if defined(QUADSPI)
/** @defgroup RCCEx_QSPI_Clock_Source QuadSPI Clock Source
* @{
*/
#define RCC_QSPICLKSOURCE_SYSCLK 0x00000000U
#define RCC_QSPICLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0
#define RCC_QSPICLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1
/**
* @}
*/
#endif /* QUADSPI */
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{
*/
#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM19 /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */
/**
* @}
*/
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{
*/
#define RCC_CRS_NONE 0x00000000U
#define RCC_CRS_TIMEOUT 0x00000001U
#define RCC_CRS_SYNCOK 0x00000002U
#define RCC_CRS_SYNCWARN 0x00000004U
#define RCC_CRS_SYNCERR 0x00000008U
#define RCC_CRS_SYNCMISS 0x00000010U
#define RCC_CRS_TRIMOVF 0x00000020U
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
* @{
*/
#define RCC_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
* @{
*/
#define RCC_CRS_SYNC_DIV1 0x00000000U /*!< Synchro Signal not divided (default) */
#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
* @{
*/
#define RCC_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
* @{
*/
#define RCC_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU /*!< The reset value of the RELOAD field corresponds
to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
/**
* @}
*/
/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
* @{
*/
#define RCC_CRS_ERRORLIMIT_DEFAULT 0x00000022U /*!< Default Frequency error limit */
/**
* @}
*/
/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
* @{
*/
#define RCC_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U /*!< The default value is 32, which corresponds to the middle of the trimming interval.
The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
corresponds to a higher output frequency */
/**
* @}
*/
/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
* @{
*/
#define RCC_CRS_FREQERRORDIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
#define RCC_CRS_FREQERRORDIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
* @{
*/
#define RCC_CRS_IT_SYNCOK CRS_CR_SYNCOKIE /*!< SYNC event OK */
#define RCC_CRS_IT_SYNCWARN CRS_CR_SYNCWARNIE /*!< SYNC warning */
#define RCC_CRS_IT_ERR CRS_CR_ERRIE /*!< Error */
#define RCC_CRS_IT_ESYNC CRS_CR_ESYNCIE /*!< Expected SYNC */
#define RCC_CRS_IT_SYNCERR CRS_CR_ERRIE /*!< SYNC error */
#define RCC_CRS_IT_SYNCMISS CRS_CR_ERRIE /*!< SYNC missed */
#define RCC_CRS_IT_TRIMOVF CRS_CR_ERRIE /*!< Trimming overflow or underflow */
/**
* @}
*/
/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
* @{
*/
#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK flag */
#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning flag */
#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /*!< Error flag */
#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC flag */
#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
* @{
*/
/** @brief Macro to configure the USART1 clock (USART1CLK).
*
* @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
* @retval None
*/
#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (__USART1_CLKSOURCE__))
/** @brief Macro to get the USART1 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK2 selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock
* @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock
*/
#define __HAL_RCC_GET_USART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL))
/** @brief Macro to configure the USART2 clock (USART2CLK).
*
* @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
* @retval None
*/
#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (__USART2_CLKSOURCE__))
/** @brief Macro to get the USART2 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock
* @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock
* @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock
* @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock
*/
#define __HAL_RCC_GET_USART2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL))
/** @brief Macro to configure the USART3 clock (USART3CLK).
*
* @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
* @retval None
*/
#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART3SEL, (__USART3_CLKSOURCE__))
/** @brief Macro to get the USART3 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock
* @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock
* @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock
* @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock
*/
#define __HAL_RCC_GET_USART3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_USART3SEL))
#if defined(UART4)
/** @brief Macro to configure the UART4 clock (UART4CLK).
*
* @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
* @retval None
*/
#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART4SEL, (__UART4_CLKSOURCE__))
/** @brief Macro to get the UART4 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock
* @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock
* @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock
* @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock
*/
#define __HAL_RCC_GET_UART4_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART4SEL))
#endif /* UART4 */
#if defined(UART5)
/** @brief Macro to configure the UART5 clock (UART5CLK).
*
* @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
* @retval None
*/
#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_UART5SEL, (__UART5_CLKSOURCE__))
/** @brief Macro to get the UART5 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock
* @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock
* @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock
* @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock
*/
#define __HAL_RCC_GET_UART5_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_UART5SEL))
#endif /* UART5 */
/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
*
* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
* @retval None
*/
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (__LPUART1_CLKSOURCE__))
/** @brief Macro to get the LPUART1 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
*/
#define __HAL_RCC_GET_LPUART1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL))
/** @brief Macro to configure the I2C1 clock (I2C1CLK).
*
* @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
* @retval None
*/
#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (__I2C1_CLKSOURCE__))
/** @brief Macro to get the I2C1 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock
* @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock
* @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock
*/
#define __HAL_RCC_GET_I2C1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))
/** @brief Macro to configure the I2C2 clock (I2C2CLK).
*
* @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
* @retval None
*/
#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C2SEL, (__I2C2_CLKSOURCE__))
/** @brief Macro to get the I2C2 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock
* @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock
* @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock
*/
#define __HAL_RCC_GET_I2C2_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C2SEL))
/** @brief Macro to configure the I2C3 clock (I2C3CLK).
*
* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
* @retval None
*/
#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (__I2C3_CLKSOURCE__))
/** @brief Macro to get the I2C3 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_I2C3CLKSOURCE_PCLK1 PCLK1 selected as I2C3 clock
* @arg @ref RCC_I2C3CLKSOURCE_HSI HSI selected as I2C3 clock
* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
*/
#define __HAL_RCC_GET_I2C3_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))
#if defined(I2C4)
/** @brief Macro to configure the I2C4 clock (I2C4CLK).
*
* @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
* @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
* @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
* @retval None
*/
#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL, (__I2C4_CLKSOURCE__))
/** @brief Macro to get the I2C4 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock
* @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock
* @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock
*/
#define __HAL_RCC_GET_I2C4_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C4SEL))
#endif /* I2C4 */
/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
*
* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
* @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
* @retval None
*/
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (__LPTIM1_CLKSOURCE__))
/** @brief Macro to get the LPTIM1 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPUART1 clock
* @arg @ref RCC_LPTIM1CLKSOURCE_HSI System Clock selected as LPUART1 clock
* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPUART1 clock
*/
#define __HAL_RCC_GET_LPTIM1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))
/**
* @brief Macro to configure the SAI1 clock source.
* @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived
* from the HSI, system PLL, System Clock or external clock.
* This parameter can be one of the following values:
* @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
* @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
* @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
*
* @retval None
*/
#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, (__SAI1_CLKSOURCE__))
/** @brief Macro to get the SAI1 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_SAI1CLKSOURCE_SYSCLK SAI1 clock = System Clock
* @arg @ref RCC_SAI1CLKSOURCE_PLL SAI1 clock = PLL "Q" clock
* @arg @ref RCC_SAI1CLKSOURCE_EXT SAI1 clock = EXT
* @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI
*
*/
#define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_SAI1SEL))
/**
* @brief Macro to configure the I2S clock source.
* @param __I2S_CLKSOURCE__ defines the I2S clock source. This clock is derived
* from the HSI, system PLL, System Clock or external clock.
* This parameter can be one of the following values:
* @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
* @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
* @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT
* @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI
*
* @retval None
*/
#define __HAL_RCC_I2S_CONFIG(__I2S_CLKSOURCE__)\
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, (__I2S_CLKSOURCE__))
/** @brief Macro to get the I2S clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_I2SCLKSOURCE_SYSCLK I2S clock = System Clock
* @arg @ref RCC_I2SCLKSOURCE_PLL I2S clock = PLL "Q" clock
* @arg @ref RCC_I2SCLKSOURCE_EXT I2S clock = EXT
* @arg @ref RCC_I2SCLKSOURCE_HSI I2S clock = HSI
*
*/
#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2S23SEL)))
#if defined(FDCAN1)
/**
* @brief Macro to configure the FDCAN clock source.
* @param __FDCAN_CLKSOURCE__ defines the FDCAN clock source. This clock is derived
* from the HSE, system PLL or PCLK1.
* This parameter can be one of the following values:
* @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
* @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
* @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
*
* @retval None
*/
#define __HAL_RCC_FDCAN_CONFIG(__FDCAN_CLKSOURCE__)\
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, (uint32_t)(__FDCAN_CLKSOURCE__))
/** @brief Macro to get the FDCAN clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_FDCANCLKSOURCE_HSE FDCAN clock = HSE
* @arg @ref RCC_FDCANCLKSOURCE_PLL FDCAN clock = PLL "Q" clock
* @arg @ref RCC_FDCANCLKSOURCE_PCLK1 FDCAN clock = PCLK1
*
*/
#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_FDCANSEL)))
#endif /* FDCAN1 */
/** @brief Macro to configure the RNG clock.
*
* @note USB and RNG peripherals share the same 48MHz clock source.
*
* @param __RNG_CLKSOURCE__ specifies the RNG clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48
* @arg @ref RCC_RNGCLKSOURCE_PLL PLL Clock selected as RNG clock
* @retval None
*/
#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__RNG_CLKSOURCE__))
/** @brief Macro to get the RNG clock.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 selected as RNG clock for devices with HSI48
* @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock selected as RNG clock
*/
#define __HAL_RCC_GET_RNG_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
#if defined(USB)
/** @brief Macro to configure the USB clock (USBCLK).
*
* @note USB, RNG peripherals share the same 48MHz clock source.
*
* @param __USB_CLKSOURCE__ specifies the USB clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
* @retval None
*/
#define __HAL_RCC_USB_CONFIG(__USB_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, (__USB_CLKSOURCE__))
/** @brief Macro to get the USB clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_USBCLKSOURCE_HSI48 HSI48 selected as 48MHz clock for devices with HSI48
* @arg @ref RCC_USBCLKSOURCE_PLL PLL "Q" clock (PLL48M1CLK) selected as USB clock
*/
#define __HAL_RCC_GET_USB_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_CLK48SEL))
#endif /* USB */
/** @brief Macro to configure the ADC12 interface clock.
* @param __ADC12_CLKSOURCE__ specifies the ADC12 digital interface clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock
* @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock
* @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock
* @retval None
*/
#define __HAL_RCC_ADC12_CONFIG(__ADC12_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC12SEL, (__ADC12_CLKSOURCE__))
/** @brief Macro to get the ADC12 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_ADC12CLKSOURCE_NONE No clock selected as ADC12 clock
* @arg @ref RCC_ADC12CLKSOURCE_PLL PLL Clock selected as ADC12 clock
* @arg @ref RCC_ADC12CLKSOURCE_SYSCLK System Clock selected as ADC12 clock
*/
#define __HAL_RCC_GET_ADC12_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC12SEL))
#if defined(ADC345_COMMON)
/** @brief Macro to configure the ADC345 interface clock.
* @param __ADC345_CLKSOURCE__ specifies the ADC345 digital interface clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock
* @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock
* @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock
* @retval None
*/
#define __HAL_RCC_ADC345_CONFIG(__ADC345_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADC345SEL, __ADC345_CLKSOURCE__)
/** @brief Macro to get the ADC345 clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_ADC345CLKSOURCE_NONE No clock selected as ADC345 clock
* @arg @ref RCC_ADC345CLKSOURCE_PLL PLL Clock selected as ADC345 clock
* @arg @ref RCC_ADC345CLKSOURCE_SYSCLK System Clock selected as ADC345 clock
*/
#define __HAL_RCC_GET_ADC345_SOURCE() (READ_BIT(RCC->CCIPR, RCC_CCIPR_ADC345SEL))
#endif /* ADC345_COMMON */
#if defined(QUADSPI)
/** @brief Macro to configure the QuadSPI clock.
* @param __QSPI_CLKSOURCE__ specifies the QuadSPI clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock
* @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock
* @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock
* @retval None
*/
#define __HAL_RCC_QSPI_CONFIG(__QSPI_CLKSOURCE__) \
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, __QSPI_CLKSOURCE__)
/** @brief Macro to get the QuadSPI clock source.
* @retval The clock source can be one of the following values:
* @arg @ref RCC_QSPICLKSOURCE_SYSCLK System Clock selected as QuadSPI clock
* @arg @ref RCC_QSPICLKSOURCE_HSI HSI clock selected as QuadSPI clock
* @arg @ref RCC_QSPICLKSOURCE_PLL PLL Q divider clock selected as QuadSPI clock
*/
#define __HAL_RCC_GET_QSPI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_QSPISEL))
#endif /* QUADSPI */
/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
*/
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Line.
* @retval None
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Line.
* @retval None
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the RCC LSE CSS Event Line.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Event Line.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.
* @retval EXTI RCC LSE CSS Line Status.
*/
#define __HAL_RCC_LSECSS_EXTI_GET_FLAG() (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
/**
* @brief Clear the RCC LSE CSS EXTI flag.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.
* @retval None.
*/
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
/**
* @brief Enable the specified CRS interrupts.
* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
* @retval None
*/
#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__))
/**
* @brief Disable the specified CRS interrupts.
* @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
* @retval None
*/
#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__))
/** @brief Check whether the CRS interrupt has occurred or not.
* @param __INTERRUPT__ specifies the CRS interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
/** @brief Clear the CRS interrupt pending bits
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt
* @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt
* @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt
* @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt
* @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt
* @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt
* @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt
*/
/* CRS IT Error Mask */
#define RCC_CRS_IT_ERROR_MASK (RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)
#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
{ \
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
} \
else \
{ \
WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
} \
} while(0)
/**
* @brief Check whether the specified CRS flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
* @arg @ref RCC_CRS_FLAG_ERR Error
* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
* @retval The new state of _FLAG_ (TRUE or FALSE).
*/
#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the CRS specified FLAG.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK
* @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning
* @arg @ref RCC_CRS_FLAG_ERR Error
* @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC
* @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow
* @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error
* @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed
* @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
* @retval None
*/
/* CRS Flag Error Mask */
#define RCC_CRS_FLAG_ERROR_MASK (RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \
if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
{ \
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
} \
else \
{ \
WRITE_REG(CRS->ICR, (__FLAG__)); \
} \
} while(0)
/**
* @}
*/
/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
* @{
*/
/**
* @brief Enable the oscillator clock for frequency error counter.
* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
* @retval None
*/
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN)
/**
* @brief Disable the oscillator clock for frequency error counter.
* @retval None
*/
#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)
/**
* @brief Enable the automatic hardware adjustment of TRIM bits.
* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
* @retval None
*/
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
/**
* @brief Enable or disable the automatic hardware adjustment of TRIM bits.
* @retval None
*/
#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
* of the synchronization source after prescaling. It is then decreased by one in order to
* reach the expected synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval None
*/
#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCCEx_Exported_Functions
* @{
*/
/** @addtogroup RCCEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
/**
* @}
*/
/** @addtogroup RCCEx_Exported_Functions_Group2
* @{
*/
void HAL_RCCEx_EnableLSECSS(void);
void HAL_RCCEx_DisableLSECSS(void);
void HAL_RCCEx_EnableLSECSS_IT(void);
void HAL_RCCEx_LSECSS_IRQHandler(void);
void HAL_RCCEx_LSECSS_Callback(void);
void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
void HAL_RCCEx_DisableLSCO(void);
/**
* @}
*/
/** @addtogroup RCCEx_Exported_Functions_Group3
* @{
*/
void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
void HAL_RCCEx_CRS_IRQHandler(void);
void HAL_RCCEx_CRS_SyncOkCallback(void);
void HAL_RCCEx_CRS_SyncWarnCallback(void);
void HAL_RCCEx_CRS_ExpectedSyncCallback(void);
void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RCCEx_Private_Macros
* @{
*/
#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
((__SOURCE__) == RCC_LSCOSOURCE_LSE))
#if defined(STM32G474xx) || defined(STM32G484xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
(((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
(((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345) || \
(((__SELECTION__) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32G471xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32G431xx) || defined(STM32G441xx)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
(((__SELECTION__) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#elif defined(STM32GBK1CB)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
(((__SELECTION__) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
(((__SELECTION__) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN) || \
(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
#endif /* STM32G474xx || STM32G484xx */
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_USART3CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_USART3CLKSOURCE_HSI))
#if defined(UART4)
#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_UART4CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_UART4CLKSOURCE_HSI))
#endif /* UART4 */
#if defined(UART5)
#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_UART5CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_UART5CLKSOURCE_HSI))
#endif /* UART5 */
#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI))
#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
#if defined(I2C4)
#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI))
#endif /* I2C4 */
#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE))
#define IS_RCC_SAI1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_SAI1CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_EXT) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI))
#define IS_RCC_I2SCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2SCLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_I2SCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_I2SCLKSOURCE_EXT) || \
((__SOURCE__) == RCC_I2SCLKSOURCE_HSI))
#if defined(FDCAN1)
#define IS_RCC_FDCANCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE) || \
((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_FDCANCLKSOURCE_PCLK1))
#endif /* FDCAN1 */
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_PLL))
#if defined(USB)
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
((__SOURCE__) == RCC_USBCLKSOURCE_PLL))
#endif /* USB */
#define IS_RCC_ADC12CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADC12CLKSOURCE_NONE) || \
((__SOURCE__) == RCC_ADC12CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_ADC12CLKSOURCE_SYSCLK))
#if defined(ADC345_COMMON)
#define IS_RCC_ADC345CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADC345CLKSOURCE_NONE) || \
((__SOURCE__) == RCC_ADC345CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_ADC345CLKSOURCE_SYSCLK))
#endif /* ADC345_COMMON */
#if defined(QUADSPI)
#define IS_RCC_QSPICLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_QSPICLKSOURCE_HSI) || \
((__SOURCE__) == RCC_QSPICLKSOURCE_SYSCLK)|| \
((__SOURCE__) == RCC_QSPICLKSOURCE_PLL))
#endif /* QUADSPI */
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \
((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU))
#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU))
#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))
#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_RCC_EX_H */
| 72,600 | C | 44.177971 | 173 | 0.578526 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_lptim.h | /**
******************************************************************************
* @file stm32g4xx_hal_lptim.h
* @author MCD Application Team
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_LPTIM_H
#define STM32G4xx_HAL_LPTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup LPTIM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types
* @{
*/
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR2_IM37 /*!< External interrupt line 37 Connected to the LPTIM EXTI Line */
/**
* @brief LPTIM Clock configuration definition
*/
typedef struct
{
uint32_t Source; /*!< Selects the clock source.
This parameter can be a value of @ref LPTIM_Clock_Source */
uint32_t Prescaler; /*!< Specifies the counter clock Prescaler.
This parameter can be a value of @ref LPTIM_Clock_Prescaler */
} LPTIM_ClockConfigTypeDef;
/**
* @brief LPTIM Clock configuration definition
*/
typedef struct
{
uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit
if the ULPTIM input is selected.
Note: This parameter is used only when Ultra low power clock source is used.
Note: If the polarity is configured on 'both edges', an auxiliary clock
(one of the Low power oscillator) must be active.
This parameter can be a value of @ref LPTIM_Clock_Polarity */
uint32_t SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter.
Note: This parameter is used only when Ultra low power clock source is used.
This parameter can be a value of @ref LPTIM_Clock_Sample_Time */
} LPTIM_ULPClockConfigTypeDef;
/**
* @brief LPTIM Trigger configuration definition
*/
typedef struct
{
uint32_t Source; /*!< Selects the Trigger source.
This parameter can be a value of @ref LPTIM_Trigger_Source */
uint32_t ActiveEdge; /*!< Selects the Trigger active edge.
Note: This parameter is used only when an external trigger is used.
This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */
uint32_t SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter.
Note: This parameter is used only when an external trigger is used.
This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */
} LPTIM_TriggerConfigTypeDef;
/**
* @brief LPTIM Initialization Structure definition
*/
typedef struct
{
LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */
LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */
LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */
uint32_t OutputPolarity; /*!< Specifies the Output polarity.
This parameter can be a value of @ref LPTIM_Output_Polarity */
uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare
values is done immediately or after the end of current period.
This parameter can be a value of @ref LPTIM_Updating_Mode */
uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event
or each external event.
This parameter can be a value of @ref LPTIM_Counter_Source */
uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output).
This parameter can be a value of @ref LPTIM_Input1_Source */
uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output).
Note: This parameter is used only for encoder feature so is used only
for LPTIM1 instance.
This parameter can be a value of @ref LPTIM_Input2_Source */
} LPTIM_InitTypeDef;
/**
* @brief HAL LPTIM State structure definition
*/
typedef enum
{
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
} HAL_LPTIM_StateTypeDef;
/**
* @brief LPTIM handle Structure definition
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
typedef struct __LPTIM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
{
LPTIM_TypeDef *Instance; /*!< Register base address */
LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
HAL_LockTypeDef Lock; /*!< LPTIM locking object */
__IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp Init Callback */
void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Base Msp DeInit Callback */
void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare match Callback */
void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload match Callback */
void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< External trigger event detection Callback */
void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Compare register write complete Callback */
void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Auto-reload register write complete Callback */
void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Up-counting direction change Callback */
void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim); /*!< Down-counting direction change Callback */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
} LPTIM_HandleTypeDef;
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LPTIM Callback ID enumeration definition
*/
typedef enum
{
HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM Base Msp Init Callback ID */
HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM Base Msp DeInit Callback ID */
HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< Compare match Callback ID */
HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U, /*!< Auto-reload match Callback ID */
HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< External trigger event detection Callback ID */
HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< Compare register write complete Callback ID */
HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U, /*!< Auto-reload register write complete Callback ID */
HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< Up-counting direction change Callback ID */
HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< Down-counting direction change Callback ID */
} HAL_LPTIM_CallbackIDTypeDef;
/**
* @brief HAL TIM Callback pointer definition
*/
typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< pointer to the LPTIM callback function */
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants
* @{
*/
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
* @{
*/
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
/**
* @}
*/
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
* @{
*/
#define LPTIM_PRESCALER_DIV1 0x00000000U
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)
#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2
#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)
#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)
#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC
/**
* @}
*/
/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity
* @{
*/
#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U
#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL
/**
* @}
*/
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
* @{
*/
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
/**
* @}
*/
/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity
* @{
*/
#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
/**
* @}
*/
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
* @{
*/
#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU
#define LPTIM_TRIGSOURCE_0 0x00000000U
#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2
#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)
#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define LPTIM_TRIGSOURCE_7 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)
#define LPTIM_TRIGSOURCE_8 LPTIM_CFGR_TRIGSEL_3
#define LPTIM_TRIGSOURCE_9 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_3)
#define LPTIM_TRIGSOURCE_10 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
#define LPTIM_TRIGSOURCE_11 (LPTIM_CFGR_TRIGSEL_0 |LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3)
#define LPTIM_TRIGSOURCE_12 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_3)
/**
* @}
*/
/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity
* @{
*/
#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0
#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1
#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN
/**
* @}
*/
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
* @{
*/
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
/**
* @}
*/
/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode
* @{
*/
#define LPTIM_UPDATE_IMMEDIATE 0x00000000U
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
/**
* @}
*/
/** @defgroup LPTIM_Counter_Source LPTIM Counter Source
* @{
*/
#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
/**
* @}
*/
/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source
* @{
*/
#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U
#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_IN1_0
#define LPTIM_INPUT1SOURCE_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
#if defined(COMP5)
#define LPTIM_INPUT1SOURCE_COMP5 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0)
#endif /* COMP5 */
#if defined(COMP7)
#define LPTIM_INPUT1SOURCE_COMP7 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source
* @{
*/
#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U
#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_IN2_0
#define LPTIM_INPUT2SOURCE_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
#if defined(COMP6)
#define LPTIM_INPUT2SOURCE_COMP6 (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0)
#endif /* COMP6 */
/**
* @}
*/
/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition
* @{
*/
#define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN
#define LPTIM_FLAG_UP LPTIM_ISR_UP
#define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK
#define LPTIM_FLAG_CMPOK LPTIM_ISR_CMPOK
#define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG
#define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM
#define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM
/**
* @}
*/
/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition
* @{
*/
#define LPTIM_IT_DOWN LPTIM_IER_DOWNIE
#define LPTIM_IT_UP LPTIM_IER_UPIE
#define LPTIM_IT_ARROK LPTIM_IER_ARROKIE
#define LPTIM_IT_CMPOK LPTIM_IER_CMPOKIE
#define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE
#define LPTIM_IT_ARRM LPTIM_IER_ARRMIE
#define LPTIM_IT_CMPM LPTIM_IER_CMPMIE
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros
* @{
*/
/** @brief Reset LPTIM handle state.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_LPTIM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @brief Enable the LPTIM peripheral.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
/**
* @brief Disable the LPTIM peripheral.
* @param __HANDLE__ LPTIM handle
* @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section.
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
* check for TIMEOUT.
* @retval None
*/
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
/**
* @brief Start the LPTIM peripheral in Continuous mode.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
/**
* @brief Start the LPTIM peripheral in single mode.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_START_SINGLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_SNGSTRT)
/**
* @brief Reset the LPTIM Counter register in synchronous mode.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_COUNTRST)
/**
* @brief Reset after read of the LPTIM Counter register in asynchronous mode.
* @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_RSTARE)
/**
* @brief Write the passed parameter in the Autoreload register.
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value
* @retval None
* @note The ARR register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
/**
* @brief Write the passed parameter in the Compare register.
* @param __HANDLE__ LPTIM handle
* @param __VALUE__ Compare value
* @retval None
* @note The CMP register can only be modified when the LPTIM instance is enabled.
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
/**
* @brief Check whether the specified LPTIM flag is set or not.
* @param __HANDLE__ LPTIM handle
* @param __FLAG__ LPTIM flag to check
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @retval The state of the specified flag (SET or RESET).
*/
#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified LPTIM flag.
* @param __HANDLE__ LPTIM handle.
* @param __FLAG__ LPTIM flag to clear.
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
* @arg LPTIM_FLAG_ARROK : Autoreload register update OK Flag.
* @arg LPTIM_FLAG_CMPOK : Compare register update OK Flag.
* @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.
* @arg LPTIM_FLAG_ARRM : Autoreload match Flag.
* @arg LPTIM_FLAG_CMPM : Compare match Flag.
* @retval None.
*/
#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/**
* @brief Enable the specified LPTIM interrupt.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/**
* @brief Disable the specified LPTIM interrupt.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None.
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/**
* @brief Check whether the specified LPTIM interrupt source is enabled or not.
* @param __HANDLE__ LPTIM handle.
* @param __INTERRUPT__ LPTIM interrupt to check.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
* @arg LPTIM_IT_ARROK : Autoreload register update OK Interrupt.
* @arg LPTIM_IT_CMPOK : Compare register update OK Interrupt.
* @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval Interrupt status.
*/
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR2\
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR2\
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR2\
|= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR2\
&= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions
* @{
*/
/** @addtogroup LPTIM_Exported_Functions_Group1
* @brief Initialization and Configuration functions.
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
/* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group2
* @brief Start-Stop operation functions.
* @{
*/
/* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################# One Pulse Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################## Set once Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################### Encoder Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################# Time out Mode ##############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/* ############################## Counter Mode ###############################*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group3
* @brief Read operation functions.
* @{
*/
/* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group4
* @brief LPTIM IRQ handler and callback functions.
* @{
*/
/* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
/* CallBack functions ********************************************************/
void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID,
pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup LPTIM_Group5
* @brief Peripheral State functions.
* @{
*/
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup LPTIM_Private_Types LPTIM Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Variables LPTIM Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Constants LPTIM Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup LPTIM_Private_Macros LPTIM Private Macros
* @{
*/
#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \
((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))
#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \
((__PRESCALER__) == LPTIM_PRESCALER_DIV128))
#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1)
#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \
((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))
#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \
((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))
#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))
#if defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
((__TRIG__) == LPTIM_TRIGSOURCE_9) || \
((__TRIG__) == LPTIM_TRIGSOURCE_10)|| \
((__TRIG__) == LPTIM_TRIGSOURCE_11)|| \
((__TRIG__) == LPTIM_TRIGSOURCE_12))
#else
#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \
((__TRIG__) == LPTIM_TRIGSOURCE_0) || \
((__TRIG__) == LPTIM_TRIGSOURCE_1) || \
((__TRIG__) == LPTIM_TRIGSOURCE_2) || \
((__TRIG__) == LPTIM_TRIGSOURCE_3) || \
((__TRIG__) == LPTIM_TRIGSOURCE_4) || \
((__TRIG__) == LPTIM_TRIGSOURCE_5) || \
((__TRIG__) == LPTIM_TRIGSOURCE_6) || \
((__TRIG__) == LPTIM_TRIGSOURCE_7) || \
((__TRIG__) == LPTIM_TRIGSOURCE_8) || \
((__TRIG__) == LPTIM_TRIGSOURCE_9))
#endif /* STM32G473xx || STM32G483xx || STM32G474xx || STM32G484xx */
#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING ) || \
((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))
#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \
((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS ))
#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \
((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL)
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL)
#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL)
#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL)
#if defined(COMP5) && defined(COMP6) && defined(COMP7)
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
((((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP5) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP7))))
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
(((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP6)))
#else
#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__) \
((((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) || \
((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP3))))
#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__) \
(((__INSTANCE__) == LPTIM1) && \
(((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2) || \
((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP4)))
#endif /* COMP5 && COMP6 && COMP7 */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{
*/
void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_LPTIM_H */
| 38,656 | C | 43.128995 | 129 | 0.550316 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h | /**
******************************************************************************
* @file stm32g4xx_ll_hrtim.h
* @author MCD Application Team
* @brief Header file of HRTIM LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_HRTIM_H
#define STM32G4xx_LL_HRTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (HRTIM1)
/** @defgroup HRTIM_LL HRTIM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
* @{
*/
static const uint16_t REG_OFFSET_TAB_TIMER[] =
{
0x00U, /* 0: MASTER */
0x80U, /* 1: TIMER A */
0x100U, /* 2: TIMER B */
0x180U, /* 3: TIMER C */
0x200U, /* 4: TIMER D */
0x280U, /* 5: TIMER E */
0x300U, /* 6: TIMER F */
};
static const uint8_t REG_OFFSET_TAB_ADCER[] =
{
0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_ADC1R */
0x04U, /* LL_HRTIM_ADCTRIG_2: HRTIM_ADC2R */
0x08U, /* LL_HRTIM_ADCTRIG_3: HRTIM_ADC3R */
0x0CU, /* LL_HRTIM_ADCTRIG_4: HRTIM_ADC4R */
0x3CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCER */
0x3CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCER */
};
static const uint8_t REG_OFFSET_TAB_ADCUR[] =
{
0x00U, /* LL_HRTIM_ADCTRIG_1: HRTIM_CR1 */
0x00U, /* LL_HRTIM_ADCTRIG_2: HRTIM_CR1 */
0x00U, /* LL_HRTIM_ADCTRIG_3: HRTIM_CR1 */
0x00U, /* LL_HRTIM_ADCTRIG_4: HRTIM_CR1 */
0x7CU, /* LL_HRTIM_ADCTRIG_5: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_6: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_7: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_8: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_9: HRTIM_ADCUR */
0x7CU, /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCUR */
};
static const uint8_t REG_SHIFT_TAB_ADCER[] =
{
0, /* LL_HRTIM_ADCTRIG_1 */
0, /* LL_HRTIM_ADCTRIG_2 */
0, /* LL_HRTIM_ADCTRIG_3 */
0, /* LL_HRTIM_ADCTRIG_4 */
0, /* LL_HRTIM_ADCTRIG_5 */
5, /* LL_HRTIM_ADCTRIG_6 */
10, /* LL_HRTIM_ADCTRIG_7 */
16, /* LL_HRTIM_ADCTRIG_8 */
21, /* LL_HRTIM_ADCTRIG_9 */
26 /* LL_HRTIM_ADCTRIG_10 */
};
static const uint8_t REG_SHIFT_TAB_ADCUR[] =
{
16, /* LL_HRTIM_ADCTRIG_1 */
19, /* LL_HRTIM_ADCTRIG_2 */
22, /* LL_HRTIM_ADCTRIG_3 */
25, /* LL_HRTIM_ADCTRIG_4 */
0, /* LL_HRTIM_ADCTRIG_5 */
4, /* LL_HRTIM_ADCTRIG_6 */
8, /* LL_HRTIM_ADCTRIG_7 */
12, /* LL_HRTIM_ADCTRIG_8 */
16, /* LL_HRTIM_ADCTRIG_9 */
20 /* LL_HRTIM_ADCTRIG_10 */
};
static const uint32_t REG_MASK_TAB_ADCER[] =
{
0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_1 */
0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_2 */
0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_3 */
0xFFFFFFFFU, /* LL_HRTIM_ADCTRIG_4 */
0x0000001FU, /* LL_HRTIM_ADCTRIG_5 */
0x000003E0U, /* LL_HRTIM_ADCTRIG_6 */
0x00007C00U, /* LL_HRTIM_ADCTRIG_7 */
0x001F0000U, /* LL_HRTIM_ADCTRIG_8 */
0x03E00000U, /* LL_HRTIM_ADCTRIG_9 */
0x7C000000U /* LL_HRTIM_ADCTRIG_10 */
};
static const uint32_t REG_MASK_TAB_ADCUR[] =
{
0x00070000U, /* LL_HRTIM_ADCTRIG_1 */
0x00380000U, /* LL_HRTIM_ADCTRIG_2 */
0x01C00000U, /* LL_HRTIM_ADCTRIG_3 */
0x0E000000U, /* LL_HRTIM_ADCTRIG_4 */
0x00000007U, /* LL_HRTIM_ADCTRIG_5 */
0x00000070U, /* LL_HRTIM_ADCTRIG_6 */
0x00000700U, /* LL_HRTIM_ADCTRIG_7 */
0x00007000U, /* LL_HRTIM_ADCTRIG_8 */
0x00070000U, /* LL_HRTIM_ADCTRIG_9 */
0x00700000U /* LL_HRTIM_ADCTRIG_10 */
};
static const uint8_t REG_OFFSET_TAB_ADCPSx[] =
{
0U, /* 0: HRTIM_ADC1R */
6U, /* 1: HRTIM_ADC2R */
12U, /* 2: HRTIM_ADC3R */
18U, /* 3: HRTIM_ADC4R */
24U, /* 4: HRTIM_ADC5R */
32U, /* 5: HRTIM_ADC6R */
38U, /* 6: HRTIM_ADC7R */
44U, /* 7: HRTIM_ADC8R */
50U, /* 8: HRTIM_ADC9R */
56U /* 9: HRTIM_ADC10R */
};
static const uint16_t REG_OFFSET_TAB_SETxR[] =
{
0x00U, /* 0: TA1 */
0x08U, /* 1: TA2 */
0x80U, /* 2: TB1 */
0x88U, /* 3: TB2 */
0x100U, /* 4: TC1 */
0x108U, /* 5: TC2 */
0x180U, /* 6: TD1 */
0x188U, /* 7: TD2 */
0x200U, /* 8: TE1 */
0x208U, /* 9: TE2 */
0x280U, /* 10: TF1 */
0x288U /* 11: TF2 */
};
static const uint16_t REG_OFFSET_TAB_OUTxR[] =
{
0x00U, /* 0: TA1 */
0x00U, /* 1: TA2 */
0x80U, /* 2: TB1 */
0x80U, /* 3: TB2 */
0x100U, /* 4: TC1 */
0x100U, /* 5: TC2 */
0x180U, /* 6: TD1 */
0x180U, /* 7: TD2 */
0x200U, /* 8: TE1 */
0x200U, /* 9: TE2 */
0x280U, /* 10: TF1 */
0x280U /* 11: TF2 */
};
static const uint8_t REG_OFFSET_TAB_EECR[] =
{
0x00U, /* LL_HRTIM_EVENT_1 */
0x00U, /* LL_HRTIM_EVENT_2 */
0x00U, /* LL_HRTIM_EVENT_3 */
0x00U, /* LL_HRTIM_EVENT_4 */
0x00U, /* LL_HRTIM_EVENT_5 */
0x04U, /* LL_HRTIM_EVENT_6 */
0x04U, /* LL_HRTIM_EVENT_7 */
0x04U, /* LL_HRTIM_EVENT_8 */
0x04U, /* LL_HRTIM_EVENT_9 */
0x04U /* LL_HRTIM_EVENT_10 */
};
static const uint8_t REG_OFFSET_TAB_FLTINR[] =
{
0x00U, /* LL_HRTIM_FAULT_1 */
0x00U, /* LL_HRTIM_FAULT_2 */
0x00U, /* LL_HRTIM_FAULT_3 */
0x00U, /* LL_HRTIM_FAULT_4 */
0x04U, /* LL_HRTIM_FAULT_5 */
0x04U /* LL_HRTIM_FAULT_6 */
};
static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
{
0x20000000U, /* 0: MASTER */
0x01FF0000U, /* 1: TIMER A */
0x01FF0000U, /* 2: TIMER B */
0x01FF0000U, /* 3: TIMER C */
0x01FF0000U, /* 4: TIMER D */
0x01FF0000U, /* 5: TIMER E */
0x01FF0000U, /* 5: TIMER E */
0x01FF0000U /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
{
12U, /* 0: MASTER */
0U, /* 1: TIMER A */
0U, /* 2: TIMER B */
0U, /* 3: TIMER C */
0U, /* 4: TIMER D */
0U, /* 5: TIMER E */
0U /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_EExSRC[] =
{
0U, /* LL_HRTIM_EVENT_1 */
6U, /* LL_HRTIM_EVENT_2 */
12U, /* LL_HRTIM_EVENT_3 */
18U, /* LL_HRTIM_EVENT_4 */
24U, /* LL_HRTIM_EVENT_5 */
0U, /* LL_HRTIM_EVENT_6 */
6U, /* LL_HRTIM_EVENT_7 */
12U, /* LL_HRTIM_EVENT_8 */
18U, /* LL_HRTIM_EVENT_9 */
24U /* LL_HRTIM_EVENT_10 */
};
static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
{
HRTIM_MCR_BRSTDMA, /* 0: MASTER */
HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */
HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */
HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */
HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */
HRTIM_TIMCR_UPDGAT, /* 5: TIMER E */
HRTIM_TIMCR_UPDGAT /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
{
2U, /* 0: MASTER */
0U, /* 1: TIMER A */
0U, /* 2: TIMER B */
0U, /* 3: TIMER C */
0U, /* 4: TIMER D */
0U, /* 5: TIMER E */
0U /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_OUTxR[] =
{
0U, /* 0: TA1 */
16U, /* 1: TA2 */
0U, /* 2: TB1 */
16U, /* 3: TB2 */
0U, /* 4: TC1 */
16U, /* 5: TC2 */
0U, /* 6: TD1 */
16U, /* 7: TD2 */
0U, /* 8: TE1 */
16U, /* 9: TE2 */
0U, /* 10: TF1 */
16U /* 11: TF2 */
};
static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
{
0U, /* 0: TA1 */
1U, /* 1: TA2 */
0U, /* 2: TB1 */
1U, /* 3: TB2 */
0U, /* 4: TC1 */
1U, /* 5: TC2 */
0U, /* 6: TD1 */
1U, /* 7: TD2 */
0U, /* 8: TE1 */
1U, /* 9: TE2 */
0U, /* 10: TF1 */
1U /* 11: TF2 */
};
static const uint8_t REG_SHIFT_TAB_FLTxE[] =
{
0U, /* LL_HRTIM_FAULT_1 */
8U, /* LL_HRTIM_FAULT_2 */
16U, /* LL_HRTIM_FAULT_3 */
24U, /* LL_HRTIM_FAULT_4 */
0U, /* LL_HRTIM_FAULT_5 */
8U /* LL_HRTIM_FAULT_6 */
};
static const uint8_t REG_SHIFT_TAB_FLTxF[] =
{
0U, /* LL_HRTIM_FAULT_1 */
8U, /* LL_HRTIM_FAULT_2 */
16U, /* LL_HRTIM_FAULT_3 */
24U, /* LL_HRTIM_FAULT_4 */
32U, /* LL_HRTIM_FAULT_5 */
40U /* LL_HRTIM_FAULT_6 */
};
static const uint8_t REG_SHIFT_TAB_FLTx[] =
{
0, /* LL_HRTIM_FAULT_1 */
1, /* LL_HRTIM_FAULT_2 */
2, /* LL_HRTIM_FAULT_3 */
3, /* LL_HRTIM_FAULT_4 */
4, /* LL_HRTIM_FAULT_5 */
5 /* LL_HRTIM_FAULT_6 */
};
static const uint8_t REG_SHIFT_TAB_INTLVD[] =
{
0U, /* 0: MASTER */
1U, /* 1: TIMER A */
1U, /* 2: TIMER B */
1U, /* 3: TIMER C */
1U, /* 4: TIMER D */
1U, /* 5: TIMER E */
1U, /* 6: TIMER F */
};
static const uint32_t REG_MASK_TAB_INTLVD[] =
{
0x000000E0U, /* 0: MASTER */
0x000001A0U, /* 1: TIMER A */
0x000001A0U, /* 2: TIMER B */
0x000001A0U, /* 3: TIMER C */
0x000001A0U, /* 4: TIMER D */
0x000001A0U, /* 5: TIMER E */
0x000001A0U, /* 6: TIMER F */
};
static const uint8_t REG_SHIFT_TAB_CPT[] =
{
12U, /* 1: TIMER A */
16U, /* 2: TIMER B */
20U, /* 3: TIMER C */
24U, /* 4: TIMER D */
28U, /* 5: TIMER E */
32U, /* 6: TIMER F */
};
static const uint32_t REG_MASK_TAB_CPT[] =
{
0xFFFF0000U, /* 1: TIMER A */
0xFFF0F000U, /* 2: TIMER B */
0xFF0FF000U, /* 3: TIMER C */
0xF0FFF000U, /* 4: TIMER D */
0x0FFFF000U, /* 5: TIMER E */
0xFFFFF000U, /* 6: TIMER F */
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
* @{
*/
#define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\
HRTIM_CR1_TAUDIS |\
HRTIM_CR1_TBUDIS |\
HRTIM_CR1_TCUDIS |\
HRTIM_CR1_TDUDIS |\
HRTIM_CR1_TEUDIS |\
HRTIM_CR1_TFUDIS))
#define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\
HRTIM_CR2_TASWU |\
HRTIM_CR2_TBSWU |\
HRTIM_CR2_TCSWU |\
HRTIM_CR2_TDSWU |\
HRTIM_CR2_TESWU |\
HRTIM_CR2_TFSWU))
#define HRTIM_CR2_SWAP_MASK ((uint32_t)(HRTIM_CR2_SWPA |\
HRTIM_CR2_SWPB |\
HRTIM_CR2_SWPC |\
HRTIM_CR2_SWPD |\
HRTIM_CR2_SWPE |\
HRTIM_CR2_SWPF))
#define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\
HRTIM_CR2_TARST |\
HRTIM_CR2_TBRST |\
HRTIM_CR2_TCRST |\
HRTIM_CR2_TDRST |\
HRTIM_CR2_TERST |\
HRTIM_CR2_TFRST))
#define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\
HRTIM_OENR_TA2OEN |\
HRTIM_OENR_TB1OEN |\
HRTIM_OENR_TB2OEN |\
HRTIM_OENR_TC1OEN |\
HRTIM_OENR_TC2OEN |\
HRTIM_OENR_TD1OEN |\
HRTIM_OENR_TD2OEN |\
HRTIM_OENR_TE1OEN |\
HRTIM_OENR_TE2OEN |\
HRTIM_OENR_TF1OEN |\
HRTIM_OENR_TF2OEN))
#define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\
HRTIM_ODISR_TA2ODIS |\
HRTIM_ODISR_TB1ODIS |\
HRTIM_ODISR_TB2ODIS |\
HRTIM_ODISR_TC1ODIS |\
HRTIM_ODISR_TC2ODIS |\
HRTIM_ODISR_TD1ODIS |\
HRTIM_ODISR_TD2ODIS |\
HRTIM_ODISR_TE1ODIS |\
HRTIM_ODISR_TE2ODIS |\
HRTIM_ODISR_TF1ODIS |\
HRTIM_ODISR_TF2ODIS))
#define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\
HRTIM_OUTR_IDLM1 |\
HRTIM_OUTR_IDLES1 |\
HRTIM_OUTR_FAULT1 |\
HRTIM_OUTR_CHP1 |\
HRTIM_OUTR_DIDL1))
#define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\
HRTIM_EECR1_EE1POL |\
HRTIM_EECR1_EE1SNS |\
HRTIM_EECR1_EE1FAST))
#define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
HRTIM_FLTINR1_FLT1SRC_0 ))
#define HRTIM_FLT_SRC_1_MASK ((uint32_t)(HRTIM_FLTINR2_FLT6SRC_1 |\
HRTIM_FLTINR2_FLT5SRC_1 |\
HRTIM_FLTINR2_FLT4SRC_1 |\
HRTIM_FLTINR2_FLT3SRC_1 |\
HRTIM_FLTINR2_FLT2SRC_1 |\
HRTIM_FLTINR2_FLT1SRC_1))
#define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\
HRTIM_BMCR_BMCLK |\
HRTIM_BMCR_BMOM))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
* @{
*/
/** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_HRTIM_ReadReg function
* @{
*/
#define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1
#define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2
#define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3
#define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4
#define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5
#define LL_HRTIM_ISR_FLT6 HRTIM_ISR_FLT6
#define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT
#define LL_HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY
#define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER
#define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1
#define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2
#define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3
#define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4
#define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP
#define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC
#define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD
#define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1
#define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2
#define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3
#define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4
#define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP
#define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD
#define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1
#define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2
#define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1
#define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1
#define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2
#define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2
#define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST
#define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
* @{
*/
#define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE
#define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE
#define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE
#define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE
#define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE
#define LL_HRTIM_IER_FLT6IE HRTIM_IER_FLT6IE
#define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE
#define LL_HRTIM_IER_DLLRDYIE HRTIM_IER_DLLRDYIE
#define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE
#define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE
#define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE
#define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE
#define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE
#define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE
#define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE
#define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE
#define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE
#define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE
#define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE
#define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE
#define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE
#define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE
#define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE
#define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE
#define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE
#define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE
#define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE
#define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE
#define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE
#define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE
* @{
* @brief Constants defining defining the synchronization input source.
*/
#define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */
#define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */
#define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE
* @{
* @brief Constants defining the source and event to be sent on the synchronization output.
*/
#define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
#define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY
* @{
* @brief Constants defining the routing and conditioning of the synchronization output event.
*/
#define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */
#define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
#define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_TIMER TIMER ID
* @{
* @brief Constants identifying a timing unit.
*/
#define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */
#define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */
#define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */
#define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */
#define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */
#define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */
#define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */
#define LL_HRTIM_TIMER_F HRTIM_MCR_TFCEN /*!< Timer F identifier */
#define LL_HRTIM_TIMER_X (HRTIM_MCR_TFCEN | HRTIM_MCR_TACEN |\
HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
#define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID
* @{
* @brief Constants identifying an HRTIM output.
*/
#define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */
#define LL_HRTIM_OUTPUT_TF1 HRTIM_OENR_TF1OEN /*!< Timer F - Output 1 identifier */
#define LL_HRTIM_OUTPUT_TF2 HRTIM_OENR_TF2OEN /*!< Timer F - Output 2 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID
* @{
* @brief Constants identifying a compare unit.
*/
#define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */
#define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID
* @{
* @brief Constants identifying a capture unit.
*/
#define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */
#define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FAULT FAULT ID
* @{
* @brief Constants identifying a fault channel.
*/
#define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */
#define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */
#define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */
#define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */
#define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */
#define LL_HRTIM_FAULT_6 HRTIM_FLTR_FLT6EN /*!< Fault channel 6 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID
* @{
* @brief Constants identifying an external event channel.
*/
#define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */
#define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */
#define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */
#define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */
#define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */
#define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */
#define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */
#define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */
#define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */
#define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE
* @{
* @brief Constants defining the state of an HRTIM output.
*/
#define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
#define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
#define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER
* @{
* @brief Constants identifying an ADC trigger.
*/
#define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
#define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */
#define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */
#define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */
#define LL_HRTIM_ADCTRIG_5 ((uint32_t)0x00000004U) /*!< ADC trigger 5 identifier */
#define LL_HRTIM_ADCTRIG_6 ((uint32_t)0x00000005U) /*!< ADC trigger 6 identifier */
#define LL_HRTIM_ADCTRIG_7 ((uint32_t)0x00000006U) /*!< ADC trigger 7 identifier */
#define LL_HRTIM_ADCTRIG_8 ((uint32_t)0x00000007U) /*!< ADC trigger 8 identifier */
#define LL_HRTIM_ADCTRIG_9 ((uint32_t)0x00000008U) /*!< ADC trigger 9 identifier */
#define LL_HRTIM_ADCTRIG_10 ((uint32_t)0x00000009U) /*!< ADC trigger 10 identifier */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
* @{
* @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
*/
#define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U /*!< HRTIM_ADCxR register update is triggered by the Timer A */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U /*!< HRTIM_ADCxR register update is triggered by the Timer B */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U /*!< HRTIM_ADCxR register update is triggered by the Timer C */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U /*!< HRTIM_ADCxR register update is triggered by the Timer D */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U /*!< HRTIM_ADCxR register update is triggered by the Timer E */
#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U /*!< HRTIM_ADCxR register update is triggered by the Timer F */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE
* @{
* @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
*/
#define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */
#define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */
#define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */
#define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */
#define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */
#define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */
#define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */
#define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */
#define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2 HRTIM_ADC1R_AD1TFC2 /*!< ADC Trigger on Timer F compare 2 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3 HRTIM_ADC1R_AD1TFC3 /*!< ADC Trigger on Timer F compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4 HRTIM_ADC1R_AD1TFC4 /*!< ADC Trigger on Timer F compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFPER HRTIM_ADC1R_AD1TFPER /*!< ADC Trigger on Timer F period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */
#define LL_HRTIM_ADCTRIG_SRC13_TIMFRST HRTIM_ADC1R_AD1TFRST /*!< ADC Trigger on Timer F reset */
#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */
#define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE
* @{
* @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
*/
#define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */
#define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */
#define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */
#define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */
#define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */
#define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */
#define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */
#define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */
#define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2 HRTIM_ADC2R_AD2TFC2 /*!< ADC Trigger on Timer F compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3 HRTIM_ADC2R_AD2TFC3 /*!< ADC Trigger on Timer F compare 3 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4 HRTIM_ADC2R_AD2TFC4 /*!< ADC Trigger on Timer F compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */
#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMFPER HRTIM_ADC2R_AD2TFPER /*!< ADC Trigger on Timer F period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */
#define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */
#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */
#define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */
/**
* @}
*/
/** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
* @{
* @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10.
*/
#define LL_HRTIM_ADCTRIG_SRC6810_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
#define LL_HRTIM_ADCTRIG_SRC6810_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC6810_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV6 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 6 */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV7 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 7 */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV8 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 8 */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV9 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 9 */
#define LL_HRTIM_ADCTRIG_SRC6810_EEV10 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 10 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2 (uint32_t)0x0D /*!< ADC extended Trigger on Timer B Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Period */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2 (uint32_t)0x10 /*!< ADC extended Trigger on Timer C Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4 (uint32_t)0x11 /*!< ADC extended Trigger on Timer C Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Period */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Reset and counter roll-over */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2 (uint32_t)0x14 /*!< ADC extended Trigger on Timer D Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Period */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Reset and counter roll-over */
#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4 (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIME_RST (uint32_t)0x1B /*!< ADC extended Trigger on Timer E Reset and counter roll-over */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4 (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Period */
/**
* @}
*/
/** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
* @{
* @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9.
*/
#define LL_HRTIM_ADCTRIG_SRC579_MCMP1 (uint32_t)0x00 /*!< ADC extended Trigger on Master Compare 1 */
#define LL_HRTIM_ADCTRIG_SRC579_MCMP2 (uint32_t)0x01 /*!< ADC extended Trigger on Master Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC579_MCMP3 (uint32_t)0x02 /*!< ADC extended Trigger on Master Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_MCMP4 (uint32_t)0x03 /*!< ADC extended Trigger on Master Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_MPER (uint32_t)0x04 /*!< ADC extended Trigger on Master Period */
#define LL_HRTIM_ADCTRIG_SRC579_EEV1 (uint32_t)0x05 /*!< ADC extended Trigger on External Event 1 */
#define LL_HRTIM_ADCTRIG_SRC579_EEV2 (uint32_t)0x06 /*!< ADC extended Trigger on External Event 2 */
#define LL_HRTIM_ADCTRIG_SRC579_EEV3 (uint32_t)0x07 /*!< ADC extended Trigger on External Event 3 */
#define LL_HRTIM_ADCTRIG_SRC579_EEV4 (uint32_t)0x08 /*!< ADC extended Trigger on External Event 4 */
#define LL_HRTIM_ADCTRIG_SRC579_EEV5 (uint32_t)0x09 /*!< ADC extended Trigger on External Event 5 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3 (uint32_t)0x0A /*!< ADC extended Trigger on Timer A Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4 (uint32_t)0x0B /*!< ADC extended Trigger on Timer A Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMA_PER (uint32_t)0x0C /*!< ADC extended Trigger on Timer A Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMA_RST (uint32_t)0x0D /*!< ADC extended Trigger on Timer A Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3 (uint32_t)0x0E /*!< ADC extended Trigger on Timer B Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4 (uint32_t)0x0F /*!< ADC extended Trigger on Timer B Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMB_PER (uint32_t)0x10 /*!< ADC extended Trigger on Timer B Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMB_RST (uint32_t)0x11 /*!< ADC extended Trigger on Timer B Reset and counter roll-over */
#define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3 (uint32_t)0x12 /*!< ADC extended Trigger on Timer C Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4 (uint32_t)0x13 /*!< ADC extended Trigger on Timer C Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMC_PER (uint32_t)0x14 /*!< ADC extended Trigger on Timer C Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3 (uint32_t)0x15 /*!< ADC extended Trigger on Timer D Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4 (uint32_t)0x16 /*!< ADC extended Trigger on Timer D Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMD_PER (uint32_t)0x17 /*!< ADC extended Trigger on Timer D Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3 (uint32_t)0x18 /*!< ADC extended Trigger on Timer E Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4 (uint32_t)0x19 /*!< ADC extended Trigger on Timer E Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIME_PER (uint32_t)0x1A /*!< ADC extended Trigger on Timer E Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2 (uint32_t)0x1B /*!< ADC extended Trigger on Timer F Compare 2 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3 (uint32_t)0x1C /*!< ADC extended Trigger on Timer F Compare 3 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4 (uint32_t)0x1D /*!< ADC extended Trigger on Timer F Compare 4 */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_PER (uint32_t)0x1E /*!< ADC extended Trigger on Timer F Period */
#define LL_HRTIM_ADCTRIG_SRC579_TIMF_RST (uint32_t)0x1F /*!< ADC extended Trigger on Timer F Reset and counter roll-over */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE DLL CALIBRATION MODE
* @{
* @brief Constants defining the DLL calibration mode.
*/
#define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT 0x00000000U /*!<Calibration is performed only once */
#define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS HRTIM_DLLCR_CALEN /*!<Calibration is performed periodically */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CALIBRATIONRATE DLL CALIBRATION RATE
* @{
* @brief Constants defining the DLL calibration periods (in micro seconds).
*/
#define LL_HRTIM_DLLCALIBRATION_RATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
#define LL_HRTIM_DLLCALIBRATION_RATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
#define LL_HRTIM_DLLCALIBRATION_RATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
#define LL_HRTIM_DLLCALIBRATION_RATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
#define LL_HRTIM_PRESCALERRATIO_MUL32 0x00000000U /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL16 ((uint32_t)0x00000001U) /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL8 ((uint32_t)0x00000002U) /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL4 ((uint32_t)0x00000003U) /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_MUL2 ((uint32_t)0x00000004U) /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
#define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_MODE COUNTER MODE
* @{
* @brief Constants defining timer counter operating mode.
*/
#define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */
#define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */
#define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER
* @{
* @brief Constants defining on which output the DAC synchronization event is sent.
*/
#define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */
#define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
#define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
#define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER
* @{
* @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
*/
#define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */
#define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */
#define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */
#define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */
#define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/
#define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */
#define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */
#define LL_HRTIM_UPDATETRIG_TIMER_F HRTIM_TIMCR_TFU /*!< Register update is triggered by the timer F update */
#define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
#define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING
* @{
* @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
*/
#define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
#define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
#define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
#define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
#define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
#define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
#define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */
#define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
#define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE
* @{
* @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
*/
#define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */
#define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
#define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
#define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER
* @{
* @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
*/
#define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */
#define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */
#define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */
#define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */
#define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */
#define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */
#define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */
#define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */
#define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */
#define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */
#define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */
#define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */
#define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */
#define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */
#define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
#define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */
#define LL_HRTIM_RESETTRIG_OTHER5_CMP1 HRTIM_RSTR_TIMFCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */
#define LL_HRTIM_RESETTRIG_OTHER5_CMP2 HRTIM_RSTR_TIMFCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER
* @{
* @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
*/
#define LL_HRTIM_CAPTURETRIG_NONE (uint64_t)0 /*!< Capture trigger is disabled */
#define LL_HRTIM_CAPTURETRIG_SW (uint64_t)HRTIM_CPT1CR_SWCPT /*!< The sw event triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_UPDATE (uint64_t)HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_1 (uint64_t)HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_2 (uint64_t)HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_3 (uint64_t)HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_4 (uint64_t)HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_5 (uint64_t)HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_6 (uint64_t)HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_7 (uint64_t)HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_8 (uint64_t)HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_9 (uint64_t)HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_EEV_10 (uint64_t)HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */
#define LL_HRTIM_CAPTURETRIG_TA1_SET (uint64_t)(HRTIM_CPT1CR_TA1SET ) <<32 /*!< Capture is triggered by TA1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TA1_RESET (uint64_t)(HRTIM_CPT1CR_TA1RST ) <<32 /*!< Capture is triggered by TA1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMACMP1 ) <<32 /*!< Timer A Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMACMP2 ) <<32 /*!< Timer A Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TB1_SET (uint64_t)(HRTIM_CPT1CR_TB1SET ) <<32 /*!< Capture is triggered by TB1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TB1_RESET (uint64_t)(HRTIM_CPT1CR_TB1RST ) <<32 /*!< Capture is triggered by TB1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMBCMP1 ) <<32 /*!< Timer B Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMBCMP2 ) <<32 /*!< Timer B Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TC1_SET (uint64_t)(HRTIM_CPT1CR_TC1SET ) <<32 /*!< Capture is triggered by TC1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TC1_RESET (uint64_t)(HRTIM_CPT1CR_TC1RST ) <<32 /*!< Capture is triggered by TC1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMCCMP1 ) <<32 /*!< Timer C Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMCCMP2 ) <<32 /*!< Timer C Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TD1_SET (uint64_t)(HRTIM_CPT1CR_TD1SET ) <<32 /*!< Capture is triggered by TD1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TD1_RESET (uint64_t)(HRTIM_CPT1CR_TD1RST ) <<32 /*!< Capture is triggered by TD1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMDCMP1 ) <<32 /*!< Timer D Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMDCMP2 ) <<32 /*!< Timer D Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TE1_SET (uint64_t)(HRTIM_CPT1CR_TE1SET ) <<32 /*!< Capture is triggered by TE1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TE1_RESET (uint64_t)(HRTIM_CPT1CR_TE1RST ) <<32 /*!< Capture is triggered by TE1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIME_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMECMP1 ) <<32 /*!< Timer E Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIME_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMECMP2 ) <<32 /*!< Timer E Compare 2 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TF1_SET (uint64_t)(HRTIM_CPT1CR_TF1SET ) <<32 /*!< Capture is triggered by TF1 output inactive to active transition */
#define LL_HRTIM_CAPTURETRIG_TF1_RESET (uint64_t)(HRTIM_CPT1CR_TF1RST ) <<32 /*!< Capture is triggered by TF1 output active to inactive transition */
#define LL_HRTIM_CAPTURETRIG_TIMF_CMP1 (uint64_t)(HRTIM_CPT1CR_TIMFCMP1 ) <<32 /*!< Timer F Compare 1 triggers Capture */
#define LL_HRTIM_CAPTURETRIG_TIMF_CMP2 (uint64_t)(HRTIM_CPT1CR_TIMFCMP2 ) <<32 /*!< Timer F Compare 2 triggers Capture */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE
* @{
* @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
*/
#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
#define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */
#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
#define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
#define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */
#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
#define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE
* @{
* @brief Constants defining how the timer behaves during a burst mode operation.
*/
#define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
#define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA
* @{
* @brief Constants defining the registers that can be written during a burst DMA operation.
*/
#define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */
#define LL_HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS
* @{
* @brief Constants defining on which output the signal is currently applied in push-pull mode.
*/
#define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
#define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS
* @{
* @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
*/
#define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
#define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
* @{
* @brief Constants defining the event filtering applied to external events by a timer.
*/
#define LL_HRTIM_EEFLTR_NONE (0x00000000U)
#define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
#define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
#define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
#define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
/* Blanking Filter for TIMER A */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER B */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER C */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER D */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER E */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER F */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
#define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
#define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
#define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
| HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
* @{
* @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
*/
#define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */
#define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
* @{
* @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
*/
#define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */
#define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */
#define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */
#define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
#define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */
#define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */
#define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */
#define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
* @{
* @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
*/
#define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */
#define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
* @{
* @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
*/
#define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */
#define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
* @{
* @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
*/
#define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */
#define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
#define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
#define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
#define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
#define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
#define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
#define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
#define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
#define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
#define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
#define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
#define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
#define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
#define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
#define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
* @{
* @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
*/
#define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */
#define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */
#define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */
#define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */
#define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */
#define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */
#define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */
#define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
* @{
* @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
*/
#define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */
#define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
#define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
#define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
#define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
#define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
#define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
#define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
#define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
#define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
#define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
#define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
#define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
#define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
#define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
#define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
* @{
* @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
*/
#define LL_HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
#define LL_HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
#define LL_HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */
#define LL_HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */
/* Timer Events mapping for Timer A */
#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer B */
#define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer C */
#define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer D */
#define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer E */
#define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer F */
#define LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define LL_HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */
#define LL_HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */
/**
* @}
*/
/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
* @{
* @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output
*/
#define LL_HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
#define LL_HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
/* Timer Events mapping for Timer A */
#define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer B */
#define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer C */
#define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer D */
#define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer E */
#define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer F */
#define LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
#define LL_HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
* @{
* @brief Constants defining the polarity of a timer output.
*/
#define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */
#define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
* @{
* @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
*/
#define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */
#define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_INTLVD_MODE INTLVD MODE
* @{
* @brief Constants defining the interleaved mode of an HRTIM Timer instance.
*/
#define LL_HRTIM_INTERLEAVED_MODE_DISABLED 0x000U /*!< HRTIM interleaved Mode is disabled */
#define LL_HRTIM_INTERLEAVED_MODE_DUAL HRTIM_MCR_HALF /*!< HRTIM interleaved Mode is Dual */
#define LL_HRTIM_INTERLEAVED_MODE_TRIPLE HRTIM_MCR_INTLVD_0 /*!< HRTIM interleaved Mode is Triple */
#define LL_HRTIM_INTERLEAVED_MODE_QUAD HRTIM_MCR_INTLVD_1 /*!< HRTIM interleaved Mode is Quad */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
* @{
* @brief Constants defining the half mode of an HRTIM Timer instance.
*/
#define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */
#define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
* @{
* @brief Constants defining the output level when output is in IDLE state
*/
#define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
#define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
* @{
* @brief Constants defining the output level when output is in FAULT state.
*/
#define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */
#define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
#define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
#define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
* @{
* @brief Constants defining whether or not chopper mode is enabled for a timer output.
*/
#define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
#define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
* @{
* @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
during a programmable period before the output takes its idle state.
*/
#define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
#define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
* @{
* @brief Constants defining the level of a timer output.
*/
#define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
#define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
* @{
* @brief Constants defining available sources associated to external events.
*/
#define LL_HRTIM_EEV1SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 1 */
#define LL_HRTIM_EEV2SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 2 */
#define LL_HRTIM_EEV3SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 3 */
#define LL_HRTIM_EEV4SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 4 */
#define LL_HRTIM_EEV5SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 5 */
#define LL_HRTIM_EEV6SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 6 */
#define LL_HRTIM_EEV7SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 7 */
#define LL_HRTIM_EEV8SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 8 */
#define LL_HRTIM_EEV9SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 9 */
#define LL_HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1 for External Event 10 */
#define LL_HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 1 */
#define LL_HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 2 */
#define LL_HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 3 */
#define LL_HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 4 */
#define LL_HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 5 */
#define LL_HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 6 */
#define LL_HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 7 */
#define LL_HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 8 */
#define LL_HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 9 */
#define LL_HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 for External Event 10 */
#define LL_HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 1 */
#define LL_HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 2 */
#define LL_HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 3 */
#define LL_HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 4 */
#define LL_HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 5 */
#define LL_HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 6 */
#define LL_HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 7 */
#define LL_HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 8 */
#define LL_HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 9 */
#define LL_HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 for External Event 10 */
#define LL_HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 1 */
#define LL_HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 2 */
#define LL_HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 3 */
#define LL_HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 4 */
#define LL_HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 5 */
#define LL_HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 6 */
#define LL_HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 7 */
#define LL_HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 8 */
#define LL_HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 9 */
#define LL_HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 10 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
* @{
* @brief Constants defining the polarity of an external event.
*/
#define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */
#define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
* @{
* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
*/
#define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */
#define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
#define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
#define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
* @{
* @brief Constants defining whether or not an external event is programmed in fast mode.
*/
#define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
#define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
* @{
* @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
*/
#define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */
#define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */
#define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */
#define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */
#define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */
#define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */
#define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */
#define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */
#define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */
#define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */
#define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */
#define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */
#define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */
#define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */
#define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */
#define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
* @{
* @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
*/
#define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */
#define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */
#define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */
#define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_COUNTER EXTERNAL EVENT A or B COUNTER
* @{
* @brief Constants defining the external event counter.
*/
#define LL_HRTIM_EE_COUNTER_A ((uint32_t)0U) /*!< External Event A Counter */
#define LL_HRTIM_EE_COUNTER_B ((uint32_t)16U) /*!< External Event B Counter */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_EE_COUNTERRSTMODE EXTERNAL EVENT A or B RESET MODE
* @{
* @brief Constants defining the external event reset mode.
*/
#define LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL ((uint32_t)0U) /*!< External Event counter is reset on each reset / roll-over event */
#define LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL ((uint32_t)HRTIM_EEFR3_EEVARSTM) /*!< External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
* @{
* @brief Constants defining whether a faults is be triggered by any external or internal fault source.
*/
#define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */
#define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC_0 /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
#define LL_HRTIM_FLT_SRC_EEVINPUT HRTIM_FLTINR2_FLT1SRC_1 /*!< Fault input is external event pin */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
* @{
* @brief Constants defining the polarity of a fault event.
*/
#define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */
#define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
* @{
* @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
*/
#define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */
#define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */
#define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */
#define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */
#define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */
#define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */
#define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */
#define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */
#define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */
#define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */
#define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */
#define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */
#define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */
#define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */
#define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */
#define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
* @{
* @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters.
*/
#define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */
#define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */
#define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */
#define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_BLKS FAULT BLANKING Source
* @{
* @brief Constants defining the Blanking Source of a fault event.
*/
#define LL_HRTIM_FLT_BLANKING_RSTALIGNED 0x00000000U /*!< Fault blanking source is Reset-aligned */
#define LL_HRTIM_FLT_BLANKING_MOVING (HRTIM_FLTINR3_FLT1BLKS) /*!< Fault blanking source is Moving window */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_FLT_RSTM FAULT Counter RESET Mode
* @{
* @brief Constants defining the Counter RESet Mode of a fault event.
*/
#define LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL 0x00000000U /*!< Fault counter is reset on each reset / roll-over event */
#define LL_HRTIM_FLT_COUNTERRST_CONDITIONAL (HRTIM_FLTINR3_FLT1RSTM) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting
period. */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
* @{
* @brief Constants defining if the burst mode is entered once or if it is continuously operating.
*/
#define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */
#define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
* @{
* @brief Constants defining the clock source for the burst mode counter.
*/
#define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIMER_F (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
#define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
#define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
#define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
#define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
* @{
* @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
*/
#define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */
#define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */
#define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */
#define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */
#define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */
#define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */
#define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */
#define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */
#define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */
#define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */
#define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */
#define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/
#define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */
#define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */
#define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */
#define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
* @{
* @brief Constants defining the events that can be used to trig the burst mode operation.
*/
#define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */
#define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 event is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
#define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
/**
* @}
*/
/** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
* @{
* @brief Constants defining the operating state of the burst mode controller.
*/
#define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */
#define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_MODE Counter Mode
* @{
* @brief Constants defining the Counter Up Down Mode.
*/
#define LL_HRTIM_COUNTING_MODE_UP 0x00000000U /*!< counter is operating in up-counting mode */
#define LL_HRTIM_COUNTING_MODE_UP_DOWN HRTIM_TIMCR2_UDM /*!< counter is operating in up-down counting mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_Roll-Over counter Mode
* @{
* @brief Constants defining the Roll-Over counter Mode.
*/
#define LL_HRTIM_ROLLOVER_MODE_PER 2U /*!< Event generated when counter reaches period value ('crest' mode) */
#define LL_HRTIM_ROLLOVER_MODE_RST 1U /*!< Event generated when counter equals 0 ('valley' mode) */
#define LL_HRTIM_ROLLOVER_MODE_BOTH 0U /*!< Event generated when counter reach both conditions (0 or HRTIM_PERxR value) */
/**
* @}
*/
/** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
* @{
* @brief Constants defining how the timer counter operates.
*/
#define LL_HRTIM_TRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */
#define LL_HRTIM_TRIGHALF_ENABLED HRTIM_TIMCR2_TRGHLF /*!< Timer Compare 2 register is behaving in triggered-half mode */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_Compare Greater than compare PWM Mode
* @{
* @brief Constants defining the greater than compare 1 or 3 PWM Mode.
*/
#define LL_HRTIM_GTCMP1_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
#define LL_HRTIM_GTCMP1_GREATER HRTIM_TIMCR2_GTCMP1 /*!< event is generated when counter is greater than compare value */
#define LL_HRTIM_GTCMP3_EQUAL 0x00000000U /*!< event is generated when counter is equal to compare value */
#define LL_HRTIM_GTCMP3_GREATER HRTIM_TIMCR2_GTCMP3 /*!< event is generated when counter is greater than compare value */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_DCDE Enabling the Dual Channel DAC Triggering
* @{
* @brief Constants enabling the Dual Channel DAC Reset trigger mechanism.
*/
#define LL_HRTIM_DCDE_DISABLED 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
#define LL_HRTIM_DCDE_ENABLED HRTIM_TIMCR2_DCDE /*!< Dual Channel DAC trigger is generated on output 1 set event */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_DCDR Dual Channel DAC Reset Trigger
* @{
* @brief Constants defining the Dual Channel DAC Reset trigger.
*/
#define LL_HRTIM_DCDR_COUNTER 0x00000000U /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
#define LL_HRTIM_DCDR_OUT1SET HRTIM_TIMCR2_DCDR /*!< Dual Channel DAC trigger is generated on output 1 set event */
/**
* @}
*/
/** @defgroup HRTIM_LL_COUNTER_DCDS Dual Channel DAC Step trigger
* @{
* @brief Constants defining the Dual Channel DAC Step trigger.
*/
#define LL_HRTIM_DCDS_CMP2 0x00000000U /*!< trigger is generated on compare 2 event */
#define LL_HRTIM_DCDS_OUT1RST HRTIM_TIMCR2_DCDS /*!< trigger is generated on output 1 reset event */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
* @{
*/
/** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in HRTIM register
* @param __INSTANCE__ HRTIM Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in HRTIM register
* @param __INSTANCE__ HRTIM Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
* @{
*/
/**
* @brief HELPER macro returning the output state from output enable/disable status
* @param __OUTPUT_STATUS_EN__ output enable status
* @param __OUTPUT_STATUS_DIS__ output Disable status
* @retval Returned value can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
* @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
* @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
*/
#define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
(((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\
((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
* @{
*/
/** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
* @{
*/
/**
* @brief Select the HRTIM synchronization input source.
* @note This function must not be called when the concerned timer(s) is (are) enabled .
* @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
* @param HRTIMx High Resolution Timer instance
* @param SyncInSrc This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
* @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
* @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
{
MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
}
/**
* @brief Get actual HRTIM synchronization input source.
* @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc
* @param HRTIMx High Resolution Timer instance
* @retval SyncInSrc Returned value can be one of the following values:
* @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
* @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
* @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
}
/**
* @brief Configure the HRTIM synchronization output.
* @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n
* MCR SYNCOUT LL_HRTIM_ConfigSyncOut
* @param HRTIMx High Resolution Timer instance
* @param Config This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
* @param Src This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
{
MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
}
/**
* @brief Set the routing and conditioning of the synchronization output event.
* @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig
* @note This function can be called only when the master timer is enabled.
* @param HRTIMx High Resolution Timer instance
* @param SyncOutConfig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
{
MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
}
/**
* @brief Get actual routing and conditioning of the synchronization output event.
* @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig
* @param HRTIMx High Resolution Timer instance
* @retval SyncOutConfig Returned value can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_DISABLED
* @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
* @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
}
/**
* @brief Set the source and event to be sent on the HRTIM synchronization output.
* @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc
* @param HRTIMx High Resolution Timer instance
* @param SyncOutSrc This parameter can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
{
MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
}
/**
* @brief Get actual source and event sent on the HRTIM synchronization output.
* @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc
* @param HRTIMx High Resolution Timer instance
* @retval SyncOutSrc Returned value can be one of the following values:
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
* @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
}
/**
* @brief Disable (temporarily) update event generation.
* @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TAUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TBUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TCUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TDUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TEUDIS LL_HRTIM_SuspendUpdate\n
* CR1 TFUDIS LL_HRTIM_SuspendUpdate
* @note Allow to temporarily disable the transfer from preload to active
* registers, whatever the selected update event. This allows to modify
* several registers in multiple timers.
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
/* clear register before applying the new value */
CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((LL_HRTIM_TIMER_ALL >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
}
/**
* @brief Enable update event generation.
* @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TAUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TBUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TCUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TDUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TEUDIS LL_HRTIM_ResumeUpdate\n
* CR1 TFUDIS LL_HRTIM_ResumeUpdate
* @note The regular update event takes place.
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
}
/**
* @brief Force an immediate transfer from the preload to the active register .
* @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n
* CR2 TASWU LL_HRTIM_ForceUpdate\n
* CR2 TBSWU LL_HRTIM_ForceUpdate\n
* CR2 TCSWU LL_HRTIM_ForceUpdate\n
* CR2 TDSWU LL_HRTIM_ForceUpdate\n
* CR2 TESWU LL_HRTIM_ForceUpdate\n
* CR2 TFSWU LL_HRTIM_ForceUpdate
* @note Any pending update request is cancelled.
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
}
/**
* @brief Reset the HRTIM timer(s) counter.
* @rmtoll CR2 MRST LL_HRTIM_CounterReset\n
* CR2 TARST LL_HRTIM_CounterReset\n
* CR2 TBRST LL_HRTIM_CounterReset\n
* CR2 TCRST LL_HRTIM_CounterReset\n
* CR2 TDRST LL_HRTIM_CounterReset\n
* CR2 TERST LL_HRTIM_CounterReset\n
* CR2 TFRST LL_HRTIM_CounterReset
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
}
/**
* @brief enable the swap of the Timer Output.
* @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
* and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
* @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
* @rmtoll CR2 SWPA LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPB LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPC LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPD LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPE LL_HRTIM_EnableSwapOutputs\n
* CR2 SWPF LL_HRTIM_EnableSwapOutputs
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
SET_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer);
}
/**
* @brief disable the swap of the Timer Output.
* @note the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
* and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
* @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
* @rmtoll CR2 SWPA LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPB LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPC LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPD LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPE LL_HRTIM_DisableSwapOutputs\n
* CR2 SWPF LL_HRTIM_DisableSwapOutputs
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
CLEAR_BIT(HRTIMx->sCommonRegs.CR2, (HRTIM_CR2_SWPA << iTimer));
}
/**
* @brief reports the Timer Outputs swap position.
* @note This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
* @rmtoll CR2 SWPA LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPB LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPC LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPD LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPE LL_HRTIM_IsEnabledSwapOutputs\n
* CR2 SWPF LL_HRTIM_IsEnabledSwapOutputs
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval
* 1: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
* HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
* 0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
* HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU);
return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer)));
}
/**
* @brief Enable the HRTIM timer(s) output(s) .
* @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n
* OENR TA2OEN LL_HRTIM_EnableOutput\n
* OENR TB1OEN LL_HRTIM_EnableOutput\n
* OENR TB2OEN LL_HRTIM_EnableOutput\n
* OENR TC1OEN LL_HRTIM_EnableOutput\n
* OENR TC2OEN LL_HRTIM_EnableOutput\n
* OENR TD1OEN LL_HRTIM_EnableOutput\n
* OENR TD2OEN LL_HRTIM_EnableOutput\n
* OENR TE1OEN LL_HRTIM_EnableOutput\n
* OENR TE2OEN LL_HRTIM_EnableOutput\n
* OENR TF1OEN LL_HRTIM_EnableOutput\n
* OENR TF2OEN LL_HRTIM_EnableOutput
* @param HRTIMx High Resolution Timer instance
* @param Outputs This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
{
SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
}
/**
* @brief Disable the HRTIM timer(s) output(s) .
* @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n
* OENR TA2OEN LL_HRTIM_DisableOutput\n
* OENR TB1OEN LL_HRTIM_DisableOutput\n
* OENR TB2OEN LL_HRTIM_DisableOutput\n
* OENR TC1OEN LL_HRTIM_DisableOutput\n
* OENR TC2OEN LL_HRTIM_DisableOutput\n
* OENR TD1OEN LL_HRTIM_DisableOutput\n
* OENR TD2OEN LL_HRTIM_DisableOutput\n
* OENR TE1OEN LL_HRTIM_DisableOutput\n
* OENR TE2OEN LL_HRTIM_DisableOutput\n
* OENR TF1OEN LL_HRTIM_DisableOutput\n
* OENR TF2OEN LL_HRTIM_DisableOutput
* @param HRTIMx High Resolution Timer instance
* @param Outputs This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
{
SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
}
/**
* @brief Indicates whether the HRTIM timer output is enabled.
* @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TA2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TB1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TB2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TC1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TC2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TD1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TD2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TE1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TE2OEN LL_HRTIM_IsEnabledOutput\n
* OENR TF1OEN LL_HRTIM_IsEnabledOutput\n
* OENR TF2OEN LL_HRTIM_IsEnabledOutput
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
}
/**
* @brief Indicates whether the HRTIM timer output is disabled.
* @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TE2ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TF1ODIS LL_HRTIM_IsDisabledOutput\n
* ODISR TF2ODIS LL_HRTIM_IsDisabledOutput
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
}
/**
* @brief Configure an ADC trigger.
* @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n
* CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n
* CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n
* CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFC2 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TFRST LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n
* ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TFC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TFC3 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TFC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TFPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n
* ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFC2 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TFRST LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n
* ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TFC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TFC3 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TFC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TFPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n
* ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @param Update This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
* @param Src This parameter can be a combination of the following values:
*
* For ADC trigger 1 and ADC trigger 3:
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
*
* For ADC trigger 2 and ADC trigger 4:
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
*
* For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
* can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
*
* For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
* can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
{
__IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
REG_OFFSET_TAB_ADCUR[ADCTrig]));
__IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
REG_OFFSET_TAB_ADCER[ADCTrig]));
MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
}
/**
* @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
* @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n
* CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n
* CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n
* CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC5USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC6USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC7USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC8USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC9USRC LL_HRTIM_SetADCTrigUpdate\n
* ADCUR ADC10USRC LL_HRTIM_SetADCTrigUpdate
* @note When the preload is disabled in the source timer, the HRTIM_ADCxR
* registers are not preloaded either: a write access will result in an
* immediate update of the trigger source.
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @param Update This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
{
__IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
REG_OFFSET_TAB_ADCUR[ADCTrig]));
MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
}
/**
* @brief Get the source timer triggering the update of the HRTIM_ADCxR register.
* @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n
* CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n
* CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n
* CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC5USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC6USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC7USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC8USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC9USRC LL_HRTIM_GetADCTrigUpdate\n
* ADCUR ADC10USRC LL_HRTIM_GetADCTrigUpdate
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @retval Update Returned value can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
* @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
{
const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
REG_OFFSET_TAB_ADCUR[ADCTrig]));
return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]);
}
/**
* @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
* @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFC2 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TFRST LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n
* ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TFC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TFC3 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TFC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TFPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n
* ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFC2 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TFRST LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n
* ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TFC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TFC3 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TFC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TFPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n
* ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @param Src
* For ADC trigger 1 and ADC trigger 3 this parameter can be a
* combination of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
*
* For ADC trigger 2 and ADC trigger 4 this parameter can be a
* combination of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
*
* For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
* can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
*
* For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
* can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
{
__IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
REG_OFFSET_TAB_ADCER[ADCTrig]));
MODIFY_REG(*preg, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
}
/**
* @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
* @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TFC2 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TFC3 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TFC4 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TFPER LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TFRST LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n
* ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TFC2 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TFC3 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TFC4 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TFPER LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n
* ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TFC2 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TFC3 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TFC4 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TFPER LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TFRST LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n
* ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TFC2 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TFC3 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TFC4 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TFPER LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n
* ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc
* ADCER ADC5TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC6TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC7TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC8TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC9TRG LL_HRTIM_SetADCTrigSrc\n
* ADCER ADC10TRG LL_HRTIM_SetADCTrigSrc
* @param HRTIMx High Resolution Timer instance
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @retval Src This parameter can be a combination of the following values:
*
* For ADC trigger 1 and ADC trigger 3 this parameter can be a
* combination of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
*
* For ADC trigger 2 and ADC trigger 4 this parameter can be a
* combination of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
*
* For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
* can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
*
* For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
* can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
* @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
{
const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
REG_OFFSET_TAB_ADCER[ADCTrig]));
return (READ_BIT(*preg, (REG_MASK_TAB_ADCER[ADCTrig])) >> REG_SHIFT_TAB_ADCER[ADCTrig]);
}
/**
* @brief Select the ADC post scaler.
* @note This function allows to adjust each ADC trigger rate individually.
* @note In center-aligned mode, the ADC trigger rate is also dependent on
* ADROM[1:0] bitfield, programmed in the source timer
* (see function @ref LL_HRTIM_TIM_SetADCRollOverMode)
* @rmtoll ADCPS2 ADC10PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS2 ADC9PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS2 ADC8PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS2 ADC7PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS2 ADC6PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS1 ADC5PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS1 ADC4PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS1 ADC3PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS1 ADC2PSC LL_HRTIM_SetADCPostScaler\n
* ADCPS1 ADC1PSC LL_HRTIM_SetADCPostScaler
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @param PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t PostScaler)
{
uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
uint64_t ratio = (uint64_t)(PostScaler) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
MODIFY_REG(HRTIMx->sCommonRegs.ADCPS1, (uint32_t)mask, (uint32_t)ratio);
MODIFY_REG(HRTIMx->sCommonRegs.ADCPS2, (uint32_t)(mask >> 32U), (uint32_t)(ratio >> 32U));
}
/**
* @brief Get the selected ADC post scaler.
* @rmtoll ADCPS2 ADC10PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS2 ADC9PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS2 ADC8PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS2 ADC7PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS2 ADC6PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS1 ADC5PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS1 ADC4PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS1 ADC3PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS1 ADC2PSC LL_HRTIM_GetADCPostScaler\n
* ADCPS1 ADC1PSC LL_HRTIM_GetADCPostScaler
* @param HRTIMx High Resolution Timer instance
* @param ADCTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ADCTRIG_1
* @arg @ref LL_HRTIM_ADCTRIG_2
* @arg @ref LL_HRTIM_ADCTRIG_3
* @arg @ref LL_HRTIM_ADCTRIG_4
* @arg @ref LL_HRTIM_ADCTRIG_5
* @arg @ref LL_HRTIM_ADCTRIG_6
* @arg @ref LL_HRTIM_ADCTRIG_7
* @arg @ref LL_HRTIM_ADCTRIG_8
* @arg @ref LL_HRTIM_ADCTRIG_9
* @arg @ref LL_HRTIM_ADCTRIG_10
* @retval PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
*/
__STATIC_INLINE uint32_t LL_HRTIM_GetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
{
uint32_t reg1 = READ_REG(HRTIMx->sCommonRegs.ADCPS1);
uint32_t reg2 = READ_REG(HRTIMx->sCommonRegs.ADCPS2);
uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
uint64_t ratio = (uint64_t)(reg1) | ((uint64_t)(reg2) << 32U);
return (uint32_t)((ratio & mask) >> (REG_OFFSET_TAB_ADCPSx[ADCTrig])) ;
}
/**
* @brief Configure the DLL calibration mode.
* @rmtoll DLLCR CALEN LL_HRTIM_ConfigDLLCalibration\n
* DLLCR CALRTE LL_HRTIM_ConfigDLLCalibration
* @param HRTIMx High Resolution Timer instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
* @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
* @param Period This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_0
* @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_1
* @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_2
* @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_3
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
{
MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
}
/**
* @brief Launch DLL calibration
* @rmtoll DLLCR CAL LL_HRTIM_StartDLLCalibration
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
* @{
*/
/**
* @brief Enable timer(s) counter.
* @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterEnable\n
* MDIER TECEN LL_HRTIM_TIM_CounterEnable\n
* MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n
* MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n
* MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n
* MDIER TACEN LL_HRTIM_TIM_CounterEnable\n
* MDIER MCEN LL_HRTIM_TIM_CounterEnable
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
}
/**
* @brief Disable timer(s) counter.
* @rmtoll MDIER TFCEN LL_HRTIM_TIM_CounterDisable\n
* MDIER TECEN LL_HRTIM_TIM_CounterDisable\n
* MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n
* MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n
* MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n
* MDIER TACEN LL_HRTIM_TIM_CounterDisable\n
* MDIER MCEN LL_HRTIM_TIM_CounterDisable
* @param HRTIMx High Resolution Timer instance
* @param Timers This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
{
CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
}
/**
* @brief Indicate whether the timer counter is enabled.
* @rmtoll MDIER TFCEN LL_HRTIM_TIM_IsCounterEnabled\n
* MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n
* MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n
* MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n
* MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n
* MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n
* MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
}
/**
* @brief Set the timer clock prescaler ratio.
* @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n
* TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler
* @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
* @note The prescaling ratio cannot be modified once the timer counter is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
}
/**
* @brief Get the timer clock prescaler ratio
* @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n
* TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Prescaler Returned value can be one of the following values:
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
* @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
* @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
}
/**
* @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable).
* @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n
* MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n
* TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n
* TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_MODE_CONTINUOUS
* @arg @ref LL_HRTIM_MODE_SINGLESHOT
* @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
}
/**
* @brief Get the counter operating mode mode
* @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n
* MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n
* TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n
* TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode Returned value can be one of the following values:
* @arg @ref LL_HRTIM_MODE_CONTINUOUS
* @arg @ref LL_HRTIM_MODE_SINGLESHOT
* @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
}
/**
* @brief Enable the half duty-cycle mode.
* @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n
* TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode
* @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
* active register is automatically updated with HRTIM_MPER/2
* (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MCR_HALF);
}
/**
* @brief Disable the half duty-cycle mode.
* @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n
* TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
CLEAR_BIT(*pReg, HRTIM_MCR_INTLVD << REG_SHIFT_TAB_INTLVD[iTimer]);
}
/**
* @brief Indicate whether half duty-cycle mode is enabled for a given timer.
* @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n
* TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
}
/**
* @brief Enable the Re-Syncronisation Update.
* @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
* or from a software update (TxSWU bit) is taken into account on the following reset/roll-over.
* @note LL_HRTIM_ForceUpdate must be called prior programming the syncrhonization mode to force
* immediate update of the slave timer registers.
* @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_EnableResyncUpdate
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
/* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
}
/**
* @brief Disable the Re-Syncronisation Update.
* @note The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
* or from a software update (TxSWU bit) is taken into account immediately.
* @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_DisableResyncUpdate
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
/* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
}
/**
* @brief Indicate whether the Re-Syncronisation Update is enabled.
* @note This bit specifies whether update source coming outside
* from the timing unit must be synchronized
* @rmtoll TIMxCR RSYNCU LL_HRTIM_TIM_IsEnabledResyncUpdate
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RSYNC bit in HRTIM_TIMxCR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMCR_RSYNCU) == (HRTIM_TIMCR_RSYNCU)) ? 1UL : 0UL);
/* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
}
/**
* @note Interleaved mode complements the Half mode and helps the implementation of interleaved topologies.
* @note When interleaved mode is enabled, the content of the compare registers is overridden.
* @rmtoll MCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
* MCR INTLVD LL_HRTIM_TIM_SetInterleavedMode\n
* TIMxCR HALF LL_HRTIM_TIM_SetInterleavedMode\n
* TIMxCR INTLVD LL_HRTIM_TIM_SetInterleavedMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
* @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
* @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
* @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, REG_MASK_TAB_INTLVD[iTimer],
((Mode & HRTIM_MCR_HALF) | ((Mode & HRTIM_MCR_INTLVD) << REG_SHIFT_TAB_INTLVD[iTimer])));
}
/**
* @brief get the Interleaved configuration.
* @rmtoll MCR INTLVD LL_HRTIM_TIM_GetInterleavedMode\n
* TIMxCR INTLVD LL_HRTIM_TIM_GetInterleavedMode
* @note The interleaved Mode is Triple or Quad if HALF bit is disabled
* the interleaved Mode is dual if HALF bit is set,
* HRTIM_MCMP1R (or HRTIM_CMP1xR) active register is automatically updated
* with HRTIM_MPER/2 or HRTIM_MPER/4
* (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval This parameter can be one of the following values:
* @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
* @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
* @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
* @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
uint32_t Mode = READ_BIT(*pReg, (REG_MASK_TAB_INTLVD[iTimer]));
return ((Mode & HRTIM_MCR_HALF) | ((Mode >> REG_SHIFT_TAB_INTLVD[iTimer]) & HRTIM_MCR_INTLVD));
}
/**
* @brief Enable the timer start when receiving a synchronization input event.
* @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n
* TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
}
/**
* @brief Disable the timer start when receiving a synchronization input event.
* @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n
* TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
}
/**
* @brief Indicate whether the timer start when receiving a synchronization input event.
* @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n
* TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
}
/**
* @brief Enable the timer reset when receiving a synchronization input event.
* @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n
* TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
}
/**
* @brief Disable the timer reset when receiving a synchronization input event.
* @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n
* TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
}
/**
* @brief Indicate whether the timer reset when receiving a synchronization input event.
* @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n
* TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
}
/**
* @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
* @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n
* TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param DACTrig This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DACTRIG_NONE
* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
}
/**
* @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
* @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n
* TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval DACTrig Returned value can be one of the following values:
* @arg @ref LL_HRTIM_DACTRIG_NONE
* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
* @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
}
/**
* @brief Enable the timer registers preload mechanism.
* @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n
* TIMxCR PREEN LL_HRTIM_TIM_EnablePreload
* @note When the preload mode is enabled, accessed registers are shadow registers.
* Their content is transferred into the active register after an update request,
* either software or synchronized with an event.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MCR_PREEN);
}
/**
* @brief Disable the timer registers preload mechanism.
* @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n
* TIMxCR PREEN LL_HRTIM_TIM_DisablePreload
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
}
/**
* @brief Indicate whether the timer registers preload mechanism is enabled.
* @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n
* TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
}
/**
* @brief Set the timer register update trigger.
* @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n
* TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n
* TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n
* TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n
* TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n
* TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n
* TIMxCR TFU LL_HRTIM_TIM_SetUpdateTrig\n
* TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param UpdateTrig This parameter can be one of the following values:
*
* For the master timer this parameter can be one of the following values:
* @arg @ref LL_HRTIM_UPDATETRIG_NONE
* @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
*
* For timer A..F this parameter can be:
* @arg @ref LL_HRTIM_UPDATETRIG_NONE
* or a combination of the following values:
* @arg @ref LL_HRTIM_UPDATETRIG_MASTER
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
* @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
* @arg @ref LL_HRTIM_UPDATETRIG_RESET
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
}
/**
* @brief Get the timer register update trigger.
* @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n
* TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n
* TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n
* TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n
* TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n
* TIMxCR TFU LL_HRTIM_TIM_GetUpdateTrig\n
* TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval UpdateTrig Returned value can be one of the following values:
*
* For the master timer this parameter can be one of the following values:
* @arg @ref LL_HRTIM_UPDATETRIG_NONE
* @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
*
* For timer A..F this parameter can be:
* @arg @ref LL_HRTIM_UPDATETRIG_NONE
* or a combination of the following values:
* @arg @ref LL_HRTIM_UPDATETRIG_MASTER
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
* @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
* @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
* @arg @ref LL_HRTIM_UPDATETRIG_RESET
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]);
}
/**
* @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
* @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n
* TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param UpdateGating This parameter can be one of the following values:
*
* For the master timer this parameter can be one of the following values:
* @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
*
* For the timer A..F this parameter can be one of the following values:
* @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
}
/**
* @brief Get the timer registers update condition.
* @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n
* TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval UpdateGating Returned value can be one of the following values:
*
* For the master timer this parameter can be one of the following values:
* @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
*
* For the timer A..F this parameter can be one of the following values:
* @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
* @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
* @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]);
}
/**
* @brief Enable the push-pull mode.
* @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
}
/**
* @brief Disable the push-pull mode.
* @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
}
/**
* @brief Indicate whether the push-pull mode is enabled.
* @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
}
/**
* @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
* @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n
* TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode
* @note In auto-delayed mode the compare match occurs independently from the timer counter value.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param CompareUnit This parameter can be one of the following values:
* @arg @ref LL_HRTIM_COMPAREUNIT_2
* @arg @ref LL_HRTIM_COMPAREUNIT_4
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
}
/**
* @brief Get the functioning mode of the compare unit.
* @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n
* TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param CompareUnit This parameter can be one of the following values:
* @arg @ref LL_HRTIM_COMPAREUNIT_2
* @arg @ref LL_HRTIM_COMPAREUNIT_4
* @retval Mode Returned value can be one of the following values:
* @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
* @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
REG_OFFSET_TAB_TIMER[iTimer]));
uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift);
}
/**
* @brief Set the timer counter value.
* @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n
* CNTxR CNTx LL_HRTIM_TIM_SetCounter
* @note This function can only be called when the timer is stopped.
* @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
* significant bits of the counter are not significant. They cannot be
* written and return 0 when read.
* @note The timer behavior is not guaranteed if the counter value is set above
* the period.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Counter Value between 0 and 0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
}
/**
* @brief Get actual timer counter value.
* @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n
* CNTxR CNTx LL_HRTIM_TIM_GetCounter
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Counter Value between 0 and 0xFFFF
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
}
/**
* @brief Set the timer period value.
* @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n
* PERxR PERx LL_HRTIM_TIM_SetPeriod
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Period Value between 0 and 0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
}
/**
* @brief Get actual timer period value.
* @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n
* PERxR PERx LL_HRTIM_TIM_GetPeriod
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Period Value between 0 and 0xFFFF
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MPER_MPER));
}
/**
* @brief Set the timer repetition period value.
* @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n
* REPxR REPx LL_HRTIM_TIM_SetRepetition
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Repetition Value between 0 and 0xFF
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
}
/**
* @brief Get actual timer repetition period value.
* @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n
* REPxR REPx LL_HRTIM_TIM_GetRepetition
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Repetition Value between 0 and 0xFF
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MREP_MREP));
}
/**
* @brief Set the compare value of the compare unit 1.
* @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n
* CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
}
/**
* @brief Get actual compare value of the compare unit 1.
* @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n
* CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
}
/**
* @brief Set the compare value of the compare unit 2.
* @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n
* CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
}
/**
* @brief Get actual compare value of the compare unit 2.
* @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n
* CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
}
/**
* @brief Set the compare value of the compare unit 3.
* @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n
* CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
}
/**
* @brief Get actual compare value of the compare unit 3.
* @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n
* CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
}
/**
* @brief Set the compare value of the compare unit 4.
* @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n
* CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
}
/**
* @brief Get actual compare value of the compare unit 4.
* @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n
* CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
}
/**
* @brief Set the reset trigger of a timer counter.
* @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n
* RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n
* RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMFCMP1 LL_HRTIM_TIM_SetResetTrig\n
* RSTxR TIMFCMP2 LL_HRTIM_TIM_SetResetTrig
* @note The reset of the timer counter can be triggered by up to 30 events
* that can be selected among the following sources:
* @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
* @arg The master timer: Reset and Compare 1..4 (5 events).
* @arg The external events EXTEVNT1..10 (10 events).
* @arg All other timing units (e.g. Timer B..F for timer A): Compare 1, 2 and 4 (12 events).
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param ResetTrig This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_RESETTRIG_NONE
* @arg @ref LL_HRTIM_RESETTRIG_UPDATE
* @arg @ref LL_HRTIM_RESETTRIG_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_EEV_1
* @arg @ref LL_HRTIM_RESETTRIG_EEV_2
* @arg @ref LL_HRTIM_RESETTRIG_EEV_3
* @arg @ref LL_HRTIM_RESETTRIG_EEV_4
* @arg @ref LL_HRTIM_RESETTRIG_EEV_5
* @arg @ref LL_HRTIM_RESETTRIG_EEV_6
* @arg @ref LL_HRTIM_RESETTRIG_EEV_7
* @arg @ref LL_HRTIM_RESETTRIG_EEV_8
* @arg @ref LL_HRTIM_RESETTRIG_EEV_9
* @arg @ref LL_HRTIM_RESETTRIG_EEV_10
* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
WRITE_REG(*pReg, ResetTrig);
}
/**
* @brief Get actual reset trigger of a timer counter.
* @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n
* RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n
* RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMFCMP1 LL_HRTIM_TIM_GetResetTrig\n
* RSTxR TIMFCMP2 LL_HRTIM_TIM_GetResetTrig
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval ResetTrig Returned value can be one of the following values:
* @arg @ref LL_HRTIM_RESETTRIG_NONE
* @arg @ref LL_HRTIM_RESETTRIG_UPDATE
* @arg @ref LL_HRTIM_RESETTRIG_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
* @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_EEV_1
* @arg @ref LL_HRTIM_RESETTRIG_EEV_2
* @arg @ref LL_HRTIM_RESETTRIG_EEV_3
* @arg @ref LL_HRTIM_RESETTRIG_EEV_4
* @arg @ref LL_HRTIM_RESETTRIG_EEV_5
* @arg @ref LL_HRTIM_RESETTRIG_EEV_6
* @arg @ref LL_HRTIM_RESETTRIG_EEV_7
* @arg @ref LL_HRTIM_RESETTRIG_EEV_8
* @arg @ref LL_HRTIM_RESETTRIG_EEV_9
* @arg @ref LL_HRTIM_RESETTRIG_EEV_10
* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
* @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
* @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
* @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_REG(*pReg));
}
/**
* @brief Get captured value for capture unit 1.
* @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Captured value
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_REG(*pReg));
}
/**
* @brief Get the counting direction when capture 1 event occurred.
* @rmtoll CPT1xR DIR LL_HRTIM_TIM_GetCapture1Direction
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Filter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_COUNTING_MODE_UP
* @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
}
/**
* @brief Get captured value for capture unit 2.
* @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Captured value
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_REG(*pReg));
}
/**
* @brief Get the counting direction when capture 2 event occurred.
* @rmtoll CPT2xR DIR LL_HRTIM_TIM_GetCapture2Direction
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Filter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_COUNTING_MODE_UP
* @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
}
/**
* @brief Set the trigger of a capture unit for a given timer.
* @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TF1SET LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TF1RST LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TFCMP1 LL_HRTIM_TIM_SetCaptureTrig\n
* CPT1xCR TFCMP2 LL_HRTIM_TIM_SetCaptureTrig
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param CaptureUnit This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CAPTUREUNIT_1
* @arg @ref LL_HRTIM_CAPTUREUNIT_2
* @param CaptureTrig This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_CAPTURETRIG_NONE
* @arg @ref LL_HRTIM_CAPTURETRIG_SW
* @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
* @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
uint64_t CaptureTrig)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU);
uint32_t cfg2 = (uint32_t)((CaptureTrig & 0xFFFFF00F00000000U) >> 32U);
cfg2 = (cfg2 & REG_MASK_TAB_CPT[iTimer]) | ((cfg2 & 0x0000000FU) << (REG_SHIFT_TAB_CPT[iTimer]));
WRITE_REG(*pReg, (cfg1 | cfg2));
}
/**
* @brief Get actual trigger of a capture unit for a given timer.
* @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TF1SET LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TF1RST LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TFCMP1 LL_HRTIM_TIM_GetCaptureTrig\n
* CPT1xCR TFCMP2 LL_HRTIM_TIM_GetCaptureTrig
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param CaptureUnit This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CAPTUREUNIT_1
* @arg @ref LL_HRTIM_CAPTUREUNIT_2
* @retval CaptureTrig This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_CAPTURETRIG_NONE
* @arg @ref LL_HRTIM_CAPTURETRIG_SW
* @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
* @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
* @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
* @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
* @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
* @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
*/
__STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
(uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U)));
uint64_t cfg;
uint32_t CaptureTrig = READ_REG(*pReg);
cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer])));
return ((uint64_t)(((uint64_t)CaptureTrig & (uint64_t)0x00000FFFU) | (uint64_t)((cfg) << 32U)));
}
/**
* @brief Enable deadtime insertion for a given timer.
* @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_OUTR_DTEN);
}
/**
* @brief Disable deadtime insertion for a given timer.
* @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
}
/**
* @brief Indicate whether deadtime insertion is enabled for a given timer.
* @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
}
/**
* @brief Set the delayed protection (DLYPRT) mode.
* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n
* OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode
* @note This function must be called prior enabling the delayed protection
* @note Balanced Idle mode is only available in push-pull mode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param DLYPRTMode Delayed protection (DLYPRT) mode
*
* For timers A, B and C this parameter can be one of the following values:
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
*
* For timers D, E and F this parameter can be one of the following values:
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
}
/**
* @brief Get the delayed protection (DLYPRT) mode.
* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n
* OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval DLYPRTMode Delayed protection (DLYPRT) mode
*
* For timers A, B and C this parameter can be one of the following values:
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
*
* For timers D, E and F this parameter can be one of the following values:
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
* @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
* @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
* @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
}
/**
* @brief Enable delayed protection (DLYPRT) for a given timer.
* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT
* @note This function must not be called once the concerned timer is enabled
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
}
/**
* @brief Disable delayed protection (DLYPRT) for a given timer.
* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT
* @note This function must not be called once the concerned timer is enabled
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
}
/**
* @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
* @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
}
/**
* @brief Enable the Balanced Idle Automatic Resume (BIAR) for a given timer.
* @rmtoll OUTxR BIAR LL_HRTIM_TIM_EnableBIAR
* @note This function must not be called once the concerned timer is enabled
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_OUTR_BIAR);
}
/**
* @brief Disable the Balanced Idle Automatic Resume (BIAR) for a given timer.
* @rmtoll OUTxR BIAR LL_HRTIM_TIM_DisableBIAR
* @note This function must not be called once the concerned timer is enabled
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_OUTR_BIAR);
}
/**
* @brief Indicate whether the Balanced Idle Automatic Resume (BIAR) is enabled for a given timer.
* @rmtoll OUTxR BIAR LL_HRTIM_TIM_IsEnabledBIAR
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_OUTR_BIAR) == (HRTIM_OUTR_BIAR)) ? 1UL : 0UL);
}
/**
* @brief Enable the fault channel(s) for a given timer.
* @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n
* FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n
* FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n
* FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n
* FLTxR FLT5EN LL_HRTIM_TIM_EnableFault\n
* FLTxR FLT6EN LL_HRTIM_TIM_EnableFault
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Faults This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, Faults);
}
/**
* @brief Disable the fault channel(s) for a given timer.
* @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n
* FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n
* FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n
* FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n
* FLTxR FLT5EN LL_HRTIM_TIM_DisableFault\n
* FLTxR FLT6EN LL_HRTIM_TIM_DisableFault
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Faults This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, Faults);
}
/**
* @brief Indicate whether the fault channel is enabled for a given timer.
* @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n
* FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n
* FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n
* FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n
* FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault\n
* FLTxR FLT6EN LL_HRTIM_TIM_IsEnabledFault
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
}
/**
* @brief Lock the fault conditioning set-up for a given timer.
* @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault
* @note Timer fault-related set-up is frozen until the next HRTIM or system reset
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
}
/**
* @brief Define how the timer behaves during a burst mode operation.
* @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n
* BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n
* BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n
* BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n
* BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n
* BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption\n
* BMCR TFBM LL_HRTIM_TIM_SetBurstModeOption
* @note This function must not be called when the burst mode is enabled
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param BurtsModeOption This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
* @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
{
uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
}
/**
* @brief Retrieve how the timer behaves during a burst mode operation.
* @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n
* BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n
* BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n
* BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n
* BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n
* BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption\n
* BMCR TFBM LL_HRTIM_TIM_GetBurstModeOption
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval BurtsMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
* @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
}
/**
* @brief Program which registers are to be written by Burst DMA transfers.
* @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n
* BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Registers Registers to be updated by the DMA request
*
* For Master timer this parameter can be can be a combination of the following values:
* @arg @ref LL_HRTIM_BURSTDMA_NONE
* @arg @ref LL_HRTIM_BURSTDMA_MCR
* @arg @ref LL_HRTIM_BURSTDMA_MICR
* @arg @ref LL_HRTIM_BURSTDMA_MDIER
* @arg @ref LL_HRTIM_BURSTDMA_MCNT
* @arg @ref LL_HRTIM_BURSTDMA_MPER
* @arg @ref LL_HRTIM_BURSTDMA_MREP
* @arg @ref LL_HRTIM_BURSTDMA_MCMP1
* @arg @ref LL_HRTIM_BURSTDMA_MCMP2
* @arg @ref LL_HRTIM_BURSTDMA_MCMP3
* @arg @ref LL_HRTIM_BURSTDMA_MCMP4
*
* For Timers A..F this parameter can be can be a combination of the following values:
* @arg @ref LL_HRTIM_BURSTDMA_NONE
* @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
* @arg @ref LL_HRTIM_BURSTDMA_TIMICR
* @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
* @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
* @arg @ref LL_HRTIM_BURSTDMA_TIMPER
* @arg @ref LL_HRTIM_BURSTDMA_TIMREP
* @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
* @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
* @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
* @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
* @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
* @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
* @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
* @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
* @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
* @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
* @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
* @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
* @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
* @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
* @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
* @arg @ref LL_HRTIM_BURSTDMA_CR2
* @arg @ref LL_HRTIM_BURSTDMA_EEFR3
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
{
const uint8_t REG_OFFSET_TAB_BDTUPR[] =
{
0x00U, /* BDMUPR ; offset = 0x000 */
0x04U, /* BDAUPR ; offset = 0x05C */
0x08U, /* BDBUPR ; offset = 0x060 */
0x0CU, /* BDCUPR ; offset = 0x064 */
0x10U, /* BDDUPR ; offset = 0x068 */
0x14U, /* BDEUPR ; offset = 0x06C */
0x1CU /* BDFUPR ; offset = 0x074 */
};
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer]));
WRITE_REG(*pReg, Registers);
}
/**
* @brief Indicate on which output the signal is currently applied.
* @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus
* @note Only significant when the timer operates in push-pull mode.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval CPPSTAT This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
* @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
}
/**
* @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
* @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval IPPSTAT This parameter can be one of the following values:
* @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
* @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
}
/**
* @brief Set the event filter for a given timer.
* @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n
* EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter
* @note This function must not be called when the timer counter is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param Filter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EEFLTR_NONE
* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Get actual event filter settings for a given timer.
* @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n
* EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @retval Filter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EEFLTR_NONE
* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
* @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
* @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
* @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Enable or disable event latch mechanism for a given timer.
* @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n
* EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus
* @note This function must not be called when the timer counter is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param LatchStatus This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EELATCH_DISABLED
* @arg @ref LL_HRTIM_EELATCH_ENABLED
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
uint32_t LatchStatus)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Get actual event latch status for a given timer.
* @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n
* EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @retval LatchStatus This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EELATCH_DISABLED
* @arg @ref LL_HRTIM_EELATCH_ENABLED
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Select the Trigger-Half operating mode for a given timer.
* @note This bitfield defines whether the compare 2 register
* @note is behaving in standard mode (compare match issued as soon as counter equal compare)
* @note or in triggered-half mode
* @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_SetTriggeredHalfMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TRIGHALF_ENABLED
* @arg @ref LL_HRTIM_TRIGHALF_DISABLED
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_TRGHLF, Mode);
}
/**
* @brief Get the Trigger-Half operating mode for a given timer.
* @note This bitfield reports whether the compare 2 register
* @note is behaving in standard mode (compare match issued as soon as counter equal compare)
* @note or in triggered-half mode
* @rmtoll TIMxCR2 TRGHLF LL_HRTIM_TIM_GetTriggeredHalfMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TRIGHALF_ENABLED
* @arg @ref LL_HRTIM_TRIGHALF_DISABLED
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(* pReg, HRTIM_TIMCR2_TRGHLF));
}
/**
* @brief Select the compare 1 operating mode.
* @note This bit defines the compare 1 operating mode:
* @note 0: the compare 1 event is generated when the counter is equal to the compare value
* @note 1: the compare 1 event is generated when the counter is greater than the compare value
* @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_SetComp1Mode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_GTCMP1_EQUAL
* @arg @ref LL_HRTIM_GTCMP1_GREATER
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP1, Mode);
}
/**
* @brief Get the selected compare 1 operating mode.
* @note This bit reports the compare 1 operating mode:
* @note 0: the compare 1 event is generated when the counter is equal to the compare value
* @note 1: the compare 1 event is generated when the counter is greater than the compare value
* @rmtoll TIMxCR2 GTCMP1 LL_HRTIM_TIM_GetComp1Mode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_GTCMP1_EQUAL
* @arg @ref LL_HRTIM_GTCMP1_GREATER
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP1));
}
/**
* @brief Select the compare 3 operating mode.
* @note This bit defines the compare 3 operating mode:
* @note 0: the compare 3 event is generated when the counter is equal to the compare value
* @note 1: the compare 3 event is generated when the counter is greater than the compare value
* @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_SetComp3Mode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_GTCMP3_EQUAL
* @arg @ref LL_HRTIM_GTCMP3_GREATER
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP3, (Mode));
}
/**
* @brief Get the selected compare 3 operating mode.
* @note This bit reports the compare 3 operating mode:
* @note 0: the compare 3 event is generated when the counter is equal to the compare value
* @note 1: the compare 3 event is generated when the counter is greater than the compare value
* @rmtoll TIMxCR2 GTCMP3 LL_HRTIM_TIM_GetComp1Mode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_GTCMP3_EQUAL
* @arg @ref LL_HRTIM_GTCMP3_GREATER
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP3));
}
/**
* @brief Select the roll-over mode.
* @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
* @note Only concerns the Roll-over event with the following destinations: Update trigger, IRQ
* and DMA requests, repetition counter decrement and External Event filtering.
* @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_SetRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_ROM, (Mode << HRTIM_TIMCR2_ROM_Pos));
}
/**
* @brief Get selected the roll-over mode.
* @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode returned value can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMCR2_ROM) >> HRTIM_TIMCR2_ROM_Pos);
}
/**
* @brief Select Fault and Event roll-over mode.
* @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
* @note only concerns the Roll-over event used by the Fault and Event counters.
* @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_SetFaultEventRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_FEROM, (Mode << HRTIM_TIMCR2_FEROM_Pos));
}
/**
* @brief Get selected Fault and Event role-over mode.
* @rmtoll TIMxCR2 FEROM LL_HRTIM_TIM_GetFaultEventRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode returned value can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMCR2_FEROM) >> HRTIM_TIMCR2_FEROM_Pos);
}
/**
* @brief Select the Burst mode roll-over mode.
* @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
* @note Only concerns the Roll-over event used in the Burst mode controller, as clock as as burst mode trigger.
* @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetBMRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_BMROM, (Mode << HRTIM_TIMCR2_BMROM_Pos));
}
/**
* @brief Get selected Burst mode roll-over mode.
* @rmtoll TIMxCR2 ROM LL_HRTIM_TIM_GetBMRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode returned value can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMCR2_BMROM) >> HRTIM_TIMCR2_BMROM_Pos);
}
/**
* @brief Select the ADC roll-over mode.
* @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
* @note Only concerns the Roll-over event used to trigger the ADC.
* @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_SetADCRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_ADROM, (Mode << HRTIM_TIMCR2_ADROM_Pos));
}
/**
* @brief Get selected ADC roll-over mode.
* @rmtoll TIMxCR2 BMROM LL_HRTIM_TIM_GetADCRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode returned value can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMCR2_ADROM) >> HRTIM_TIMCR2_ADROM_Pos);
}
/**
* @brief Select the ADC roll-over mode.
* @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
* @note Only concerns concerns the Roll-over event which sets and/or resets the outputs,
* as per HRTIM_SETxyR and HRTIM_RSTxyR settings (see function @ref LL_HRTIM_OUT_SetOutputSetSrc()
* and function @ref LL_HRTIM_OUT_SetOutputResetSrc() respectively).
* @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_SetOutputRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_OUTROM, (Mode << HRTIM_TIMCR2_OUTROM_Pos));
}
/**
* @brief Get selected ADC roll-over mode.
* @rmtoll TIMxCR2 OUTROM LL_HRTIM_TIM_GetOutputRollOverMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode returned value can be one of the following values:
* @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
* @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
* @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMCR2_OUTROM) >> HRTIM_TIMCR2_OUTROM_Pos);
}
/**
* @brief Select the counting mode.
* @note The up-down counting mode is available for both continuous and single-shot
* (retriggerable and nonretriggerable) operating modes
* (see function @ref LL_HRTIM_TIM_SetCounterMode()).
* @note The counter roll-over event is defined differently in-up-down counting mode to
* support various operating condition.
* See @ref LL_HRTIM_TIM_SetCounterMode()
* @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_SetCountingMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_COUNTING_MODE_UP
* @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_UDM, Mode);
}
/**
* @brief Get selected counting mode.
* @rmtoll TIMxCR2 UDM LL_HRTIM_TIM_GetCountingMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Mode returned value can be one of the following values:
* @arg @ref LL_HRTIM_COUNTING_MODE_UP
* @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
* @retval None
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMCR2_UDM));
}
/**
* @brief Select Dual Channel DAC Reset trigger.
* @note Significant only when Dual channel DAC trigger is enabled
* (see function @ref LL_HRTIM_TIM_EnableDualDacTrigger()).
* @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_SetDualDacResetTrigger
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DCDR_COUNTER
* @arg @ref LL_HRTIM_DCDR_OUT1SET
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDR, Mode);
}
/**
* @brief Get selected Dual Channel DAC Reset trigger.
* @rmtoll TIMxCR2 DCDR LL_HRTIM_TIM_GetDualDacResetTrigger
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Trigger returned value can be one of the following values:
* @arg @ref LL_HRTIM_DCDR_COUNTER
* @arg @ref LL_HRTIM_DCDR_OUT1SET
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDR));
}
/**
* @brief Select Dual Channel DAC Reset trigger.
* @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_SetDualDacStepTrigger
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DCDS_CMP2
* @arg @ref LL_HRTIM_DCDS_OUT1RST
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDS, Mode);
}
/**
* @brief Get selected Dual Channel DAC Reset trigger.
* @rmtoll TIMxCR2 DCDS LL_HRTIM_TIM_GetDualDacStepTrigger
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Trigger returned value can be one of the following values:
* @arg @ref LL_HRTIM_DCDS_CMP2
* @arg @ref LL_HRTIM_DCDS_OUT1RST
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDS));
}
/**
* @brief Enable Dual Channel DAC trigger.
* @note Only significant when balanced Idle mode is enabled (see function @ref LL_HRTIM_TIM_SetDLYPRTMode()).
* @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_EnableDualDacTrigger
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(* pReg, HRTIM_TIMCR2_DCDE);
}
/**
* @brief Disable Dual Channel DAC trigger.
* @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_DisableDualDacTrigger
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(* pReg, HRTIM_TIMCR2_DCDE);
}
/**
* @brief Indicate whether Dual Channel DAC trigger is enabled for a given timer.
* @rmtoll TIMxCR2 DCDE LL_HRTIM_TIM_IsEnabledDualDacTrigger
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of DCDE bit in HRTIM_TIMxCR2 register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(* pReg, HRTIM_TIMCR2_DCDE) == (HRTIM_TIMCR2_DCDE)) ? 1UL : 0UL);
}
/**
* @brief Set the external event counter threshold.
* @note The external event is propagated to the timer only if the number
* of active edges is greater than the external event counter threshold.
* @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_SetEventCounterThreshold\n
* EEFxR3 EEVACNT LL_HRTIM_TIM_SetEventCounterThreshold
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=63
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
uint32_t Threshold)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVACNT << EventCounter), Threshold << (HRTIM_EEFR3_EEVACNT_Pos + EventCounter));
}
/**
* @brief Get the programmed external event counter threshold.
* @rmtoll EEFxR3 EEVBCNT LL_HRTIM_TIM_GetEventCounterThreshold\n
* EEFxR3 EEVACNT LL_HRTIM_TIM_GetEventCounterThreshold
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @retval Threshold Value between Min_Data=0 and Max_Data=63
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
uint32_t EventCounter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACNT) << EventCounter)) >> ((HRTIM_EEFR3_EEVACNT_Pos + EventCounter))) ;
}
/**
* @brief Select the external event counter source.
* @note External event counting is only valid for edge-sensitive
* external events (See function LL_HRTIM_EE_Config() and function
* LL_HRTIM_EE_SetSensitivity()).
* @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_SetEventCounterSource\n
* EEFxR3 EEVASEL LL_HRTIM_TIM_SetEventCounterSource
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
uint32_t Event)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
uint32_t iEvent = (uint32_t)(POSITION_VAL(Event));
/* register SEL value is 0 if LL_HRTIM_EVENT_1, 1 if LL_HRTIM_EVENT_1, etc
and 9 if LL_HRTIM_EVENT_10 */
MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVASEL << EventCounter), iEvent << (HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
}
/**
* @brief get the selected external event counter source.
* LL_HRTIM_EE_SetSensitivity()).
* @rmtoll EEFxR3 EEVBSEL LL_HRTIM_TIM_GetEventCounterSource\n
* EEFxR3 EEVASEL LL_HRTIM_TIM_GetEventCounterSource
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @retval Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
uint32_t EventCounter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
/* returned value is 0 if SEL is LL_HRTIM_EVENT_1, 1 if SEL is LL_HRTIM_EVENT_1, etc
and 9 if SEL is LL_HRTIM_EVENT_10 */
return ((uint32_t)0x1U << iEvent) ;
}
/**
* @brief Select the external event counter reset mode.
* @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_SetEventCounterResetMode\n
* EEFxR3 EEVARSTM LL_HRTIM_TIM_SetEventCounterResetMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
* @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
uint32_t Mode)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVARSTM << (EventCounter)), Mode << (EventCounter));
}
/**
* @brief Get selected external event counter reset mode.
* @rmtoll EEFxR3 EEVBRSTM LL_HRTIM_TIM_GetEventCounterResetMode\n
* EEFxR3 EEVARSTM LL_HRTIM_TIM_GetEventCounterResetMode
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @retval Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
* @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
uint32_t EventCounter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVARSTM) << (EventCounter))) >> (EventCounter)) ;
}
/**
* @brief Reset the external event counter.
* @rmtoll EEFxR3 EEVACRES LL_HRTIM_TIM_ResetEventCounter\n
* EEFxR3 EEVBCRES LL_HRTIM_TIM_ResetEventCounter
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACRES) << EventCounter);
}
/**
* @brief Enable the external event counter.
* @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_EnableEventCounter\n
* EEFxR3 EEVBCE LL_HRTIM_TIM_EnableEventCounter
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
}
/**
* @brief Disable the external event counter.
* @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_DisableEventCounter\n
* EEFxR3 EEVBCE LL_HRTIM_TIM_DisableEventCounter
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
CLEAR_BIT(*pReg, (HRTIM_EEFR3_EEVACE << EventCounter));
}
/**
* @brief Indicate whether the external event counter is enabled for a given timer.
* @rmtoll EEFxR3 EEVACE LL_HRTIM_TIM_IsEnabledEventCounter\n
* EEFxR3 EEVBCE LL_HRTIM_TIM_IsEnabledEventCounter
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param EventCounter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_COUNTER_A
* @arg @ref LL_HRTIM_EE_COUNTER_B
* @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer,
uint32_t EventCounter)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
uint32_t temp; /* MISRAC-2012 compliance */
temp = READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
return ((temp == ((uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
* @{
*/
/**
* @brief Configure the dead time insertion feature for a given timer.
* @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n
* DTxR SDTF LL_HRTIM_DT_Config\n
* DTxR SDRT LL_HRTIM_DT_Config
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
* @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
* @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
}
/**
* @brief Set the deadtime prescaler value.
* @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
* @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
* @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
}
/**
* @brief Get actual deadtime prescaler value.
* @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
* @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
* @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
* @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
}
/**
* @brief Set the deadtime rising value.
* @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param RisingValue Value between 0 and 0x1FF
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
}
/**
* @brief Get actual deadtime rising value.
* @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval RisingValue Value between 0 and 0x1FF
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_DTR_DTR));
}
/**
* @brief Set the deadtime sign on rising edge.
* @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param RisingSign This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DT_RISING_POSITIVE
* @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
}
/**
* @brief Get actual deadtime sign on rising edge.
* @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval RisingSign This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DT_RISING_POSITIVE
* @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
}
/**
* @brief Set the deadime falling value.
* @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param FallingValue Value between 0 and 0x1FF
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
}
/**
* @brief Get actual deadtime falling value
* @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval FallingValue Value between 0 and 0x1FF
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
}
/**
* @brief Set the deadtime sign on falling edge.
* @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param FallingSign This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
* @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
}
/**
* @brief Get actual deadtime sign on falling edge.
* @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval FallingSign This parameter can be one of the following values:
* @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
* @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
*/
__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
}
/**
* @brief Lock the deadtime value and sign on rising edge.
* @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_DTR_DTRLK);
}
/**
* @brief Lock the deadtime sign on rising edge.
* @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
}
/**
* @brief Lock the deadtime value and sign on falling edge.
* @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_DTR_DTFLK);
}
/**
* @brief Lock the deadtime sign on falling edge.
* @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
* @{
*/
/**
* @brief Configure the chopper stage for a given timer.
* @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n
* CHPxR CARDTY LL_HRTIM_CHP_Config\n
* CHPxR STRTPW LL_HRTIM_CHP_Config
* @note This function must not be called if the chopper mode is already
* enabled for one of the timer outputs.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
}
/**
* @brief Set prescaler determining the carrier frequency to be added on top
* of the timer output signals when chopper mode is enabled.
* @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler
* @note This function must not be called if the chopper mode is already
* enabled for one of the timer outputs.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
}
/**
* @brief Get actual chopper stage prescaler value.
* @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
* @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
*/
__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
}
/**
* @brief Set the chopper duty cycle.
* @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle
* @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
* @note This function must not be called if the chopper mode is already
* enabled for one of the timer outputs.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param DutyCycle This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
}
/**
* @brief Get actual chopper duty cycle.
* @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval DutyCycle This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
* @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
*/
__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
}
/**
* @brief Set the start pulse width.
* @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth
* @note This function must not be called if the chopper mode is already
* enabled for one of the timer outputs.
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @param PulseWidth This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
}
/**
* @brief Get actual start pulse width.
* @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval PulseWidth This parameter can be one of the following values:
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
* @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
*/
__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_Output_Management Output_Management
* @{
*/
/**
* @brief Set the timer output set source.
* @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n
* SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param SetSrc This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUTSET_NONE
* @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
* @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
REG_OFFSET_TAB_SETxR[iOutput]));
WRITE_REG(*pReg, SetSrc);
}
/**
* @brief Get the timer output set source.
* @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n
* SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval SetSrc This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUTSET_NONE
* @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
* @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
REG_OFFSET_TAB_SETxR[iOutput]));
return (uint32_t) READ_REG(*pReg);
}
/**
* @brief Set the timer output reset source.
* @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n
* RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param ResetSrc This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUTRESET_NONE
* @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
REG_OFFSET_TAB_SETxR[iOutput]));
WRITE_REG(*pReg, ResetSrc);
}
/**
* @brief Get the timer output set source.
* @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n
* RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval ResetSrc This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_OUTPUTRESET_NONE
* @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
* @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
* @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
* @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
* (source = TIMy and destination = TIMx, Compare Unit = CMPz).
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
REG_OFFSET_TAB_SETxR[iOutput]));
return (uint32_t) READ_REG(*pReg);
}
/**
* @brief Configure a timer output.
* @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n
* OUTxR IDLEM1 LL_HRTIM_OUT_Config\n
* OUTxR IDLES1 LL_HRTIM_OUT_Config\n
* OUTxR FAULT1 LL_HRTIM_OUT_Config\n
* OUTxR CHP1 LL_HRTIM_OUT_Config\n
* OUTxR DIDL1 LL_HRTIM_OUT_Config\n
* OUTxR POL2 LL_HRTIM_OUT_Config\n
* OUTxR IDLEM2 LL_HRTIM_OUT_Config\n
* OUTxR IDLES2 LL_HRTIM_OUT_Config\n
* OUTxR FAULT2 LL_HRTIM_OUT_Config\n
* OUTxR CHP2 LL_HRTIM_OUT_Config\n
* OUTxR DIDL2 LL_HRTIM_OUT_Config
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
* @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
* @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
(Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
}
/**
* @brief Set the polarity of a timer output.
* @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n
* OUTxR POL2 LL_HRTIM_OUT_SetPolarity
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
* @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
}
/**
* @brief Get actual polarity of the timer output.
* @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n
* OUTxR POL2 LL_HRTIM_OUT_GetPolarity
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval Polarity This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
* @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
/**
* @brief Set the output IDLE mode.
* @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n
* OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode
* @note This function must not be called when the burst mode is active
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param IdleMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_NO_IDLE
* @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
}
/**
* @brief Get actual output IDLE mode.
* @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n
* OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval IdleMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_NO_IDLE
* @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
/**
* @brief Set the output IDLE level.
* @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n
* OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel
* @note This function must be called prior enabling the timer.
* @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param IdleLevel This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
* @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
}
/**
* @brief Get actual output IDLE level.
* @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n
* OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval IdleLevel This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
* @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
/**
* @brief Set the output FAULT state.
* @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n
* OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState
* @note This function must not called when the timer is enabled and a fault
* channel is enabled at timer level.
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param FaultState This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
}
/**
* @brief Get actual FAULT state.
* @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n
* OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval FaultState This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
* @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
/**
* @brief Set the output chopper mode.
* @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n
* OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode
* @note This function must not called when the timer is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param ChopperMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
}
/**
* @brief Get actual output chopper mode
* @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n
* OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval ChopperMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
* @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
/**
* @brief Set the output burst mode entry mode.
* @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n
* OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode
* @note This function must not called when the timer is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param BMEntryMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
}
/**
* @brief Get actual output burst mode entry mode.
* @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n
* OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval BMEntryMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
* @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
}
/**
* @brief Get the level (active or inactive) of the designated output when the
* delayed protection was triggered.
* @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n
* TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval OutputLevel This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
* @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
HRTIM_TIMISR_O1STAT_Pos);
}
/**
* @brief Force the timer output to its active or inactive level.
* @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n
* RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n
* SETx2R SST LL_HRTIM_OUT_ForceLevel\n
* RSTx2R SRT LL_HRTIM_OUT_ForceLevel
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @param OutputLevel This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
* @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
{
const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
{
0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */
0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */
};
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
SET_BIT(*pReg, HRTIM_SET1R_SST);
}
/**
* @brief Get actual output level, before the output stage (chopper, polarity).
* @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n
* TIMxISR O2CPY LL_HRTIM_OUT_GetLevel
* @param HRTIMx High Resolution Timer instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUTPUT_TA1
* @arg @ref LL_HRTIM_OUTPUT_TA2
* @arg @ref LL_HRTIM_OUTPUT_TB1
* @arg @ref LL_HRTIM_OUTPUT_TB2
* @arg @ref LL_HRTIM_OUTPUT_TC1
* @arg @ref LL_HRTIM_OUTPUT_TC2
* @arg @ref LL_HRTIM_OUTPUT_TD1
* @arg @ref LL_HRTIM_OUTPUT_TD2
* @arg @ref LL_HRTIM_OUTPUT_TE1
* @arg @ref LL_HRTIM_OUTPUT_TE2
* @arg @ref LL_HRTIM_OUTPUT_TF1
* @arg @ref LL_HRTIM_OUTPUT_TF2
* @retval OutputLevel This parameter can be one of the following values:
* @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
* @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
*/
__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)
{
uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
REG_OFFSET_TAB_OUTxR[iOutput]));
return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
HRTIM_TIMISR_O1CPY_Pos);
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
* @{
*/
/**
* @brief Configure external event conditioning.
* @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n
* EECR1 EE1POL LL_HRTIM_EE_Config\n
* EECR1 EE1SNS LL_HRTIM_EE_Config\n
* EECR1 EE1FAST LL_HRTIM_EE_Config\n
* EECR1 EE2SRC LL_HRTIM_EE_Config\n
* EECR1 EE2POL LL_HRTIM_EE_Config\n
* EECR1 EE2SNS LL_HRTIM_EE_Config\n
* EECR1 EE2FAST LL_HRTIM_EE_Config\n
* EECR1 EE3SRC LL_HRTIM_EE_Config\n
* EECR1 EE3POL LL_HRTIM_EE_Config\n
* EECR1 EE3SNS LL_HRTIM_EE_Config\n
* EECR1 EE3FAST LL_HRTIM_EE_Config\n
* EECR1 EE4SRC LL_HRTIM_EE_Config\n
* EECR1 EE4POL LL_HRTIM_EE_Config\n
* EECR1 EE4SNS LL_HRTIM_EE_Config\n
* EECR1 EE4FAST LL_HRTIM_EE_Config\n
* EECR1 EE5SRC LL_HRTIM_EE_Config\n
* EECR1 EE5POL LL_HRTIM_EE_Config\n
* EECR1 EE5SNS LL_HRTIM_EE_Config\n
* EECR1 EE5FAST LL_HRTIM_EE_Config\n
* EECR2 EE6SRC LL_HRTIM_EE_Config\n
* EECR2 EE6POL LL_HRTIM_EE_Config\n
* EECR2 EE6SNS LL_HRTIM_EE_Config\n
* EECR2 EE6FAST LL_HRTIM_EE_Config\n
* EECR2 EE7SRC LL_HRTIM_EE_Config\n
* EECR2 EE7POL LL_HRTIM_EE_Config\n
* EECR2 EE7SNS LL_HRTIM_EE_Config\n
* EECR2 EE7FAST LL_HRTIM_EE_Config\n
* EECR2 EE8SRC LL_HRTIM_EE_Config\n
* EECR2 EE8POL LL_HRTIM_EE_Config\n
* EECR2 EE8SNS LL_HRTIM_EE_Config\n
* EECR2 EE8FAST LL_HRTIM_EE_Config\n
* EECR2 EE9SRC LL_HRTIM_EE_Config\n
* EECR2 EE9POL LL_HRTIM_EE_Config\n
* EECR2 EE9SNS LL_HRTIM_EE_Config\n
* EECR2 EE9FAST LL_HRTIM_EE_Config\n
* EECR2 EE10SRC LL_HRTIM_EE_Config\n
* EECR2 EE10POL LL_HRTIM_EE_Config\n
* EECR2 EE10SNS LL_HRTIM_EE_Config\n
* EECR2 EE10FAST LL_HRTIM_EE_Config
* @note This function must not be called when the timer counter is enabled.
* @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
* @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param Configuration This parameter must be a combination of all the following values:
* @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
* @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
* @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
* @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
(Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Set the external event source.
* @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n
* EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n
* EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n
* EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n
* EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n
* EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n
* EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n
* EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n
* EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n
* EECR2 EE10SRC LL_HRTIM_EE_SetSrc
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param Src This parameter can be one of the following values:
* @arg External event source 1
* @arg External event source 2
* @arg External event source 3
* @arg External event source 4
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Get actual external event source.
* @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n
* EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n
* EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n
* EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n
* EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n
* EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n
* EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n
* EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n
* EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n
* EECR2 EE10SRC LL_HRTIM_EE_GetSrc
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @retval EventSrc This parameter can be one of the following values:
* @arg External event source 1
* @arg External event source 2
* @arg External event source 3
* @arg External event source 4
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
/**
* @brief Set the polarity of an external event.
* @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n
* EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n
* EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n
* EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n
* EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n
* EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n
* EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n
* EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n
* EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n
* EECR2 EE10POL LL_HRTIM_EE_SetPolarity
* @note This function must not be called when the timer counter is enabled.
* @note Event polarity is only significant when event detection is level-sensitive.
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_POLARITY_HIGH
* @arg @ref LL_HRTIM_EE_POLARITY_LOW
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Get actual polarity setting of an external event.
* @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n
* EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n
* EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n
* EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n
* EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n
* EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n
* EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n
* EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n
* EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n
* EECR2 EE10POL LL_HRTIM_EE_GetPolarity
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @retval Polarity This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_POLARITY_HIGH
* @arg @ref LL_HRTIM_EE_POLARITY_LOW
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
/**
* @brief Set the sensitivity of an external event.
* @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n
* EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n
* EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n
* EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n
* EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n
* EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n
* EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n
* EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n
* EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n
* EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param Sensitivity This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
* @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
* @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
* @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Get actual sensitivity setting of an external event.
* @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n
* EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n
* EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n
* EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n
* EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n
* EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n
* EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n
* EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n
* EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n
* EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @retval Polarity This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
* @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
* @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
* @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
/**
* @brief Set the fast mode of an external event.
* @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n
* EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n
* EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n
* EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n
* EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n
* EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n
* EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n
* EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n
* EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n
* EECR2 EE10FAST LL_HRTIM_EE_SetFastMode
* @note This function must not be called when the timer counter is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @param FastMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
* @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Get actual fast mode setting of an external event.
* @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n
* EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n
* EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n
* EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n
* EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n
* EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n
* EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n
* EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n
* EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n
* EECR2 EE10FAST LL_HRTIM_EE_GetFastMode
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_1
* @arg @ref LL_HRTIM_EVENT_2
* @arg @ref LL_HRTIM_EVENT_3
* @arg @ref LL_HRTIM_EVENT_4
* @arg @ref LL_HRTIM_EVENT_5
* @retval FastMode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
* @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
REG_OFFSET_TAB_EECR[iEvent]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
/**
* @brief Set the digital noise filter of a external event.
* @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n
* EECR3 EE7F LL_HRTIM_EE_SetFilter\n
* EECR3 EE8F LL_HRTIM_EE_SetFilter\n
* EECR3 EE9F LL_HRTIM_EE_SetFilter\n
* EECR3 EE10F LL_HRTIM_EE_SetFilter
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @param Filter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_FILTER_NONE
* @arg @ref LL_HRTIM_EE_FILTER_1
* @arg @ref LL_HRTIM_EE_FILTER_2
* @arg @ref LL_HRTIM_EE_FILTER_3
* @arg @ref LL_HRTIM_EE_FILTER_4
* @arg @ref LL_HRTIM_EE_FILTER_5
* @arg @ref LL_HRTIM_EE_FILTER_6
* @arg @ref LL_HRTIM_EE_FILTER_7
* @arg @ref LL_HRTIM_EE_FILTER_8
* @arg @ref LL_HRTIM_EE_FILTER_9
* @arg @ref LL_HRTIM_EE_FILTER_10
* @arg @ref LL_HRTIM_EE_FILTER_11
* @arg @ref LL_HRTIM_EE_FILTER_12
* @arg @ref LL_HRTIM_EE_FILTER_13
* @arg @ref LL_HRTIM_EE_FILTER_14
* @arg @ref LL_HRTIM_EE_FILTER_15
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
(Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
}
/**
* @brief Get actual digital noise filter setting of a external event.
* @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n
* EECR3 EE7F LL_HRTIM_EE_GetFilter\n
* EECR3 EE8F LL_HRTIM_EE_GetFilter\n
* EECR3 EE9F LL_HRTIM_EE_GetFilter\n
* EECR3 EE10F LL_HRTIM_EE_GetFilter
* @param HRTIMx High Resolution Timer instance
* @param Event This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EVENT_6
* @arg @ref LL_HRTIM_EVENT_7
* @arg @ref LL_HRTIM_EVENT_8
* @arg @ref LL_HRTIM_EVENT_9
* @arg @ref LL_HRTIM_EVENT_10
* @retval Filter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_FILTER_NONE
* @arg @ref LL_HRTIM_EE_FILTER_1
* @arg @ref LL_HRTIM_EE_FILTER_2
* @arg @ref LL_HRTIM_EE_FILTER_3
* @arg @ref LL_HRTIM_EE_FILTER_4
* @arg @ref LL_HRTIM_EE_FILTER_5
* @arg @ref LL_HRTIM_EE_FILTER_6
* @arg @ref LL_HRTIM_EE_FILTER_7
* @arg @ref LL_HRTIM_EE_FILTER_8
* @arg @ref LL_HRTIM_EE_FILTER_9
* @arg @ref LL_HRTIM_EE_FILTER_10
* @arg @ref LL_HRTIM_EE_FILTER_11
* @arg @ref LL_HRTIM_EE_FILTER_12
* @arg @ref LL_HRTIM_EE_FILTER_13
* @arg @ref LL_HRTIM_EE_FILTER_14
* @arg @ref LL_HRTIM_EE_FILTER_15
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)
{
uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
(uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]);
}
/**
* @brief Set the external event prescaler.
* @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler
* @param HRTIMx High Resolution Timer instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
* @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
* @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
* @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
{
MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
}
/**
* @brief Get actual external event prescaler setting.
* @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler
* @param HRTIMx High Resolution Timer instance
* @retval Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
* @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
* @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
* @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
*/
__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_Fault_management Fault_management
* @{
*/
/**
* @brief Configure fault signal conditioning Polarity and Source.
* @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n
* FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n
* FLTINR1 FLT2P LL_HRTIM_FLT_Config\n
* FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n
* FLTINR1 FLT3P LL_HRTIM_FLT_Config\n
* FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n
* FLTINR1 FLT4P LL_HRTIM_FLT_Config\n
* FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n
* FLTINR2 FLT5P LL_HRTIM_FLT_Config\n
* FLTINR2 FLT5SRC LL_HRTIM_FLT_Config\n
* FLTINR2 FLT6P LL_HRTIM_FLT_Config\n
* FLTINR2 FLT6SRC LL_HRTIM_FLT_Config
* @note This function must not be called when the fault channel is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_EEVINPUT
* @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
__IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
uint64_t cfg;
uint64_t mask;
cfg = ((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_CONFIG_MASK) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
(((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
mask = ((uint64_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 and polarity bits */
((uint64_t)(HRTIM_FLT_SRC_1_MASK) << 32U); /* this for SouRCe bit 1 */
MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
}
/**
* @brief Set the source of a fault signal.
* @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n
* FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n
* FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n
* FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n
* FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc\n
* FLTINR2 FLT6SRC LL_HRTIM_FLT_SetSrc
* @note This function must not be called when the fault channel is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @param Src This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
* @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
* @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
__IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
uint64_t cfg = ( (uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe 0 bit */
(((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
uint64_t mask = ( (uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) | /* this for SouRCe bit 0 */
(((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */
MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
}
/**
* @brief Get actual source of a fault signal.
* @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n
* FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n
* FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n
* FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n
* FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc\n
* FLTINR2 FLT6SRC LL_HRTIM_FLT_GetSrc
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval Source This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
* @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
* @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
__IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
uint64_t Src0;
uint32_t Src1;
uint32_t temp1, temp2; /* temp variables used for MISRA-C */
/* this for SouRCe bit 1 */
Src1 = READ_BIT(*pReg2, HRTIM_FLT_SRC_1_MASK) >> REG_SHIFT_TAB_FLTx[iFault] ;
temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT6SRC_0));
temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT4SRC_0));
/* this for SouRCe bit 0 */
Src0 = (uint64_t)temp1 << 32U;
Src0 |= (uint64_t)temp2;
Src0 = (Src0 >> REG_SHIFT_TAB_FLTxF[iFault]) ;
return ((uint32_t)(Src0 | Src1));
}
/**
* @brief Set the polarity of a fault signal.
* @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n
* FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n
* FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n
* FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n
* FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity\n
* FLTINR2 FLT6P LL_HRTIM_FLT_SetPolarity
* @note This function must not be called when the fault channel is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_POLARITY_LOW
* @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
__IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(HRTIM_FLTINR1_FLT1P)) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1P) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
/* for Polarity bit */
MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg >> 32U));
}
/**
* @brief Get actual polarity of a fault signal.
* @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n
* FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n
* FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n
* FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n
* FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity\n
* FLTINR2 FLT6P LL_HRTIM_FLT_GetPolarity
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval Polarity This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_POLARITY_LOW
* @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
__IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
uint32_t temp1, temp2; /* temp variables used for MISRA-C */
uint64_t cfg;
temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT6P));
temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT4P));
cfg = (uint64_t)temp1 << 32 ;
cfg |= (uint64_t)temp2;
cfg = (cfg >> REG_SHIFT_TAB_FLTxF[iFault]) ;
return (uint32_t)(cfg);
}
/**
* @brief Set the digital noise filter of a fault signal.
* @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n
* FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n
* FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n
* FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n
* FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter\n
* FLTINR2 FLT6F LL_HRTIM_FLT_SetFilter
* @note This function must not be called when the fault channel is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @param Filter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_FILTER_NONE
* @arg @ref LL_HRTIM_FLT_FILTER_1
* @arg @ref LL_HRTIM_FLT_FILTER_2
* @arg @ref LL_HRTIM_FLT_FILTER_3
* @arg @ref LL_HRTIM_FLT_FILTER_4
* @arg @ref LL_HRTIM_FLT_FILTER_5
* @arg @ref LL_HRTIM_FLT_FILTER_6
* @arg @ref LL_HRTIM_FLT_FILTER_7
* @arg @ref LL_HRTIM_FLT_FILTER_8
* @arg @ref LL_HRTIM_FLT_FILTER_9
* @arg @ref LL_HRTIM_FLT_FILTER_10
* @arg @ref LL_HRTIM_FLT_FILTER_11
* @arg @ref LL_HRTIM_FLT_FILTER_12
* @arg @ref LL_HRTIM_FLT_FILTER_13
* @arg @ref LL_HRTIM_FLT_FILTER_14
* @arg @ref LL_HRTIM_FLT_FILTER_15
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
__IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for filter bits */
uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ; /* this for Polarity bit */
MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(flt));
MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(flt >> 32U));
}
/**
* @brief Get actual digital noise filter setting of a fault signal.
* @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n
* FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n
* FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n
* FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n
* FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter\n
* FLTINR2 FLT6F LL_HRTIM_FLT_GetFilter
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval Filter This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_FILTER_NONE
* @arg @ref LL_HRTIM_FLT_FILTER_1
* @arg @ref LL_HRTIM_FLT_FILTER_2
* @arg @ref LL_HRTIM_FLT_FILTER_3
* @arg @ref LL_HRTIM_FLT_FILTER_4
* @arg @ref LL_HRTIM_FLT_FILTER_5
* @arg @ref LL_HRTIM_FLT_FILTER_6
* @arg @ref LL_HRTIM_FLT_FILTER_7
* @arg @ref LL_HRTIM_FLT_FILTER_8
* @arg @ref LL_HRTIM_FLT_FILTER_9
* @arg @ref LL_HRTIM_FLT_FILTER_10
* @arg @ref LL_HRTIM_FLT_FILTER_11
* @arg @ref LL_HRTIM_FLT_FILTER_12
* @arg @ref LL_HRTIM_FLT_FILTER_13
* @arg @ref LL_HRTIM_FLT_FILTER_14
* @arg @ref LL_HRTIM_FLT_FILTER_15
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
__IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
uint32_t temp1, temp2; /* temp variables used for MISRA-C */
uint64_t flt;
temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT6F));
temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT4F));
flt = (uint64_t)temp1 << 32U;
flt |= (uint64_t)temp2;
flt = (flt >> REG_SHIFT_TAB_FLTxF[iFault]) ;
return (uint32_t)(flt);
}
/**
* @brief Set the fault circuitry prescaler.
* @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler
* @param HRTIMx High Resolution Timer instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
{
MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
}
/**
* @brief Get actual fault circuitry prescaler setting.
* @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler
* @param HRTIMx High Resolution Timer instance
* @retval Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
* @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
}
/**
* @brief Lock the fault signal conditioning settings.
* @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n
* FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n
* FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n
* FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n
* FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock\n
* FLTINR2 FLT6LCK LL_HRTIM_FLT_Lock
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
}
/**
* @brief Enable the fault circuitry for the designated fault input.
* @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n
* FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n
* FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n
* FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n
* FLTINR2 FLT5E LL_HRTIM_FLT_Enable\n
* FLTINR2 FLT6E LL_HRTIM_FLT_Enable
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
}
/**
* @brief Disable the fault circuitry for for the designated fault input.
* @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n
* FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n
* FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n
* FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n
* FLTINR2 FLT5E LL_HRTIM_FLT_Disable\n
* FLTINR2 FLT6E LL_HRTIM_FLT_Disable
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
}
/**
* @brief Indicate whether the fault circuitry is enabled for a given fault input.
* @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n
* FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n
* FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n
* FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n
* FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled\n
* FLTINR2 FLT6E LL_HRTIM_FLT_IsEnabled
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
REG_OFFSET_TAB_FLTINR[iFault]));
return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
(HRTIM_FLTINR1_FLT1E)) ? 1UL : 0UL);
}
/**
* @brief Enable the Blanking of the fault circuitry for the designated fault input.
* @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_EnableBlanking\n
* FLTINR1 FLT2BLKE LL_HRTIM_FLT_EnableBlanking\n
* FLTINR1 FLT3BLKE LL_HRTIM_FLT_EnableBlanking\n
* FLTINR1 FLT4BLKE LL_HRTIM_FLT_EnableBlanking\n
* FLTINR2 FLT5BLKE LL_HRTIM_FLT_EnableBlanking\n
* FLTINR2 FLT6BLKE LL_HRTIM_FLT_EnableBlanking
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]);
}
/**
* @brief Disable the Blanking of the fault circuitry for the designated fault input.
* @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_DisableBlanking\n
* FLTINR1 FLT2BLKE LL_HRTIM_FLT_DisableBlanking\n
* FLTINR1 FLT3BLKE LL_HRTIM_FLT_DisableBlanking\n
* FLTINR1 FLT4BLKE LL_HRTIM_FLT_DisableBlanking\n
* FLTINR2 FLT5BLKE LL_HRTIM_FLT_DisableBlanking\n
* FLTINR2 FLT6BLKE LL_HRTIM_FLT_DisableBlanking
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
CLEAR_BIT(*pReg, (HRTIM_FLTINR3_FLT1BLKE << REG_SHIFT_TAB_FLTxE[iFault]));
}
/**
* @brief Indicate whether the Blanking of the fault circuitry is enabled for a given fault input.
* @rmtoll FLTINR1 FLT1BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
* FLTINR1 FLT2BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
* FLTINR1 FLT3BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
* FLTINR1 FLT4BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
* FLTINR2 FLT5BLKE LL_HRTIM_FLT_IsEnabledBlanking\n
* FLTINR2 FLT6BLKE LL_HRTIM_FLT_IsEnabledBlanking
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval State of FLTxBLKE bit in HRTIM_FLTINRx register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
uint32_t temp; /* MISRAC-2012 compliance */
temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault];
return ((temp == (HRTIM_FLTINR3_FLT1BLKE)) ? 1UL : 0UL);
}
/**
* @brief Set the Blanking Source of the fault circuitry for a given fault input.
* @note Fault inputs can be temporary disabled to blank spurious fault events.
* @note This function allows for selection amongst 2 possible blanking sources.
* @note Events triggering blanking window start and blanking window end depend
* on both the selected blanking source and the fault input.
* @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_SetBlankingSrc\n
* FLTINR3 FLT2BLKS LL_HRTIM_FLT_SetBlankingSrc\n
* FLTINR3 FLT3BLKS LL_HRTIM_FLT_SetBlankingSrc\n
* FLTINR3 FLT4BLKS LL_HRTIM_FLT_SetBlankingSrc\n
* FLTINR4 FLT5BLKS LL_HRTIM_FLT_SetBlankingSrc\n
* FLTINR4 FLT6BLKS LL_HRTIM_FLT_SetBlankingSrc
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @param Source parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_BLANKING_RSTALIGNED
* @arg @ref LL_HRTIM_FLT_BLANKING_MOVING
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Source)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault]));
}
/**
* @brief Get the Blanking Source of the fault circuitry is enabled for a given fault input.
* @rmtoll FLTINR3 FLT1BLKS LL_HRTIM_FLT_GetBlankingSrc\n
* FLTINR3 FLT2BLKS LL_HRTIM_FLT_GetBlankingSrc\n
* FLTINR3 FLT3BLKS LL_HRTIM_FLT_GetBlankingSrc\n
* FLTINR3 FLT4BLKS LL_HRTIM_FLT_GetBlankingSrc\n
* FLTINR4 FLT5BLKS LL_HRTIM_FLT_GetBlankingSrc\n
* FLTINR4 FLT6BLKS LL_HRTIM_FLT_GetBlankingSrc
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]));
}
/**
* @brief Set the Counter threshold value of a fault counter.
* @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_SetCounterThreshold\n
* FLTINR3 FLT2CNT LL_HRTIM_FLT_SetCounterThreshold\n
* FLTINR3 FLT3CNT LL_HRTIM_FLT_SetCounterThreshold\n
* FLTINR3 FLT4CNT LL_HRTIM_FLT_SetCounterThreshold\n
* FLTINR4 FLT5CNT LL_HRTIM_FLT_SetCounterThreshold\n
* FLTINR4 FLT6CNT LL_HRTIM_FLT_SetCounterThreshold
* @note This function must not be called when the fault channel is enabled.
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @param Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Threshold)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxE[iFault]));
}
/**
* @brief Get actual the Counter threshold value of a fault counter.
* @rmtoll FLTINR3 FLT1CNT LL_HRTIM_FLT_GetCounterThreshold\n
* FLTINR3 FLT2CNT LL_HRTIM_FLT_GetCounterThreshold\n
* FLTINR3 FLT3CNT LL_HRTIM_FLT_GetCounterThreshold\n
* FLTINR3 FLT4CNT LL_HRTIM_FLT_GetCounterThreshold\n
* FLTINR4 FLT5CNT LL_HRTIM_FLT_GetCounterThreshold\n
* FLTINR4 FLT6CNT LL_HRTIM_FLT_GetCounterThreshold
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]);
}
/**
* @brief Set the mode of reset of a fault counter to 'always reset'.
* @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_SetResetMode\n
* FLTINR3 FLT2RSTM LL_HRTIM_FLT_SetResetMode\n
* FLTINR3 FLT3RSTM LL_HRTIM_FLT_SetResetMode\n
* FLTINR3 FLT4RSTM LL_HRTIM_FLT_SetResetMode\n
* FLTINR4 FLT5RSTM LL_HRTIM_FLT_SetResetMode\n
* FLTINR4 FLT6RSTM LL_HRTIM_FLT_SetResetMode
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
* @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Mode)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]);
}
/**
* @brief Get the mode of reset of a fault counter to 'reset on event'.
* @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_GetResetMode\n
* FLTINR3 FLT2RSTM LL_HRTIM_FLT_GetResetMode\n
* FLTINR3 FLT3RSTM LL_HRTIM_FLT_GetResetMode\n
* FLTINR3 FLT4RSTM LL_HRTIM_FLT_GetResetMode\n
* FLTINR4 FLT5RSTM LL_HRTIM_FLT_GetResetMode\n
* FLTINR4 FLT6RSTM LL_HRTIM_FLT_GetResetMode
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
* @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
*/
__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
return READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]);
}
/**
* @brief Reset the fault counter for a fault circuitry
* @rmtoll FLTINR3 FLT1RSTM LL_HRTIM_FLT_ResetCounter\n
* FLTINR3 FLT2RSTM LL_HRTIM_FLT_ResetCounter\n
* FLTINR3 FLT3RSTM LL_HRTIM_FLT_ResetCounter\n
* FLTINR3 FLT4RSTM LL_HRTIM_FLT_ResetCounter\n
* FLTINR4 FLT5RSTM LL_HRTIM_FLT_ResetCounter\n
* FLTINR4 FLT6RSTM LL_HRTIM_FLT_ResetCounter
* @param HRTIMx High Resolution Timer instance
* @param Fault This parameter can be one of the following values:
* @arg @ref LL_HRTIM_FAULT_1
* @arg @ref LL_HRTIM_FAULT_2
* @arg @ref LL_HRTIM_FAULT_3
* @arg @ref LL_HRTIM_FAULT_4
* @arg @ref LL_HRTIM_FAULT_5
* @arg @ref LL_HRTIM_FAULT_6
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
{
uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
REG_OFFSET_TAB_FLTINR[iFault]));
SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CRES) << REG_SHIFT_TAB_FLTxE[iFault]);
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
* @{
*/
/**
* @brief Configure the burst mode controller.
* @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n
* BMCR BMCLK LL_HRTIM_BM_Config\n
* BMCR BMPRSC LL_HRTIM_BM_Config
* @param HRTIMx High Resolution Timer instance
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
* @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
{
MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
}
/**
* @brief Set the burst mode controller operating mode.
* @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode
* @param HRTIMx High Resolution Timer instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
* @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
{
MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
}
/**
* @brief Get actual burst mode controller operating mode.
* @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode
* @param HRTIMx High Resolution Timer instance
* @retval Mode This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
* @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)
{
return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
}
/**
* @brief Set the burst mode controller clock source.
* @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc
* @param HRTIMx High Resolution Timer instance
* @param ClockSrc This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
* @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
{
MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
}
/**
* @brief Get actual burst mode controller clock source.
* @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc
* @param HRTIMx High Resolution Timer instance
* @retval ClockSrc This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
* @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
* @retval ClockSrc This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
* @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
* @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
* @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)
{
return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
}
/**
* @brief Set the burst mode controller prescaler.
* @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler
* @param HRTIMx High Resolution Timer instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
{
MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
}
/**
* @brief Get actual burst mode controller prescaler setting.
* @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler
* @param HRTIMx High Resolution Timer instance
* @retval Prescaler This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
* @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)
{
return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
}
/**
* @brief Enable burst mode compare and period registers preload.
* @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
}
/**
* @brief Disable burst mode compare and period registers preload.
* @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
}
/**
* @brief Indicate whether burst mode compare and period registers are preloaded.
* @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload
* @param HRTIMx High Resolution Timer instance
* @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)
{
uint32_t temp; /* MISRAC-2012 compliance */
temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
}
/**
* @brief Set the burst mode controller trigger
* @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n
* BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n
* BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n
* BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n
* BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n
* BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n
* BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n
* BMTRGR TARST LL_HRTIM_BM_SetTrig\n
* BMTRGR TAREP LL_HRTIM_BM_SetTrig\n
* BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n
* BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n
* BMTRGR TBRST LL_HRTIM_BM_SetTrig\n
* BMTRGR TBREP LL_HRTIM_BM_SetTrig\n
* BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n
* BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n
* BMTRGR TCRST LL_HRTIM_BM_SetTrig\n
* BMTRGR TCREP LL_HRTIM_BM_SetTrig\n
* BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n
* BMTRGR TDRST LL_HRTIM_BM_SetTrig\n
* BMTRGR TDREP LL_HRTIM_BM_SetTrig\n
* BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n
* BMTRGR TEREP LL_HRTIM_BM_SetTrig\n
* BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n
* BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n
* BMTRGR TFREP LL_HRTIM_BM_SetTrig\n
* BMTRGR TFRST LL_HRTIM_BM_SetTrig\n
* BMTRGR TFCMP1 LL_HRTIM_BM_SetTrig\n
* BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n
* BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n
* BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n
* BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n
* BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig
* @param HRTIMx High Resolution Timer instance
* @param Trig This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_BM_TRIG_NONE
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
* @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
* @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
* @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
* @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
{
WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
}
/**
* @brief Get actual burst mode controller trigger.
* @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n
* BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n
* BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n
* BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n
* BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n
* BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n
* BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n
* BMTRGR TARST LL_HRTIM_BM_GetTrig\n
* BMTRGR TAREP LL_HRTIM_BM_GetTrig\n
* BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n
* BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n
* BMTRGR TBRST LL_HRTIM_BM_GetTrig\n
* BMTRGR TBREP LL_HRTIM_BM_GetTrig\n
* BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n
* BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n
* BMTRGR TCRST LL_HRTIM_BM_GetTrig\n
* BMTRGR TCREP LL_HRTIM_BM_GetTrig\n
* BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n
* BMTRGR TDRST LL_HRTIM_BM_GetTrig\n
* BMTRGR TDREP LL_HRTIM_BM_GetTrig\n
* BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n
* BMTRGR TEREP LL_HRTIM_BM_GetTrig\n
* BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n
* BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n
* BMTRGR TFREP LL_HRTIM_BM_GetTrig\n
* BMTRGR TFRST LL_HRTIM_BM_GetTrig\n
* BMTRGR TFCMP1 LL_HRTIM_BM_GetTrig\n
* BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n
* BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n
* BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n
* BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n
* BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig
* @param HRTIMx High Resolution Timer instance
* @retval Trig This parameter can be a combination of the following values:
* @arg @ref LL_HRTIM_BM_TRIG_NONE
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
* @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
* @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
* @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
* @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
* @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
* @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
* @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
* @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
* @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)
{
return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
}
/**
* @brief Set the burst mode controller compare value.
* @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare
* @param HRTIMx High Resolution Timer instance
* @param CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
{
WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
}
/**
* @brief Get actual burst mode controller compare value.
* @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare
* @param HRTIMx High Resolution Timer instance
* @retval CompareValue Compare value must be above or equal to 3
* periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
* 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)
{
return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
}
/**
* @brief Set the burst mode controller period.
* @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod
* @param HRTIMx High Resolution Timer instance
* @param Period The period value must be above or equal to 3 periods of the fHRTIM clock,
* that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
* The maximum value is 0x0000 FFDF.
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
{
WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
}
/**
* @brief Get actual burst mode controller period.
* @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod
* @param HRTIMx High Resolution Timer instance
* @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
* that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
* The maximum value is 0x0000 FFDF.
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)
{
return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
}
/**
* @brief Enable the burst mode controller
* @rmtoll BMCR BME LL_HRTIM_BM_Enable
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
}
/**
* @brief Disable the burst mode controller
* @rmtoll BMCR BME LL_HRTIM_BM_Disable
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
}
/**
* @brief Indicate whether the burst mode controller is enabled.
* @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled
* @param HRTIMx High Resolution Timer instance
* @retval State of BME bit in HRTIM_BMCR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
}
/**
* @brief Trigger the burst operation (software trigger)
* @rmtoll BMTRGR SW LL_HRTIM_BM_Start
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
}
/**
* @brief Stop the burst mode operation.
* @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop
* @note Causes a burst mode early termination.
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
}
/**
* @brief Get actual burst mode status
* @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus
* @param HRTIMx High Resolution Timer instance
* @retval Status This parameter can be one of the following values:
* @arg @ref LL_HRTIM_BM_STATUS_NORMAL
* @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
*/
__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)
{
return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Clear the Fault 1 interrupt flag.
* @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
}
/**
* @brief Indicate whether Fault 1 interrupt occurred.
* @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
}
/**
* @brief Clear the Fault 2 interrupt flag.
* @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
}
/**
* @brief Indicate whether Fault 2 interrupt occurred.
* @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
}
/**
* @brief Clear the Fault 3 interrupt flag.
* @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
}
/**
* @brief Indicate whether Fault 3 interrupt occurred.
* @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
}
/**
* @brief Clear the Fault 4 interrupt flag.
* @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
}
/**
* @brief Indicate whether Fault 4 interrupt occurred.
* @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
}
/**
* @brief Clear the Fault 5 interrupt flag.
* @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
}
/**
* @brief Indicate whether Fault 5 interrupt occurred.
* @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
}
/**
* @brief Clear the Fault 6 interrupt flag.
* @rmtoll ICR FLT6C LL_HRTIM_ClearFlag_FLT6
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT6C);
}
/**
* @brief Indicate whether Fault 6 interrupt occurred.
* @rmtoll ICR FLT6 LL_HRTIM_IsActiveFlag_FLT6
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT6 bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT6(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT6) == (HRTIM_ISR_FLT6)) ? 1UL : 0UL);
}
/**
* @brief Clear the System Fault interrupt flag.
* @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
}
/**
* @brief Indicate whether System Fault interrupt occurred.
* @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT
* @param HRTIMx High Resolution Timer instance
* @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
}
/**
* @brief Clear the DLL ready interrupt flag.
* @rmtoll ICR DLLRDYC LL_HRTIM_ClearFlag_DLLRDY
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
}
/**
* @brief Indicate whether DLL ready interrupt occurred.
* @rmtoll ISR DLLRDY LL_HRTIM_IsActiveFlag_DLLRDY
* @param HRTIMx High Resolution Timer instance
* @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL);
}
/**
* @brief Clear the Burst Mode period interrupt flag.
* @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
}
/**
* @brief Indicate whether Burst Mode period interrupt occurred.
* @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER
* @param HRTIMx High Resolution Timer instance
* @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
}
/**
* @brief Clear the Synchronization Input interrupt flag.
* @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
}
/**
* @brief Indicate whether the Synchronization Input interrupt occurred.
* @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC
* @param HRTIMx High Resolution Timer instance
* @retval State of SYNC bit in HRTIM_MISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
}
/**
* @brief Clear the update interrupt flag for a given timer (including the master timer) .
* @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n
* TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MUPD);
}
/**
* @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
* @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n
* TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
}
/**
* @brief Clear the repetition interrupt flag for a given timer (including the master timer) .
* @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n
* TIMxICR REPC LL_HRTIM_ClearFlag_REP
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MREP);
}
/**
* @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) .
* @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n
* TIMxISR REP LL_HRTIM_IsActiveFlag_REP
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
}
/**
* @brief Clear the compare 1 match interrupt for a given timer (including the master timer).
* @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n
* TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MCMP1);
}
/**
* @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) .
* @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n
* TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
}
/**
* @brief Clear the compare 2 match interrupt for a given timer (including the master timer).
* @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n
* TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MCMP2);
}
/**
* @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) .
* @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n
* TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
}
/**
* @brief Clear the compare 3 match interrupt for a given timer (including the master timer).
* @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n
* TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MCMP3);
}
/**
* @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) .
* @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n
* TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
}
/**
* @brief Clear the compare 4 match interrupt for a given timer (including the master timer).
* @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n
* TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MICR_MCMP4);
}
/**
* @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) .
* @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n
* TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
}
/**
* @brief Clear the capture 1 interrupt flag for a given timer.
* @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
}
/**
* @brief Indicate whether the capture 1 interrupt occurred for a given timer.
* @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
}
/**
* @brief Clear the capture 2 interrupt flag for a given timer.
* @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
}
/**
* @brief Indicate whether the capture 2 interrupt occurred for a given timer.
* @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
}
/**
* @brief Clear the output 1 set interrupt flag for a given timer.
* @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
}
/**
* @brief Indicate whether the output 1 set interrupt occurred for a given timer.
* @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
}
/**
* @brief Clear the output 1 reset interrupt flag for a given timer.
* @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
}
/**
* @brief Indicate whether the output 1 reset interrupt occurred for a given timer.
* @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
}
/**
* @brief Clear the output 2 set interrupt flag for a given timer.
* @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
}
/**
* @brief Indicate whether the output 2 set interrupt occurred for a given timer.
* @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
}
/**
* @brief Clear the output 2reset interrupt flag for a given timer.
* @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
}
/**
* @brief Indicate whether the output 2 reset interrupt occurred for a given timer.
* @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
}
/**
* @brief Clear the reset and/or roll-over interrupt flag for a given timer.
* @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
}
/**
* @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer.
* @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
}
/**
* @brief Clear the delayed protection interrupt flag for a given timer.
* @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
}
/**
* @brief Indicate whether the delayed protection interrupt occurred for a given timer.
* @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable the fault 1 interrupt.
* @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
}
/**
* @brief Disable the fault 1 interrupt.
* @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
}
/**
* @brief Indicate whether the fault 1 interrupt is enabled.
* @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
}
/**
* @brief Enable the fault 2 interrupt.
* @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
}
/**
* @brief Disable the fault 2 interrupt.
* @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
}
/**
* @brief Indicate whether the fault 2 interrupt is enabled.
* @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
}
/**
* @brief Enable the fault 3 interrupt.
* @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
}
/**
* @brief Disable the fault 3 interrupt.
* @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
}
/**
* @brief Indicate whether the fault 3 interrupt is enabled.
* @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
}
/**
* @brief Enable the fault 4 interrupt.
* @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
}
/**
* @brief Disable the fault 4 interrupt.
* @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
}
/**
* @brief Indicate whether the fault 4 interrupt is enabled.
* @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
}
/**
* @brief Enable the fault 5 interrupt.
* @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
}
/**
* @brief Disable the fault 5 interrupt.
* @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
}
/**
* @brief Indicate whether the fault 5 interrupt is enabled.
* @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
}
/**
* @brief Enable the fault 6 interrupt.
* @rmtoll IER FLT6IE LL_HRTIM_EnableIT_FLT6
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
}
/**
* @brief Disable the fault 6 interrupt.
* @rmtoll IER FLT6IE LL_HRTIM_DisableIT_FLT6
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
}
/**
* @brief Indicate whether the fault 6 interrupt is enabled.
* @rmtoll IER FLT6IE LL_HRTIM_IsEnabledIT_FLT6
* @param HRTIMx High Resolution Timer instance
* @retval State of FLT6IE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT6(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6) == (HRTIM_IER_FLT6)) ? 1UL : 0UL);
}
/**
* @brief Enable the system fault interrupt.
* @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
}
/**
* @brief Disable the system fault interrupt.
* @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
}
/**
* @brief Indicate whether the system fault interrupt is enabled.
* @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT
* @param HRTIMx High Resolution Timer instance
* @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
}
/**
* @brief Enable the DLL ready interrupt.
* @rmtoll IER DLLRDYIE LL_HRTIM_EnableIT_DLLRDY
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
}
/**
* @brief Disable the DLL ready interrupt.
* @rmtoll IER DLLRDYIE LL_HRTIM_DisableIT_DLLRDY
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
}
/**
* @brief Indicate whether the DLL ready interrupt is enabled.
* @rmtoll IER DLLRDYIE LL_HRTIM_IsEnabledIT_DLLRDY
* @param HRTIMx High Resolution Timer instance
* @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL);
}
/**
* @brief Enable the burst mode period interrupt.
* @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
}
/**
* @brief Disable the burst mode period interrupt.
* @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
}
/**
* @brief Indicate whether the burst mode period interrupt is enabled.
* @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER
* @param HRTIMx High Resolution Timer instance
* @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
}
/**
* @brief Enable the synchronization input interrupt.
* @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
}
/**
* @brief Disable the synchronization input interrupt.
* @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
}
/**
* @brief Indicate whether the synchronization input interrupt is enabled.
* @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC
* @param HRTIMx High Resolution Timer instance
* @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
}
/**
* @brief Enable the update interrupt for a given timer.
* @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n
* TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
}
/**
* @brief Disable the update interrupt for a given timer.
* @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n
* TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
}
/**
* @brief Indicate whether the update interrupt is enabled for a given timer.
* @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n
* TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
}
/**
* @brief Enable the repetition interrupt for a given timer.
* @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n
* TIMxDIER REPIE LL_HRTIM_EnableIT_REP
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
}
/**
* @brief Disable the repetition interrupt for a given timer.
* @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n
* TIMxDIER REPIE LL_HRTIM_DisableIT_REP
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
}
/**
* @brief Indicate whether the repetition interrupt is enabled for a given timer.
* @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n
* TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
}
/**
* @brief Enable the compare 1 interrupt for a given timer.
* @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n
* TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
}
/**
* @brief Disable the compare 1 interrupt for a given timer.
* @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n
* TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
}
/**
* @brief Indicate whether the compare 1 interrupt is enabled for a given timer.
* @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n
* TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the compare 2 interrupt for a given timer.
* @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n
* TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
}
/**
* @brief Disable the compare 2 interrupt for a given timer.
* @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n
* TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
}
/**
* @brief Indicate whether the compare 2 interrupt is enabled for a given timer.
* @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n
* TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the compare 3 interrupt for a given timer.
* @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n
* TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
}
/**
* @brief Disable the compare 3 interrupt for a given timer.
* @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n
* TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
}
/**
* @brief Indicate whether the compare 3 interrupt is enabled for a given timer.
* @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n
* TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the compare 4 interrupt for a given timer.
* @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n
* TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
}
/**
* @brief Disable the compare 4 interrupt for a given timer.
* @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n
* TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
}
/**
* @brief Indicate whether the compare 4 interrupt is enabled for a given timer.
* @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n
* TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the capture 1 interrupt for a given timer.
* @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
}
/**
* @brief Enable the capture 1 interrupt for a given timer.
* @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
}
/**
* @brief Indicate whether the capture 1 interrupt is enabled for a given timer.
* @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the capture 2 interrupt for a given timer.
* @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
}
/**
* @brief Enable the capture 2 interrupt for a given timer.
* @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
}
/**
* @brief Indicate whether the capture 2 interrupt is enabled for a given timer.
* @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the output 1 set interrupt for a given timer.
* @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
}
/**
* @brief Disable the output 1 set interrupt for a given timer.
* @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
}
/**
* @brief Indicate whether the output 1 set interrupt is enabled for a given timer.
* @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the output 1 reset interrupt for a given timer.
* @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
}
/**
* @brief Disable the output 1 reset interrupt for a given timer.
* @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
}
/**
* @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
* @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the output 2 set interrupt for a given timer.
* @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
}
/**
* @brief Disable the output 2 set interrupt for a given timer.
* @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
}
/**
* @brief Indicate whether the output 2 set interrupt is enabled for a given timer.
* @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the output 2 reset interrupt for a given timer.
* @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
}
/**
* @brief Disable the output 2 reset interrupt for a given timer.
* @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
}
/**
* @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
* @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
}
/**
* @brief Enable the reset/roll-over interrupt for a given timer.
* @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
}
/**
* @brief Disable the reset/roll-over interrupt for a given timer.
* @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
}
/**
* @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer.
* @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
}
/**
* @brief Enable the delayed protection interrupt for a given timer.
* @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
}
/**
* @brief Disable the delayed protection interrupt for a given timer.
* @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
}
/**
* @brief Indicate whether the delayed protection interrupt is enabled for a given timer.
* @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable the synchronization input DMA request.
* @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
{
SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
}
/**
* @brief Disable the synchronization input DMA request
* @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC
* @param HRTIMx High Resolution Timer instance
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
{
CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
}
/**
* @brief Indicate whether the synchronization input DMA request is enabled.
* @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC
* @param HRTIMx High Resolution Timer instance
* @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
{
return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
}
/**
* @brief Enable the update DMA request for a given timer.
* @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n
* TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
}
/**
* @brief Disable the update DMA request for a given timer.
* @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n
* TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
}
/**
* @brief Indicate whether the update DMA request is enabled for a given timer.
* @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n
* TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
}
/**
* @brief Enable the repetition DMA request for a given timer.
* @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n
* TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
}
/**
* @brief Disable the repetition DMA request for a given timer.
* @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n
* TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
}
/**
* @brief Indicate whether the repetition DMA request is enabled for a given timer.
* @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n
* TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
}
/**
* @brief Enable the compare 1 DMA request for a given timer.
* @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n
* TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
}
/**
* @brief Disable the compare 1 DMA request for a given timer.
* @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n
* TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
}
/**
* @brief Indicate whether the compare 1 DMA request is enabled for a given timer.
* @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n
* TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the compare 2 DMA request for a given timer.
* @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n
* TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
}
/**
* @brief Disable the compare 2 DMA request for a given timer.
* @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n
* TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
}
/**
* @brief Indicate whether the compare 2 DMA request is enabled for a given timer.
* @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n
* TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the compare 3 DMA request for a given timer.
* @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n
* TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
}
/**
* @brief Disable the compare 3 DMA request for a given timer.
* @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n
* TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
}
/**
* @brief Indicate whether the compare 3 DMA request is enabled for a given timer.
* @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n
* TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the compare 4 DMA request for a given timer.
* @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n
* TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
}
/**
* @brief Disable the compare 4 DMA request for a given timer.
* @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n
* TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
}
/**
* @brief Indicate whether the compare 4 DMA request is enabled for a given timer.
* @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n
* TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_MASTER
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the capture 1 DMA request for a given timer.
* @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
}
/**
* @brief Disable the capture 1 DMA request for a given timer.
* @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
}
/**
* @brief Indicate whether the capture 1 DMA request is enabled for a given timer.
* @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the capture 2 DMA request for a given timer.
* @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
}
/**
* @brief Disable the capture 2 DMA request for a given timer.
* @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
}
/**
* @brief Indicate whether the capture 2 DMA request is enabled for a given timer.
* @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the output 1 set DMA request for a given timer.
* @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
}
/**
* @brief Disable the output 1 set DMA request for a given timer.
* @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
}
/**
* @brief Indicate whether the output 1 set DMA request is enabled for a given timer.
* @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the output 1 reset DMA request for a given timer.
* @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
}
/**
* @brief Disable the output 1 reset DMA request for a given timer.
* @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
}
/**
* @brief Indicate whether the output 1 reset interrupt is enabled for a given timer.
* @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the output 2 set DMA request for a given timer.
* @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
}
/**
* @brief Disable the output 2 set DMA request for a given timer.
* @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
}
/**
* @brief Indicate whether the output 2 set DMA request is enabled for a given timer.
* @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the output 2 reset DMA request for a given timer.
* @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
}
/**
* @brief Disable the output 2 reset DMA request for a given timer.
* @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
}
/**
* @brief Indicate whether the output 2 reset DMA request is enabled for a given timer.
* @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
}
/**
* @brief Enable the reset/roll-over DMA request for a given timer.
* @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
}
/**
* @brief Disable the reset/roll-over DMA request for a given timer.
* @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
}
/**
* @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer.
* @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
}
/**
* @brief Enable the delayed protection DMA request for a given timer.
* @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
}
/**
* @brief Disable the delayed protection DMA request for a given timer.
* @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval None
*/
__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
__IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
}
/**
* @brief Indicate whether the delayed protection DMA request is enabled for a given timer.
* @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT
* @param HRTIMx High Resolution Timer instance
* @param Timer This parameter can be one of the following values:
* @arg @ref LL_HRTIM_TIMER_A
* @arg @ref LL_HRTIM_TIMER_B
* @arg @ref LL_HRTIM_TIMER_C
* @arg @ref LL_HRTIM_TIMER_D
* @arg @ref LL_HRTIM_TIMER_E
* @arg @ref LL_HRTIM_TIMER_F
* @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
*/
__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
{
uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
REG_OFFSET_TAB_TIMER[iTimer]));
return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
* @{
*/
ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* HRTIM1 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_HRTIM_H */
| 720,136 | C | 50.819601 | 230 | 0.603206 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h | /**
******************************************************************************
* @file stm32g4xx_ll_lpuart.h
* @author MCD Application Team
* @brief Header file of LPUART LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_LPUART_H
#define STM32G4xx_LL_LPUART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (LPUART1)
/** @defgroup LPUART_LL LPUART
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
* @{
*/
/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
static const uint16_t LPUART_PRESCALER_TAB[] =
{
(uint16_t)1,
(uint16_t)2,
(uint16_t)4,
(uint16_t)6,
(uint16_t)8,
(uint16_t)10,
(uint16_t)12,
(uint16_t)16,
(uint16_t)32,
(uint16_t)64,
(uint16_t)128,
(uint16_t)256
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
* @{
*/
/* Defines used in Baud Rate related macros and corresponding register setting computation */
#define LPUART_LPUARTDIV_FREQ_MUL 256U
#define LPUART_BRR_MASK 0x000FFFFFU
#define LPUART_BRR_MIN_VALUE 0x00000300U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
* @{
*/
/**
* @brief LL LPUART Init Structure definition
*/
typedef struct
{
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref LPUART_LL_EC_PARITY.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
This feature can be modified afterwards using unitary
function @ref LL_LPUART_SetHWFlowCtrl().*/
} LL_LPUART_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
* @{
*/
/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_LPUART_WriteReg function
* @{
*/
#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */
#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_LPUART_ReadReg function
* @{
*/
#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */
#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */
#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions
* @{
*/
#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
interrupt enable */
#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO
not full interrupt enable */
#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
* @{
*/
#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_DIRECTION Direction
* @{
*/
#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_PARITY Parity Control
* @{
*/
#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
* @{
*/
#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */
#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
* @{
*/
#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\
USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\
USART_PRESC_PRESCALER_1 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
USART_PRESC_PRESCALER_1 |\
USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
* @{
*/
#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
* @{
*/
#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
* @{
*/
#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
* @{
*/
#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
* @{
*/
#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received
in positive/direct logic. (1=H, 0=L) */
#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
in negative/inverse logic. (1=L, 0=H).
The parity bit is also inverted. */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_BITORDER Bit Order
* @{
*/
#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first,
following the start bit */
#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
following the start bit */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
* @{
*/
#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
* @{
*/
#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested
when there is space in the receive buffer */
#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted
when the nCTS input is asserted (tied to 0)*/
#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
* @{
*/
#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
* @{
*/
#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
/**
* @}
*/
/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
* @{
*/
/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in LPUART register
* @param __INSTANCE__ LPUART Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in LPUART register
* @param __INSTANCE__ LPUART Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
* @{
*/
/**
* @brief Compute LPUARTDIV value according to Peripheral Clock and
* expected Baud Rate (20-bit value of LPUARTDIV is returned)
* @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
* @param __PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @param __BAUDRATE__ Baud Rate value to achieve
* @retval LPUARTDIV value to be used for BRR register filling
*/
#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
* LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
* @{
*/
/** @defgroup LPUART_LL_EF_Configuration Configuration functions
* @{
*/
/**
* @brief LPUART Enable
* @rmtoll CR1 UE LL_LPUART_Enable
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR1, USART_CR1_UE);
}
/**
* @brief LPUART Disable
* @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
* and current operations are discarded. The configuration of the LPUART is kept, but all the status
* flags, in the LPUARTx_ISR are set to their default values.
* @note In order to go into low-power mode without generating errors on the line,
* the TE bit must be reset before and the software must wait
* for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
* The DMA requests are also reset when UE = 0 so the DMA channel must
* be disabled before resetting the UE bit.
* @rmtoll CR1 UE LL_LPUART_Disable
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
}
/**
* @brief Indicate if LPUART is enabled
* @rmtoll CR1 UE LL_LPUART_IsEnabled
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
/**
* @brief FIFO Mode Enable
* @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
}
/**
* @brief FIFO Mode Disable
* @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
}
/**
* @brief Indicate if FIFO Mode is enabled
* @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
}
/**
* @brief Configure TX FIFO Threshold
* @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold
* @param LPUARTx LPUART Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
{
ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Return TX FIFO Threshold Configuration
* @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Configure RX FIFO Threshold
* @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold
* @param LPUARTx LPUART Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
{
ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Return RX FIFO Threshold Configuration
* @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
*/
__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Configure TX and RX FIFOs Threshold
* @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n
* CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold
* @param LPUARTx LPUART Instance
* @param TXThreshold This parameter can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
* @param RXThreshold This parameter can be one of the following values:
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
* @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
* @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
* @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
(RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
* @brief LPUART enabled in STOP Mode
* @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
* LPUART clock selection is HSI or LSE in RCC.
* @rmtoll CR1 UESM LL_LPUART_EnableInStopMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
}
/**
* @brief LPUART disabled in STOP Mode
* @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
* @rmtoll CR1 UESM LL_LPUART_DisableInStopMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
}
/**
* @brief Indicate if LPUART is enabled in STOP Mode
* (able to wake up MCU from Stop mode or not)
* @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
/**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_LPUART_EnableDirectionRx
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
}
/**
* @brief Receiver Disable
* @rmtoll CR1 RE LL_LPUART_DisableDirectionRx
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
}
/**
* @brief Transmitter Enable
* @rmtoll CR1 TE LL_LPUART_EnableDirectionTx
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
}
/**
* @brief Transmitter Disable
* @rmtoll CR1 TE LL_LPUART_DisableDirectionTx
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
}
/**
* @brief Configure simultaneously enabled/disabled states
* of Transmitter and Receiver
* @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n
* CR1 TE LL_LPUART_SetTransferDirection
* @param LPUARTx LPUART Instance
* @param TransferDirection This parameter can be one of the following values:
* @arg @ref LL_LPUART_DIRECTION_NONE
* @arg @ref LL_LPUART_DIRECTION_RX
* @arg @ref LL_LPUART_DIRECTION_TX
* @arg @ref LL_LPUART_DIRECTION_TX_RX
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
{
ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
}
/**
* @brief Return enabled/disabled states of Transmitter and Receiver
* @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n
* CR1 TE LL_LPUART_GetTransferDirection
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_DIRECTION_NONE
* @arg @ref LL_LPUART_DIRECTION_RX
* @arg @ref LL_LPUART_DIRECTION_TX
* @arg @ref LL_LPUART_DIRECTION_TX_RX
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
}
/**
* @brief Configure Parity (enabled/disabled and parity mode if enabled)
* @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
* When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
* (depending on data width) and parity is checked on the received data.
* @rmtoll CR1 PS LL_LPUART_SetParity\n
* CR1 PCE LL_LPUART_SetParity
* @param LPUARTx LPUART Instance
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_LPUART_PARITY_NONE
* @arg @ref LL_LPUART_PARITY_EVEN
* @arg @ref LL_LPUART_PARITY_ODD
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
}
/**
* @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
* @rmtoll CR1 PS LL_LPUART_GetParity\n
* CR1 PCE LL_LPUART_GetParity
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_PARITY_NONE
* @arg @ref LL_LPUART_PARITY_EVEN
* @arg @ref LL_LPUART_PARITY_ODD
*/
__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
}
/**
* @brief Set Receiver Wake Up method from Mute mode.
* @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod
* @param LPUARTx LPUART Instance
* @param Method This parameter can be one of the following values:
* @arg @ref LL_LPUART_WAKEUP_IDLELINE
* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
}
/**
* @brief Return Receiver Wake Up method from Mute mode
* @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_WAKEUP_IDLELINE
* @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
*/
__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
}
/**
* @brief Set Word length (nb of data bits, excluding start and stop bits)
* @rmtoll CR1 M LL_LPUART_SetDataWidth
* @param LPUARTx LPUART Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_LPUART_DATAWIDTH_7B
* @arg @ref LL_LPUART_DATAWIDTH_8B
* @arg @ref LL_LPUART_DATAWIDTH_9B
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
}
/**
* @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
* @rmtoll CR1 M LL_LPUART_GetDataWidth
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_DATAWIDTH_7B
* @arg @ref LL_LPUART_DATAWIDTH_8B
* @arg @ref LL_LPUART_DATAWIDTH_9B
*/
__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
}
/**
* @brief Allow switch between Mute Mode and Active mode
* @rmtoll CR1 MME LL_LPUART_EnableMuteMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
}
/**
* @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
* @rmtoll CR1 MME LL_LPUART_DisableMuteMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
}
/**
* @brief Indicate if switch between Mute Mode and Active mode is allowed
* @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
/**
* @brief Configure Clock source prescaler for baudrate generator and oversampling
* @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler
* @param LPUARTx LPUART Instance
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
{
MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
}
/**
* @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
* @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
*/
__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
}
/**
* @brief Set the length of the stop bits
* @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength
* @param LPUARTx LPUART Instance
* @param StopBits This parameter can be one of the following values:
* @arg @ref LL_LPUART_STOPBITS_1
* @arg @ref LL_LPUART_STOPBITS_2
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
}
/**
* @brief Retrieve the length of the stop bits
* @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_STOPBITS_1
* @arg @ref LL_LPUART_STOPBITS_2
*/
__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
}
/**
* @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
* @note Call of this function is equivalent to following function call sequence :
* - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
* - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
* - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
* @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n
* CR1 PCE LL_LPUART_ConfigCharacter\n
* CR1 M LL_LPUART_ConfigCharacter\n
* CR2 STOP LL_LPUART_ConfigCharacter
* @param LPUARTx LPUART Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_LPUART_DATAWIDTH_7B
* @arg @ref LL_LPUART_DATAWIDTH_8B
* @arg @ref LL_LPUART_DATAWIDTH_9B
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_LPUART_PARITY_NONE
* @arg @ref LL_LPUART_PARITY_EVEN
* @arg @ref LL_LPUART_PARITY_ODD
* @param StopBits This parameter can be one of the following values:
* @arg @ref LL_LPUART_STOPBITS_1
* @arg @ref LL_LPUART_STOPBITS_2
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
uint32_t StopBits)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
}
/**
* @brief Configure TX/RX pins swapping setting.
* @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap
* @param LPUARTx LPUART Instance
* @param SwapConfig This parameter can be one of the following values:
* @arg @ref LL_LPUART_TXRX_STANDARD
* @arg @ref LL_LPUART_TXRX_SWAPPED
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
}
/**
* @brief Retrieve TX/RX pins swapping configuration.
* @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_TXRX_STANDARD
* @arg @ref LL_LPUART_TXRX_SWAPPED
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
}
/**
* @brief Configure RX pin active level logic
* @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel
* @param LPUARTx LPUART Instance
* @param PinInvMethod This parameter can be one of the following values:
* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
}
/**
* @brief Retrieve RX pin active level logic configuration
* @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
*/
__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
}
/**
* @brief Configure TX pin active level logic
* @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel
* @param LPUARTx LPUART Instance
* @param PinInvMethod This parameter can be one of the following values:
* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
}
/**
* @brief Retrieve TX pin active level logic configuration
* @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
}
/**
* @brief Configure Binary data logic.
*
* @note Allow to define how Logical data from the data register are send/received :
* either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
* @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic
* @param LPUARTx LPUART Instance
* @param DataLogic This parameter can be one of the following values:
* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
}
/**
* @brief Retrieve Binary data configuration
* @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
*/
__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
}
/**
* @brief Configure transfer bit order (either Less or Most Significant Bit First)
* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
* @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder
* @param LPUARTx LPUART Instance
* @param BitOrder This parameter can be one of the following values:
* @arg @ref LL_LPUART_BITORDER_LSBFIRST
* @arg @ref LL_LPUART_BITORDER_MSBFIRST
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
}
/**
* @brief Return transfer bit order (either Less or Most Significant Bit First)
* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
* @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_BITORDER_LSBFIRST
* @arg @ref LL_LPUART_BITORDER_MSBFIRST
*/
__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
}
/**
* @brief Set Address of the LPUART node.
* @note This is used in multiprocessor communication during Mute mode or Stop mode,
* for wake up with address mark detection.
* @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
* (b7-b4 should be set to 0)
* 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
* (This is used in multiprocessor communication during Mute mode or Stop mode,
* for wake up with 7-bit address mark detection.
* The MSB of the character sent by the transmitter should be equal to 1.
* It may also be used for character detection during normal reception,
* Mute mode inactive (for example, end of block detection in ModBus protocol).
* In this case, the whole received character (8-bit) is compared to the ADD[7:0]
* value and CMF flag is set on match)
* @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n
* CR2 ADDM7 LL_LPUART_ConfigNodeAddress
* @param LPUARTx LPUART Instance
* @param AddressLen This parameter can be one of the following values:
* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
* @param NodeAddress 4 or 7 bit Address of the LPUART node.
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
{
MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
(uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
}
/**
* @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2.
* @note If 4-bit Address Detection is selected in ADDM7,
* only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
* If 7-bit Address Detection is selected in ADDM7,
* only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
* @rmtoll CR2 ADD LL_LPUART_GetNodeAddress
* @param LPUARTx LPUART Instance
* @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
*/
__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
}
/**
* @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
* @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_ADDRESS_DETECT_4B
* @arg @ref LL_LPUART_ADDRESS_DETECT_7B
*/
__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
}
/**
* @brief Enable RTS HW Flow Control
* @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
}
/**
* @brief Disable RTS HW Flow Control
* @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
}
/**
* @brief Enable CTS HW Flow Control
* @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
}
/**
* @brief Disable CTS HW Flow Control
* @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
}
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
* @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n
* CR3 CTSE LL_LPUART_SetHWFlowCtrl
* @param LPUARTx LPUART Instance
* @param HardwareFlowControl This parameter can be one of the following values:
* @arg @ref LL_LPUART_HWCONTROL_NONE
* @arg @ref LL_LPUART_HWCONTROL_RTS
* @arg @ref LL_LPUART_HWCONTROL_CTS
* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
{
MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
}
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
* @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n
* CR3 CTSE LL_LPUART_GetHWFlowCtrl
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_HWCONTROL_NONE
* @arg @ref LL_LPUART_HWCONTROL_RTS
* @arg @ref LL_LPUART_HWCONTROL_CTS
* @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
*/
__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
}
/**
* @brief Enable Overrun detection
* @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
}
/**
* @brief Disable Overrun detection
* @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
}
/**
* @brief Indicate if Overrun detection is enabled
* @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
/**
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @rmtoll CR3 WUS LL_LPUART_SetWKUPType
* @param LPUARTx LPUART Instance
* @param Type This parameter can be one of the following values:
* @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
{
MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
}
/**
* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @rmtoll CR3 WUS LL_LPUART_GetWKUPType
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
* @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
* @arg @ref LL_LPUART_WAKEUP_ON_RXNE
*/
__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
}
/**
* @brief Configure LPUART BRR register for achieving expected Baud Rate value.
*
* @note Compute and set LPUARTDIV value in BRR Register (full BRR content)
* according to used Peripheral Clock and expected Baud Rate values
* @note Peripheral clock and Baud Rate values provided as function parameters should be valid
* (Baud rate value != 0).
* @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
* a care should be taken when generating high baud rates using high PeriphClk
* values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
* @rmtoll BRR BRR LL_LPUART_SetBaudRate
* @param LPUARTx LPUART Instance
* @param PeriphClk Peripheral Clock
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @param BaudRate Baud Rate
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t BaudRate)
{
if (BaudRate != 0U)
{
LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
}
}
/**
* @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register
* (full BRR content), and to used Peripheral Clock values
* @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
* @rmtoll BRR BRR LL_LPUART_GetBaudRate
* @param LPUARTx LPUART Instance
* @param PeriphClk Peripheral Clock
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_LPUART_PRESCALER_DIV1
* @arg @ref LL_LPUART_PRESCALER_DIV2
* @arg @ref LL_LPUART_PRESCALER_DIV4
* @arg @ref LL_LPUART_PRESCALER_DIV6
* @arg @ref LL_LPUART_PRESCALER_DIV8
* @arg @ref LL_LPUART_PRESCALER_DIV10
* @arg @ref LL_LPUART_PRESCALER_DIV12
* @arg @ref LL_LPUART_PRESCALER_DIV16
* @arg @ref LL_LPUART_PRESCALER_DIV32
* @arg @ref LL_LPUART_PRESCALER_DIV64
* @arg @ref LL_LPUART_PRESCALER_DIV128
* @arg @ref LL_LPUART_PRESCALER_DIV256
* @retval Baud Rate
*/
__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)
{
uint32_t lpuartdiv;
uint32_t brrresult;
uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
{
brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
}
else
{
brrresult = 0x0UL;
}
return (brrresult);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
* @{
*/
/**
* @brief Enable Single Wire Half-Duplex mode
* @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Disable Single Wire Half-Duplex mode
* @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
* @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
* @{
*/
/**
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime
* @param LPUARTx LPUART Instance
* @param Time Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
}
/**
* @brief Return DEDT (Driver Enable De-Assertion Time)
* @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime
* @param LPUARTx LPUART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : c
*/
__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
}
/**
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime
* @param LPUARTx LPUART Instance
* @param Time Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
{
MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
}
/**
* @brief Return DEAT (Driver Enable Assertion Time)
* @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime
* @param LPUARTx LPUART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
*/
__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
}
/**
* @brief Enable Driver Enable (DE) Mode
* @rmtoll CR3 DEM LL_LPUART_EnableDEMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
}
/**
* @brief Disable Driver Enable (DE) Mode
* @rmtoll CR3 DEM LL_LPUART_DisableDEMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
}
/**
* @brief Indicate if Driver Enable (DE) Mode is enabled
* @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
/**
* @brief Select Driver Enable Polarity
* @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity
* @param LPUARTx LPUART Instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPUART_DE_POLARITY_HIGH
* @arg @ref LL_LPUART_DE_POLARITY_LOW
* @retval None
*/
__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
{
MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
}
/**
* @brief Return Driver Enable Polarity
* @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity
* @param LPUARTx LPUART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPUART_DE_POLARITY_HIGH
* @arg @ref LL_LPUART_DE_POLARITY_LOW
*/
__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)
{
return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if the LPUART Parity Error Flag is set or not
* @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Framing Error Flag is set or not
* @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Noise error detected Flag is set or not
* @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART OverRun Error Flag is set or not
* @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART IDLE line detected Flag is set or not
* @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
/**
* @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
* @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Transmission Complete Flag is set or not
* @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF
/**
* @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
* @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART CTS interrupt Flag is set or not
* @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART CTS Flag is set or not
* @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Busy Flag is set or not
* @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Character Match Flag is set or not
* @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Send Break Flag is set or not
* @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not
* @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Wake Up from stop mode Flag is set or not
* @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not
* @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not
* @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART TX FIFO Empty Flag is set or not
* @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART RX FIFO Full Flag is set or not
* @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART TX FIFO Threshold Flag is set or not
* @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART RX FIFO Threshold Flag is set or not
* @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
}
/**
* @brief Clear Parity Error Flag
* @rmtoll ICR PECF LL_LPUART_ClearFlag_PE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
}
/**
* @brief Clear Framing Error Flag
* @rmtoll ICR FECF LL_LPUART_ClearFlag_FE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
}
/**
* @brief Clear Noise detected Flag
* @rmtoll ICR NECF LL_LPUART_ClearFlag_NE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
}
/**
* @brief Clear OverRun Error Flag
* @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
}
/**
* @brief Clear IDLE line detected Flag
* @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
}
/**
* @brief Clear Transmission Complete Flag
* @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
}
/**
* @brief Clear CTS Interrupt Flag
* @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
}
/**
* @brief Clear Character Match Flag
* @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
}
/**
* @brief Clear Wake Up from stop mode Flag
* @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
{
WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable IDLE Interrupt
* @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE
/**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
* @brief Enable Transmission Complete Interrupt
* @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF
/**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt
* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
* @brief Enable Parity Error Interrupt
* @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
}
/**
* @brief Enable Character Match Interrupt
* @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
}
/**
* @brief Enable TX FIFO Empty Interrupt
* @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Enable RX FIFO Full Interrupt
* @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
}
/**
* @brief Enable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
* - 0: Interrupt is inhibited
* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
* @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Enable CTS Interrupt
* @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Enable Wake Up from Stop Mode Interrupt
* @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
}
/**
* @brief Enable TX FIFO Threshold Interrupt
* @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
}
/**
* @brief Enable RX FIFO Threshold Interrupt
* @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
}
/**
* @brief Disable IDLE Interrupt
* @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE
/**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
* @brief Disable Transmission Complete Interrupt
* @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF
/**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt
* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
* @brief Disable Parity Error Interrupt
* @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
}
/**
* @brief Disable Character Match Interrupt
* @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
}
/**
* @brief Disable TX FIFO Empty Interrupt
* @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Disable RX FIFO Full Interrupt
* @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
}
/**
* @brief Disable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
* - 0: Interrupt is inhibited
* - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
* @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Disable CTS Interrupt
* @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Disable Wake Up from Stop Mode Interrupt
* @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
}
/**
* @brief Disable TX FIFO Threshold Interrupt
* @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
}
/**
* @brief Disable RX FIFO Threshold Interrupt
* @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
}
/**
* @brief Check if the LPUART IDLE Interrupt source is enabled or disabled.
* @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE
/**
* @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
* @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF
/**
* @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
* @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Parity Error Interrupt is enabled or disabled.
* @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Character Match Interrupt is enabled or disabled.
* @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
* @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
* @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Error Interrupt is enabled or disabled.
* @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART CTS Interrupt is enabled or disabled.
* @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
* @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
* @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
}
/**
* @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
* @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable DMA Mode for reception
* @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
}
/**
* @brief Disable DMA Mode for reception
* @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
}
/**
* @brief Check if DMA Mode is enabled for reception
* @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Mode for transmission
* @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
{
ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
}
/**
* @brief Disable DMA Mode for transmission
* @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
{
ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
}
/**
* @brief Check if DMA Mode is enabled for transmission
* @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Disabling on Reception Error
* @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
}
/**
* @brief Disable DMA Disabling on Reception Error
* @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
{
CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
}
/**
* @brief Indicate if DMA Disabling on Reception Error is disabled
* @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr
* @param LPUARTx LPUART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)
{
return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
/**
* @brief Get the LPUART data register address used for DMA transfer
* @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n
* @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr
* @param LPUARTx LPUART Instance
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
* @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)
{
uint32_t data_reg_addr;
if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
data_reg_addr = (uint32_t) &(LPUARTx->TDR);
}
else
{
/* return address of RDR register */
data_reg_addr = (uint32_t) &(LPUARTx->RDR);
}
return data_reg_addr;
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Read Receiver Data register (Receive Data value, 8 bits)
* @rmtoll RDR RDR LL_LPUART_ReceiveData8
* @param LPUARTx LPUART Instance
* @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)
{
return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
* @brief Read Receiver Data register (Receive Data value, 9 bits)
* @rmtoll RDR RDR LL_LPUART_ReceiveData9
* @param LPUARTx LPUART Instance
* @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
*/
__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)
{
return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
}
/**
* @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
* @rmtoll TDR TDR LL_LPUART_TransmitData8
* @param LPUARTx LPUART Instance
* @param Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
{
LPUARTx->TDR = Value;
}
/**
* @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
* @rmtoll TDR TDR LL_LPUART_TransmitData9
* @param LPUARTx LPUART Instance
* @param Value between Min_Data=0x00 and Max_Data=0x1FF
* @retval None
*/
__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
{
LPUARTx->TDR = Value & 0x1FFUL;
}
/**
* @}
*/
/** @defgroup LPUART_LL_EF_Execution Execution
* @{
*/
/**
* @brief Request Break sending
* @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
}
/**
* @brief Put LPUART in mute mode and set the RWU flag
* @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
}
/**
* @brief Request a Receive Data and FIFO flush
* @note Allows to discard the received data without reading them, and avoid an overrun
* condition.
* @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush
* @param LPUARTx LPUART Instance
* @retval None
*/
__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
{
SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);
ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);
void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* LPUART1 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_LPUART_H */
| 94,732 | C | 34.734817 | 120 | 0.634854 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_flash_ex.h
* @author MCD Application Team
* @brief Header file of FLASH HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_FLASH_EX_H
#define STM32G4xx_HAL_FLASH_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASHEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
*/
/* Extended Program operation functions *************************************/
/** @addtogroup FLASHEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
HAL_StatusTypeDef HAL_FLASHEx_EnableSecMemProtection(uint32_t Bank);
void HAL_FLASHEx_EnableDebugger(void);
void HAL_FLASHEx_DisableDebugger(void);
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASHEx_Private_Functions
* @{
*/
void FLASH_PageErase(uint32_t Page, uint32_t Banks);
void FLASH_FlushCaches(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_FLASH_EX_H */
| 2,407 | C | 25.755555 | 93 | 0.49273 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_crc_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_crc_ex.h
* @author MCD Application Team
* @brief Header file of CRC HAL extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_CRC_EX_H
#define STM32G4xx_HAL_CRC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup CRCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants
* @{
*/
/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE 0x00000000U /*!< No input data inversion */
#define CRC_INPUTDATA_INVERSION_BYTE CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_HALFWORD CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */
#define CRC_INPUTDATA_INVERSION_WORD CRC_CR_REV_IN /*!< Word-wise input data inversion */
/**
* @}
*/
/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE 0x00000000U /*!< No output data inversion */
#define CRC_OUTPUTDATA_INVERSION_ENABLE CRC_CR_REV_OUT /*!< Bit-wise output data inversion */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros
* @{
*/
/**
* @brief Set CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
* @param __HANDLE__ CRC handle
* @retval None
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
* @param __HANDLE__ CRC handle
* @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros
* @{
*/
#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \
((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \
((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \
((MODE) == CRC_INPUTDATA_INVERSION_WORD))
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \
((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup CRCEx_Exported_Functions
* @{
*/
/** @addtogroup CRCEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);
HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);
HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_CRC_EX_H */
| 4,500 | C | 28.807947 | 112 | 0.512889 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rng.h | /**
******************************************************************************
* @file stm32g4xx_ll_rng.h
* @author MCD Application Team
* @brief Header file of RNG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_RNG_H
#define STM32G4xx_LL_RNG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (RNG)
/** @defgroup RNG_LL RNG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures
* @{
*/
/**
* @brief LL RNG Init Structure Definition
*/
typedef struct
{
uint32_t ClockErrorDetection; /*!< Clock error detection.
This parameter can be one value of @ref RNG_LL_CED.
This parameter can be modified using unitary
functions @ref LL_RNG_EnableClkErrorDetect(). */
} LL_RNG_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants
* @{
*/
/** @defgroup RNG_LL_CED Clock Error Detection
* @{
*/
#define LL_RNG_CED_ENABLE 0x00000000U /*!< Clock error detection enabled */
#define LL_RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection disabled */
/**
* @}
*/
/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RNG_ReadReg function
* @{
*/
#define LL_RNG_SR_DRDY RNG_SR_DRDY /*!< Register contains valid random data */
#define LL_RNG_SR_CECS RNG_SR_CECS /*!< Clock error current status */
#define LL_RNG_SR_SECS RNG_SR_SECS /*!< Seed error current status */
#define LL_RNG_SR_CEIS RNG_SR_CEIS /*!< Clock error interrupt status */
#define LL_RNG_SR_SEIS RNG_SR_SEIS /*!< Seed error interrupt status */
/**
* @}
*/
/** @defgroup RNG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_RNG_ReadReg and LL_RNG_WriteReg macros
* @{
*/
#define LL_RNG_CR_IE RNG_CR_IE /*!< RNG Interrupt enable */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros
* @{
*/
/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in RNG register
* @param __INSTANCE__ RNG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in RNG register
* @param __INSTANCE__ RNG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions
* @{
*/
/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions
* @{
*/
/**
* @brief Enable Random Number Generation
* @rmtoll CR RNGEN LL_RNG_Enable
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_RNGEN);
}
/**
* @brief Disable Random Number Generation
* @rmtoll CR RNGEN LL_RNG_Disable
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);
}
/**
* @brief Check if Random Number Generator is enabled
* @rmtoll CR RNGEN LL_RNG_IsEnabled
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Clock Error Detection
* @rmtoll CR CED LL_RNG_EnableClkErrorDetect
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_CED);
}
/**
* @brief Disable RNG Clock Error Detection
* @rmtoll CR CED LL_RNG_DisableClkErrorDetect
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_CED);
}
/**
* @brief Check if RNG Clock Error Detection is enabled
* @rmtoll CR CED LL_RNG_IsEnabledClkErrorDetect
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Indicate if the RNG Data ready Flag is set or not
* @rmtoll SR DRDY LL_RNG_IsActiveFlag_DRDY
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);
}
/**
* @brief Indicate if the Clock Error Current Status Flag is set or not
* @rmtoll SR CECS LL_RNG_IsActiveFlag_CECS
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);
}
/**
* @brief Indicate if the Seed Error Current Status Flag is set or not
* @rmtoll SR SECS LL_RNG_IsActiveFlag_SECS
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);
}
/**
* @brief Indicate if the Clock Error Interrupt Status Flag is set or not
* @rmtoll SR CEIS LL_RNG_IsActiveFlag_CEIS
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);
}
/**
* @brief Indicate if the Seed Error Interrupt Status Flag is set or not
* @rmtoll SR SEIS LL_RNG_IsActiveFlag_SEIS
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);
}
/**
* @brief Clear Clock Error interrupt Status (CEIS) Flag
* @rmtoll SR CEIS LL_RNG_ClearFlag_CEIS
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)
{
WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);
}
/**
* @brief Clear Seed Error interrupt Status (SEIS) Flag
* @rmtoll SR SEIS LL_RNG_ClearFlag_SEIS
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)
{
WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);
}
/**
* @}
*/
/** @defgroup RNG_LL_EF_IT_Management IT Management
* @{
*/
/**
* @brief Enable Random Number Generator Interrupt
* (applies for either Seed error, Clock Error or Data ready interrupts)
* @rmtoll CR IE LL_RNG_EnableIT
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)
{
SET_BIT(RNGx->CR, RNG_CR_IE);
}
/**
* @brief Disable Random Number Generator Interrupt
* (applies for either Seed error, Clock Error or Data ready interrupts)
* @rmtoll CR IE LL_RNG_DisableIT
* @param RNGx RNG Instance
* @retval None
*/
__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)
{
CLEAR_BIT(RNGx->CR, RNG_CR_IE);
}
/**
* @brief Check if Random Number Generator Interrupt is enabled
* (applies for either Seed error, Clock Error or Data ready interrupts)
* @rmtoll CR IE LL_RNG_IsEnabledIT
* @param RNGx RNG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)
{
return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RNG_LL_EF_Data_Management Data Management
* @{
*/
/**
* @brief Return32-bit Random Number value
* @rmtoll DR RNDATA LL_RNG_ReadRandData32
* @param RNGx RNG Instance
* @retval Generated 32-bit random value
*/
__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)
{
return (uint32_t)(READ_REG(RNGx->DR));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);
void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);
ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* RNG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_RNG_H */
| 10,533 | C | 25.335 | 103 | 0.565841 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crs.h | /**
******************************************************************************
* @file stm32g4xx_ll_crs.h
* @author MCD Application Team
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2018 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_CRS_H
#define __STM32G4xx_LL_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(CRS)
/** @defgroup CRS_LL CRS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
* @{
*/
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CRS_ReadReg function
* @{
*/
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
/**
* @}
*/
/** @defgroup CRS_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
* @{
*/
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
* @{
*/
#define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
#define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
* @{
*/
#define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
* @{
*/
#define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
#define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
* @{
*/
/**
* @brief Reset value of the RELOAD field
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
*/
#define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
/**
* @brief Reset value of Frequency error limit.
*/
#define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
/**
* @brief Reset value of the HSI48 Calibration field
* @note The default value is 64, which corresponds to the middle of the trimming interval.
* The trimming step is specified in the product datasheet.
* A higher TRIM value corresponds to a higher output frequency
*/
#define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x40U)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
* @{
*/
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
* @{
*/
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between
* the target frequency and the frequency of the synchronization source after
* prescaling. It is then decreased by one in order to reach the expected
* synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval Reload value (in Hz)
*/
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
* @{
*/
/** @defgroup CRS_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Frequency error counter
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
{
SET_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Disable Frequency error counter
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Check if Frequency error counter is enabled or not
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
{
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Disable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Check if Automatic trimming is enabled or not
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
}
/**
* @brief Set HSI48 oscillator smooth trimming
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
* @param Value a number between Min_Data = 0 and Max_Data = 63
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);
}
/**
* @brief Get HSI48 oscillator smooth trimming
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
* @retval a number between Min_Data = 0 and Max_Data = 63
*/
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);
}
/**
* @brief Set counter reload value
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
}
/**
* @brief Get counter reload value
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
}
/**
* @brief Set frequency error limit
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
* @param Value a number between Min_Data = 0 and Max_Data = 255
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);
}
/**
* @brief Get frequency error limit
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
* @retval A number between Min_Data = 0 and Max_Data = 255
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);
}
/**
* @brief Set division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
* @param Divider This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
}
/**
* @brief Get division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
}
/**
* @brief Set SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
}
/**
* @brief Get SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
}
/**
* @brief Set input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
}
/**
* @brief Get input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
}
/**
* @brief Configure CRS for the synchronization
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
* CFGR FELIM LL_CRS_ConfigSynchronization\n
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
* @param Settings This parameter can be a combination of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
uint32_t ReloadValue, uint32_t Settings)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
* @{
*/
/**
* @brief Generate software SYNC event
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Get the frequency error direction latched in the time of the last
* SYNC event
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief Get the frequency error counter value latched in the time of the last SYNC event
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if SYNC event OK signal occurred or not
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC warning signal occurred or not
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
}
/**
* @brief Check if Synchronization or trimming error signal occurred or not
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Check if Expected SYNC signal occurred or not
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC error signal occurred or not
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC missed error signal occurred or not
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
}
/**
* @brief Check if Trimming overflow or underflow occurred or not
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
}
/**
* @brief Clear the SYNC event OK flag
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
}
/**
* @brief Clear the SYNC warning flag
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
}
/**
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
* the ERR flag
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
}
/**
* @brief Clear Expected SYNC flag
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Disable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Check if SYNC event OK interrupt is enabled or not
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Disable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Check if SYNC warning interrupt is enabled or not
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
{
SET_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Disable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Check if Synchronization or trimming error interrupt is enabled or not
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Disable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Check if Expected SYNC interrupt is enabled or not
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRS_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRS) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_CRS_H */
| 24,270 | C | 30.037084 | 143 | 0.606098 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cryp_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_cryp_ex.h
* @author MCD Application Team
* @brief Header file of CRYPEx HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_CRYP_EX_H
#define STM32G4xx_HAL_CRYP_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
#if defined(AES)
/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Private types -------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Types CRYPEx Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
* @{
*/
/** @addtogroup CRYPEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup CRYPEx_Exported_Functions_Group2
* @{
*/
void HAL_CRYPEx_EnableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* AES */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_CRYP_EX_H */
| 2,970 | C | 21.679389 | 116 | 0.465657 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h | /**
******************************************************************************
* @file stm32g4xx_hal_adc.h
* @author MCD Application Team
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_ADC_H
#define STM32G4xx_HAL_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/* Include low level driver */
#include "stm32g4xx_ll_adc.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup ADC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Types ADC Exported Types
* @{
*/
/**
* @brief ADC group regular oversampling structure definition
*/
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode.
This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode.
The oversampling is either temporary stopped or reset upon an injected
sequence interruption.
If oversampling is enabled on both regular and injected groups, this parameter
is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"
(the oversampling buffer is zeroed during injection sequence).
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
} ADC_OversamplingTypeDef;
/**
* @brief Structure definition of ADC instance and ADC group regular.
* @note Parameters of this structure are shared within 2 scopes:
* - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
* GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
* - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
* ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling, SamplingMode.
* @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled
* - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.
* - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter
* (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
Note: The ADC clock configuration is common to all ADC instances.
Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
Note: This parameter can be modified only if all ADC instances are disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
Refer to reference manual for alignments formats versus resolutions.
This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion data, based on following formula:
DATA = DATA(raw) * (gain compensation coef) / 4096
2.12 bit format, unsigned: 2 bits exponents / 12 bits mantissa
Gain step is 1/4096 = 0.000244
Gain range is 0.0000 to 3.999756
This parameter value can be
0 Gain compensation will be disabled and coefficient set to 0
1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified value
Note: Gain compensation when enabled is applied to all channels. */
uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).
Scan direction is upward: from rank 1 to rank 'n'.
This parameter can be a value of @ref ADC_Scan_mode */
uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.
This parameter can be a value of @ref ADC_EOCSelection. */
FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous
conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,
using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().
This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun
for low frequency applications.
This parameter can be set to ENABLE or DISABLE.
Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA).
Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait).
Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:
use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.
(in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */
FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
after the first ADC conversion start trigger occurred (software start or external trigger).
This parameter can be set to ENABLE or DISABLE. */
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16.
Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
continuous mode or external trigger that could launch a conversion). */
FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
This parameter can be set to ENABLE or DISABLE. */
uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.
If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start.
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */
uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion.
This parameter can be a value of @ref ADC_regular_sampling_mode */
FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
or in continuous mode (DMA transfer unlimited, whatever number of conversions).
This parameter can be set to ENABLE or DISABLE.
Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter applies to ADC group regular only.
This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Note: Error reporting with respect to the conversion mode:
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
} ADC_InitTypeDef;
/**
* @brief Structure definition of ADC channel for regular group
* @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
* - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.
* - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)
* on the fly).
*/
typedef struct
{
uint32_t Channel; /*!< Specify the channel to configure into ADC regular group.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
uint32_t Rank; /*!< Specify the rank in the regular group sequencer.
This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */
uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
Conversion time is the addition of sampling time and processing time
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
Caution: This parameter applies to a channel that can be used into regular and/or injected group.
It overwrites the last setting.
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values. */
uint32_t SingleDiff; /*!< Select single-ended or differential input.
In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
It overwrites the last setting.
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
of another parameter update on the fly) */
uint32_t OffsetNumber; /*!< Select the offset number
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
uint32_t Offset; /*!< Define the offset to be applied on the raw converted data.
Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
0x3FF, 0xFF or 0x3F respectively.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.
This parameter can be a value of @ref ADCEx_OffsetSign.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
FunctionalState OffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
This parameter value can be ENABLE or DISABLE.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
} ADC_ChannelConfTypeDef;
/**
* @brief Structure definition of ADC analog watchdog
* @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.
* - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and injected groups.
*/
typedef struct
{
uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel.
For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')
For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)
This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels.
For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.
For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.
This parameter can be a value of @ref ADC_analog_watchdog_mode. */
uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog.
For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
This parameter can be set to ENABLE or DISABLE */
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application):
ADC data register bitfield [15:4] (12 most significant bits). */
uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application):
ADC data register bitfield [15:4] (12 most significant bits). */
uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider.
Before setting flag or raising interrupt, analog watchdog can wait to have several
consecutive out-of-window samples. This parameter allows to configure this number.
This parameter only applies to Analog watchdog 1. For others, use value ADC_AWD_FILTERING_NONE.
This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
} ADC_AnalogWDGConfTypeDef;
/**
* @brief ADC group injected contexts queue configuration
* @note Structure intended to be used only through structure "ADC_HandleTypeDef"
*/
typedef struct
{
uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
HAL_ADCEx_InjectedConfigChannel() call to finally initialize
JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
} ADC_InjectionConfigTypeDef;
/** @defgroup ADC_States ADC States
* @{
*/
/**
* @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit.
* For example:
* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */
/**
* @}
*/
/**
* @brief ADC handle Structure definition
*/
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
typedef struct __ADC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
{
ADC_TypeDef *Instance; /*!< Register base address */
ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */
DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
HAL_LockTypeDef Lock; /*!< ADC locking object */
__IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */
__IO uint32_t ErrorCode; /*!< ADC Error code */
ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */
void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */
void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */
void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */
void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */
void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */
void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */
void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */
void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
} ADC_HandleTypeDef;
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL ADC Callback ID enumeration definition
*/
typedef enum
{
HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */
HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */
HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */
HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */
HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */
HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */
HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */
HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */
HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */
HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */
HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */
} HAL_ADC_CallbackIDTypeDef;
/**
* @brief HAL ADC Callback pointer definition
*/
typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_Exported_Constants ADC Exported Constants
* @{
*/
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking,
enable/disable, erroneous state, ...) */
#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */
#define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */
#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */
#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */
#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */
#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */
#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */
#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */
#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */
#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */
#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */
#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */
#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */
#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */
#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */
#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */
#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
* @{
*/
#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
/** @defgroup ADC_Scan_mode ADC sequencer scan mode
* @{
*/
#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */
#define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */
/**
* @}
*/
/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
* @{
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */
#define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC1 (LL_ADC_REG_TRIG_EXT_TIM2_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_CC1 (LL_ADC_REG_TRIG_EXT_TIM3_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_CC1 (LL_ADC_REG_TRIG_EXT_TIM4_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T7_TRGO (LL_ADC_REG_TRIG_EXT_TIM7_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T8_CC1 (LL_ADC_REG_TRIG_EXT_TIM8_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T20_TRGO (LL_ADC_REG_TRIG_EXT_TIM20_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T20_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T20_CC1 (LL_ADC_REG_TRIG_EXT_TIM20_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T20_CC2 (LL_ADC_REG_TRIG_EXT_TIM20_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_T20_CC3 (LL_ADC_REG_TRIG_EXT_TIM20_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG1 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG2 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG3 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG4 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG5 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG6 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG7 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG8 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG9 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_HRTIM_TRG10 (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10) /*!< ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT2 (LL_ADC_REG_TRIG_EXT_EXTI_LINE2) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIG_LPTIM_OUT (LL_ADC_REG_TRIG_EXT_LPTIM_OUT) /*!< ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */
#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
* @{
*/
#define ADC_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
Note: First conversion is using minimal sampling time (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
Trigger rising edge = start sampling
Trigger falling edge = stop sampling and start conversion */
/**
* @}
*/
/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
* @{
*/
#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */
#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */
#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */
#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */
#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */
#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */
#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */
#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */
#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */
#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */
#define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */
#define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
#define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
#define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
#define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
#define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
#define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
#define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
#define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */
#define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */
#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */
#define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */
#define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */
#define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */
#define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */
#define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */
#define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number
* @{
*/
/* Note: VrefInt, TempSensor and Vbat internal channels are not available on */
/* all ADC instances (refer to Reference Manual). */
#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */
#define ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */
#define ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */
#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */
#define ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_VOPAMP1) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */
#define ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_VOPAMP2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */
#define ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_VOPAMP3_ADC2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */
#define ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_VOPAMP3_ADC3) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */
#define ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_VOPAMP4) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */
#define ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_VOPAMP5) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availability */
#define ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_VOPAMP6) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 availability */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
* @{
*/
#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_filtering_config ADC Analog Watchdog filtering configuration
* @{
*/
#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
#define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
/**
* @}
*/
/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
* @{
*/
#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */
#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */
#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */
#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */
#define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
*/
#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular
* @{
*/
#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */
#define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */
/**
* @}
*/
/** @defgroup ADC_Event_type ADC Event type
* @{
*/
#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */
#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */
#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */
#define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
/**
* @}
*/
#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */
/** @defgroup ADC_interrupts_definition ADC interrupts definition
* @{
*/
#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */
#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */
#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */
#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */
#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */
#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */
#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */
#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */
#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */
#define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */
#define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */
/**
* @}
*/
/** @defgroup ADC_flags_definition ADC flags definition
* @{
*/
#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */
#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */
#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */
#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */
#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */
#define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */
#define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */
#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
#define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup ADC_Private_Macros ADC Private Macros
* @{
*/
/* Macro reserved for internal HAL driver usage, not intended to be used in */
/* code of final user. */
/**
* @brief Return resolution bits in CFGR register RES[1:0] field.
* @param __HANDLE__ ADC handle
* @retval Value of bitfield RES in CFGR register.
*/
#define ADC_GET_RESOLUTION(__HANDLE__) \
(LL_ADC_GetResolution((__HANDLE__)->Instance))
/**
* @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
* @param __HANDLE__ ADC handle
* @retval None
*/
#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/**
* @brief Simultaneously clear and set specific bits of the handle State.
* @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
* the first parameter is the ADC handle State, the second parameter is the
* bit field to clear, the third and last parameter is the bit field to set.
* @retval None
*/
#define ADC_STATE_CLR_SET MODIFY_REG
/**
* @brief Verify that a given value is aligned with the ADC resolution range.
* @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
* @param __ADC_VALUE__ value checked against the resolution.
* @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
*/
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
/**
* @brief Verify the length of the scheduled regular conversions group.
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
*/
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
/**
* @brief Verify the number of scheduled regular conversions in discontinuous mode.
* @param NUMBER number of scheduled regular conversions in discontinuous mode.
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
*/
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
/**
* @brief Verify the ADC clock setting.
* @param __ADC_CLOCK__ programmed ADC clock.
* @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
*/
#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
/**
* @brief Verify the ADC resolution setting.
* @param __RESOLUTION__ programmed ADC resolution.
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
*/
#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
((__RESOLUTION__) == ADC_RESOLUTION_6B) )
/**
* @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
* @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
*/
#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
((__RESOLUTION__) == ADC_RESOLUTION_6B) )
/**
* @brief Verify the ADC converted data alignment.
* @param __ALIGN__ programmed ADC converted data alignment.
* @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
*/
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
((__ALIGN__) == ADC_DATAALIGN_LEFT) )
/**
* @brief Verify the ADC gain compensation.
* @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
* @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
*/
#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
/**
* @brief Verify the ADC scan mode.
* @param __SCAN_MODE__ programmed ADC scan mode.
* @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
*/
#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
((__SCAN_MODE__) == ADC_SCAN_ENABLE) )
/**
* @brief Verify the ADC edge trigger setting for regular group.
* @param __EDGE__ programmed ADC edge trigger setting.
* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
*/
#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) )
/**
* @brief Verify the ADC regular conversions external trigger.
* @param __HANDLE__ ADC handle
* @param __REGTRIG__ programmed ADC regular conversions external trigger.
* @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
*/
#if defined(STM32G474xx) || defined(STM32G484xx)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
(((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
(((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#elif defined(STM32G471xx)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
((((__HANDLE__)->Instance == ADC3)) && \
(((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT) || \
((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
(((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11))) || \
(((__HANDLE__)->Instance == ADC3) && \
(((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1) || \
((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2))) || \
((__REGTRIG__) == ADC_SOFTWARE_START) )
#endif
/**
* @brief Verify the ADC regular conversions external trigger.
* @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
* @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
*/
#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL) || \
((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB) || \
((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) )
/**
* @brief Verify the ADC regular conversions check for converted data availability.
* @param __EOC_SELECTION__ converted data availability check.
* @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
*/
#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \
((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) )
/**
* @brief Verify the ADC regular conversions overrun handling.
* @param __OVR__ ADC regular conversions overrun handling.
* @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
*/
#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \
((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) )
/**
* @brief Verify the ADC conversions sampling time.
* @param __TIME__ ADC conversions sampling time.
* @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
*/
#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) )
/**
* @brief Verify the ADC regular channel setting.
* @param __CHANNEL__ programmed ADC regular channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
((__CHANNEL__) == ADC_REGULAR_RANK_16) )
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup ADC_Private_Constants ADC Private Constants
* @{
*/
/* Fixed timeout values for ADC conversion (including sampling time) */
/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */
/* Maximum conversion time is 12.5 + Maximum sampling time */
/* or 12.5 + 640.5 = 653 ADC clock cycles */
/* Minimum ADC Clock frequency is 0.14 MHz */
/* Maximum conversion time is */
/* 653 / 0.14 MHz = 4.66 ms */
#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_Exported_Macros ADC Exported Macros
* @{
*/
/* Macro for internal HAL driver usage, and possibly can be used into code of */
/* final user. */
/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
* @{
*/
/** @brief Reset ADC handle state.
* @param __HANDLE__ ADC handle
* @retval None
*/
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
do{ \
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET)
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @brief Enable ADC interrupt.
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC Interrupt
* This parameter can be one of the following values:
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval None
*/
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable ADC interrupt.
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC Interrupt
* This parameter can be one of the following values:
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval None
*/
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
* @param __HANDLE__ ADC handle
* @param __INTERRUPT__ ADC interrupt source to check
* This parameter can be one of the following values:
* @arg @ref ADC_IT_RDY ADC Ready interrupt source
* @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source
* @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source
* @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source
* @arg @ref ADC_IT_OVR ADC overrun interrupt source
* @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source
* @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval State of interruption (SET or RESET)
*/
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Check whether the specified ADC flag is set or not.
* @param __HANDLE__ ADC handle
* @param __FLAG__ ADC flag
* This parameter can be one of the following values:
* @arg @ref ADC_FLAG_RDY ADC Ready flag
* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
* @retval State of flag (TRUE or FALSE).
*/
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the specified ADC flag.
* @param __HANDLE__ ADC handle
* @param __FLAG__ ADC flag
* This parameter can be one of the following values:
* @arg @ref ADC_FLAG_RDY ADC Ready flag
* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
* @retval None
*/
/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
(((__HANDLE__)->Instance->ISR) = (__FLAG__))
/**
* @}
*/
/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
* @{
*/
/**
* @brief Helper macro to get ADC channel number in decimal format
* from literals ADC_CHANNEL_x.
* @note Example:
* __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
* will return decimal number "4".
* @note The input can be a value from functions where a channel
* number is returned, either defined with number
* or with bitfield (only one bit must be set).
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref ADC_CHANNEL_0
* @arg @ref ADC_CHANNEL_1 (8)
* @arg @ref ADC_CHANNEL_2 (8)
* @arg @ref ADC_CHANNEL_3 (8)
* @arg @ref ADC_CHANNEL_4 (8)
* @arg @ref ADC_CHANNEL_5 (8)
* @arg @ref ADC_CHANNEL_6
* @arg @ref ADC_CHANNEL_7
* @arg @ref ADC_CHANNEL_8
* @arg @ref ADC_CHANNEL_9
* @arg @ref ADC_CHANNEL_10
* @arg @ref ADC_CHANNEL_11
* @arg @ref ADC_CHANNEL_12
* @arg @ref ADC_CHANNEL_13
* @arg @ref ADC_CHANNEL_14
* @arg @ref ADC_CHANNEL_15
* @arg @ref ADC_CHANNEL_16
* @arg @ref ADC_CHANNEL_17
* @arg @ref ADC_CHANNEL_18
* @arg @ref ADC_CHANNEL_VREFINT (7)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref ADC_CHANNEL_VBAT (6)
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
__LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
/**
* @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
* from number in decimal format.
* @note Example:
* __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
* will return a data equivalent to "ADC_CHANNEL_4".
* @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
* @retval Returned value can be one of the following values:
* @arg @ref ADC_CHANNEL_0
* @arg @ref ADC_CHANNEL_1 (8)
* @arg @ref ADC_CHANNEL_2 (8)
* @arg @ref ADC_CHANNEL_3 (8)
* @arg @ref ADC_CHANNEL_4 (8)
* @arg @ref ADC_CHANNEL_5 (8)
* @arg @ref ADC_CHANNEL_6
* @arg @ref ADC_CHANNEL_7
* @arg @ref ADC_CHANNEL_8
* @arg @ref ADC_CHANNEL_9
* @arg @ref ADC_CHANNEL_10
* @arg @ref ADC_CHANNEL_11
* @arg @ref ADC_CHANNEL_12
* @arg @ref ADC_CHANNEL_13
* @arg @ref ADC_CHANNEL_14
* @arg @ref ADC_CHANNEL_15
* @arg @ref ADC_CHANNEL_16
* @arg @ref ADC_CHANNEL_17
* @arg @ref ADC_CHANNEL_18
* @arg @ref ADC_CHANNEL_VREFINT (7)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref ADC_CHANNEL_VBAT (6)
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
__LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
/**
* @brief Helper macro to determine whether the selected channel
* corresponds to literal definitions of driver.
* @note The different literal definitions of ADC channels are:
* - ADC internal channel:
* ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
* - ADC external channel (channel connected to a GPIO pin):
* ADC_CHANNEL_1, ADC_CHANNEL_2, ...
* @note The channel parameter must be a value defined from literal
* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
* ADC_CHANNEL_TEMPSENSOR, ...),
* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
* must not be a value from functions where a channel number is
* returned from ADC registers,
* because internal and external channels share the same channel
* number in ADC registers. The differentiation is made only with
* parameters definitions of driver.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref ADC_CHANNEL_0
* @arg @ref ADC_CHANNEL_1 (8)
* @arg @ref ADC_CHANNEL_2 (8)
* @arg @ref ADC_CHANNEL_3 (8)
* @arg @ref ADC_CHANNEL_4 (8)
* @arg @ref ADC_CHANNEL_5 (8)
* @arg @ref ADC_CHANNEL_6
* @arg @ref ADC_CHANNEL_7
* @arg @ref ADC_CHANNEL_8
* @arg @ref ADC_CHANNEL_9
* @arg @ref ADC_CHANNEL_10
* @arg @ref ADC_CHANNEL_11
* @arg @ref ADC_CHANNEL_12
* @arg @ref ADC_CHANNEL_13
* @arg @ref ADC_CHANNEL_14
* @arg @ref ADC_CHANNEL_15
* @arg @ref ADC_CHANNEL_16
* @arg @ref ADC_CHANNEL_17
* @arg @ref ADC_CHANNEL_18
* @arg @ref ADC_CHANNEL_VREFINT (7)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref ADC_CHANNEL_VBAT (6)
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
__LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
/**
* @brief Helper macro to convert a channel defined from parameter
* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
* ADC_CHANNEL_TEMPSENSOR, ...),
* to its equivalent parameter definition of a ADC external channel
* (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
* @note The channel parameter can be, additionally to a value
* defined from parameter definition of a ADC internal channel
* (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
* a value defined from parameter definition of
* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
* or a value from functions where a channel number is returned
* from ADC registers.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref ADC_CHANNEL_0
* @arg @ref ADC_CHANNEL_1 (8)
* @arg @ref ADC_CHANNEL_2 (8)
* @arg @ref ADC_CHANNEL_3 (8)
* @arg @ref ADC_CHANNEL_4 (8)
* @arg @ref ADC_CHANNEL_5 (8)
* @arg @ref ADC_CHANNEL_6
* @arg @ref ADC_CHANNEL_7
* @arg @ref ADC_CHANNEL_8
* @arg @ref ADC_CHANNEL_9
* @arg @ref ADC_CHANNEL_10
* @arg @ref ADC_CHANNEL_11
* @arg @ref ADC_CHANNEL_12
* @arg @ref ADC_CHANNEL_13
* @arg @ref ADC_CHANNEL_14
* @arg @ref ADC_CHANNEL_15
* @arg @ref ADC_CHANNEL_16
* @arg @ref ADC_CHANNEL_17
* @arg @ref ADC_CHANNEL_18
* @arg @ref ADC_CHANNEL_VREFINT (7)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref ADC_CHANNEL_VBAT (6)
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval Returned value can be one of the following values:
* @arg @ref ADC_CHANNEL_0
* @arg @ref ADC_CHANNEL_1
* @arg @ref ADC_CHANNEL_2
* @arg @ref ADC_CHANNEL_3
* @arg @ref ADC_CHANNEL_4
* @arg @ref ADC_CHANNEL_5
* @arg @ref ADC_CHANNEL_6
* @arg @ref ADC_CHANNEL_7
* @arg @ref ADC_CHANNEL_8
* @arg @ref ADC_CHANNEL_9
* @arg @ref ADC_CHANNEL_10
* @arg @ref ADC_CHANNEL_11
* @arg @ref ADC_CHANNEL_12
* @arg @ref ADC_CHANNEL_13
* @arg @ref ADC_CHANNEL_14
* @arg @ref ADC_CHANNEL_15
* @arg @ref ADC_CHANNEL_16
* @arg @ref ADC_CHANNEL_17
* @arg @ref ADC_CHANNEL_18
*/
#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
/**
* @brief Helper macro to determine whether the internal channel
* selected is available on the ADC instance selected.
* @note The channel parameter must be a value defined from parameter
* definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
* ADC_CHANNEL_TEMPSENSOR, ...),
* must not be a value defined from parameter definition of
* ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
* or a value from functions where a channel number is
* returned from ADC registers,
* because internal and external channels share the same channel
* number in ADC registers. The differentiation is made only with
* parameters definitions of driver.
* @param __ADC_INSTANCE__ ADC instance
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref ADC_CHANNEL_VREFINT (7)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref ADC_CHANNEL_VBAT (6)
* @arg @ref ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
* Value "1" if the internal channel selected is available on the ADC instance selected.
*/
#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Helper macro to get the ADC multimode conversion data of ADC master
* or ADC slave from raw value with both ADC conversion data concatenated.
* @note This macro is intended to be used when multimode transfer by DMA
* is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
* In this case the transferred data need to processed with this macro
* to separate the conversion data of ADC master and ADC slave.
* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_MASTER
* @arg @ref LL_ADC_MULTI_SLAVE
* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
__LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select the ADC common instance
* to which is belonging the selected ADC instance.
* @note ADC common register instance can be used for:
* - Set parameters common to several ADC instances
* - Multimode (for devices with several ADC instances)
* Refer to functions having argument "ADCxy_COMMON" as parameter.
* @param __ADCx__ ADC instance
* @retval ADC common register instance
*/
#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
__LL_ADC_COMMON_INSTANCE((__ADCx__))
/**
* @brief Helper macro to check if all ADC instances sharing the same
* ADC common instance are disabled.
* @note This check is required by functions with setting conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* Refer to functions having argument "ADCxy_COMMON" as parameter.
* @note On devices with only 1 ADC common instance, parameter of this macro
* is useless and can be ignored (parameter kept for compatibility
* with devices featuring several ADC common instances).
* @param __ADCXY_COMMON__ ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Value "0" if all ADC instances sharing the same ADC common instance
* are disabled.
* Value "1" if at least one ADC instance sharing the same ADC common instance
* is enabled.
*/
#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
/**
* @brief Helper macro to define the ADC conversion data full-scale digital
* value corresponding to the selected ADC resolution.
* @note ADC conversion data full-scale corresponds to voltage range
* determined by analog voltage references Vref+ and Vref-
* (refer to reference manual).
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_12B
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @arg @ref ADC_RESOLUTION_6B
* @retval ADC conversion data full-scale digital value
*/
#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
__LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
/**
* @brief Helper macro to convert the ADC conversion data from
* a resolution to another resolution.
* @param __DATA__ ADC conversion data to be converted
* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
* This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_12B
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @arg @ref ADC_RESOLUTION_6B
* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
* This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_12B
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @arg @ref ADC_RESOLUTION_6B
* @retval ADC conversion data to the requested resolution
*/
#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__) \
__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
(__ADC_RESOLUTION_CURRENT__),\
(__ADC_RESOLUTION_TARGET__))
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
* corresponding to a ADC conversion data (unit: digital value).
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
* (unit: digital value).
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_12B
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @arg @ref ADC_RESOLUTION_6B
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
__ADC_RESOLUTION__) \
__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
(__ADC_DATA__),\
(__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
* (unit: mVolt) from ADC conversion data of internal voltage
* reference VrefInt.
* @note Computation is using VrefInt calibration value
* stored in system memory for each device during production.
* @note This voltage depends on user board environment: voltage level
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
* @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
* Otherwise, this macro performs the processing to scale
* ADC conversion data to 12 bits.
* @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
* of internal voltage reference VrefInt (unit: digital value).
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_12B
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @arg @ref ADC_RESOLUTION_6B
* @retval Analog reference voltage (unit: mV)
*/
#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
__ADC_RESOLUTION__) \
__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
(__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
* from ADC conversion data of internal temperature sensor.
* @note Computation is using temperature sensor calibration values
* stored in system memory for each device during production.
* @note Calculation formula:
* Temperature = ((TS_ADC_DATA - TS_CAL1)
* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
* with TS_ADC_DATA = temperature sensor raw data measured by ADC
* Avg_Slope = (TS_CAL2 - TS_CAL1)
* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
* TS_CAL1 = equivalent TS_ADC_DATA at temperature
* TEMP_DEGC_CAL1 (calibrated in factory)
* TS_CAL2 = equivalent TS_ADC_DATA at temperature
* TEMP_DEGC_CAL2 (calibrated in factory)
* Caution: Calculation relevancy under reserve that calibration
* parameters are correct (address and data).
* To calculate temperature using temperature sensor
* datasheet typical values (generic values less, therefore
* less accurate than calibrated values),
* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
* @note As calculation input, the analog reference voltage (Vref+) must be
* defined as it impacts the ADC LSB equivalent voltage.
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
* Otherwise, this macro performs the processing to scale
* ADC conversion data to 12 bits.
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
* temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
* sensor voltage has been measured.
* This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_12B
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @arg @ref ADC_RESOLUTION_6B
* @retval Temperature (unit: degree Celsius)
*/
#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \
__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
(__TEMPSENSOR_ADC_DATA__),\
(__ADC_RESOLUTION__))
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
* from ADC conversion data of internal temperature sensor.
* @note Computation is using temperature sensor typical values
* (refer to device datasheet).
* @note Calculation formula:
* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
* / Avg_Slope + CALx_TEMP
* with TS_ADC_DATA = temperature sensor raw data measured by ADC
* (unit: digital value)
* Avg_Slope = temperature sensor slope
* (unit: uV/Degree Celsius)
* TS_TYP_CALx_VOLT = temperature sensor digital value at
* temperature CALx_TEMP (unit: mV)
* Caution: Calculation relevancy under reserve the temperature sensor
* of the current device has characteristics in line with
* datasheet typical values.
* If temperature sensor calibration values are available on
* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
* temperature calculation will be more accurate using
* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
* @note As calculation input, the analog reference voltage (Vref+) must be
* defined as it impacts the ADC LSB equivalent voltage.
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @note ADC measurement data must correspond to a resolution of 12bits
* (full scale digital value 4095). If not the case, the data must be
* preliminarily rescaled to an equivalent resolution of 12 bits.
* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
* On STM32G4, refer to device datasheet parameter "Avg_Slope".
* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
* On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
* This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_12B
* @arg @ref ADC_RESOLUTION_10B
* @arg @ref ADC_RESOLUTION_8B
* @arg @ref ADC_RESOLUTION_6B
* @retval Temperature (unit: degree Celsius)
*/
#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
__TEMPSENSOR_TYP_CALX_V__,\
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
(__TEMPSENSOR_TYP_CALX_V__),\
(__TEMPSENSOR_CALX_TEMP__),\
(__VREFANALOG_VOLTAGE__),\
(__TEMPSENSOR_ADC_DATA__),\
(__ADC_RESOLUTION__))
/**
* @}
*/
/**
* @}
*/
/* Include ADC HAL Extended module */
#include "stm32g4xx_hal_adc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADC_Exported_Functions
* @{
*/
/** @addtogroup ADC_Exported_Functions_Group1
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
pADC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group2
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
/* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
/* ADC sampling control */
HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
/**
* @}
*/
/* Peripheral State functions *************************************************/
/** @addtogroup ADC_Exported_Functions_Group4
* @{
*/
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/**
* @}
*/
/* Private functions -----------------------------------------------------------*/
/** @addtogroup ADC_Private_Functions ADC Private Functions
* @{
*/
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAError(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_ADC_H */
| 144,826 | C | 70.168059 | 386 | 0.564747 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cortex.h | /**
******************************************************************************
* @file stm32g4xx_ll_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL CORTEX driver contains a set of generic APIs that can be
used by user:
(+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
functions
(+) Low power mode configuration (SCB register of Cortex-MCU)
(+) MPU API to configure and enable regions
(+) API to access to MCU info (CPUID register)
(+) API to enable fault handler (SHCSR accesses)
@endverbatim
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_CORTEX_H
#define __STM32G4xx_LL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
/** @defgroup CORTEX_LL CORTEX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
* @{
*/
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/
#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
* @{
*/
#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */
#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */
#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
* @{
*/
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */
#define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */
#define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
* @{
*/
#define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */
#define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */
#define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */
#define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */
#define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */
#define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */
#define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */
#define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
* @{
*/
#define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
#define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
* @{
*/
#define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
#define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
#define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
#define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
#define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
#define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
* @{
*/
#define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
#define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
#define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
#define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
* @{
*/
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
* @{
*/
#define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */
#define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
* @{
*/
#define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */
#define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */
/**
* @}
*/
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
* @{
*/
#define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */
#define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
* @{
*/
/**
* @brief This function checks if the Systick counter flag is active or not.
* @note It can be used in timeout function on application side.
* @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
{
return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);
}
/**
* @brief Configures the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
{
if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
{
SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
else
{
CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
}
/**
* @brief Get the SysTick clock source
* @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
* @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
*/
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
{
return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
}
/**
* @brief Enable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
{
SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Disable SysTick exception request
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT
* @retval None
*/
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
{
CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
}
/**
* @brief Checks if the SYSTICK interrupt is enabled or disabled.
* @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
{
return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
* @{
*/
/**
* @brief Processor uses sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleep(void)
{
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Processor uses deep sleep as its low power mode
* @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
{
/* Set SLEEPDEEP bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
}
/**
* @brief Configures sleep-on-exit when returning from Handler mode to Thread mode.
* @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
* empty main application.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
{
/* Set SLEEPONEXIT bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Do not sleep when returning to Thread mode.
* @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
{
/* Clear SLEEPONEXIT bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
}
/**
* @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the
* processor.
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
{
/* Set SEVEONPEND bit of Cortex System Control Register */
SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are
* excluded
* @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend
* @retval None
*/
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
{
/* Clear SEVEONPEND bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
* @{
*/
/**
* @brief Enable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
{
/* Enable the system handler fault */
SET_BIT(SCB->SHCSR, Fault);
}
/**
* @brief Disable a fault in System handler control register (SHCSR)
* @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault
* @param Fault This parameter can be a combination of the following values:
* @arg @ref LL_HANDLER_FAULT_USG
* @arg @ref LL_HANDLER_FAULT_BUS
* @arg @ref LL_HANDLER_FAULT_MEM
* @retval None
*/
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
{
/* Disable the system handler fault */
CLEAR_BIT(SCB->SHCSR, Fault);
}
/**
* @}
*/
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
* @{
*/
/**
* @brief Get Implementer code
* @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer
* @retval Value should be equal to 0x41 for ARM
*/
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
}
/**
* @brief Get Variant number (The r value in the rnpn product revision identifier)
* @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant
* @retval Value between 0 and 255 (0x0: revision 0)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
}
/**
* @brief Get Architecture number
* @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture
* @retval Value should be equal to 0xF for Cortex-M4 devices
*/
__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
}
/**
* @brief Get Part number
* @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo
* @retval Value should be equal to 0xC24 for Cortex-M4
*/
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
}
/**
* @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
* @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision
* @retval Value between 0 and 255 (0x1: patch 1)
*/
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
{
return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
}
/**
* @}
*/
#if __MPU_PRESENT
/** @defgroup CORTEX_LL_EF_MPU MPU
* @{
*/
/**
* @brief Enable MPU with input options
* @rmtoll MPU_CTRL ENABLE LL_MPU_Enable
* @param Options This parameter can be one of the following values:
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
* @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
* @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
* @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
* @retval None
*/
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
{
/* Enable the MPU*/
WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
/* Ensure MPU settings take effects */
__DSB();
/* Sequence instruction fetches using update settings */
__ISB();
}
/**
* @brief Disable MPU
* @rmtoll MPU_CTRL ENABLE LL_MPU_Disable
* @retval None
*/
__STATIC_INLINE void LL_MPU_Disable(void)
{
/* Make sure outstanding transfers are done */
__DMB();
/* Disable MPU*/
WRITE_REG(MPU->CTRL, 0U);
}
/**
* @brief Check if MPU is enabled or not
* @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
{
return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);
}
/**
* @brief Enable a MPU region
* @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Enable the MPU region */
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @brief Configure and enable a region
* @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR REGION LL_MPU_ConfigRegion\n
* MPU_RBAR ADDR LL_MPU_ConfigRegion\n
* MPU_RASR XN LL_MPU_ConfigRegion\n
* MPU_RASR AP LL_MPU_ConfigRegion\n
* MPU_RASR S LL_MPU_ConfigRegion\n
* MPU_RASR C LL_MPU_ConfigRegion\n
* MPU_RASR B LL_MPU_ConfigRegion\n
* MPU_RASR SIZE LL_MPU_ConfigRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @param Address Value of region base address
* @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
* @param Attributes This parameter can be a combination of the following values:
* @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
* or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
* or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
* or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
* or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
* or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
* @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
* or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
* @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
* @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
* @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
* @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
* @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
* @retval None
*/
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Set base address */
WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
/* Configure MPU */
WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));
}
/**
* @brief Disable a region
* @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n
* MPU_RASR ENABLE LL_MPU_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_MPU_REGION_NUMBER0
* @arg @ref LL_MPU_REGION_NUMBER1
* @arg @ref LL_MPU_REGION_NUMBER2
* @arg @ref LL_MPU_REGION_NUMBER3
* @arg @ref LL_MPU_REGION_NUMBER4
* @arg @ref LL_MPU_REGION_NUMBER5
* @arg @ref LL_MPU_REGION_NUMBER6
* @arg @ref LL_MPU_REGION_NUMBER7
* @retval None
*/
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
{
/* Set Region number */
WRITE_REG(MPU->RNR, Region);
/* Disable the MPU region */
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
}
/**
* @}
*/
#endif /* __MPU_PRESENT */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_CORTEX_H */
| 24,173 | C | 36.890282 | 176 | 0.606793 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_crc.h | /**
******************************************************************************
* @file stm32g4xx_ll_crc.h
* @author MCD Application Team
* @brief Header file of CRC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_CRC_H
#define STM32G4xx_LL_CRC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(CRC)
/** @defgroup CRC_LL CRC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants
* @{
*/
/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length
* @{
*/
#define LL_CRC_POLYLENGTH_32B 0x00000000U /*!< 32 bits Polynomial size */
#define LL_CRC_POLYLENGTH_16B CRC_CR_POLYSIZE_0 /*!< 16 bits Polynomial size */
#define LL_CRC_POLYLENGTH_8B CRC_CR_POLYSIZE_1 /*!< 8 bits Polynomial size */
#define LL_CRC_POLYLENGTH_7B (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0) /*!< 7 bits Polynomial size */
/**
* @}
*/
/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse
* @{
*/
#define LL_CRC_INDATA_REVERSE_NONE 0x00000000U /*!< Input Data bit order not affected */
#define LL_CRC_INDATA_REVERSE_BYTE CRC_CR_REV_IN_0 /*!< Input Data bit reversal done by byte */
#define LL_CRC_INDATA_REVERSE_HALFWORD CRC_CR_REV_IN_1 /*!< Input Data bit reversal done by half-word */
#define LL_CRC_INDATA_REVERSE_WORD (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0) /*!< Input Data bit reversal done by word */
/**
* @}
*/
/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse
* @{
*/
#define LL_CRC_OUTDATA_REVERSE_NONE 0x00000000U /*!< Output Data bit order not affected */
#define LL_CRC_OUTDATA_REVERSE_BIT CRC_CR_REV_OUT /*!< Output Data bit reversal done by bit */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_Polynomial_Value Default CRC generating polynomial value
* @brief Normal representation of this polynomial value is
* X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .
* @{
*/
#define LL_CRC_DEFAULT_CRC32_POLY 0x04C11DB7U /*!< Default CRC generating polynomial value */
/**
* @}
*/
/** @defgroup CRC_LL_EC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define LL_CRC_DEFAULT_CRC_INITVALUE 0xFFFFFFFFU /*!< Default CRC computation initialization value */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros
* @{
*/
/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)
/**
* @brief Read a value in CRC register
* @param __INSTANCE__ CRC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions
* @{
*/
/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions
* @{
*/
/**
* @brief Reset the CRC calculation unit.
* @note If Programmable Initial CRC value feature
* is available, also set the Data Register to the value stored in the
* CRC_INIT register, otherwise, reset Data Register to its default value.
* @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit
* @param CRCx CRC Instance
* @retval None
*/
__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)
{
SET_BIT(CRCx->CR, CRC_CR_RESET);
}
/**
* @brief Configure size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_SetPolynomialSize
* @param CRCx CRC Instance
* @param PolySize This parameter can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)
{
MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);
}
/**
* @brief Return size of the polynomial.
* @rmtoll CR POLYSIZE LL_CRC_GetPolynomialSize
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_POLYLENGTH_32B
* @arg @ref LL_CRC_POLYLENGTH_16B
* @arg @ref LL_CRC_POLYLENGTH_8B
* @arg @ref LL_CRC_POLYLENGTH_7B
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));
}
/**
* @brief Configure the reversal of the bit order of the input data
* @rmtoll CR REV_IN LL_CRC_SetInputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);
}
/**
* @brief Return type of reversal for input data bit order
* @rmtoll CR REV_IN LL_CRC_GetInputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_INDATA_REVERSE_NONE
* @arg @ref LL_CRC_INDATA_REVERSE_BYTE
* @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD
* @arg @ref LL_CRC_INDATA_REVERSE_WORD
*/
__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));
}
/**
* @brief Configure the reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_SetOutputDataReverseMode
* @param CRCx CRC Instance
* @param ReverseMode This parameter can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)
{
MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);
}
/**
* @brief Return type of reversal of the bit order of the Output data
* @rmtoll CR REV_OUT LL_CRC_GetOutputDataReverseMode
* @param CRCx CRC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRC_OUTDATA_REVERSE_NONE
* @arg @ref LL_CRC_OUTDATA_REVERSE_BIT
*/
__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));
}
/**
* @brief Initialize the Programmable initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to write the correct value
* @note LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.
* @rmtoll INIT INIT LL_CRC_SetInitialData
* @param CRCx CRC Instance
* @param InitCrc Value to be programmed in Programmable initial CRC value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)
{
WRITE_REG(CRCx->INIT, InitCrc);
}
/**
* @brief Return current Initial CRC value.
* @note If the CRC size is less than 32 bits, the least significant bits
* are used to read the correct value
* @rmtoll INIT INIT LL_CRC_GetInitialData
* @param CRCx CRC Instance
* @retval Value programmed in Programmable initial CRC value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->INIT));
}
/**
* @brief Initialize the Programmable polynomial value
* (coefficients of the polynomial to be used for CRC calculation).
* @note LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_SetPolynomialCoef
* @param CRCx CRC Instance
* @param PolynomCoef Value to be programmed in Programmable Polynomial value register
* @retval None
*/
__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)
{
WRITE_REG(CRCx->POL, PolynomCoef);
}
/**
* @brief Return current Programmable polynomial value
* @note Please check Reference Manual and existing Errata Sheets,
* regarding possible limitations for Polynomial values usage.
* For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65
* @rmtoll POL POL LL_CRC_GetPolynomialCoef
* @param CRCx CRC Instance
* @retval Value programmed in Programmable Polynomial value register
*/
__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->POL));
}
/**
* @}
*/
/** @defgroup CRC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write given 32-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData32
* @param CRCx CRC Instance
* @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)
{
WRITE_REG(CRCx->DR, InData);
}
/**
* @brief Write given 16-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData16
* @param CRCx CRC Instance
* @param InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)
{
__IO uint16_t *pReg;
pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR); /* Derogation MisraC2012 R.11.5 */
*pReg = InData;
}
/**
* @brief Write given 8-bit data to the CRC calculator
* @rmtoll DR DR LL_CRC_FeedData8
* @param CRCx CRC Instance
* @param InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)
{
*(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;
}
/**
* @brief Return current CRC calculation result. 32 bits value is returned.
* @rmtoll DR DR LL_CRC_ReadData32
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (32 bits).
*/
__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->DR));
}
/**
* @brief Return current CRC calculation result. 16 bits value is returned.
* @note This function is expected to be used in a 16 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData16
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (16 bits).
*/
__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)
{
return (uint16_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 8 bits value is returned.
* @note This function is expected to be used in a 8 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData8
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (8 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)
{
return (uint8_t)READ_REG(CRCx->DR);
}
/**
* @brief Return current CRC calculation result. 7 bits value is returned.
* @note This function is expected to be used in a 7 bits CRC polynomial size context.
* @rmtoll DR DR LL_CRC_ReadData7
* @param CRCx CRC Instance
* @retval Current CRC calculation result as stored in CRC_DR register (7 bits).
*/
__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)
{
return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);
}
/**
* @brief Return data stored in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one 32-bit long data.
* @rmtoll IDR IDR LL_CRC_Read_IDR
* @param CRCx CRC Instance
* @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).
*/
__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)
{
return (uint32_t)(READ_REG(CRCx->IDR));
}
/**
* @brief Store data in the Independent Data(IDR) register.
* @note This register can be used as a temporary storage location for one 32-bit long data.
* @rmtoll IDR IDR LL_CRC_Write_IDR
* @param CRCx CRC Instance
* @param InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)
{
*((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_CRC_H */
| 15,520 | C | 32.595238 | 137 | 0.601804 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_iwdg.h | /**
******************************************************************************
* @file stm32g4xx_ll_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_IWDG_H
#define STM32G4xx_LL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(IWDG)
/** @defgroup IWDG_LL IWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants
* @{
*/
#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */
#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */
#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */
#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_IWDG_ReadReg function
* @{
*/
#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */
#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */
#define LL_IWDG_SR_WVU IWDG_SR_WVU /*!< Watchdog counter window value update */
/**
* @}
*/
/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider
* @{
*/
#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */
#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0) /*!< Divider by 8 */
#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1) /*!< Divider by 16 */
#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */
#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2) /*!< Divider by 64 */
#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */
#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< Divider by 256 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros
* @{
*/
/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in IWDG register
* @param __INSTANCE__ IWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Start the Independent Watchdog
* @note Except if the hardware watchdog option is selected
* @rmtoll KR KEY LL_IWDG_Enable
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
}
/**
* @brief Reloads IWDG counter with value defined in the reload register
* @rmtoll KR KEY LL_IWDG_ReloadCounter
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
}
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_EnableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
}
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers
* @rmtoll KR KEY LL_IWDG_DisableWriteAccess
* @param IWDGx IWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
{
WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
}
/**
* @brief Select the prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_SetPrescaler
* @param IWDGx IWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
{
WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
}
/**
* @brief Get the selected prescaler of the IWDG
* @rmtoll PR PR LL_IWDG_GetPrescaler
* @param IWDGx IWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_IWDG_PRESCALER_4
* @arg @ref LL_IWDG_PRESCALER_8
* @arg @ref LL_IWDG_PRESCALER_16
* @arg @ref LL_IWDG_PRESCALER_32
* @arg @ref LL_IWDG_PRESCALER_64
* @arg @ref LL_IWDG_PRESCALER_128
* @arg @ref LL_IWDG_PRESCALER_256
*/
__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->PR));
}
/**
* @brief Specify the IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_SetReloadCounter
* @param IWDGx IWDG Instance
* @param Counter Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
{
WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
}
/**
* @brief Get the specified IWDG down-counter reload value
* @rmtoll RLR RL LL_IWDG_GetReloadCounter
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->RLR));
}
/**
* @brief Specify high limit of the window value to be compared to the down-counter.
* @rmtoll WINR WIN LL_IWDG_SetWindow
* @param IWDGx IWDG Instance
* @param Window Value between Min_Data=0 and Max_Data=0x0FFF
* @retval None
*/
__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)
{
WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);
}
/**
* @brief Get the high limit of the window value specified.
* @rmtoll WINR WIN LL_IWDG_GetWindow
* @param IWDGx IWDG Instance
* @retval Value between Min_Data=0 and Max_Data=0x0FFF
*/
__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)
{
return (READ_REG(IWDGx->WINR));
}
/**
* @}
*/
/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if flag Prescaler Value Update is set or not
* @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Reload Value Update is set or not
* @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
}
/**
* @brief Check if flag Window Value Update is set or not
* @rmtoll SR WVU LL_IWDG_IsActiveFlag_WVU
* @param IWDGx IWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);
}
/**
* @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not
* @rmtoll SR PVU LL_IWDG_IsReady\n
* SR RVU LL_IWDG_IsReady\n
* SR WVU LL_IWDG_IsReady
* @param IWDGx IWDG Instance
* @retval State of bits (1 or 0).
*/
__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)
{
return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* IWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_IWDG_H */
| 10,347 | C | 29.525074 | 125 | 0.549338 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usb.h | /**
******************************************************************************
* @file stm32g4xx_ll_usb.h
* @author MCD Application Team
* @brief Header file of USB Low Layer HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_USB_H
#define STM32G4xx_LL_USB_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined (USB)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup USB_LL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief USB Mode definition
*/
typedef enum
{
USB_DEVICE_MODE = 0
} USB_ModeTypeDef;
/**
* @brief USB Initialization Structure definition
*/
typedef struct
{
uint32_t dev_endpoints; /*!< Device Endpoints number.
This parameter depends on the used USB core.
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint32_t speed; /*!< USB Core speed.
This parameter can be any value of @ref PCD_Speed/HCD_Speed
(HCD_SPEED_xxx, HCD_SPEED_xxx) */
uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */
uint32_t phy_itface; /*!< Select the used PHY interface.
This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */
uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */
uint32_t low_power_enable; /*!< Enable or disable Low Power mode */
uint32_t lpm_enable; /*!< Enable or disable Battery charging. */
uint32_t battery_charging_enable; /*!< Enable or disable Battery charging. */
} USB_CfgTypeDef;
typedef struct
{
uint8_t num; /*!< Endpoint number
This parameter must be a number between Min_Data = 1 and Max_Data = 15 */
uint8_t is_in; /*!< Endpoint direction
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t is_stall; /*!< Endpoint stall condition
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint8_t type; /*!< Endpoint type
This parameter can be any value of @ref USB_EP_Type */
uint8_t data_pid_start; /*!< Initial data PID
This parameter must be a number between Min_Data = 0 and Max_Data = 1 */
uint16_t pmaadress; /*!< PMA Address
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr0; /*!< PMA Address0
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint16_t pmaaddr1; /*!< PMA Address1
This parameter can be any value between Min_addr = 0 and Max_addr = 1K */
uint8_t doublebuffer; /*!< Double buffer enable
This parameter can be 0 or 1 */
uint16_t tx_fifo_num; /*!< This parameter is not required by USB Device FS peripheral, it is used
only by USB OTG FS peripheral
This parameter is added to ensure compatibility across USB peripherals */
uint32_t maxpacket; /*!< Endpoint Max packet size
This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
uint8_t *xfer_buff; /*!< Pointer to transfer buffer */
uint32_t xfer_len; /*!< Current transfer length */
uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */
uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */
uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */
} USB_EPTypeDef;
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS
* @{
*/
#define EP_MPS_64 0U
#define EP_MPS_32 1U
#define EP_MPS_16 2U
#define EP_MPS_8 3U
/**
* @}
*/
/** @defgroup USB_LL_EP_Type USB Low Layer EP Type
* @{
*/
#define EP_TYPE_CTRL 0U
#define EP_TYPE_ISOC 1U
#define EP_TYPE_BULK 2U
#define EP_TYPE_INTR 3U
#define EP_TYPE_MSK 3U
/**
* @}
*/
/** @defgroup USB_LL Device Speed
* @{
*/
#define USBD_FS_SPEED 2U
/**
* @}
*/
#define BTABLE_ADDRESS 0x000U
#define PMA_ACCESS 1U
#define EP_ADDR_MSK 0x7U
#ifndef USE_USB_DOUBLE_BUFFER
#define USE_USB_DOUBLE_BUFFER 1U
#endif /* USE_USB_DOUBLE_BUFFER */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions
* @{
*/
HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg);
HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode);
#if defined (HAL_PCD_MODULE_ENABLED)
HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep);
#endif /* defined (HAL_PCD_MODULE_ENABLED) */
HAL_StatusTypeDef USB_SetDevAddress(USB_TypeDef *USBx, uint8_t address);
HAL_StatusTypeDef USB_DevConnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DevDisconnect(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_StopDevice(USB_TypeDef *USBx);
uint32_t USB_ReadInterrupts(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_TypeDef *USBx);
HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_TypeDef *USBx);
void USB_WritePMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
void USB_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf,
uint16_t wPMABufAddr, uint16_t wNBytes);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32G4xx_LL_USB_H */
| 8,298 | C | 33.579167 | 114 | 0.500723 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_utils.h | /**
******************************************************************************
* @file stm32g4xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_UTILS_H
#define STM32G4xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
This parameter can be a value of @ref RCC_LL_EC_PLLM_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 8 and Max_Data = 86
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
uint32_t PLLR; /*!< Division for the main system clock.
This parameter can be a value of @ref RCC_LL_EC_PLLR_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL_ConfigDomain_SYS(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
/**
* @}
*/
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP81 0x00000005U /*!< WLCSP81 package type */
#define LL_UTILS_PACKAGETYPE_LQFP128 0x00000007U /*!< LQFP128 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000008U /*!< UFQFPN32 package type */
#define LL_UTILS_PACKAGETYPE_LQFP32 0x00000009U /*!< LQFP32 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x0000000AU /*!< UFQFPN48 package type */
#define LL_UTILS_PACKAGETYPE_LQFP48 0x0000000BU /*!< LQFP48 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP49 0x0000000CU /*!< WLCSP49 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA64 0x0000000DU /*!< UFBGA64 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA100 0x0000000EU /*!< UFBGA100 package type */
#define LL_UTILS_PACKAGETYPE_LQFP48_EBIKE 0x00000010U /*!< LQFP48 EBIKE package type */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0x0000FFFFUL);
}
/**
* @brief Get Package type
* @retval Returned value can be one of the following values:
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP81
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP128
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP32
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP49
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA64
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_EBIKE
*
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU);
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_UTILS_H */
| 10,880 | C | 33.216981 | 133 | 0.547886 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h | /**
******************************************************************************
* @file stm32g4xx_ll_usart.h
* @author MCD Application Team
* @brief Header file of USART LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_USART_H
#define STM32G4xx_LL_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (USART1) || defined (USART2) || defined (USART3) || defined (UART4) || defined (UART5)
/** @defgroup USART_LL USART
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup USART_LL_Private_Variables USART Private Variables
* @{
*/
/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
static const uint32_t USART_PRESCALER_TAB[] =
{
1UL,
2UL,
4UL,
6UL,
8UL,
10UL,
12UL,
16UL,
32UL,
64UL,
128UL,
256UL
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_Private_Macros USART Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_ES_INIT USART Exported Init structures
* @{
*/
/**
* @brief LL USART Init Structure definition
*/
typedef struct
{
uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate.
This parameter can be a value of @ref USART_LL_EC_PRESCALER.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetPrescaler().*/
uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetBaudRate().*/
uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetDataWidth().*/
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_LL_EC_STOPBITS.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetStopBitsLength().*/
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_LL_EC_PARITY.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetParity().*/
uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_DIRECTION.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetTransferDirection().*/
uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetHWFlowCtrl().*/
uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8.
This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
This feature can be modified afterwards using unitary
function @ref LL_USART_SetOverSampling().*/
} LL_USART_InitTypeDef;
/**
* @brief LL USART Clock Init Structure definition
*/
typedef struct
{
uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_LL_EC_CLOCK.
USART HW configuration can be modified afterwards using unitary functions
@ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
For more details, refer to description of this function. */
uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_LL_EC_POLARITY.
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetClockPolarity().
For more details, refer to description of this function. */
uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_LL_EC_PHASE.
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetClockPhase().
For more details, refer to description of this function. */
uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
USART HW configuration can be modified afterwards using unitary
functions @ref LL_USART_SetLastClkPulseOutput().
For more details, refer to description of this function. */
} LL_USART_ClockInitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_LL_Exported_Constants USART Exported Constants
* @{
*/
/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_USART_WriteReg function
* @{
*/
#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */
#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */
#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */
#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */
#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */
#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */
#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */
#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */
#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */
#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */
#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */
#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */
#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */
#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */
#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */
/**
* @}
*/
/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_USART_ReadReg function
* @{
*/
#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */
#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */
#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */
#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */
#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */
#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */
#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/
#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */
#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */
#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */
#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */
#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */
#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */
#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */
#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */
#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */
#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */
#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */
#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */
#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */
#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */
#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */
#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */
#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */
#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */
#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */
#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */
/**
* @}
*/
/** @defgroup USART_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions
* @{
*/
#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */
#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */
#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */
#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */
#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */
#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */
#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */
#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */
#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */
#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */
#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */
#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */
#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */
#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */
#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */
#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */
#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */
/**
* @}
*/
/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
* @{
*/
#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */
#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */
#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */
#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */
#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */
#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */
/**
* @}
*/
/** @defgroup USART_LL_EC_DIRECTION Communication Direction
* @{
*/
#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */
#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */
#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */
#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */
/**
* @}
*/
/** @defgroup USART_LL_EC_PARITY Parity Control
* @{
*/
#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */
#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */
#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */
/**
* @}
*/
/** @defgroup USART_LL_EC_WAKEUP Wakeup
* @{
*/
#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */
#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */
/**
* @}
*/
/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
* @{
*/
#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
/**
* @}
*/
/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
* @{
*/
#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */
#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_EC_CLOCK Clock Signal
* @{
*/
#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */
#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
* @{
*/
#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */
#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */
/**
* @}
*/
/** @defgroup USART_LL_EC_PHASE Clock Phase
* @{
*/
#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */
#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */
/**
* @}
*/
/** @defgroup USART_LL_EC_POLARITY Clock Polarity
* @{
*/
#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/
#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */
/**
* @}
*/
/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
* @{
*/
#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */
#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */
#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */
#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */
#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */
#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */
#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */
#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */
#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */
#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */
#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
/**
* @}
*/
/** @defgroup USART_LL_EC_STOPBITS Stop Bits
* @{
*/
#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */
#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */
#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */
#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */
/**
* @}
*/
/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
* @{
*/
#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */
#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */
/**
* @}
*/
/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
* @{
*/
#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */
#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */
/**
* @}
*/
/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
* @{
*/
#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */
#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */
/**
* @}
*/
/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
* @{
*/
#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
/**
* @}
*/
/** @defgroup USART_LL_EC_BITORDER Bit Order
* @{
*/
#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */
#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */
/**
* @}
*/
/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
* @{
*/
#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */
#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */
#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
/**
* @}
*/
/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
* @{
*/
#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */
#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
/**
* @}
*/
/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
* @{
*/
#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */
#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */
/**
* @}
*/
/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
* @{
*/
#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */
#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */
#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */
/**
* @}
*/
/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
* @{
*/
#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */
#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */
/**
* @}
*/
/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
* @{
*/
#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */
#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */
/**
* @}
*/
/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
* @{
*/
#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */
#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */
/**
* @}
*/
/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup USART_LL_Exported_Macros USART Exported Macros
* @{
*/
/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in USART register
* @param __INSTANCE__ USART Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in USART register
* @param __INSTANCE__ USART Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
* @{
*/
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
* expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
* @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
* @param __PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
*/
#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
(((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @brief Compute USARTDIV value according to Peripheral Clock and
* expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
* @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance
* @param __PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @param __BAUDRATE__ Baud rate value to achieve
* @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
*/
#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+ ((__BAUDRATE__)/2U))/(__BAUDRATE__))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup USART_LL_Exported_Functions USART Exported Functions
* @{
*/
/** @defgroup USART_LL_EF_Configuration Configuration functions
* @{
*/
/**
* @brief USART Enable
* @rmtoll CR1 UE LL_USART_Enable
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR1, USART_CR1_UE);
}
/**
* @brief USART Disable (all USART prescalers and outputs are disabled)
* @note When USART is disabled, USART prescalers and outputs are stopped immediately,
* and current operations are discarded. The configuration of the USART is kept, but all the status
* flags, in the USARTx_ISR are set to their default values.
* @rmtoll CR1 UE LL_USART_Disable
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
}
/**
* @brief Indicate if USART is enabled
* @rmtoll CR1 UE LL_USART_IsEnabled
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
}
/**
* @brief FIFO Mode Enable
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_EnableFIFO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
}
/**
* @brief FIFO Mode Disable
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_DisableFIFO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
}
/**
* @brief Indicate if FIFO Mode is enabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
}
/**
* @brief Configure TX FIFO Threshold
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold
* @param USARTx USART Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Return TX FIFO Threshold Configuration
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
*/
__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
}
/**
* @brief Configure RX FIFO Threshold
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold
* @param USARTx USART Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
{
ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Return RX FIFO Threshold Configuration
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
*/
__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
}
/**
* @brief Configure TX and RX FIFOs Threshold
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n
* CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold
* @param USARTx USART Instance
* @param TXThreshold This parameter can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
* @param RXThreshold This parameter can be one of the following values:
* @arg @ref LL_USART_FIFOTHRESHOLD_1_8
* @arg @ref LL_USART_FIFOTHRESHOLD_1_4
* @arg @ref LL_USART_FIFOTHRESHOLD_1_2
* @arg @ref LL_USART_FIFOTHRESHOLD_3_4
* @arg @ref LL_USART_FIFOTHRESHOLD_7_8
* @arg @ref LL_USART_FIFOTHRESHOLD_8_8
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
{
ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
(RXThreshold << USART_CR3_RXFTCFG_Pos));
}
/**
* @brief USART enabled in STOP Mode.
* @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
* USART clock selection is HSI or LSE in RCC.
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_EnableInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
* @brief USART disabled in STOP Mode.
* @note When this function is disabled, USART is not able to wake up the MCU from Stop mode
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_DisableInStopMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
}
/**
* @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
}
/**
* @brief Receiver Enable (Receiver is enabled and begins searching for a start bit)
* @rmtoll CR1 RE LL_USART_EnableDirectionRx
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
}
/**
* @brief Receiver Disable
* @rmtoll CR1 RE LL_USART_DisableDirectionRx
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
}
/**
* @brief Transmitter Enable
* @rmtoll CR1 TE LL_USART_EnableDirectionTx
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
}
/**
* @brief Transmitter Disable
* @rmtoll CR1 TE LL_USART_DisableDirectionTx
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
}
/**
* @brief Configure simultaneously enabled/disabled states
* of Transmitter and Receiver
* @rmtoll CR1 RE LL_USART_SetTransferDirection\n
* CR1 TE LL_USART_SetTransferDirection
* @param USARTx USART Instance
* @param TransferDirection This parameter can be one of the following values:
* @arg @ref LL_USART_DIRECTION_NONE
* @arg @ref LL_USART_DIRECTION_RX
* @arg @ref LL_USART_DIRECTION_TX
* @arg @ref LL_USART_DIRECTION_TX_RX
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
{
ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
}
/**
* @brief Return enabled/disabled states of Transmitter and Receiver
* @rmtoll CR1 RE LL_USART_GetTransferDirection\n
* CR1 TE LL_USART_GetTransferDirection
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_DIRECTION_NONE
* @arg @ref LL_USART_DIRECTION_RX
* @arg @ref LL_USART_DIRECTION_TX
* @arg @ref LL_USART_DIRECTION_TX_RX
*/
__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
}
/**
* @brief Configure Parity (enabled/disabled and parity mode if enabled).
* @note This function selects if hardware parity control (generation and detection) is enabled or disabled.
* When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
* (9th or 8th bit depending on data width) and parity is checked on the received data.
* @rmtoll CR1 PS LL_USART_SetParity\n
* CR1 PCE LL_USART_SetParity
* @param USARTx USART Instance
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_USART_PARITY_NONE
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
* @retval None
*/
__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
{
MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
}
/**
* @brief Return Parity configuration (enabled/disabled and parity mode if enabled)
* @rmtoll CR1 PS LL_USART_GetParity\n
* CR1 PCE LL_USART_GetParity
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_PARITY_NONE
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
*/
__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
}
/**
* @brief Set Receiver Wake Up method from Mute mode.
* @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod
* @param USARTx USART Instance
* @param Method This parameter can be one of the following values:
* @arg @ref LL_USART_WAKEUP_IDLELINE
* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
* @retval None
*/
__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
{
MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
}
/**
* @brief Return Receiver Wake Up method from Mute mode
* @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_WAKEUP_IDLELINE
* @arg @ref LL_USART_WAKEUP_ADDRESSMARK
*/
__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
}
/**
* @brief Set Word length (i.e. nb of data bits, excluding start and stop bits)
* @rmtoll CR1 M0 LL_USART_SetDataWidth\n
* CR1 M1 LL_USART_SetDataWidth
* @param USARTx USART Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_USART_DATAWIDTH_7B
* @arg @ref LL_USART_DATAWIDTH_8B
* @arg @ref LL_USART_DATAWIDTH_9B
* @retval None
*/
__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
{
MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
}
/**
* @brief Return Word length (i.e. nb of data bits, excluding start and stop bits)
* @rmtoll CR1 M0 LL_USART_GetDataWidth\n
* CR1 M1 LL_USART_GetDataWidth
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_DATAWIDTH_7B
* @arg @ref LL_USART_DATAWIDTH_8B
* @arg @ref LL_USART_DATAWIDTH_9B
*/
__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
}
/**
* @brief Allow switch between Mute Mode and Active mode
* @rmtoll CR1 MME LL_USART_EnableMuteMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
}
/**
* @brief Prevent Mute Mode use. Set Receiver in active mode permanently.
* @rmtoll CR1 MME LL_USART_DisableMuteMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
}
/**
* @brief Indicate if switch between Mute Mode and Active mode is allowed
* @rmtoll CR1 MME LL_USART_IsEnabledMuteMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
}
/**
* @brief Set Oversampling to 8-bit or 16-bit mode
* @rmtoll CR1 OVER8 LL_USART_SetOverSampling
* @param USARTx USART Instance
* @param OverSampling This parameter can be one of the following values:
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval None
*/
__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
{
MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
}
/**
* @brief Return Oversampling mode
* @rmtoll CR1 OVER8 LL_USART_GetOverSampling
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
*/
__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
}
/**
* @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput
* @param USARTx USART Instance
* @param LastBitClockPulse This parameter can be one of the following values:
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
* @retval None
*/
__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
{
MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
}
/**
* @brief Retrieve Clock pulse of the last data bit output configuration
* (Last bit Clock pulse output to the SCLK pin or not)
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
*/
__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
}
/**
* @brief Select the phase of the clock output on the SCLK pin in synchronous mode
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_SetClockPhase
* @param USARTx USART Instance
* @param ClockPhase This parameter can be one of the following values:
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
* @retval None
*/
__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
{
MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
}
/**
* @brief Return phase of the clock output on the SCLK pin in synchronous mode
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPHA LL_USART_GetClockPhase
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
*/
__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
}
/**
* @brief Select the polarity of the clock output on the SCLK pin in synchronous mode
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_SetClockPolarity
* @param USARTx USART Instance
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
{
MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
}
/**
* @brief Return polarity of the clock output on the SCLK pin in synchronous mode
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CPOL LL_USART_GetClockPolarity
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
}
/**
* @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
* - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
* - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
* @rmtoll CR2 CPHA LL_USART_ConfigClock\n
* CR2 CPOL LL_USART_ConfigClock\n
* CR2 LBCL LL_USART_ConfigClock
* @param USARTx USART Instance
* @param Phase This parameter can be one of the following values:
* @arg @ref LL_USART_PHASE_1EDGE
* @arg @ref LL_USART_PHASE_2EDGE
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_USART_POLARITY_LOW
* @arg @ref LL_USART_POLARITY_HIGH
* @param LBCPOutput This parameter can be one of the following values:
* @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
* @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
{
MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
}
/**
* @brief Configure Clock source prescaler for baudrate generator and oversampling
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_SetPrescaler
* @param USARTx USART Instance
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @retval None
*/
__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
}
/**
* @brief Retrieve the Clock source prescaler for baudrate generator and oversampling
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll PRESC PRESCALER LL_USART_GetPrescaler
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
*/
__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
}
/**
* @brief Enable Clock output on SCLK pin
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
}
/**
* @brief Disable Clock output on SCLK pin
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
}
/**
* @brief Indicate if Clock output on SCLK pin is enabled
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
}
/**
* @brief Set the length of the stop bits
* @rmtoll CR2 STOP LL_USART_SetStopBitsLength
* @param USARTx USART Instance
* @param StopBits This parameter can be one of the following values:
* @arg @ref LL_USART_STOPBITS_0_5
* @arg @ref LL_USART_STOPBITS_1
* @arg @ref LL_USART_STOPBITS_1_5
* @arg @ref LL_USART_STOPBITS_2
* @retval None
*/
__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
{
MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
}
/**
* @brief Retrieve the length of the stop bits
* @rmtoll CR2 STOP LL_USART_GetStopBitsLength
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_STOPBITS_0_5
* @arg @ref LL_USART_STOPBITS_1
* @arg @ref LL_USART_STOPBITS_1_5
* @arg @ref LL_USART_STOPBITS_2
*/
__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
}
/**
* @brief Configure Character frame format (Datawidth, Parity control, Stop Bits)
* @note Call of this function is equivalent to following function call sequence :
* - Data Width configuration using @ref LL_USART_SetDataWidth() function
* - Parity Control and mode configuration using @ref LL_USART_SetParity() function
* - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
* @rmtoll CR1 PS LL_USART_ConfigCharacter\n
* CR1 PCE LL_USART_ConfigCharacter\n
* CR1 M0 LL_USART_ConfigCharacter\n
* CR1 M1 LL_USART_ConfigCharacter\n
* CR2 STOP LL_USART_ConfigCharacter
* @param USARTx USART Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_USART_DATAWIDTH_7B
* @arg @ref LL_USART_DATAWIDTH_8B
* @arg @ref LL_USART_DATAWIDTH_9B
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_USART_PARITY_NONE
* @arg @ref LL_USART_PARITY_EVEN
* @arg @ref LL_USART_PARITY_ODD
* @param StopBits This parameter can be one of the following values:
* @arg @ref LL_USART_STOPBITS_0_5
* @arg @ref LL_USART_STOPBITS_1
* @arg @ref LL_USART_STOPBITS_1_5
* @arg @ref LL_USART_STOPBITS_2
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
uint32_t StopBits)
{
MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
}
/**
* @brief Configure TX/RX pins swapping setting.
* @rmtoll CR2 SWAP LL_USART_SetTXRXSwap
* @param USARTx USART Instance
* @param SwapConfig This parameter can be one of the following values:
* @arg @ref LL_USART_TXRX_STANDARD
* @arg @ref LL_USART_TXRX_SWAPPED
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
{
MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
}
/**
* @brief Retrieve TX/RX pins swapping configuration.
* @rmtoll CR2 SWAP LL_USART_GetTXRXSwap
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_TXRX_STANDARD
* @arg @ref LL_USART_TXRX_SWAPPED
*/
__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
}
/**
* @brief Configure RX pin active level logic
* @rmtoll CR2 RXINV LL_USART_SetRXPinLevel
* @param USARTx USART Instance
* @param PinInvMethod This parameter can be one of the following values:
* @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
{
MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
}
/**
* @brief Retrieve RX pin active level logic configuration
* @rmtoll CR2 RXINV LL_USART_GetRXPinLevel
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
*/
__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
}
/**
* @brief Configure TX pin active level logic
* @rmtoll CR2 TXINV LL_USART_SetTXPinLevel
* @param USARTx USART Instance
* @param PinInvMethod This parameter can be one of the following values:
* @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
{
MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
}
/**
* @brief Retrieve TX pin active level logic configuration
* @rmtoll CR2 TXINV LL_USART_GetTXPinLevel
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
* @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
*/
__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
}
/**
* @brief Configure Binary data logic.
* @note Allow to define how Logical data from the data register are send/received :
* either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
* @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic
* @param USARTx USART Instance
* @param DataLogic This parameter can be one of the following values:
* @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
* @retval None
*/
__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
{
MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
}
/**
* @brief Retrieve Binary data configuration
* @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
* @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
*/
__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
}
/**
* @brief Configure transfer bit order (either Less or Most Significant Bit First)
* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
* @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder
* @param USARTx USART Instance
* @param BitOrder This parameter can be one of the following values:
* @arg @ref LL_USART_BITORDER_LSBFIRST
* @arg @ref LL_USART_BITORDER_MSBFIRST
* @retval None
*/
__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
{
MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
}
/**
* @brief Return transfer bit order (either Less or Most Significant Bit First)
* @note MSB First means data is transmitted/received with the MSB first, following the start bit.
* LSB First means data is transmitted/received with data bit 0 first, following the start bit.
* @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_BITORDER_LSBFIRST
* @arg @ref LL_USART_BITORDER_MSBFIRST
*/
__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
}
/**
* @brief Enable Auto Baud-Rate Detection
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_ABREN);
}
/**
* @brief Disable Auto Baud-Rate Detection
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
}
/**
* @brief Indicate if Auto Baud-Rate Detection mechanism is enabled
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
}
/**
* @brief Set Auto Baud-Rate mode bits
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode
* @param USARTx USART Instance
* @param AutoBaudRateMode This parameter can be one of the following values:
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
* @retval None
*/
__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
{
MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
}
/**
* @brief Return Auto Baud-Rate mode
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
*/
__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
}
/**
* @brief Enable Receiver Timeout
* @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
}
/**
* @brief Disable Receiver Timeout
* @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
}
/**
* @brief Indicate if Receiver Timeout feature is enabled
* @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
}
/**
* @brief Set Address of the USART node.
* @note This is used in multiprocessor communication during Mute mode or Stop mode,
* for wake up with address mark detection.
* @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7.
* (b7-b4 should be set to 0)
* 8bits address node is used when 7-bit Address Detection is selected in ADDM7.
* (This is used in multiprocessor communication during Mute mode or Stop mode,
* for wake up with 7-bit address mark detection.
* The MSB of the character sent by the transmitter should be equal to 1.
* It may also be used for character detection during normal reception,
* Mute mode inactive (for example, end of block detection in ModBus protocol).
* In this case, the whole received character (8-bit) is compared to the ADD[7:0]
* value and CMF flag is set on match)
* @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n
* CR2 ADDM7 LL_USART_ConfigNodeAddress
* @param USARTx USART Instance
* @param AddressLen This parameter can be one of the following values:
* @arg @ref LL_USART_ADDRESS_DETECT_4B
* @arg @ref LL_USART_ADDRESS_DETECT_7B
* @param NodeAddress 4 or 7 bit Address of the USART node.
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
{
MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
(uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
}
/**
* @brief Return 8 bit Address of the USART node as set in ADD field of CR2.
* @note If 4-bit Address Detection is selected in ADDM7,
* only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
* If 7-bit Address Detection is selected in ADDM7,
* only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
* @rmtoll CR2 ADD LL_USART_GetNodeAddress
* @param USARTx USART Instance
* @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
*/
__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
}
/**
* @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
* @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_ADDRESS_DETECT_4B
* @arg @ref LL_USART_ADDRESS_DETECT_7B
*/
__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
}
/**
* @brief Enable RTS HW Flow Control
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_RTSE);
}
/**
* @brief Disable RTS HW Flow Control
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
}
/**
* @brief Enable CTS HW Flow Control
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_CTSE);
}
/**
* @brief Disable CTS HW Flow Control
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
}
/**
* @brief Configure HW Flow Control mode (both CTS and RTS)
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n
* CR3 CTSE LL_USART_SetHWFlowCtrl
* @param USARTx USART Instance
* @param HardwareFlowControl This parameter can be one of the following values:
* @arg @ref LL_USART_HWCONTROL_NONE
* @arg @ref LL_USART_HWCONTROL_RTS
* @arg @ref LL_USART_HWCONTROL_CTS
* @arg @ref LL_USART_HWCONTROL_RTS_CTS
* @retval None
*/
__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
{
MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
}
/**
* @brief Return HW Flow Control configuration (both CTS and RTS)
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n
* CR3 CTSE LL_USART_GetHWFlowCtrl
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_HWCONTROL_NONE
* @arg @ref LL_USART_HWCONTROL_RTS
* @arg @ref LL_USART_HWCONTROL_CTS
* @arg @ref LL_USART_HWCONTROL_RTS_CTS
*/
__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
}
/**
* @brief Enable One bit sampling method
* @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
}
/**
* @brief Disable One bit sampling method
* @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
}
/**
* @brief Indicate if One bit sampling method is enabled
* @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
}
/**
* @brief Enable Overrun detection
* @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
}
/**
* @brief Disable Overrun detection
* @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
}
/**
* @brief Indicate if Overrun detection is enabled
* @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
}
/**
* @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_SetWKUPType
* @param USARTx USART Instance
* @param Type This parameter can be one of the following values:
* @arg @ref LL_USART_WAKEUP_ON_ADDRESS
* @arg @ref LL_USART_WAKEUP_ON_STARTBIT
* @arg @ref LL_USART_WAKEUP_ON_RXNE
* @retval None
*/
__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
{
MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
}
/**
* @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUS LL_USART_GetWKUPType
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_WAKEUP_ON_ADDRESS
* @arg @ref LL_USART_WAKEUP_ON_STARTBIT
* @arg @ref LL_USART_WAKEUP_ON_RXNE
*/
__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
}
/**
* @brief Configure USART BRR register for achieving expected Baud Rate value.
* @note Compute and set USARTDIV value in BRR Register (full BRR content)
* according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
* @note Peripheral clock and Baud rate values provided as function parameters should be valid
* (Baud rate value != 0)
* @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
* @rmtoll BRR BRR LL_USART_SetBaudRate
* @param USARTx USART Instance
* @param PeriphClk Peripheral Clock
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @param OverSampling This parameter can be one of the following values:
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
* @param BaudRate Baud Rate
* @retval None
*/
__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling,
uint32_t BaudRate)
{
uint32_t usartdiv;
uint32_t brrtemp;
if (PrescalerValue > LL_USART_PRESCALER_DIV256)
{
/* Do not overstep the size of USART_PRESCALER_TAB */
}
else if (BaudRate == 0U)
{
/* Can Not divide per 0 */
}
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
brrtemp = usartdiv & 0xFFF0U;
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
USARTx->BRR = brrtemp;
}
else
{
USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
}
}
/**
* @brief Return current Baud Rate value, according to USARTDIV present in BRR register
* (full BRR content), and to used Peripheral Clock and Oversampling mode values
* @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
* @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
* @rmtoll BRR BRR LL_USART_GetBaudRate
* @param USARTx USART Instance
* @param PeriphClk Peripheral Clock
* @param PrescalerValue This parameter can be one of the following values:
* @arg @ref LL_USART_PRESCALER_DIV1
* @arg @ref LL_USART_PRESCALER_DIV2
* @arg @ref LL_USART_PRESCALER_DIV4
* @arg @ref LL_USART_PRESCALER_DIV6
* @arg @ref LL_USART_PRESCALER_DIV8
* @arg @ref LL_USART_PRESCALER_DIV10
* @arg @ref LL_USART_PRESCALER_DIV12
* @arg @ref LL_USART_PRESCALER_DIV16
* @arg @ref LL_USART_PRESCALER_DIV32
* @arg @ref LL_USART_PRESCALER_DIV64
* @arg @ref LL_USART_PRESCALER_DIV128
* @arg @ref LL_USART_PRESCALER_DIV256
* @param OverSampling This parameter can be one of the following values:
* @arg @ref LL_USART_OVERSAMPLING_16
* @arg @ref LL_USART_OVERSAMPLING_8
* @retval Baud Rate
*/
__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
uint32_t OverSampling)
{
uint32_t usartdiv;
uint32_t brrresult = 0x0U;
uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
usartdiv = USARTx->BRR;
if (usartdiv == 0U)
{
/* Do not perform a division by 0 */
}
else if (OverSampling == LL_USART_OVERSAMPLING_8)
{
usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
if (usartdiv != 0U)
{
brrresult = (periphclkpresc * 2U) / usartdiv;
}
}
else
{
if ((usartdiv & 0xFFFFU) != 0U)
{
brrresult = periphclkpresc / usartdiv;
}
}
return (brrresult);
}
/**
* @brief Set Receiver Time Out Value (expressed in nb of bits duration)
* @rmtoll RTOR RTO LL_USART_SetRxTimeout
* @param USARTx USART Instance
* @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
{
MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
}
/**
* @brief Get Receiver Time Out Value (expressed in nb of bits duration)
* @rmtoll RTOR RTO LL_USART_GetRxTimeout
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
*/
__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
}
/**
* @brief Set Block Length value in reception
* @rmtoll RTOR BLEN LL_USART_SetBlockLength
* @param USARTx USART Instance
* @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
{
MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
}
/**
* @brief Get Block Length value in reception
* @rmtoll RTOR BLEN LL_USART_GetBlockLength
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
* @{
*/
/**
* @brief Enable IrDA mode
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_EnableIrda
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_IREN);
}
/**
* @brief Disable IrDA mode
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_DisableIrda
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
}
/**
* @brief Indicate if IrDA mode is enabled
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IREN LL_USART_IsEnabledIrda
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
}
/**
* @brief Configure IrDA Power Mode (Normal or Low Power)
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode
* @param USARTx USART Instance
* @param PowerMode This parameter can be one of the following values:
* @arg @ref LL_USART_IRDA_POWER_NORMAL
* @arg @ref LL_USART_IRDA_POWER_LOW
* @retval None
*/
__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
{
MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
}
/**
* @brief Retrieve IrDA Power Mode configuration (Normal or Low Power)
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_IRDA_POWER_NORMAL
* @arg @ref LL_USART_PHASE_2EDGE
*/
__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
}
/**
* @brief Set Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler
* @param USARTx USART Instance
* @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
* @brief Return Irda prescaler value, used for dividing the USART clock source
* to achieve the Irda Low Power frequency (8 bits value)
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler
* @param USARTx USART Instance
* @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
* @{
*/
/**
* @brief Enable Smartcard NACK transmission
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_NACK);
}
/**
* @brief Disable Smartcard NACK transmission
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
}
/**
* @brief Indicate if Smartcard NACK transmission is enabled
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
}
/**
* @brief Enable Smartcard mode
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_EnableSmartcard
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_SCEN);
}
/**
* @brief Disable Smartcard mode
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_DisableSmartcard
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
}
/**
* @brief Indicate if Smartcard mode is enabled
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
}
/**
* @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
* In transmission mode, it specifies the number of automatic retransmission retries, before
* generating a transmission error (FE bit set).
* In reception mode, it specifies the number or erroneous reception trials, before generating a
* reception error (RXNE and PE bits set)
* @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount
* @param USARTx USART Instance
* @param AutoRetryCount Value between Min_Data=0 and Max_Data=7
* @retval None
*/
__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
{
MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
}
/**
* @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount
* @param USARTx USART Instance
* @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
*/
__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
}
/**
* @brief Set Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler
* @param USARTx USART Instance
* @param PrescalerValue Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
{
MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
}
/**
* @brief Return Smartcard prescaler value, used for dividing the USART clock
* source to provide the SMARTCARD Clock (5 bits value)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler
* @param USARTx USART Instance
* @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
*/
__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
}
/**
* @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime
* @param USARTx USART Instance
* @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
{
MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
}
/**
* @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods
* (GT[7:0] bits : Guard time value)
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime
* @param USARTx USART Instance
* @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
*/
__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
* @{
*/
/**
* @brief Enable Single Wire Half-Duplex mode
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Disable Single Wire Half-Duplex mode
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Indicate if Single Wire Half-Duplex mode is enabled
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
* @{
*/
/**
* @brief Enable SPI Synchronous Slave mode
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_EnableSPISlave
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
}
/**
* @brief Disable SPI Synchronous Slave mode
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_DisableSPISlave
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
}
/**
* @brief Indicate if SPI Synchronous Slave mode is enabled
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
}
/**
* @brief Enable SPI Slave Selection using NSS input pin
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave Selection depends on NSS input pin
* (The slave is selected when NSS is low and deselected when NSS is high).
* @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
}
/**
* @brief Disable SPI Slave Selection using NSS input pin
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @note SPI Slave will be always selected and NSS input pin will be ignored.
* @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
}
/**
* @brief Indicate if SPI Slave Selection depends on NSS input pin
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
* @{
*/
/**
* @brief Set LIN Break Detection Length
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen
* @param USARTx USART Instance
* @param LINBDLength This parameter can be one of the following values:
* @arg @ref LL_USART_LINBREAK_DETECT_10B
* @arg @ref LL_USART_LINBREAK_DETECT_11B
* @retval None
*/
__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
{
MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
}
/**
* @brief Return LIN Break Detection Length
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_LINBREAK_DETECT_10B
* @arg @ref LL_USART_LINBREAK_DETECT_11B
*/
__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
}
/**
* @brief Enable LIN mode
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_EnableLIN
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_LINEN);
}
/**
* @brief Disable LIN mode
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_DisableLIN
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
}
/**
* @brief Indicate if LIN mode is enabled
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LINEN LL_USART_IsEnabledLIN
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
* @{
*/
/**
* @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime
* @param USARTx USART Instance
* @param Time Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
{
MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
}
/**
* @brief Return DEDT (Driver Enable De-Assertion Time)
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
}
/**
* @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime
* @param USARTx USART Instance
* @param Time Value between Min_Data=0 and Max_Data=31
* @retval None
*/
__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
{
MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
}
/**
* @brief Return DEAT (Driver Enable Assertion Time)
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime
* @param USARTx USART Instance
* @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
*/
__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
}
/**
* @brief Enable Driver Enable (DE) Mode
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_EnableDEMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_DEM);
}
/**
* @brief Disable Driver Enable (DE) Mode
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_DisableDEMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
}
/**
* @brief Indicate if Driver Enable (DE) Mode is enabled
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEM LL_USART_IsEnabledDEMode
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
}
/**
* @brief Select Driver Enable Polarity
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_SetDESignalPolarity
* @param USARTx USART Instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_USART_DE_POLARITY_HIGH
* @arg @ref LL_USART_DE_POLARITY_LOW
* @retval None
*/
__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
{
MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
}
/**
* @brief Return Driver Enable Polarity
* @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
* Driver Enable feature is supported by the USARTx instance.
* @rmtoll CR3 DEP LL_USART_GetDESignalPolarity
* @param USARTx USART Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_USART_DE_POLARITY_HIGH
* @arg @ref LL_USART_DE_POLARITY_LOW
*/
__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)
{
return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
}
/**
* @}
*/
/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
* @{
*/
/**
* @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
* @note In UART mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - CLKEN bit in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* @note Other remaining configurations items related to Asynchronous Mode
* (as Baud Rate, Word length, Parity, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n
* CR2 CLKEN LL_USART_ConfigAsyncMode\n
* CR3 SCEN LL_USART_ConfigAsyncMode\n
* CR3 IREN LL_USART_ConfigAsyncMode\n
* CR3 HDSEL LL_USART_ConfigAsyncMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
{
/* In Asynchronous mode, the following bits must be kept cleared:
- LINEN, CLKEN bits in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
}
/**
* @brief Perform basic configuration of USART for enabling use in Synchronous Mode
* @note In Synchronous mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the USART in Synchronous mode.
* @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
* Synchronous mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
* @note Other remaining configurations items related to Synchronous Mode
* (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n
* CR2 CLKEN LL_USART_ConfigSyncMode\n
* CR3 SCEN LL_USART_ConfigSyncMode\n
* CR3 IREN LL_USART_ConfigSyncMode\n
* CR3 HDSEL LL_USART_ConfigSyncMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
{
/* In Synchronous mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- SCEN, IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
/* set the UART/USART in Synchronous mode */
SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
}
/**
* @brief Perform basic configuration of USART for enabling use in LIN Mode
* @note In LIN mode, the following bits must be kept cleared:
* - STOP and CLKEN bits in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also set the UART/USART in LIN mode.
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
* @note Other remaining configurations items related to LIN Mode
* (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
* dedicated functions
* @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n
* CR2 STOP LL_USART_ConfigLINMode\n
* CR2 LINEN LL_USART_ConfigLINMode\n
* CR3 IREN LL_USART_ConfigLINMode\n
* CR3 SCEN LL_USART_ConfigLINMode\n
* CR3 HDSEL LL_USART_ConfigLINMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
{
/* In LIN mode, the following bits must be kept cleared:
- STOP and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
/* Set the UART/USART in LIN mode */
SET_BIT(USARTx->CR2, USART_CR2_LINEN);
}
/**
* @brief Perform basic configuration of USART for enabling use in Half Duplex Mode
* @note In Half Duplex mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - CLKEN bit in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* This function also sets the UART/USART in Half Duplex mode.
* @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
* Half-Duplex mode is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
* @note Other remaining configurations items related to Half Duplex Mode
* (as Baud Rate, Word length, Parity, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n
* CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n
* CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n
* CR3 SCEN LL_USART_ConfigHalfDuplexMode\n
* CR3 IREN LL_USART_ConfigHalfDuplexMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
{
/* In Half Duplex mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN and IREN bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
/* set the UART/USART in Half Duplex mode */
SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
}
/**
* @brief Perform basic configuration of USART for enabling use in Smartcard Mode
* @note In Smartcard mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also configures Stop bits to 1.5 bits and
* sets the USART in Smartcard mode (SCEN bit).
* Clock Output is also enabled (CLKEN).
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
* - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
* - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
* @note Other remaining configurations items related to Smartcard Mode
* (as Baud Rate, Word length, Parity, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n
* CR2 STOP LL_USART_ConfigSmartcardMode\n
* CR2 CLKEN LL_USART_ConfigSmartcardMode\n
* CR3 HDSEL LL_USART_ConfigSmartcardMode\n
* CR3 SCEN LL_USART_ConfigSmartcardMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
{
/* In Smartcard mode, the following bits must be kept cleared:
- LINEN bit in the USART_CR2 register,
- IREN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
/* Configure Stop bits to 1.5 bits */
/* Synchronous mode is activated by default */
SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
/* set the UART/USART in Smartcard mode */
SET_BIT(USARTx->CR3, USART_CR3_SCEN);
}
/**
* @brief Perform basic configuration of USART for enabling use in Irda Mode
* @note In IRDA mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - STOP and CLKEN bits in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* This function also sets the UART/USART in IRDA mode (IREN bit).
* @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
* IrDA feature is supported by the USARTx instance.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
* - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
* @note Other remaining configurations items related to Irda Mode
* (as Baud Rate, Word length, Power mode, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n
* CR2 CLKEN LL_USART_ConfigIrdaMode\n
* CR2 STOP LL_USART_ConfigIrdaMode\n
* CR3 SCEN LL_USART_ConfigIrdaMode\n
* CR3 HDSEL LL_USART_ConfigIrdaMode\n
* CR3 IREN LL_USART_ConfigIrdaMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
{
/* In IRDA mode, the following bits must be kept cleared:
- LINEN, STOP and CLKEN bits in the USART_CR2 register,
- SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
/* set the UART/USART in IRDA mode */
SET_BIT(USARTx->CR3, USART_CR3_IREN);
}
/**
* @brief Perform basic configuration of USART for enabling use in Multi processor Mode
* (several USARTs connected in a network, one of the USARTs can be the master,
* its TX output connected to the RX inputs of the other slaves USARTs).
* @note In MultiProcessor mode, the following bits must be kept cleared:
* - LINEN bit in the USART_CR2 register,
* - CLKEN bit in the USART_CR2 register,
* - SCEN bit in the USART_CR3 register,
* - IREN bit in the USART_CR3 register,
* - HDSEL bit in the USART_CR3 register.
* @note Call of this function is equivalent to following function call sequence :
* - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
* - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
* - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
* - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
* - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
* @note Other remaining configurations items related to Multi processor Mode
* (as Baud Rate, Wake Up Method, Node address, ...) should be set using
* dedicated functions
* @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n
* CR2 CLKEN LL_USART_ConfigMultiProcessMode\n
* CR3 SCEN LL_USART_ConfigMultiProcessMode\n
* CR3 HDSEL LL_USART_ConfigMultiProcessMode\n
* CR3 IREN LL_USART_ConfigMultiProcessMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
{
/* In Multi Processor mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- IREN, SCEN and HDSEL bits in the USART_CR3 register.
*/
CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
}
/**
* @}
*/
/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if the USART Parity Error Flag is set or not
* @rmtoll ISR PE LL_USART_IsActiveFlag_PE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Framing Error Flag is set or not
* @rmtoll ISR FE LL_USART_IsActiveFlag_FE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Noise error detected Flag is set or not
* @rmtoll ISR NE LL_USART_IsActiveFlag_NE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART OverRun Error Flag is set or not
* @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART IDLE line detected Flag is set or not
* @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE
/**
* @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Transmission Complete Flag is set or not
* @rmtoll ISR TC LL_USART_IsActiveFlag_TC
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF
/**
* @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART LIN Break Detection Flag is set or not
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART CTS interrupt Flag is set or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART CTS Flag is set or not
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Receiver Time Out Flag is set or not
* @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART End Of Block Flag is set or not
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
}
/**
* @brief Check if the SPI Slave Underrun error flag is set or not
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Auto-Baud Rate Error Flag is set or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Auto-Baud Rate Flag is set or not
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Busy Flag is set or not
* @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Character Match Flag is set or not
* @rmtoll ISR CMF LL_USART_IsActiveFlag_CM
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Send Break Flag is set or not
* @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Receive Wake Up from mute mode Flag is set or not
* @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Wake Up from stop mode Flag is set or not
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Transmit Enable Acknowledge Flag is set or not
* @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Receive Enable Acknowledge Flag is set or not
* @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART TX FIFO Empty Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART RX FIFO Full Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
}
/**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
* @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART TX FIFO Threshold Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART RX FIFO Threshold Flag is set or not
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
}
/**
* @brief Clear Parity Error Flag
* @rmtoll ICR PECF LL_USART_ClearFlag_PE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_PECF);
}
/**
* @brief Clear Framing Error Flag
* @rmtoll ICR FECF LL_USART_ClearFlag_FE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_FECF);
}
/**
* @brief Clear Noise Error detected Flag
* @rmtoll ICR NECF LL_USART_ClearFlag_NE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_NECF);
}
/**
* @brief Clear OverRun Error Flag
* @rmtoll ICR ORECF LL_USART_ClearFlag_ORE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
}
/**
* @brief Clear IDLE line detected Flag
* @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
}
/**
* @brief Clear TX FIFO Empty Flag
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
}
/**
* @brief Clear Transmission Complete Flag
* @rmtoll ICR TCCF LL_USART_ClearFlag_TC
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
}
/**
* @brief Clear Smartcard Transmission Complete Before Guard Time Flag
* @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
}
/**
* @brief Clear LIN Break Detection Flag
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
}
/**
* @brief Clear CTS Interrupt Flag
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
}
/**
* @brief Clear Receiver Time Out Flag
* @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
}
/**
* @brief Clear End Of Block Flag
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
}
/**
* @brief Clear SPI Slave Underrun Flag
* @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
* SPI Slave mode feature is supported by the USARTx instance.
* @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
}
/**
* @brief Clear Character Match Flag
* @rmtoll ICR CMCF LL_USART_ClearFlag_CM
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
}
/**
* @brief Clear Wake Up from stop mode Flag
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
{
WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable IDLE Interrupt
* @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE
/**
* @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
* @brief Enable Transmission Complete Interrupt
* @rmtoll CR1 TCIE LL_USART_EnableIT_TC
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF
/**
* @brief Enable TX Empty and TX FIFO Not Full Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
* @brief Enable Parity Error Interrupt
* @rmtoll CR1 PEIE LL_USART_EnableIT_PE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
}
/**
* @brief Enable Character Match Interrupt
* @rmtoll CR1 CMIE LL_USART_EnableIT_CM
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
}
/**
* @brief Enable Receiver Timeout Interrupt
* @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
}
/**
* @brief Enable End Of Block Interrupt
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
/**
* @brief Enable TX FIFO Empty Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Enable RX FIFO Full Interrupt
* @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
}
/**
* @brief Enable LIN Break Detection Interrupt
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
}
/**
* @brief Enable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
* 0: Interrupt is inhibited
* 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
* @rmtoll CR3 EIE LL_USART_EnableIT_ERROR
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Enable CTS Interrupt
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Enable Wake Up from Stop Mode Interrupt
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
/**
* @brief Enable TX FIFO Threshold Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
}
/**
* @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
/**
* @brief Enable RX FIFO Threshold Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
}
/**
* @brief Disable IDLE Interrupt
* @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
}
/* Legacy define */
#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE
/**
* @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
}
/**
* @brief Disable Transmission Complete Interrupt
* @rmtoll CR1 TCIE LL_USART_DisableIT_TC
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
}
/* Legacy define */
#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF
/**
* @brief Disable TX Empty and TX FIFO Not Full Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
}
/**
* @brief Disable Parity Error Interrupt
* @rmtoll CR1 PEIE LL_USART_DisableIT_PE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
}
/**
* @brief Disable Character Match Interrupt
* @rmtoll CR1 CMIE LL_USART_DisableIT_CM
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
}
/**
* @brief Disable Receiver Timeout Interrupt
* @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
}
/**
* @brief Disable End Of Block Interrupt
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
}
/**
* @brief Disable TX FIFO Empty Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
}
/**
* @brief Disable RX FIFO Full Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
}
/**
* @brief Disable LIN Break Detection Interrupt
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
}
/**
* @brief Disable Error Interrupt
* @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
* error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
* 0: Interrupt is inhibited
* 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
* @rmtoll CR3 EIE LL_USART_DisableIT_ERROR
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
}
/**
* @brief Disable CTS Interrupt
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
}
/**
* @brief Disable Wake Up from Stop Mode Interrupt
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
}
/**
* @brief Disable TX FIFO Threshold Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
}
/**
* @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
}
/**
* @brief Disable RX FIFO Threshold Interrupt
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
}
/**
* @brief Check if the USART IDLE Interrupt source is enabled or disabled.
* @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE
/**
* @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Transmission Complete Interrupt is enabled or disabled.
* @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
}
/* Legacy define */
#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF
/**
* @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Parity Error Interrupt is enabled or disabled.
* @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Character Match Interrupt is enabled or disabled.
* @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled.
* @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART End Of Block Interrupt is enabled or disabled.
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled.
* @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
* LIN feature is supported by the USARTx instance.
* @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Error Interrupt is enabled or disabled.
* @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART CTS Interrupt is enabled or disabled.
* @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
* Hardware Flow control feature is supported by the USARTx instance.
* @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
* @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
* Wake-up from Stop mode feature is supported by the USARTx instance.
* @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
}
/**
* @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
}
/**
* @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
* @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
* Smartcard feature is supported by the USARTx instance.
* @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
}
/**
* @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable DMA Mode for reception
* @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
}
/**
* @brief Disable DMA Mode for reception
* @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
}
/**
* @brief Check if DMA Mode is enabled for reception
* @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Mode for transmission
* @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
{
ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
}
/**
* @brief Disable DMA Mode for transmission
* @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
{
ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
}
/**
* @brief Check if DMA Mode is enabled for transmission
* @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Disabling on Reception Error
* @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->CR3, USART_CR3_DDRE);
}
/**
* @brief Disable DMA Disabling on Reception Error
* @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
{
CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
}
/**
* @brief Indicate if DMA Disabling on Reception Error is disabled
* @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr
* @param USARTx USART Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)
{
return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
}
/**
* @brief Get the data register address used for DMA transfer
* @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n
* @rmtoll TDR TDR LL_USART_DMA_GetRegAddr
* @param USARTx USART Instance
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
* @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)
{
uint32_t data_reg_addr;
if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
{
/* return address of TDR register */
data_reg_addr = (uint32_t) &(USARTx->TDR);
}
else
{
/* return address of RDR register */
data_reg_addr = (uint32_t) &(USARTx->RDR);
}
return data_reg_addr;
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Read Receiver Data register (Receive Data value, 8 bits)
* @rmtoll RDR RDR LL_USART_ReceiveData8
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)
{
return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
}
/**
* @brief Read Receiver Data register (Receive Data value, 9 bits)
* @rmtoll RDR RDR LL_USART_ReceiveData9
* @param USARTx USART Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x1FF
*/
__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)
{
return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
}
/**
* @brief Write in Transmitter Data Register (Transmit Data value, 8 bits)
* @rmtoll TDR TDR LL_USART_TransmitData8
* @param USARTx USART Instance
* @param Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
{
USARTx->TDR = Value;
}
/**
* @brief Write in Transmitter Data Register (Transmit Data value, 9 bits)
* @rmtoll TDR TDR LL_USART_TransmitData9
* @param USARTx USART Instance
* @param Value between Min_Data=0x00 and Max_Data=0x1FF
* @retval None
*/
__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
{
USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
}
/**
* @}
*/
/** @defgroup USART_LL_EF_Execution Execution
* @{
*/
/**
* @brief Request an Automatic Baud Rate measurement on next received data frame
* @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
* Auto Baud Rate detection feature is supported by the USARTx instance.
* @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
}
/**
* @brief Request Break sending
* @rmtoll RQR SBKRQ LL_USART_RequestBreakSending
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
}
/**
* @brief Put USART in mute mode and set the RWU flag
* @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
}
/**
* @brief Request a Receive Data and FIFO flush
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @note Allows to discard the received data without reading them, and avoid an overrun
* condition.
* @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
}
/**
* @brief Request a Transmit data and FIFO flush
* @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
* FIFO mode feature is supported by the USARTx instance.
* @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush
* @param USARTx USART Instance
* @retval None
*/
__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
{
SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);
ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);
void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_USART_H */
| 174,201 | C | 38.573376 | 214 | 0.639336 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_pcd_ex.h
* @author MCD Application Team
* @brief Header file of PCD HAL Extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_PCD_EX_H
#define STM32G4xx_HAL_PCD_EX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined (USB)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup PCDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
uint16_t ep_kind, uint32_t pmaadress);
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32G4xx_HAL_PCD_EX_H */
| 2,413 | C | 26.123595 | 81 | 0.510568 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_rtc_ex.h
* @author MCD Application Team
* @brief Header file of RTC HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_RTC_EX_H
#define STM32G4xx_HAL_RTC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup RTCEx RTCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
* @{
*/
/** @defgroup RTCEx_Tamper_structure_definition RTCEx Tamper structure definition
* @{
*/
typedef struct
{
uint32_t Tamper; /*!< Specifies the Tamper Pin.
This parameter can be a value of @ref RTCEx_Tamper_Pins */
uint32_t Trigger; /*!< Specifies the Tamper Trigger.
This parameter can be a value of @ref RTCEx_Tamper_Trigger */
uint32_t NoErase; /*!< Specifies the Tamper no erase mode.
This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */
uint32_t MaskFlag; /*!< Specifies the Tamper Flag masking.
This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */
uint32_t Filter; /*!< Specifies the TAMP Filter Tamper.
This parameter can be a value of @ref RTCEx_Tamper_Filter */
uint32_t SamplingFrequency; /*!< Specifies the sampling frequency.
This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies */
uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration .
This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration */
uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp .
This parameter can be a value of @ref RTCEx_Tamper_Pull_UP */
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
} RTC_TamperTypeDef;
/**
* @}
*/
/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition
* @{
*/
typedef struct
{
uint32_t IntTamper; /*!< Specifies the Internal Tamper Pin.
This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */
uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection.
This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */
} RTC_InternalTamperTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
* @{
*/
/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTCEx Time Stamp Edges definition
* @{
*/
#define RTC_TIMESTAMPEDGE_RISING 0x00000000U
#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE
/**
* @}
*/
/** @defgroup RTCEx_TimeStamp_Pin_Selections RTCEx TimeStamp Pin Selection
* @{
*/
#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U
/**
* @}
*/
/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions
* @{
*/
#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U
#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0
#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1
#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)
#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2
#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)
/**
* @}
*/
/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth calib period Definitions
* @{
*/
#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibration
period is 32s, else 2exp20 RTCCLK pulses */
#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibration
period is 16s, else 2exp19 RTCCLK pulses */
#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibration
period is 8s, else 2exp18 RTCCLK pulses */
/**
* @}
*/
/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth calib Plus pulses Definitions
* @{
*/
#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added
during a X -second window = Y - CALM[8:0]
with Y = 512, 256, 128 when X = 32, 16, 8 */
#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited
during a 32-second window = CALM[8:0] */
/**
* @}
*/
/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions
* @{
*/
#define RTC_CALIBOUTPUT_512HZ 0x00000000U
#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL
/**
* @}
*/
/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTCEx Add 1 Second Parameter Definitions
* @{
*/
#define RTC_SHIFTADD1S_RESET 0x00000000U
#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S
/**
* @}
*/
/** @defgroup RTCEx_Tamper_Pins RTCEx Tamper Pins Definition
* @{
*/
#define RTC_TAMPER_1 TAMP_CR1_TAMP1E
#define RTC_TAMPER_2 TAMP_CR1_TAMP2E
#if (RTC_TAMP_NB == 3)
#define RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3 )
#elif (RTC_TAMP_NB == 8)
#define RTC_TAMPER_3 TAMP_CR1_TAMP3E
#define RTC_TAMPER_4 TAMP_CR1_TAMP4E
#define RTC_TAMPER_5 TAMP_CR1_TAMP5E
#define RTC_TAMPER_6 TAMP_CR1_TAMP6E
#define RTC_TAMPER_7 TAMP_CR1_TAMP7E
#define RTC_TAMPER_8 TAMP_CR1_TAMP8E
#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2 |\
RTC_TAMPER_3 | RTC_TAMPER_4 |\
RTC_TAMPER_5 | RTC_TAMPER_6 |\
RTC_TAMPER_7 | RTC_TAMPER_8 )
#else
#define RTC_TAMPER_ALL (RTC_TAMPER_1 | RTC_TAMPER_2)
#endif /* RTC_TAMP_NB */
/**
* @}
*/
/** @defgroup RTCEx_Internal_Tamper_Pins RTCEx Internal Tamper Pins Definition
* @{
*/
#if defined (RTC_TAMP_INT_1_SUPPORT)
#define RTC_INT_TAMPER_1 TAMP_CR1_ITAMP1E
#else
#define RTC_INT_TAMPER_1 0U
#endif /* RTC_TAMP_INT_1_SUPPORT */
#if defined (RTC_TAMP_INT_2_SUPPORT)
#define RTC_INT_TAMPER_2 TAMP_CR1_ITAMP2E
#else
#define RTC_INT_TAMPER_2 0U
#endif /* RTC_TAMP_INT_2_SUPPORT */
#define RTC_INT_TAMPER_3 TAMP_CR1_ITAMP3E
#define RTC_INT_TAMPER_4 TAMP_CR1_ITAMP4E
#define RTC_INT_TAMPER_5 TAMP_CR1_ITAMP5E
#if defined (RTC_TAMP_INT_6_SUPPORT)
#define RTC_INT_TAMPER_6 TAMP_CR1_ITAMP6E
#else
#define RTC_INT_TAMPER_6 0U
#endif /* RTC_TAMP_INT_6_SUPPORT */
#if defined (RTC_TAMP_INT_7_SUPPORT)
#define RTC_INT_TAMPER_7 TAMP_CR1_ITAMP7E
#else
#define RTC_INT_TAMPER_7 0U
#endif /* RTC_TAMP_INT_7_SUPPORT */
#if defined (RTC_TAMP_INT_8_SUPPORT)
#define RTC_INT_TAMPER_8 TAMP_CR1_ITAMP8E
#else
#define RTC_INT_TAMPER_8 0U
#endif /* RTC_TAMP_INT_8_SUPPORT */
#define RTC_INT_TAMPER_ALL ( RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\
RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\
RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\
RTC_INT_TAMPER_7 | RTC_INT_TAMPER_8 )
/**
* @}
*/
/** @defgroup RTCEx_Tamper_Trigger RTCEx Tamper Trigger
* @{
*/
#define RTC_TAMPERTRIGGER_RISINGEDGE 0x00U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x01U /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */
#define RTC_TAMPERTRIGGER_LOWLEVEL 0x02U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
#define RTC_TAMPERTRIGGER_HIGHLEVEL 0x03U /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */
/**
* @}
*/
/** @defgroup RTCEx_Tamper_MaskFlag RTCEx Tamper MaskFlag
* @{
*/
#define RTC_TAMPERMASK_FLAG_DISABLE 0x00U
#define RTC_TAMPERMASK_FLAG_ENABLE 0x01U
/**
* @}
*/
/** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp
* @{
*/
#define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00U
#define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01U
/**
* @}
*/
/** @defgroup RTCEx_Tamper_Filter RTCEx Tamper Filter
* @{
*/
#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
#define RTC_TAMPERFILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2
consecutive samples at the active level */
#define RTC_TAMPERFILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4
consecutive samples at the active level */
#define RTC_TAMPERFILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8
consecutive samples at the active level */
/**
* @}
*/
/** @defgroup RTCEx_Tamper_Sampling_Frequencies RTCEx Tamper Sampling Frequencies
* @{
*/
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 32768 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 16384 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 8192 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 4096 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 2048 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 1024 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 512 */
#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \
TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled
with a frequency = RTCCLK / 256 */
/**
* @}
*/
/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration RTCEx Tamper Pin Precharge Duration
* @{
*/
#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before
sampling during 1 RTCCLK cycle */
#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before
sampling during 2 RTCCLK cycles */
#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before
sampling during 4 RTCCLK cycles */
#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK (TAMP_FLTCR_TAMPPRCH_0 | TAMP_FLTCR_TAMPPRCH_1) /*!< Tamper pins are pre-charged before
sampling during 8 RTCCLK cycles */
/**
* @}
*/
/** @defgroup RTCEx_Tamper_Pull_UP RTCEx Tamper Pull UP
* @{
*/
#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */
#define RTC_TAMPER_PULLUP_DISABLE TAMP_FLTCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */
/**
* @}
*/
/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection RTCEx Tamper TimeStamp On Tamper Detection
* @{
*/
#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */
#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_CR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */
/**
* @}
*/
/** @defgroup RTCEx_Internal_Tamper_Interrupt RTCEx Internal Tamper Interrupt
* @{
*/
#define RTC_IT_TAMP_1 TAMP_IER_TAMP1IE /*!< Tamper 1 Interrupt */
#define RTC_IT_TAMP_2 TAMP_IER_TAMP2IE /*!< Tamper 2 Interrupt */
#if (RTC_TAMP_NB == 3)
#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */
#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 | RTC_IT_TAMP_3 )
#elif (RTC_TAMP_NB == 8)
#define RTC_IT_TAMP_3 TAMP_IER_TAMP3IE /*!< Tamper 3 Interrupt */
#define RTC_IT_TAMP_4 TAMP_IER_TAMP4IE /*!< Tamper 4 Interrupt */
#define RTC_IT_TAMP_5 TAMP_IER_TAMP5IE /*!< Tamper 5 Interrupt */
#define RTC_IT_TAMP_6 TAMP_IER_TAMP6IE /*!< Tamper 6 Interrupt */
#define RTC_IT_TAMP_7 TAMP_IER_TAMP7IE /*!< Tamper 7 Interrupt */
#define RTC_IT_TAMP_8 TAMP_IER_TAMP8IE /*!< Tamper 8 Interrupt */
#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2 |\
RTC_IT_TAMP_3 | RTC_IT_TAMP_4 |\
RTC_IT_TAMP_5 | RTC_IT_TAMP_6 |\
RTC_IT_TAMP_7 | RTC_IT_TAMP_8 )
#else
#define RTC_IT_TAMP_ALL (RTC_IT_TAMP_1 | RTC_IT_TAMP_2)
#endif /* RTC_TAMP_NB */
#if defined (RTC_TAMP_INT_1_SUPPORT)
#define RTC_IT_INT_TAMP_1 TAMP_IER_ITAMP1IE /*!< Tamper 1 internal Interrupt */
#else
#define RTC_IT_INT_TAMP_1 0U
#endif /* RTC_TAMP_INT_1_SUPPORT */
#if defined (RTC_TAMP_INT_2_SUPPORT)
#define RTC_IT_INT_TAMP_2 TAMP_IER_ITAMP2IE /*!< Tamper 2 internal Interrupt */
#else
#define RTC_IT_INT_TAMP_2 0U
#endif /* RTC_TAMP_INT_2_SUPPORT */
#define RTC_IT_INT_TAMP_3 TAMP_IER_ITAMP3IE /*!< Tamper 3 internal Interrupt */
#define RTC_IT_INT_TAMP_4 TAMP_IER_ITAMP4IE /*!< Tamper 4 internal Interrupt */
#define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE /*!< Tamper 5 internal Interrupt */
#if defined (RTC_TAMP_INT_6_SUPPORT)
#define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE /*!< Tamper 6 internal Interrupt */
#else
#define RTC_IT_INT_TAMP_6 0U
#endif /* RTC_TAMP_INT_6_SUPPORT */
#if defined (RTC_TAMP_INT_7_SUPPORT)
#define RTC_IT_INT_TAMP_7 TAMP_IER_ITAMP7IE /*!< Tamper 7 internal Interrupt */
#else
#define RTC_IT_INT_TAMP_7 0U
#endif /* RTC_TAMP_INT_7_SUPPORT */
#if defined (RTC_TAMP_INT_8_SUPPORT)
#define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE /*!< Tamper 8 internal Interrupt */
#else
#define RTC_IT_INT_TAMP_8 0U
#endif /* RTC_TAMP_INT_8_SUPPORT */
#define RTC_IT_INT_TAMP_ALL (RTC_IT_INT_TAMP_1 | RTC_IT_INT_TAMP_2 |\
RTC_IT_INT_TAMP_3 | RTC_IT_INT_TAMP_4 |\
RTC_IT_INT_TAMP_5 | RTC_IT_INT_TAMP_6 |\
RTC_IT_INT_TAMP_7 | RTC_IT_INT_TAMP_8 )
/**
* @}
*/
/** @defgroup RTCEx_Flags RTCEx Flags
* @{
*/
#define RTC_FLAG_TAMP_1 TAMP_SR_TAMP1F
#define RTC_FLAG_TAMP_2 TAMP_SR_TAMP2F
#if (RTC_TAMP_NB == 3)
#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F
#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3)
#elif (RTC_TAMP_NB == 8)
#define RTC_FLAG_TAMP_3 TAMP_SR_TAMP3F
#define RTC_FLAG_TAMP_4 TAMP_SR_TAMP4F
#define RTC_FLAG_TAMP_5 TAMP_SR_TAMP5F
#define RTC_FLAG_TAMP_6 TAMP_SR_TAMP6F
#define RTC_FLAG_TAMP_7 TAMP_SR_TAMP7F
#define RTC_FLAG_TAMP_8 TAMP_SR_TAMP8F
#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2 | RTC_FLAG_TAMP_3 |\
RTC_FLAG_TAMP_4 | RTC_FLAG_TAMP_5 |\
RTC_FLAG_TAMP_6 | RTC_FLAG_TAMP_7 | RTC_FLAG_TAMP_8)
#else
#define RTC_FLAG_TAMP_ALL (RTC_FLAG_TAMP_1 | RTC_FLAG_TAMP_2)
#endif /* RTC_TAMP_NB */
#if defined (RTC_TAMP_INT_1_SUPPORT)
#define RTC_FLAG_INT_TAMP_1 TAMP_SR_ITAMP1F /*!< Tamper 1 Interrupt flag */
#else
#define RTC_FLAG_INT_TAMP_1 0U
#endif /* RTC_TAMP_INT_1_SUPPORT */
#if defined (RTC_TAMP_INT_2_SUPPORT)
#define RTC_FLAG_INT_TAMP_2 TAMP_SR_ITAMP2F /*!< Tamper 2 Interrupt flag */
#else
#define RTC_FLAG_INT_TAMP_2 0U
#endif /* RTC_TAMP_INT_2_SUPPORT */
#define RTC_FLAG_INT_TAMP_3 TAMP_SR_ITAMP3F /*!< Tamper 3 Interrupt flag */
#define RTC_FLAG_INT_TAMP_4 TAMP_SR_ITAMP4F /*!< Tamper 4 Interrupt flag */
#define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F /*!< Tamper 5 Interrupt flag */
#if defined (RTC_TAMP_INT_6_SUPPORT)
#define RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F /*!< Tamper 6 Interrupt flag */
#else
#define RTC_FLAG_INT_TAMP_6 0U
#endif /* RTC_TAMP_INT_6_SUPPORT */
#if defined (RTC_TAMP_INT_7_SUPPORT)
#define RTC_FLAG_INT_TAMP_7 TAMP_SR_ITAMP7F /*!< Tamper 7 Interrupt flag */
#else
#define RTC_FLAG_INT_TAMP_7 0U
#endif /* RTC_TAMP_INT_7_SUPPORT */
#if defined (RTC_TAMP_INT_8_SUPPORT)
#define RTC_FLAG_INT_TAMP_8 TAMP_SR_ITAMP8F /*!< Tamper 8 Interrupt flag */
#else
#define RTC_FLAG_INT_TAMP_8 0U
#endif /* RTC_TAMP_INT_8_SUPPORT */
#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP_1 | RTC_FLAG_INT_TAMP_2 |\
RTC_FLAG_INT_TAMP_3 | RTC_FLAG_INT_TAMP_4 |\
RTC_FLAG_INT_TAMP_5 | RTC_FLAG_INT_TAMP_6 |\
RTC_FLAG_INT_TAMP_7 | RTC_FLAG_INT_TAMP_8)
/**
* @}
*/
/** @defgroup RTCEx_Backup_Registers RTCEx Backup Registers Definition
* @{
*/
#define RTC_BKP_NUMBER RTC_BACKUP_NB
#if (RTC_BACKUP_NB == 5)
#define RTC_BKP_DR0 0x00000000U
#define RTC_BKP_DR1 0x00000001U
#define RTC_BKP_DR2 0x00000002U
#define RTC_BKP_DR3 0x00000003U
#define RTC_BKP_DR4 0x00000004U
#elif (RTC_BACKUP_NB == 16)
#define RTC_BKP_DR0 0x00U
#define RTC_BKP_DR1 0x01U
#define RTC_BKP_DR2 0x02U
#define RTC_BKP_DR3 0x03U
#define RTC_BKP_DR4 0x04U
#define RTC_BKP_DR5 0x05U
#define RTC_BKP_DR6 0x06U
#define RTC_BKP_DR7 0x07U
#define RTC_BKP_DR8 0x08U
#define RTC_BKP_DR9 0x09U
#define RTC_BKP_DR10 0x0AU
#define RTC_BKP_DR11 0x0BU
#define RTC_BKP_DR12 0x0CU
#define RTC_BKP_DR13 0x0DU
#define RTC_BKP_DR14 0x0EU
#define RTC_BKP_DR15 0x0FU
#elif (RTC_BACKUP_NB == 32)
#define RTC_BKP_DR0 0x00U
#define RTC_BKP_DR1 0x01U
#define RTC_BKP_DR2 0x02U
#define RTC_BKP_DR3 0x03U
#define RTC_BKP_DR4 0x04U
#define RTC_BKP_DR5 0x05U
#define RTC_BKP_DR6 0x06U
#define RTC_BKP_DR7 0x07U
#define RTC_BKP_DR8 0x08U
#define RTC_BKP_DR9 0x09U
#define RTC_BKP_DR10 0x0AU
#define RTC_BKP_DR11 0x0BU
#define RTC_BKP_DR12 0x0CU
#define RTC_BKP_DR13 0x0DU
#define RTC_BKP_DR14 0x0EU
#define RTC_BKP_DR15 0x0FU
#define RTC_BKP_DR16 0x10U
#define RTC_BKP_DR17 0x11U
#define RTC_BKP_DR18 0x12U
#define RTC_BKP_DR19 0x13U
#define RTC_BKP_DR20 0x14U
#define RTC_BKP_DR21 0x15U
#define RTC_BKP_DR22 0x16U
#define RTC_BKP_DR23 0x17U
#define RTC_BKP_DR24 0x18U
#define RTC_BKP_DR25 0x19U
#define RTC_BKP_DR26 0x1AU
#define RTC_BKP_DR27 0x1BU
#define RTC_BKP_DR28 0x1CU
#define RTC_BKP_DR29 0x1DU
#define RTC_BKP_DR30 0x1EU
#define RTC_BKP_DR31 0x1FU
#else
#error "no RTC Backup Registers Definition"
#endif /* RTC_BKP_NUMBER */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
* @{
*/
/** @brief Clear the specified RTC pending flag.
* @param __HANDLE__ specifies the RTC Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref RTC_CLEAR_ITSF Clear Internal Time-stamp flag
* @arg @ref RTC_CLEAR_TSOVF Clear Time-stamp overflow flag
* @arg @ref RTC_CLEAR_TSF Clear Time-stamp flag
* @arg @ref RTC_CLEAR_WUTF Clear Wakeup timer flag
* @arg @ref RTC_CLEAR_ALRBF Clear Alarm B flag
* @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag
* @retval None
*/
#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR = (__FLAG__))
/** @brief Check whether the specified RTC flag is set or not.
* @param __HANDLE__ specifies the RTC Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref RTC_FLAG_RECALPF Recalibration pending Flag
* @arg @ref RTC_FLAG_INITF Initialization flag
* @arg @ref RTC_FLAG_RSF Registers synchronization flag
* @arg @ref RTC_FLAG_INITS Initialization status flag
* @arg @ref RTC_FLAG_SHPF Shift operation pending flag
* @arg @ref RTC_FLAG_WUTWF Wakeup timer write flag
* @arg @ref RTC_FLAG_ALRBWF Alarm B write flag
* @arg @ref RTC_FLAG_ALRAWF Alarm A write flag
* @arg @ref RTC_FLAG_ITSF Internal Time-stamp flag
* @arg @ref RTC_FLAG_TSOVF Time-stamp overflow flag
* @arg @ref RTC_FLAG_TSF Time-stamp flag
* @arg @ref RTC_FLAG_WUTF Wakeup timer flag
* @arg @ref RTC_FLAG_ALRBF Alarm B flag
* @arg @ref RTC_FLAG_ALRAF Alarm A flag
* @retval None
*/
#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? ((__HANDLE__)->Instance->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \
((__HANDLE__)->Instance->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))
/* ---------------------------------WAKEUPTIMER---------------------------------*/
/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer
* @{
*/
/**
* @brief Enable the RTC WakeUp Timer peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
/**
* @brief Disable the RTC WakeUp Timer peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
/**
* @brief Enable the RTC WakeUpTimer interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.
* This parameter can be:
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the RTC WakeUpTimer interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.
* This parameter can be:
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
* This parameter can be:
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)\
& ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL)
/**
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
* This parameter can be:
* @arg @ref RTC_IT_WUT WakeUpTimer interrupt
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR)\
& (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
/**
* @brief Get the selected RTC WakeUpTimers flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not.
* This parameter can be:
* @arg @ref RTC_FLAG_WUTF
* @arg @ref RTC_FLAG_WUTWF
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
/**
* @brief Clear the RTC Wake Up timers pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear.
* This parameter can be:
* @arg @ref RTC_FLAG_WUTF
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_WUTF))
/* WAKE-UP TIMER EXTI */
/* ------------------ */
/**
* @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_FALLING_IT() (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Clear the interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Clear the interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Enable event on the RTC WakeUp Timer associated Exti line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable event on the RTC WakeUp Timer associated Exti line.
* @retval None.
*/
#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @}
*/
/* ---------------------------------TIMESTAMP---------------------------------*/
/** @defgroup RTCEx_Timestamp RTC Timestamp
* @{
*/
/**
* @brief Enable the RTC TimeStamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
/**
* @brief Disable the RTC TimeStamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
/**
* @brief Enable the RTC TimeStamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.
* This parameter can be:
* @arg @ref RTC_IT_TS TimeStamp interrupt
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the RTC TimeStamp interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.
* This parameter can be:
* @arg @ref RTC_IT_TS TimeStamp interrupt
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
* This parameter can be:
* @arg @ref RTC_IT_TS TimeStamp interrupt
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)\
& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
/**
* @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
* This parameter can be:
* @arg @ref RTC_IT_TS TimeStamp interrupt
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR)\
& (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
/**
* @brief Get the selected RTC TimeStamps flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not.
* This parameter can be:
* @arg @ref RTC_FLAG_TSF
* @arg @ref RTC_FLAG_TSOVF
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
/**
* @brief Clear the RTC Time Stamps pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC TimeStamp Flag to clear.
* This parameter can be:
* @arg @ref RTC_FLAG_TSF
* @arg @ref RTC_FLAG_TSOVF
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), (__FLAG__)))
/* TIMESTAMP TIMER EXTI */
/* -------------------- */
/**
* @brief Enable interrupt on the RTC Timestamp associated Exti line.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
/**
* @brief Disable interrupt on the RTC Timestamp associated Exti line.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
/**
* @brief set the rising edge for interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
/**
* @brief set the falling edge for interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
/**
* @brief Clear the interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
/**
* @brief Clear the interrupt on the RTC Timestamp associated Exti line.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR1 = RTC_EXTI_LINE_TIMESTAMP_EVENT)
/**
* @brief Enable event on the RTC Timestamp associated Exti line.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT)
/**
* @brief Disable event on the RTC Timestamp associated Exti line.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT))
/**
* @brief Enable the RTC internal TimeStamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))
/**
* @brief Disable the RTC internal TimeStamp peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))
/**
* @brief Get the selected RTC Internal Time Stamps flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.
* This parameter can be:
* @arg @ref RTC_FLAG_ITSF
* @retval None
*/
#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__),(__FLAG__)))
/**
* @brief Clear the RTC Internal Time Stamps pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.
* This parameter can be:
* @arg @ref RTC_FLAG_ITSF
* @retval None
*/
#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_CLEAR_FLAG((__HANDLE__), RTC_CLEAR_ITSF))
/**
* @brief Enable the RTC TimeStamp on Tamper detection.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPTS))
/**
* @brief Disable the RTC TimeStamp on Tamper detection.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPTS))
/**
* @brief Enable the RTC Tamper detection output.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))
/**
* @brief Disable the RTC Tamper detection output.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))
/**
* @}
*/
/* ------------------------------Calibration----------------------------------*/
/** @defgroup RTCEx_Calibration RTC Calibration
* @{
*/
/**
* @brief Enable the RTC calibration output.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
/**
* @brief Disable the calibration output.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
/**
* @brief Enable the clock reference detection.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
/**
* @brief Disable the clock reference detection.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
/**
* @brief Get the selected RTC shift operations flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
* This parameter can be:
* @arg @ref RTC_FLAG_SHPF
* @retval None
*/
#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
/**
* @}
*/
/* ------------------------------Tamper----------------------------------*/
/** @defgroup RTCEx_Tamper RTCEx tamper
* @{
*/
/**
* @brief Enable the TAMP Tamper input detection.
* @param __HANDLE__ specifies the RTC handle.
* @param __TAMPER__ specifies the RTC Tamper source to be enabled.
* This parameter can be any combination of the following values:
* @arg RTC_TAMPER_ALL: All tampers
* @arg RTC_TAMPER_1: Tamper1
* @arg RTC_TAMPER_2: Tamper2
* @retval None
*/
#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__))
/**
* @brief Disable the TAMP Tamper input detection.
* @param __HANDLE__ specifies the RTC handle.
* @param __TAMPER__ specifies the RTC Tamper sources to be enabled.
* This parameter can be any combination of the following values:
* @arg RTC_TAMPER_ALL: All tampers
* @arg RTC_TAMPER_1: Tamper1
* @arg RTC_TAMPER_2: Tamper2
*/
#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__))
/**************************************************************************************************/
/**
* @brief Enable the TAMP Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP_ALL: All tampers interrupts
* @arg RTC_IT_TAMP_1: Tamper1 interrupt
* @arg RTC_IT_TAMP_2: Tamper2 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__))
/**
* @brief Disable the TAMP Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP_ALL: All tampers interrupts
* @arg RTC_IT_TAMP_1: Tamper1 interrupt
* @arg RTC_IT_TAMP_2: Tamper2 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__))
/**************************************************************************************************/
/**
* @brief Check whether the specified TAMP Tamper interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be:
* @arg RTC_IT_TAMP_ALL: All tampers interrupts
* @arg RTC_IT_TAMP_1: Tamper1 interrupt
* @arg RTC_IT_TAMP_2: Tamper2 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR)\
& (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
/**
* @brief Check whether the specified TAMP Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
* This parameter can be:
* @arg RTC_IT_TAMP_ALL: All tampers interrupts
* @arg RTC_IT_TAMP_1: Tamper1 interrupt
* @arg RTC_IT_TAMP_2: Tamper2 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER)\
& (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)
/**
* @brief Get the selected TAMP Tampers flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
* This parameter can be:
* @arg RTC_FLAG_TAMP_ALL: All tampers flag
* @arg RTC_FLAG_TAMP_1: Tamper1 flag
* @arg RTC_FLAG_TAMP_2: Tamper2 flag
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((TAMP->SR) & (__FLAG__)) != 0UL)
/**
* @brief Clear the TAMP Tampers pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
* @arg RTC_FLAG_TAMP_ALL: All tampers flag
* @arg RTC_FLAG_TAMP_1: Tamper1 flag
* @arg RTC_FLAG_TAMP_2: Tamper2 flag
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((TAMP->SCR) = (__FLAG__))
/**
* @brief Enable interrupt on the RTC Tamper associated Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
/**
* @brief Disable interrupt on the RTC Tamper associated Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
/**
* @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
/**
* @brief Enable interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
/**
* @brief Clear the interrupt on the RTC WakeUp Timer associated Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_TAMPER_EVENT)
/**
* @brief Enable event on the RTC Tamper associated Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT)
/**
* @brief Disable event on the RTC Tamper associated Exti line.
* @retval None
*/
#define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
* @{
*/
/* RTC TimeStamp functions *****************************************/
/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions
* @{
*/
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp,
RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/* RTC Wake-up functions ******************************************************/
/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions
* @{
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
*/
/* Extended Control functions ************************************************/
/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod,
uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);
HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/* Extended RTC features functions *******************************************/
/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions
* @{
*/
void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
/**
* @}
*/
/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions
* @{
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);
HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout);
HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);
HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);
HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);
void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
#if (RTC_TAMP_NB == 3)
void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
#endif /* RTC_TAMP_NB */
#ifdef RTC_TAMP_INT_1_SUPPORT
void HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);
#endif /* RTC_TAMP_INT_1_SUPPORT */
#ifdef RTC_TAMP_INT_2_SUPPORT
void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc);
#endif /* RTC_TAMP_INT_2_SUPPORT */
void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);
void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);
#ifdef RTC_TAMP_INT_6_SUPPORT
void HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);
#endif /* RTC_TAMP_INT_6_SUPPORT */
#ifdef RTC_TAMP_INT_7_SUPPORT
void HAL_RTCEx_InternalTamper7EventCallback(RTC_HandleTypeDef *hrtc);
#endif /* RTC_TAMP_INT_7_SUPPORT */
/**
* @}
*/
/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions
* @{
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTCEx_Private_Constants RTCEx Private Constants
* @{
*/
#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR1_IM17 /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define RTC_EXTI_LINE_TIMESTAMP_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper/Time Stamp/CSS_LSE events */
#define RTC_EXTI_LINE_TAMPER_EVENT EXTI_IMR1_IM19 /*!< External interrupt line 19 Connected to the RTC tamper/Time Stamp/CSS_LSE events */
#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR1_IM20 /*!< External interrupt line 20 Connected to the RTC Wakeup event */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RTCEx_Private_Macros RTCEx Private Macros
* @{
*/
/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters
* @{
*/
#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))
#define IS_RTC_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(MODE) (((MODE) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \
((MODE) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \
((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT)
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)
#define IS_RTC_LOW_POWER_CALIB(LPCAL) (((LPCAL) == RTC_LPCAL_SET) || \
((LPCAL) == RTC_LPCAL_RESET))
#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & RTC_TAMPER_ALL) != 0x00U) && \
(((__TAMPER__) & ~RTC_TAMPER_ALL) == 0x00U))
#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__) ((((__INT_TAMPER__) & RTC_INT_TAMPER_ALL) != 0x00U) && \
(((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))
#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))
#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \
((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))
#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \
((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))
#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \
((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \
((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \
((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))
#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \
((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \
((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))
#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
#define IS_RTC_BKP(__BKP__) ((__BKP__) < RTC_BKP_NUMBER)
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
((SEL) == RTC_SHIFTADD1S_SET))
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_RTC_EX_H */
| 60,006 | C | 42.357659 | 169 | 0.549462 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_sai.h | /**
******************************************************************************
* @file stm32g4xx_hal_sai.h
* @author MCD Application Team
* @brief Header file of SAI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SAI_H
#define STM32G4xx_HAL_SAI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SAI
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SAI_Exported_Types SAI Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */
HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */
HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */
HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */
HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */
} HAL_SAI_StateTypeDef;
/**
* @brief SAI Callback prototype
*/
typedef void (*SAIcallback)(void);
/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition
* @brief SAI PDM Init structure definition
* @{
*/
typedef struct
{
FunctionalState Activation; /*!< Enable/disable PDM interface */
uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used.
This parameter must be a number between Min_Data = 1 and Max_Data = 3. */
uint32_t ClockEnable; /*!< Specifies which clock must be enabled.
This parameter can be a values combination of @ref SAI_PDM_ClockEnable */
} SAI_PdmInitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition
* @brief SAI Init Structure definition
* @{
*/
typedef struct
{
uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode.
This parameter can be a value of @ref SAI_Block_Mode */
uint32_t Synchro; /*!< Specifies SAI Block synchronization
This parameter can be a value of @ref SAI_Block_Synchronization */
uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common
for BlockA and BlockB
This parameter can be a value of @ref SAI_Block_SyncExt
@note If both audio blocks of same SAI are used, this parameter has
to be set to the same value for each audio block */
uint32_t MckOutput; /*!< Specifies whether master clock output will be generated or not.
This parameter can be a value of @ref SAI_Block_MckOutput */
uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven.
This parameter can be a value of @ref SAI_Block_Output_Drive
@note This value has to be set before enabling the audio block
but after the audio block configuration. */
uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not.
This parameter can be a value of @ref SAI_Block_NoDivider
@note If bit NODIV in the SAI_xCR1 register is cleared, the frame length
should be aligned to a number equal to a power of 2, from 8 to 256.
If bit NODIV in the SAI_xCR1 register is set, the frame length can
take any of the values from 8 to 256. */
uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold.
This parameter can be a value of @ref SAI_Block_Fifo_Threshold */
uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling.
This parameter can be a value of @ref SAI_Audio_Frequency */
uint32_t Mckdiv; /*!< Specifies the master clock divider.
This parameter must be a number between Min_Data = 0 and Max_Data = 63.
@note This parameter is used only if AudioFrequency is set to
SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */
uint32_t MckOverSampling; /*!< Specifies the master clock oversampling.
This parameter can be a value of @ref SAI_Block_Mck_OverSampling */
uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected.
This parameter can be a value of @ref SAI_Mono_Stereo_Mode */
uint32_t CompandingMode; /*!< Specifies the companding mode type.
This parameter can be a value of @ref SAI_Block_Companding_Mode */
uint32_t TriState; /*!< Specifies the companding mode type.
This parameter can be a value of @ref SAI_TRIState_Management */
SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */
/* This part of the structure is automatically filled if your are using the high level initialisation
function HAL_SAI_InitProtocol */
uint32_t Protocol; /*!< Specifies the SAI Block protocol.
This parameter can be a value of @ref SAI_Block_Protocol */
uint32_t DataSize; /*!< Specifies the SAI Block data size.
This parameter can be a value of @ref SAI_Block_Data_Size */
uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */
uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity.
This parameter can be a value of @ref SAI_Block_Clock_Strobing */
} SAI_InitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
* @brief SAI Frame Init structure definition
* @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
* @{
*/
typedef struct
{
uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.
This parameter must be a number between Min_Data = 8 and Max_Data = 256.
@note If master clock MCLK_x pin is declared as an output, the frame length
should be aligned to a number equal to power of 2 in order to keep
in an audio frame, an integer number of MCLK pulses by bit Clock. */
uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length.
This Parameter specifies the length in number of bit clock (SCK + 1)
of the active level of FS signal in audio frame.
This parameter must be a number between Min_Data = 1 and Max_Data = 128 */
uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition.
This parameter can be a value of @ref SAI_Block_FS_Definition */
uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity.
This parameter can be a value of @ref SAI_Block_FS_Polarity */
uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset.
This parameter can be a value of @ref SAI_Block_FS_Offset */
} SAI_FrameInitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
* @brief SAI Block Slot Init Structure definition
* @note For SPDIF protocol, these parameters are not used (set by hardware).
* @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
* @{
*/
typedef struct
{
uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot.
This parameter must be a number between Min_Data = 0 and Max_Data = 24 */
uint32_t SlotSize; /*!< Specifies the Slot Size.
This parameter can be a value of @ref SAI_Block_Slot_Size */
uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame.
This parameter must be a number between Min_Data = 1 and Max_Data = 16 */
uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated.
This parameter can be a value of @ref SAI_Block_Slot_Active */
} SAI_SlotInitTypeDef;
/**
* @}
*/
/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition
* @brief SAI handle Structure definition
* @{
*/
typedef struct __SAI_HandleTypeDef
{
SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */
SAI_InitTypeDef Init; /*!< SAI communication parameters */
SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */
SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */
uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */
uint16_t XferSize; /*!< SAI transfer size */
uint16_t XferCount; /*!< SAI transfer counter */
DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */
SAIcallback mutecallback; /*!< SAI mute callback */
void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */
HAL_LockTypeDef Lock; /*!< SAI locking object */
__IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */
__IO uint32_t ErrorCode; /*!< SAI Error code */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */
void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */
void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */
void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */
void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */
void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */
void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
} SAI_HandleTypeDef;
/**
* @}
*/
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
/**
* @brief SAI callback ID enumeration definition
*/
typedef enum
{
HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */
HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */
HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */
HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */
HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */
HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */
HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */
} HAL_SAI_CallbackIDTypeDef;
/**
* @brief SAI callback pointer definition
*/
typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SAI_Exported_Constants SAI Exported Constants
* @{
*/
/** @defgroup SAI_Error_Code SAI Error Code
* @{
*/
#define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */
#define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */
#define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */
#define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */
#define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */
#define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */
#define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */
#define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
#define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup SAI_Block_SyncExt SAI External synchronisation
* @{
*/
#define SAI_SYNCEXT_DISABLE 0U
#define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U
#define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U
/**
* @}
*/
/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output
* @{
*/
#define SAI_MCK_OUTPUT_DISABLE 0x00000000U
#define SAI_MCK_OUTPUT_ENABLE SAI_xCR1_MCKEN
/**
* @}
*/
/** @defgroup SAI_Protocol SAI Supported protocol
* @{
*/
#define SAI_I2S_STANDARD 0U
#define SAI_I2S_MSBJUSTIFIED 1U
#define SAI_I2S_LSBJUSTIFIED 2U
#define SAI_PCM_LONG 3U
#define SAI_PCM_SHORT 4U
/**
* @}
*/
/** @defgroup SAI_Protocol_DataSize SAI protocol data size
* @{
*/
#define SAI_PROTOCOL_DATASIZE_16BIT 0U
#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U
#define SAI_PROTOCOL_DATASIZE_24BIT 2U
#define SAI_PROTOCOL_DATASIZE_32BIT 3U
/**
* @}
*/
/** @defgroup SAI_Audio_Frequency SAI Audio Frequency
* @{
*/
#define SAI_AUDIO_FREQUENCY_192K 192000U
#define SAI_AUDIO_FREQUENCY_96K 96000U
#define SAI_AUDIO_FREQUENCY_48K 48000U
#define SAI_AUDIO_FREQUENCY_44K 44100U
#define SAI_AUDIO_FREQUENCY_32K 32000U
#define SAI_AUDIO_FREQUENCY_22K 22050U
#define SAI_AUDIO_FREQUENCY_16K 16000U
#define SAI_AUDIO_FREQUENCY_11K 11025U
#define SAI_AUDIO_FREQUENCY_8K 8000U
#define SAI_AUDIO_FREQUENCY_MCKDIV 0U
/**
* @}
*/
/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling
* @{
*/
#define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U
#define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR
/**
* @}
*/
/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable
* @{
*/
#define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1
#define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2
/**
* @}
*/
/** @defgroup SAI_Block_Mode SAI Block Mode
* @{
*/
#define SAI_MODEMASTER_TX 0x00000000U
#define SAI_MODEMASTER_RX SAI_xCR1_MODE_0
#define SAI_MODESLAVE_TX SAI_xCR1_MODE_1
#define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)
/**
* @}
*/
/** @defgroup SAI_Block_Protocol SAI Block Protocol
* @{
*/
#define SAI_FREE_PROTOCOL 0x00000000U
#define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0
#define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1
/**
* @}
*/
/** @defgroup SAI_Block_Data_Size SAI Block Data Size
* @{
*/
#define SAI_DATASIZE_8 SAI_xCR1_DS_1
#define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
#define SAI_DATASIZE_16 SAI_xCR1_DS_2
#define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)
#define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)
#define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)
/**
* @}
*/
/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission
* @{
*/
#define SAI_FIRSTBIT_MSB 0x00000000U
#define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST
/**
* @}
*/
/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing
* @{
*/
#define SAI_CLOCKSTROBING_FALLINGEDGE 0U
#define SAI_CLOCKSTROBING_RISINGEDGE 1U
/**
* @}
*/
/** @defgroup SAI_Block_Synchronization SAI Block Synchronization
* @{
*/
#define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */
#define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */
#define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */
#define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */
/**
* @}
*/
/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive
* @{
*/
#define SAI_OUTPUTDRIVE_DISABLE 0x00000000U
#define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV
/**
* @}
*/
/** @defgroup SAI_Block_NoDivider SAI Block NoDivider
* @{
*/
#define SAI_MASTERDIVIDER_ENABLE 0x00000000U
#define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV
/**
* @}
*/
/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition
* @{
*/
#define SAI_FS_STARTFRAME 0x00000000U
#define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF
/**
* @}
*/
/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity
* @{
*/
#define SAI_FS_ACTIVE_LOW 0x00000000U
#define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL
/**
* @}
*/
/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset
* @{
*/
#define SAI_FS_FIRSTBIT 0x00000000U
#define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size
* @{
*/
#define SAI_SLOTSIZE_DATASIZE 0x00000000U
#define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0
#define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1
/**
* @}
*/
/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active
* @{
*/
#define SAI_SLOT_NOTACTIVE 0x00000000U
#define SAI_SLOTACTIVE_0 0x00000001U
#define SAI_SLOTACTIVE_1 0x00000002U
#define SAI_SLOTACTIVE_2 0x00000004U
#define SAI_SLOTACTIVE_3 0x00000008U
#define SAI_SLOTACTIVE_4 0x00000010U
#define SAI_SLOTACTIVE_5 0x00000020U
#define SAI_SLOTACTIVE_6 0x00000040U
#define SAI_SLOTACTIVE_7 0x00000080U
#define SAI_SLOTACTIVE_8 0x00000100U
#define SAI_SLOTACTIVE_9 0x00000200U
#define SAI_SLOTACTIVE_10 0x00000400U
#define SAI_SLOTACTIVE_11 0x00000800U
#define SAI_SLOTACTIVE_12 0x00001000U
#define SAI_SLOTACTIVE_13 0x00002000U
#define SAI_SLOTACTIVE_14 0x00004000U
#define SAI_SLOTACTIVE_15 0x00008000U
#define SAI_SLOTACTIVE_ALL 0x0000FFFFU
/**
* @}
*/
/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode
* @{
*/
#define SAI_STEREOMODE 0x00000000U
#define SAI_MONOMODE SAI_xCR1_MONO
/**
* @}
*/
/** @defgroup SAI_TRIState_Management SAI TRIState Management
* @{
*/
#define SAI_OUTPUT_NOTRELEASED 0x00000000U
#define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS
/**
* @}
*/
/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold
* @{
*/
#define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U
#define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0
#define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1
#define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)
#define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2
/**
* @}
*/
/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode
* @{
*/
#define SAI_NOCOMPANDING 0x00000000U
#define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1
#define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)
#define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)
#define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)
/**
* @}
*/
/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value
* @{
*/
#define SAI_ZERO_VALUE 0x00000000U
#define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL
/**
* @}
*/
/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition
* @{
*/
#define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE
#define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE
#define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE
#define SAI_IT_FREQ SAI_xIMR_FREQIE
#define SAI_IT_CNRDY SAI_xIMR_CNRDYIE
#define SAI_IT_AFSDET SAI_xIMR_AFSDETIE
#define SAI_IT_LFSDET SAI_xIMR_LFSDETIE
/**
* @}
*/
/** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition
* @{
*/
#define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR
#define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET
#define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG
#define SAI_FLAG_FREQ SAI_xSR_FREQ
#define SAI_FLAG_CNRDY SAI_xSR_CNRDY
#define SAI_FLAG_AFSDET SAI_xSR_AFSDET
#define SAI_FLAG_LFSDET SAI_xSR_LFSDET
/**
* @}
*/
/** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level
* @{
*/
#define SAI_FIFOSTATUS_EMPTY 0x00000000U
#define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U
#define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U
#define SAI_FIFOSTATUS_HALFFULL 0x00030000U
#define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U
#define SAI_FIFOSTATUS_FULL 0x00050000U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SAI_Exported_Macros SAI Exported Macros
* @brief macros to handle interrupts and specific configurations
* @{
*/
/** @brief Reset SAI handle state.
* @param __HANDLE__ specifies the SAI Handle.
* @retval None
*/
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SAI_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/** @brief Enable the specified SAI interrupts.
* @param __HANDLE__ specifies the SAI Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
* @arg SAI_IT_FREQ: FIFO request interrupt enable
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
* @retval None
*/
#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))
/** @brief Disable the specified SAI interrupts.
* @param __HANDLE__ specifies the SAI Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
* @arg SAI_IT_FREQ: FIFO request interrupt enable
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
* @retval None
*/
#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))
/** @brief Check whether the specified SAI interrupt source is enabled or not.
* @param __HANDLE__ specifies the SAI Handle.
* @param __INTERRUPT__ specifies the SAI interrupt source to check.
* This parameter can be one of the following values:
* @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable
* @arg SAI_IT_MUTEDET: Mute detection interrupt enable
* @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable
* @arg SAI_IT_FREQ: FIFO request interrupt enable
* @arg SAI_IT_CNRDY: Codec not ready interrupt enable
* @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable
* @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SAI flag is set or not.
* @param __HANDLE__ specifies the SAI Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SAI_FLAG_OVRUDR: Overrun underrun flag.
* @arg SAI_FLAG_MUTEDET: Mute detection flag.
* @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.
* @arg SAI_FLAG_FREQ: FIFO request flag.
* @arg SAI_FLAG_CNRDY: Codec not ready flag.
* @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.
* @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified SAI pending flag.
* @param __HANDLE__ specifies the SAI Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg SAI_FLAG_OVRUDR: Clear Overrun underrun
* @arg SAI_FLAG_MUTEDET: Clear Mute detection
* @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration
* @arg SAI_FLAG_FREQ: Clear FIFO request
* @arg SAI_FLAG_CNRDY: Clear Codec not ready
* @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection
* @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection
*
* @retval None
*/
#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))
/** @brief Enable SAI.
* @param __HANDLE__ specifies the SAI Handle.
* @retval None
*/
#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN)
/** @brief Disable SAI.
* @param __HANDLE__ specifies the SAI Handle.
* @retval None
*/
#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
/**
* @}
*/
/* Include SAI HAL Extension module */
#include "stm32g4xx_hal_sai_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SAI_Exported_Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup SAI_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);
void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);
void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);
#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)
/* SAI callbacks register/unregister functions ********************************/
HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai,
HAL_SAI_CallbackIDTypeDef CallbackID,
pSAI_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai,
HAL_SAI_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_SAI_REGISTER_CALLBACKS */
/**
* @}
*/
/* I/O operation functions ***************************************************/
/** @addtogroup SAI_Exported_Functions_Group2
* @{
*/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);
/* Abort function */
HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);
/* Mute management */
HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);
HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);
HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);
HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);
/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);
void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);
void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);
/**
* @}
*/
/** @addtogroup SAI_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);
uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SAI_Private_Macros SAI Private Macros
* @{
*/
#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\
((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\
((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))
#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\
((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\
((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\
((PROTOCOL) == SAI_PCM_LONG) ||\
((PROTOCOL) == SAI_PCM_SHORT))
#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\
((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\
((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\
((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))
#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \
((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))
#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \
((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))
#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U))
#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \
(((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))
#define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \
((MODE) == SAI_MODEMASTER_RX) || \
((MODE) == SAI_MODESLAVE_TX) || \
((MODE) == SAI_MODESLAVE_RX))
#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \
((PROTOCOL) == SAI_AC97_PROTOCOL) || \
((PROTOCOL) == SAI_SPDIF_PROTOCOL))
#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \
((DATASIZE) == SAI_DATASIZE_10) || \
((DATASIZE) == SAI_DATASIZE_16) || \
((DATASIZE) == SAI_DATASIZE_20) || \
((DATASIZE) == SAI_DATASIZE_24) || \
((DATASIZE) == SAI_DATASIZE_32))
#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \
((BIT) == SAI_FIRSTBIT_LSB))
#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \
((SYNCHRO) == SAI_SYNCHRONOUS) || \
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
((VALUE) == SAI_MCK_OUTPUT_DISABLE))
#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \
((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))
#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \
((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))
#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)
#define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \
((VALUE) == SAI_LAST_SENT_VALUE))
#define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \
((MODE) == SAI_ULAW_1CPL_COMPANDING) || \
((MODE) == SAI_ALAW_1CPL_COMPANDING) || \
((MODE) == SAI_ULAW_2CPL_COMPANDING) || \
((MODE) == SAI_ALAW_2CPL_COMPANDING))
#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \
((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \
((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \
((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \
((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))
#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\
((STATE) == SAI_OUTPUT_RELEASED))
#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\
((MODE) == SAI_STEREOMODE))
#define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL)
#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))
#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \
((SIZE) == SAI_SLOTSIZE_16B) || \
((SIZE) == SAI_SLOTSIZE_32B))
#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)
#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \
((OFFSET) == SAI_FS_BEFOREFIRSTBIT))
#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \
((POLARITY) == SAI_FS_ACTIVE_HIGH))
#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \
((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))
#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)
#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))
#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup SAI_Private_Functions SAI Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SAI_H */
| 39,292 | C | 39.760373 | 121 | 0.571109 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_pcd.h | /**
******************************************************************************
* @file stm32g4xx_hal_pcd.h
* @author MCD Application Team
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_PCD_H
#define STM32G4xx_HAL_PCD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_ll_usb.h"
#if defined (USB)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup PCD
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PCD_Exported_Types PCD Exported Types
* @{
*/
/**
* @brief PCD State structure definition
*/
typedef enum
{
HAL_PCD_STATE_RESET = 0x00,
HAL_PCD_STATE_READY = 0x01,
HAL_PCD_STATE_ERROR = 0x02,
HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
} PCD_StateTypeDef;
/* Device LPM suspend state */
typedef enum
{
LPM_L0 = 0x00, /* on */
LPM_L1 = 0x01, /* LPM L1 sleep */
LPM_L2 = 0x02, /* suspend */
LPM_L3 = 0x03, /* off */
} PCD_LPM_StateTypeDef;
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00, /* on */
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
} PCD_LPM_MsgTypeDef;
typedef enum
{
PCD_BCD_ERROR = 0xFF,
PCD_BCD_CONTACT_DETECTION = 0xFE,
PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD,
PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC,
PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB,
PCD_BCD_DISCOVERY_COMPLETED = 0x00,
} PCD_BCD_MsgTypeDef;
typedef USB_TypeDef PCD_TypeDef;
typedef USB_CfgTypeDef PCD_InitTypeDef;
typedef USB_EPTypeDef PCD_EPTypeDef;
/**
* @brief PCD Handle Structure definition
*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
typedef struct __PCD_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
__IO uint8_t USB_Address; /*!< USB Address */
PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
__IO uint32_t ErrorCode; /*!< PCD Error code */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */
uint32_t BESL;
uint32_t lpm_active; /*!< Enable or disable the Link Power Management .
This parameter can be set to ENABLE or DISABLE */
uint32_t battery_charging_active; /*!< Enable or disable Battery charging.
This parameter can be set to ENABLE or DISABLE */
void *pData; /*!< Pointer to upper stack Handler */
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */
void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */
void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */
void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */
void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */
void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */
void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */
void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */
void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */
void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */
void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */
void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */
void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */
void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */
void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
} PCD_HandleTypeDef;
/**
* @}
*/
/* Include PCD HAL Extended module */
#include "stm32g4xx_hal_pcd_ex.h"
/* Exported constants --------------------------------------------------------*/
/** @defgroup PCD_Exported_Constants PCD Exported Constants
* @{
*/
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_FULL USBD_FS_SPEED
/**
* @}
*/
/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
#define PCD_PHY_ULPI 1U
#define PCD_PHY_EMBEDDED 2U
#define PCD_PHY_UTMI 3U
/**
* @}
*/
/** @defgroup PCD_Error_Code_definition PCD Error Code definition
* @brief PCD Error Code definition
* @{
*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PCD_Exported_Macros PCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)
#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\
& (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\
&= (uint16_t)(~(__INTERRUPT__)))
#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR1 |= USB_WAKEUP_EXTI_LINE
#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR1 &= ~(USB_WAKEUP_EXTI_LINE)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCD_Exported_Functions PCD Exported Functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition
* @brief HAL USB OTG PCD Callback ID enumeration definition
* @{
*/
typedef enum
{
HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */
HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */
HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */
HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */
HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */
HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */
HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */
HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */
HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */
} HAL_PCD_CallbackIDTypeDef;
/**
* @}
*/
/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition
* @brief HAL USB OTG PCD Callback pointer definition
* @{
*/
typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */
typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */
typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */
typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */
typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */
typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */
typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */
/**
* @}
*/
HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID,
pPCD_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd,
HAL_PCD_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataOutStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd,
pPCD_DataInStageCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoOutIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd,
pPCD_IsoInIncpltCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd,
pPCD_BcdCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd,
pPCD_LpmCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
/**
* @}
*/
/* I/O operation functions ***************************************************/
/* Non-Blocking mode: Interrupt */
/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint16_t ep_mps, uint8_t ep_type);
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
uint8_t *pBuf, uint32_t len);
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
* @{
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PCD_Private_Constants PCD Private Constants
* @{
*/
/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt
* @{
*/
#define USB_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */
/**
* @}
*/
/** @defgroup PCD_EP0_MPS PCD EP0 MPS
* @{
*/
#define PCD_EP0MPS_64 EP_MPS_64
#define PCD_EP0MPS_32 EP_MPS_32
#define PCD_EP0MPS_16 EP_MPS_16
#define PCD_EP0MPS_08 EP_MPS_8
/**
* @}
*/
/** @defgroup PCD_ENDP PCD ENDP
* @{
*/
#define PCD_ENDP0 0U
#define PCD_ENDP1 1U
#define PCD_ENDP2 2U
#define PCD_ENDP3 3U
#define PCD_ENDP4 4U
#define PCD_ENDP5 5U
#define PCD_ENDP6 6U
#define PCD_ENDP7 7U
/**
* @}
*/
/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind
* @{
*/
#define PCD_SNG_BUF 0U
#define PCD_DBL_BUF 1U
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
*/
/******************** Bit definition for USB_COUNTn_RX register *************/
#define USB_CNTRX_NBLK_MSK (0x1FU << 10)
#define USB_CNTRX_BLSIZE (0x1U << 15)
/* SetENDPOINT */
#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)\
(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue))
/* GetENDPOINT */
#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)))
/* ENDPOINT transfer */
#define USB_EP0StartXfer USB_EPStartXfer
/**
* @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wType Endpoint Type.
* @retval None
*/
#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum))\
& USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX)))
/**
* @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval Endpoint Type
*/
#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
/**
* @brief free buffer used from the application realizing it to the line
* toggles bit SW_BUF in the double buffered endpoint register
* @param USBx USB device.
* @param bEpNum, bDir
* @retval None
*/
#define PCD_FREE_USER_BUFFER(USBx, bEpNum, bDir) \
do { \
if ((bDir) == 0U) \
{ \
/* OUT double buffered endpoint */ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
else if ((bDir) == 1U) \
{ \
/* IN double buffered endpoint */ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0)
/**
* @brief sets the status for tx transfer (bits STAT_TX[1:0]).
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TX_STATUS */
/**
* @brief sets the status for rx transfer (bits STAT_TX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wState new state
* @retval None
*/
#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wState))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_RX_STATUS */
/**
* @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wStaterx new state.
* @param wStatetx new state.
* @retval None
*/
#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \
/* toggle first bit ? */ \
if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \
{ \
_wRegVal ^= USB_EPRX_DTOG2; \
} \
/* toggle first bit ? */ \
if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG1; \
} \
/* toggle second bit ? */ \
if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \
{ \
_wRegVal ^= USB_EPTX_DTOG2; \
} \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_TXRX_STATUS */
/**
* @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
* /STAT_RX[1:0])
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval status
*/
#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
/**
* @brief sets directly the VALID tx/rx-status into the endpoint register
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
/**
* @brief checks stall condition in an endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval TRUE = endpoint in stall condition.
*/
#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL)
#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL)
/**
* @brief set & clear EP_KIND bit.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \
} while(0) /* PCD_SET_EP_KIND */
#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_EP_KIND */
/**
* @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Sets/clears directly EP_KIND bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_SET_BULK_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum))
#define PCD_CLEAR_BULK_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
/**
* @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \
} while(0) /* PCD_CLEAR_RX_EP_CTR */
#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \
} while(0) /* PCD_CLEAR_TX_EP_CTR */
/**
* @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \
} while(0) /* PCD_RX_DTOG */
#define PCD_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wEPVal; \
\
_wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \
} while(0) /* PCD_TX_DTOG */
/**
* @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\
{ \
PCD_RX_DTOG((USBx), (bEpNum)); \
} \
} while(0) /* PCD_CLEAR_RX_DTOG */
#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \
\
if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\
{ \
PCD_TX_DTOG((USBx), (bEpNum)); \
} \
} while(0) /* PCD_CLEAR_TX_DTOG */
/**
* @brief Sets address in an endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param bAddr Address.
* @retval None
*/
#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \
do { \
uint16_t _wRegVal; \
\
_wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \
\
PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \
} while(0) /* PCD_SET_EP_ADDRESS */
/**
* @brief Gets address in an endpoint register.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE\
+ ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U)))
/**
* @brief sets address of the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wAddr address to be set (must be word aligned).
* @retval None
*/
#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_TX_ADDRESS */
#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \
do { \
__IO uint16_t *_wRegVal; \
uint32_t _wRegBase = (uint32_t)USBx; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \
*_wRegVal = ((wAddr) >> 1) << 1; \
} while(0) /* PCD_SET_EP_RX_ADDRESS */
/**
* @brief Gets address of the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval address of the buffer.
*/
#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
/**
* @brief Sets counter of rx buffer with no. of blocks.
* @param pdwReg Register pointer
* @param wCount Counter.
* @param wNBlocks no. of Blocks.
* @retval None
*/
#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 5; \
if (((wCount) & 0x1fU) == 0U) \
{ \
(wNBlocks)--; \
} \
*(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \
} while(0) /* PCD_CALC_BLK32 */
#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \
do { \
(wNBlocks) = (wCount) >> 1; \
if (((wCount) & 0x1U) != 0U) \
{ \
(wNBlocks)++; \
} \
*(pdwReg) = (uint16_t)((wNBlocks) << 10); \
} while(0) /* PCD_CALC_BLK2 */
#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \
do { \
uint32_t wNBlocks; \
\
if ((wCount) > 62U) \
{ \
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
} \
else \
{ \
if ((wCount) == 0U) \
{ \
*(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \
*(pdwReg) |= USB_CNTRX_BLSIZE; \
} \
else \
{ \
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
} \
} \
} while(0) /* PCD_SET_EP_CNT_RX_REG */
#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *pdwReg; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \
} while(0)
/**
* @brief sets counter for the tx/rx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wCount Counter value.
* @retval None
*/
#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \
*_wRegVal = (uint16_t)(wCount); \
} while(0)
#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \
do { \
uint32_t _wRegBase = (uint32_t)(USBx); \
__IO uint16_t *_wRegVal; \
\
_wRegBase += (uint32_t)(USBx)->BTABLE; \
_wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \
} while(0)
/**
* @brief gets counter of the tx buffer.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval Counter value
*/
#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU)
#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU)
/**
* @brief Sets buffer 0/1 address in a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wBuf0Addr buffer 0 address.
* @retval Counter value
*/
#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \
do { \
PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \
} while(0) /* PCD_SET_EP_DBUF0_ADDR */
#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \
do { \
PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF1_ADDR */
/**
* @brief Sets addresses in a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param wBuf0Addr: buffer 0 address.
* @param wBuf1Addr = buffer 1 address.
* @retval None
*/
#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \
do { \
PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \
PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \
} while(0) /* PCD_SET_EP_DBUF_ADDR */
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
/**
* @brief Gets buffer 0/1 address of a double buffer endpoint.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @param bDir endpoint dir EP_DBUF_OUT = OUT
* EP_DBUF_IN = IN
* @param wCount: Counter value
* @retval None
*/
#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \
do { \
if ((bDir) == 0U) \
/* OUT endpoint */ \
{ \
PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \
} \
else \
{ \
if ((bDir) == 1U) \
{ \
/* IN endpoint */ \
PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \
} \
} \
} while(0) /* SetEPDblBuf0Count*/
#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \
do { \
uint32_t _wBase = (uint32_t)(USBx); \
__IO uint16_t *_wEPRegVal; \
\
if ((bDir) == 0U) \
{ \
/* OUT endpoint */ \
PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \
} \
else \
{ \
if ((bDir) == 1U) \
{ \
/* IN endpoint */ \
_wBase += (uint32_t)(USBx)->BTABLE; \
_wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \
*_wEPRegVal = (uint16_t)(wCount); \
} \
} \
} while(0) /* SetEPDblBuf1Count */
#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \
do { \
PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
} while(0) /* PCD_SET_EP_DBUF_CNT */
/**
* @brief Gets buffer 0/1 rx/tx counter for double buffering.
* @param USBx USB peripheral instance register address.
* @param bEpNum Endpoint Number.
* @retval None
*/
#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (USB) */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_PCD_H */
| 35,515 | C | 34.374502 | 155 | 0.568661 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_gpio.h | /**
******************************************************************************
* @file stm32g4xx_ll_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_GPIO_H
#define STM32G4xx_LL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG)
/** @defgroup GPIO_LL GPIO
* @{
*/
/** MISRA C:2012 deviation rule has been granted for following rules:
* Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..]
* which may be out of array bounds [..,UNKNOWN] in following APIs:
* LL_GPIO_GetAFPin_0_7
* LL_GPIO_SetAFPin_0_7
* LL_GPIO_SetAFPin_8_15
* LL_GPIO_GetAFPin_8_15
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures
* @{
*/
/**
* @brief LL GPIO Init Structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_LL_EC_PIN */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_MODE.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_SPEED.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/
uint32_t OutputType; /*!< Specifies the operating output type for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/
uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_PULL.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/
uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins.
This parameter can be a value of @ref GPIO_LL_EC_AF.
GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/
} LL_GPIO_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_LL_EC_PIN PIN
* @{
*/
#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */
#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */
#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */
#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */
#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */
#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */
#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */
#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */
#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */
#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */
#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */
#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */
#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */
#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */
#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */
#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */
#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \
GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \
GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \
GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \
GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \
GPIO_BSRR_BS15) /*!< Select all pins */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_MODE Mode
* @{
*/
#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */
#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */
#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */
#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_OUTPUT Output Type
* @{
*/
#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */
#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_SPEED Output Speed
* @{
*/
#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */
#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */
#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */
#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */
/**
* @}
*/
#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW
#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM
#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH
#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH
/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down
* @{
*/
#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */
#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */
#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */
/**
* @}
*/
/** @defgroup GPIO_LL_EC_AF Alternate Function
* @{
*/
#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */
#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */
#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */
#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */
#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */
#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */
#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */
#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */
#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */
#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */
#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */
#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */
#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */
#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */
#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */
#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros
* @{
*/
/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in GPIO register
* @param __INSTANCE__ GPIO Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration
* @{
*/
/**
* @brief Configure gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_SetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
{
MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U)), (Mode << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio mode for a dedicated pin on dedicated port.
* @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll MODER MODEy LL_GPIO_GetPinMode
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_MODE_INPUT
* @arg @ref LL_GPIO_MODE_OUTPUT
* @arg @ref LL_GPIO_MODE_ALTERNATE
* @arg @ref LL_GPIO_MODE_ANALOG
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->MODER,
(GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @param OutputType This parameter can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)
{
MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));
}
/**
* @brief Return gpio output type for several pins on dedicated port.
* @note Output type as to be set when gpio pin is in output or
* alternate modes. Possible type are Push-pull or Open-drain.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_OUTPUT_PUSHPULL
* @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin));
}
/**
* @brief Configure gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Speed This parameter can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed)
{
MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U)),
(Speed << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio speed for a dedicated pin on dedicated port.
* @note I/O speed can be Low, Medium, Fast or High speed.
* @note Warning: only one pin can be passed as parameter.
* @note Refer to datasheet for frequency specifications and the power
* supply and load conditions for each speed.
* @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_SPEED_FREQ_LOW
* @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
* @arg @ref LL_GPIO_SPEED_FREQ_HIGH
* @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->OSPEEDR,
(GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Pull This parameter can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)
{
MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U)), (Pull << (POSITION_VAL(Pin) * 2U)));
}
/**
* @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port
* @note Warning: only one pin can be passed as parameter.
* @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_PULL_NO
* @arg @ref LL_GPIO_PULL_UP
* @arg @ref LL_GPIO_PULL_DOWN
*/
__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->PUPDR,
(GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U)),
(Alternate << (POSITION_VAL(Pin) * 4U)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.
* @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[0],
(GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
}
/**
* @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @note Warning: only one pin can be passed as parameter.
* @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @param Alternate This parameter can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)
{
MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U)),
(Alternate << (POSITION_VAL(Pin >> 8U) * 4U)));
}
/**
* @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.
* @note Possible values are from AF0 to AF15 depending on target.
* @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15
* @param GPIOx GPIO Port
* @param Pin This parameter can be one of the following values:
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_GPIO_AF_0
* @arg @ref LL_GPIO_AF_1
* @arg @ref LL_GPIO_AF_2
* @arg @ref LL_GPIO_AF_3
* @arg @ref LL_GPIO_AF_4
* @arg @ref LL_GPIO_AF_5
* @arg @ref LL_GPIO_AF_6
* @arg @ref LL_GPIO_AF_7
* @arg @ref LL_GPIO_AF_8
* @arg @ref LL_GPIO_AF_9
* @arg @ref LL_GPIO_AF_10
* @arg @ref LL_GPIO_AF_11
* @arg @ref LL_GPIO_AF_12
* @arg @ref LL_GPIO_AF_13
* @arg @ref LL_GPIO_AF_14
* @arg @ref LL_GPIO_AF_15
*/
__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)
{
return (uint32_t)(READ_BIT(GPIOx->AFR[1],
(GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U));
}
/**
* @brief Lock configuration of several pins for a dedicated port.
* @note When the lock sequence has been applied on a port bit, the
* value of this port bit can no longer be modified until the
* next reset.
* @note Each lock bit freezes a specific configuration register
* (control and alternate function registers).
* @rmtoll LCKR LCKK LL_GPIO_LockPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
__IO uint32_t temp;
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
WRITE_REG(GPIOx->LCKR, PinMask);
WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);
/* Read LCKR register. This read is mandatory to complete key lock sequence */
temp = READ_REG(GPIOx->LCKR);
(void) temp;
}
/**
* @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.
* @rmtoll LCKR LCKy LL_GPIO_IsPinLocked
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Return 1 if one of the pin of a dedicated port is locked. else return 0.
* @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked
* @param GPIOx GPIO Port
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)
{
return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup GPIO_LL_EF_Data_Access Data Access
* @{
*/
/**
* @brief Return full input data register value for a dedicated port.
* @rmtoll IDR IDy LL_GPIO_ReadInputPort
* @param GPIOx GPIO Port
* @retval Input data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->IDR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll IDR IDy LL_GPIO_IsInputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Write output data register for the port.
* @rmtoll ODR ODy LL_GPIO_WriteOutputPort
* @param GPIOx GPIO Port
* @param PortValue Level value for each pin of the port
* @retval None
*/
__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)
{
WRITE_REG(GPIOx->ODR, PortValue);
}
/**
* @brief Return full output data register value for a dedicated port.
* @rmtoll ODR ODy LL_GPIO_ReadOutputPort
* @param GPIOx GPIO Port
* @retval Output data register value of port
*/
__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)
{
return (uint32_t)(READ_REG(GPIOx->ODR));
}
/**
* @brief Return if input data level for several pins of dedicated port is high or low.
* @rmtoll ODR ODy LL_GPIO_IsOutputPinSet
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);
}
/**
* @brief Set several pins to high level on dedicated gpio port.
* @rmtoll BSRR BSy LL_GPIO_SetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BSRR, PinMask);
}
/**
* @brief Set several pins to low level on dedicated gpio port.
* @rmtoll BRR BRy LL_GPIO_ResetOutputPin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
WRITE_REG(GPIOx->BRR, PinMask);
}
/**
* @brief Toggle data value for several pin of dedicated port.
* @rmtoll ODR ODy LL_GPIO_TogglePin
* @param GPIOx GPIO Port
* @param PinMask This parameter can be a combination of the following values:
* @arg @ref LL_GPIO_PIN_0
* @arg @ref LL_GPIO_PIN_1
* @arg @ref LL_GPIO_PIN_2
* @arg @ref LL_GPIO_PIN_3
* @arg @ref LL_GPIO_PIN_4
* @arg @ref LL_GPIO_PIN_5
* @arg @ref LL_GPIO_PIN_6
* @arg @ref LL_GPIO_PIN_7
* @arg @ref LL_GPIO_PIN_8
* @arg @ref LL_GPIO_PIN_9
* @arg @ref LL_GPIO_PIN_10
* @arg @ref LL_GPIO_PIN_11
* @arg @ref LL_GPIO_PIN_12
* @arg @ref LL_GPIO_PIN_13
* @arg @ref LL_GPIO_PIN_14
* @arg @ref LL_GPIO_PIN_15
* @arg @ref LL_GPIO_PIN_ALL
* @retval None
*/
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
{
uint32_t odr = READ_REG(GPIOx->ODR);
WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);
ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);
void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_GPIO_H */
| 37,962 | C | 37.153769 | 160 | 0.547732 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_i2c.h | /**
******************************************************************************
* @file stm32g4xx_ll_i2c.h
* @author MCD Application Team
* @brief Header file of I2C LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_I2C_H
#define STM32G4xx_LL_I2C_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
/** @defgroup I2C_LL I2C
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_LL_Private_Constants I2C Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2C_LL_Private_Macros I2C Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
* @{
*/
typedef struct
{
uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE.
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetMode(). */
uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
This parameter must be set by referring to the STM32CubeMX Tool and
the helper macro @ref __LL_I2C_CONVERT_TIMINGS().
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetTiming(). */
uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION.
This feature can be modified afterwards using unitary functions
@ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
uint32_t DigitalFilter; /*!< Configures the digital noise filter.
This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F.
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetDigitalFilter(). */
uint32_t OwnAddress1; /*!< Specifies the device own address 1.
This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF.
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetOwnAddress1(). */
uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive
match code or next received byte.
This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE.
This feature can be modified afterwards using unitary function
@ref LL_I2C_AcknowledgeNextData(). */
uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1.
This feature can be modified afterwards using unitary function
@ref LL_I2C_SetOwnAddress1(). */
} LL_I2C_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
* @{
*/
/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_I2C_WriteReg function
* @{
*/
#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
/**
* @}
*/
/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_I2C_ReadReg function
* @{
*/
#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
/**
* @}
*/
/** @defgroup I2C_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
* @{
*/
#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
/**
* @}
*/
/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
* @{
*/
#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode
(Default address not acknowledge) */
#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
/**
* @}
*/
/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
* @{
*/
#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
* @{
*/
#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
* @{
*/
#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
* @{
*/
#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done.
All Address2 are acknowledged. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
* @{
*/
#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
* @{
*/
#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
* @{
*/
#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_MODE Transfer End Mode
* @{
*/
#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode
with no HW PEC comparison. */
#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode
with no HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode
with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode
with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode
with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)
/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)
/*!< Enable SMBUS Software end mode with HW PEC comparison. */
/**
* @}
*/
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
* @{
*/
#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U
/*!< Don't Generate Stop and Start condition. */
#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
/*!< Generate Stop condition (Size should be set to 0). */
#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
/*!< Generate Start for read request. */
#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/*!< Generate Start for write request. */
#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
/*!< Generate Restart for read request, slave 7Bit address. */
#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/*!< Generate Restart for write request, slave 7Bit address. */
#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \
I2C_CR2_RD_WRN | I2C_CR2_HEAD10R)
/*!< Generate Restart for read request, slave 10Bit address. */
#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/*!< Generate Restart for write request, slave 10Bit address.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
* @{
*/
#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master,
slave enters receiver mode. */
#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master,
slave enters transmitter mode.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
* @{
*/
#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for
transmission */
#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for
reception */
/**
* @}
*/
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
* @{
*/
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect
SCL low level timeout. */
#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect
both SCL and SDA high level timeout.*/
/**
* @}
*/
/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
* @{
*/
#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock)
enable bit */
#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \
I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB
(extended clock) enable bits */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
* @{
*/
/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in I2C register
* @param __INSTANCE__ I2C Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in I2C register
* @param __INSTANCE__ I2C Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
* @{
*/
/**
* @brief Configure the SDA setup, hold time and the SCL high, low period.
* @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
* @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
(tscldel = (SCLDEL+1)xtpresc)
* @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
(tsdadel = SDADELxtpresc)
* @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
(tsclh = (SCLH+1)xtpresc)
* @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF.
(tscll = (SCLL+1)xtpresc)
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \
((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
(((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
(((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
(((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
(((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
* @{
*/
/** @defgroup I2C_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable I2C peripheral (PE = 1).
* @rmtoll CR1 PE LL_I2C_Enable
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_PE);
}
/**
* @brief Disable I2C peripheral (PE = 0).
* @note When PE = 0, the I2C SCL and SDA lines are released.
* Internal state machines and status bits are put back to their reset value.
* When cleared, PE must be kept low for at least 3 APB clock cycles.
* @rmtoll CR1 PE LL_I2C_Disable
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
}
/**
* @brief Check if the I2C peripheral is enabled or disabled.
* @rmtoll CR1 PE LL_I2C_IsEnabled
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
}
/**
* @brief Configure Noise Filters (Analog and Digital).
* @note If the analog filter is also enabled, the digital filter is added to analog filter.
* The filters can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
* CR1 DNF LL_I2C_ConfigFilters
* @param I2Cx I2C Instance.
* @param AnalogFilter This parameter can be one of the following values:
* @arg @ref LL_I2C_ANALOGFILTER_ENABLE
* @arg @ref LL_I2C_ANALOGFILTER_DISABLE
* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
{
MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
}
/**
* @brief Configure Digital Noise Filter.
* @note If the analog filter is also enabled, the digital filter is added to analog filter.
* This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
* @param I2Cx I2C Instance.
* @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled)
and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
* This parameter is used to configure the digital noise filter on SDA and SCL input.
* The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
{
MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
}
/**
* @brief Get the current Digital Noise Filter configuration.
* @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
}
/**
* @brief Enable Analog Noise Filter.
* @note This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
}
/**
* @brief Disable Analog Noise Filter.
* @note This filter can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
}
/**
* @brief Check if Analog Noise Filter is enabled or disabled.
* @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA transmission requests.
* @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
}
/**
* @brief Disable DMA transmission requests.
* @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
}
/**
* @brief Check if DMA transmission requests are enabled or disabled.
* @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA reception requests.
* @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
}
/**
* @brief Disable DMA reception requests.
* @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
}
/**
* @brief Check if DMA reception requests are enabled or disabled.
* @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Get the data register address used for DMA transfer
* @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
* RXDR RXDATA LL_I2C_DMA_GetRegAddr
* @param I2Cx I2C Instance
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
{
uint32_t data_reg_addr;
if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
{
/* return address of TXDR register */
data_reg_addr = (uint32_t) &(I2Cx->TXDR);
}
else
{
/* return address of RXDR register */
data_reg_addr = (uint32_t) &(I2Cx->RXDR);
}
return data_reg_addr;
}
/**
* @brief Enable Clock stretching.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
}
/**
* @brief Disable Clock stretching.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
}
/**
* @brief Check if Clock stretching is enabled or disabled.
* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
}
/**
* @brief Enable hardware byte control in slave mode.
* @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
}
/**
* @brief Disable hardware byte control in slave mode.
* @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
}
/**
* @brief Check if hardware byte control in slave mode is enabled or disabled.
* @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
}
/**
* @brief Enable Wakeup from STOP.
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when Digital Filter is disabled.
* @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
}
/**
* @brief Disable Wakeup from STOP.
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);
}
/**
* @brief Check if Wakeup from STOP is enabled or disabled.
* @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not
* WakeUpFromStop feature is supported by the I2Cx Instance.
* @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
}
/**
* @brief Enable General Call.
* @note When enabled the Address 0x00 is ACKed.
* @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
}
/**
* @brief Disable General Call.
* @note When disabled the Address 0x00 is NACKed.
* @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
}
/**
* @brief Check if General Call is enabled or disabled.
* @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
}
/**
* @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
* @note Changing this bit is not allowed, when the START bit is set.
* @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
* @param I2Cx I2C Instance.
* @param AddressingMode This parameter can be one of the following values:
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
}
/**
* @brief Get the Master addressing mode.
* @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
*/
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
}
/**
* @brief Set the Own Address1.
* @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
* OAR1 OA1MODE LL_I2C_SetOwnAddress1
* @param I2Cx I2C Instance.
* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
* @param OwnAddrSize This parameter can be one of the following values:
* @arg @ref LL_I2C_OWNADDRESS1_7BIT
* @arg @ref LL_I2C_OWNADDRESS1_10BIT
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
{
MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
}
/**
* @brief Enable acknowledge on Own Address1 match address.
* @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
}
/**
* @brief Disable acknowledge on Own Address1 match address.
* @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
}
/**
* @brief Check if Own Address1 acknowledge is enabled or disabled.
* @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
}
/**
* @brief Set the 7bits Own Address2.
* @note This action has no effect if own address2 is enabled.
* @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
* OAR2 OA2MSK LL_I2C_SetOwnAddress2
* @param I2Cx I2C Instance.
* @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
* @param OwnAddrMask This parameter can be one of the following values:
* @arg @ref LL_I2C_OWNADDRESS2_NOMASK
* @arg @ref LL_I2C_OWNADDRESS2_MASK01
* @arg @ref LL_I2C_OWNADDRESS2_MASK02
* @arg @ref LL_I2C_OWNADDRESS2_MASK03
* @arg @ref LL_I2C_OWNADDRESS2_MASK04
* @arg @ref LL_I2C_OWNADDRESS2_MASK05
* @arg @ref LL_I2C_OWNADDRESS2_MASK06
* @arg @ref LL_I2C_OWNADDRESS2_MASK07
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
{
MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
}
/**
* @brief Enable acknowledge on Own Address2 match address.
* @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
}
/**
* @brief Disable acknowledge on Own Address2 match address.
* @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
}
/**
* @brief Check if Own Address1 acknowledge is enabled or disabled.
* @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
}
/**
* @brief Configure the SDA setup, hold time and the SCL high, low period.
* @note This bit can only be programmed when the I2C is disabled (PE = 0).
* @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
* @param I2Cx I2C Instance.
* @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
* @note This parameter is computed with the STM32CubeMX Tool.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
{
WRITE_REG(I2Cx->TIMINGR, Timing);
}
/**
* @brief Get the Timing Prescaler setting.
* @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
}
/**
* @brief Get the SCL low period setting.
* @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
}
/**
* @brief Get the SCL high period setting.
* @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
}
/**
* @brief Get the SDA hold time.
* @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
}
/**
* @brief Get the SDA setup time.
* @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
}
/**
* @brief Configure peripheral mode.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
* CR1 SMBDEN LL_I2C_SetMode
* @param I2Cx I2C Instance.
* @param PeripheralMode This parameter can be one of the following values:
* @arg @ref LL_I2C_MODE_I2C
* @arg @ref LL_I2C_MODE_SMBUS_HOST
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
{
MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
}
/**
* @brief Get peripheral mode.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
* CR1 SMBDEN LL_I2C_GetMode
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_MODE_I2C
* @arg @ref LL_I2C_MODE_SMBUS_HOST
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
*/
__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
}
/**
* @brief Enable SMBus alert (Host or Device mode)
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is drived low and
* Alert Response Address Header acknowledge is enabled.
* SMBus Host mode:
* - SMBus Alert pin management is supported.
* @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
}
/**
* @brief Disable SMBus alert (Host or Device mode)
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note SMBus Device mode:
* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
* Alert Response Address Header acknowledge is disabled.
* SMBus Host mode:
* - SMBus Alert pin management is not supported.
* @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
}
/**
* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
}
/**
* @brief Enable SMBus Packet Error Calculation (PEC).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
}
/**
* @brief Disable SMBus Packet Error Calculation (PEC).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
}
/**
* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
}
/**
* @brief Configure the SMBus Clock Timeout.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
* TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
* TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
* @param I2Cx I2C Instance.
* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
* @param TimeoutAMode This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
* @param TimeoutB
* @retval None
*/
__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
uint32_t TimeoutB)
{
MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
}
/**
* @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
* @param I2Cx I2C Instance.
* @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
{
WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
}
/**
* @brief Get the SMBus Clock TimeoutA setting.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
}
/**
* @brief Set the SMBus Clock TimeoutA mode.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This bit can only be programmed when TimeoutA is disabled.
* @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
* @param I2Cx I2C Instance.
* @param TimeoutAMode This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
{
WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
}
/**
* @brief Get the SMBus Clock TimeoutA mode.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
}
/**
* @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note These bits can only be programmed when TimeoutB is disabled.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
* @param I2Cx I2C Instance.
* @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
{
WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
}
/**
* @brief Get the SMBus Extended Cumulative Clock TimeoutB setting.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
}
/**
* @brief Enable the SMBus Clock Timeout.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
* @param I2Cx I2C Instance.
* @param ClockTimeout This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA
* @arg @ref LL_I2C_SMBUS_TIMEOUTB
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
}
/**
* @brief Disable the SMBus Clock Timeout.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
* @param I2Cx I2C Instance.
* @param ClockTimeout This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA
* @arg @ref LL_I2C_SMBUS_TIMEOUTB
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
}
/**
* @brief Check if the SMBus Clock Timeout is enabled or disabled.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
* TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
* @param I2Cx I2C Instance.
* @param ClockTimeout This parameter can be one of the following values:
* @arg @ref LL_I2C_SMBUS_TIMEOUTA
* @arg @ref LL_I2C_SMBUS_TIMEOUTB
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
{
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
(ClockTimeout)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable TXIS interrupt.
* @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
}
/**
* @brief Disable TXIS interrupt.
* @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
}
/**
* @brief Check if the TXIS Interrupt is enabled or disabled.
* @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
}
/**
* @brief Enable RXNE interrupt.
* @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
}
/**
* @brief Disable RXNE interrupt.
* @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
}
/**
* @brief Check if the RXNE Interrupt is enabled or disabled.
* @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Address match interrupt (slave mode only).
* @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
}
/**
* @brief Disable Address match interrupt (slave mode only).
* @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
}
/**
* @brief Check if Address match interrupt is enabled or disabled.
* @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Not acknowledge received interrupt.
* @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
}
/**
* @brief Disable Not acknowledge received interrupt.
* @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
}
/**
* @brief Check if Not acknowledge received interrupt is enabled or disabled.
* @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable STOP detection interrupt.
* @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
}
/**
* @brief Disable STOP detection interrupt.
* @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
}
/**
* @brief Check if STOP detection interrupt is enabled or disabled.
* @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Transfer Complete interrupt.
* @note Any of these events will generate interrupt :
* Transfer Complete (TC)
* Transfer Complete Reload (TCR)
* @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
}
/**
* @brief Disable Transfer Complete interrupt.
* @note Any of these events will generate interrupt :
* Transfer Complete (TC)
* Transfer Complete Reload (TCR)
* @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
}
/**
* @brief Check if Transfer Complete interrupt is enabled or disabled.
* @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Error interrupts.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
* Bus Error detection (BERR)
* Overrun/Underrun (OVR)
* SMBus Timeout detection (TIMEOUT)
* SMBus PEC error detection (PECERR)
* SMBus Alert pin event detection (ALERT)
* @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
}
/**
* @brief Disable Error interrupts.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note Any of these errors will generate interrupt :
* Arbitration Loss (ARLO)
* Bus Error detection (BERR)
* Overrun/Underrun (OVR)
* SMBus Timeout detection (TIMEOUT)
* SMBus PEC error detection (PECERR)
* SMBus Alert pin event detection (ALERT)
* @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
}
/**
* @brief Check if Error interrupts are enabled or disabled.
* @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
* @{
*/
/**
* @brief Indicate the status of Transmit data register empty flag.
* @note RESET: When next data is written in Transmit data register.
* SET: When Transmit data register is empty.
* @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Transmit interrupt flag.
* @note RESET: When next data is written in Transmit data register.
* SET: When Transmit data register is empty.
* @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Receive data register not empty flag.
* @note RESET: When Receive data register is read.
* SET: When the received data is copied in Receive data register.
* @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Address matched flag (slave mode).
* @note RESET: Clear default value.
* SET: When the received slave address matched with one of the enabled slave address.
* @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Not Acknowledge received flag.
* @note RESET: Clear default value.
* SET: When a NACK is received after a byte transmission.
* @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Stop detection flag.
* @note RESET: Clear default value.
* SET: When a Stop condition is detected.
* @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Transfer complete flag (master mode).
* @note RESET: Clear default value.
* SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
* @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Transfer complete flag (master mode).
* @note RESET: Clear default value.
* SET: When RELOAD=1 and NBYTES date have been transferred.
* @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Bus error flag.
* @note RESET: Clear default value.
* SET: When a misplaced Start or Stop condition is detected.
* @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Arbitration lost flag.
* @note RESET: Clear default value.
* SET: When arbitration lost.
* @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Overrun/Underrun flag (slave mode).
* @note RESET: Clear default value.
* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
* @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of SMBus PEC error flag in reception.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When the received PEC does not match with the PEC register content.
* @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of SMBus Timeout detection flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When a timeout or extended clock timeout occurs.
* @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of SMBus alert flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note RESET: Clear default value.
* SET: When SMBus host configuration, SMBus alert enabled and
* a falling edge event occurs on SMBA pin.
* @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of Bus Busy flag.
* @note RESET: Clear default value.
* SET: When a Start condition is detected.
* @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
}
/**
* @brief Clear Address Matched flag.
* @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
}
/**
* @brief Clear Not Acknowledge flag.
* @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
}
/**
* @brief Clear Stop detection flag.
* @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
}
/**
* @brief Clear Transmit data register empty flag (TXE).
* @note This bit can be clear by software in order to flush the transmit data register (TXDR).
* @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
{
WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
}
/**
* @brief Clear Bus error flag.
* @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
}
/**
* @brief Clear Arbitration lost flag.
* @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
}
/**
* @brief Clear Overrun/Underrun flag.
* @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
}
/**
* @brief Clear SMBus PEC error flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
}
/**
* @brief Clear SMBus Timeout detection flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
}
/**
* @brief Clear SMBus Alert flag.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
}
/**
* @}
*/
/** @defgroup I2C_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Enable automatic STOP condition generation (master mode).
* @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
* This bit has no effect in slave mode or when RELOAD bit is set.
* @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
}
/**
* @brief Disable automatic STOP condition generation (master mode).
* @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
* @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
}
/**
* @brief Check if automatic STOP condition is enabled or disabled.
* @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
}
/**
* @brief Enable reload mode (master mode).
* @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
* @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
}
/**
* @brief Disable reload mode (master mode).
* @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
* @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
}
/**
* @brief Check if reload mode is enabled or disabled.
* @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
}
/**
* @brief Configure the number of bytes for transfer.
* @note Changing these bits when START bit is set is not allowed.
* @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
* @param I2Cx I2C Instance.
* @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
}
/**
* @brief Get the number of bytes configured for transfer.
* @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
}
/**
* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code
or next received byte.
* @note Usage in Slave mode only.
* @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
* @param I2Cx I2C Instance.
* @param TypeAcknowledge This parameter can be one of the following values:
* @arg @ref LL_I2C_ACK
* @arg @ref LL_I2C_NACK
* @retval None
*/
__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
}
/**
* @brief Generate a START or RESTART condition
* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
* This action has no effect when RELOAD is set.
* @rmtoll CR2 START LL_I2C_GenerateStartCondition
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_START);
}
/**
* @brief Generate a STOP condition after the current byte transfer (master mode).
* @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
}
/**
* @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
* @note The master sends the complete 10bit slave address read sequence :
* Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address
in Read direction.
* @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
{
CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
}
/**
* @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
* @note The master only sends the first 7 bits of 10bit address in Read direction.
* @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
}
/**
* @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
* @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
}
/**
* @brief Configure the transfer direction (master mode).
* @note Changing these bits when START bit is set is not allowed.
* @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
* @param I2Cx I2C Instance.
* @param TransferRequest This parameter can be one of the following values:
* @arg @ref LL_I2C_REQUEST_WRITE
* @arg @ref LL_I2C_REQUEST_READ
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
}
/**
* @brief Get the transfer direction requested (master mode).
* @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_REQUEST_WRITE
* @arg @ref LL_I2C_REQUEST_READ
*/
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
}
/**
* @brief Configure the slave address for transfer (master mode).
* @note Changing these bits when START bit is set is not allowed.
* @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
* @param I2Cx I2C Instance.
* @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
* @retval None
*/
__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
}
/**
* @brief Get the slave address programmed for transfer.
* @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
*/
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
}
/**
* @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
* @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
* CR2 ADD10 LL_I2C_HandleTransfer\n
* CR2 RD_WRN LL_I2C_HandleTransfer\n
* CR2 START LL_I2C_HandleTransfer\n
* CR2 STOP LL_I2C_HandleTransfer\n
* CR2 RELOAD LL_I2C_HandleTransfer\n
* CR2 NBYTES LL_I2C_HandleTransfer\n
* CR2 AUTOEND LL_I2C_HandleTransfer\n
* CR2 HEAD10R LL_I2C_HandleTransfer
* @param I2Cx I2C Instance.
* @param SlaveAddr Specifies the slave address to be programmed.
* @param SlaveAddrSize This parameter can be one of the following values:
* @arg @ref LL_I2C_ADDRSLAVE_7BIT
* @arg @ref LL_I2C_ADDRSLAVE_10BIT
* @param TransferSize Specifies the number of bytes to be programmed.
* This parameter must be a value between Min_Data=0 and Max_Data=255.
* @param EndMode This parameter can be one of the following values:
* @arg @ref LL_I2C_MODE_RELOAD
* @arg @ref LL_I2C_MODE_AUTOEND
* @arg @ref LL_I2C_MODE_SOFTEND
* @arg @ref LL_I2C_MODE_SMBUS_RELOAD
* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
* @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
* @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
* @param Request This parameter can be one of the following values:
* @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
* @arg @ref LL_I2C_GENERATE_STOP
* @arg @ref LL_I2C_GENERATE_START_READ
* @arg @ref LL_I2C_GENERATE_START_WRITE
* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
* @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
* @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
* @retval None
*/
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
}
/**
* @brief Indicate the value of transfer direction (slave mode).
* @note RESET: Write transfer, Slave enters in receiver mode.
* SET: Read transfer, Slave enters in transmitter mode.
* @rmtoll ISR DIR LL_I2C_GetTransferDirection
* @param I2Cx I2C Instance.
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2C_DIRECTION_WRITE
* @arg @ref LL_I2C_DIRECTION_READ
*/
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
}
/**
* @brief Return the slave matched address.
* @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
}
/**
* @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition
or an Address Matched is received.
* This bit has no effect when RELOAD bit is set.
* This bit has no effect in device mode when SBC bit is not set.
* @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
* @param I2Cx I2C Instance.
* @retval None
*/
__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
{
SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
}
/**
* @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
* @param I2Cx I2C Instance.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
{
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
}
/**
* @brief Get the SMBus Packet Error byte calculated.
* @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
* SMBus feature is supported by the I2Cx Instance.
* @rmtoll PECR PEC LL_I2C_GetSMBusPEC
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
{
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
}
/**
* @brief Read Receive Data register.
* @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
* @param I2Cx I2C Instance.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
{
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
}
/**
* @brief Write in Transmit Data Register .
* @rmtoll TXDR TXDATA LL_I2C_TransmitData8
* @param I2Cx I2C Instance.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
{
WRITE_REG(I2Cx->TXDR, Data);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* I2C1 || I2C2 || I2C3 || I2C4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_I2C_H */
| 83,872 | C | 35.899692 | 119 | 0.61601 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_irda_ex.h
* @author MCD Application Team
* @brief Header file of IRDA HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_IRDA_EX_H
#define STM32G4xx_HAL_IRDA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup IRDAEx IRDAEx
* @brief IRDA Extended HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants
* @{
*/
/** @defgroup IRDAEx_Word_Length IRDAEx Word Length
* @{
*/
#define IRDA_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long frame */
#define IRDA_WORDLENGTH_8B 0x00000000U /*!< 8-bit long frame */
#define IRDA_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long frame */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros
* @{
*/
/** @brief Report the IRDA clock source.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#if defined(UART5)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(UART4)
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* UART5 */
/** @brief Compute the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/** @brief Ensure that IRDA frame length is valid.
* @param __LENGTH__ IRDA frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \
((__LENGTH__) == IRDA_WORDLENGTH_8B) || \
((__LENGTH__) == IRDA_WORDLENGTH_9B))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_IRDA_EX_H */
| 23,563 | C | 54.706856 | 110 | 0.267581 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_pwr.h | /**
******************************************************************************
* @file stm32g4xx_ll_pwr.h
* @author MCD Application Team
* @brief Header file of PWR LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_PWR_H
#define STM32G4xx_LL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(PWR)
/** @defgroup PWR_LL PWR
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_PWR_WriteReg function
* @{
*/
#define LL_PWR_SCR_CSBF PWR_SCR_CSBF
#define LL_PWR_SCR_CWUF PWR_SCR_CWUF
#define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
#define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
#define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
#define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
#define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
/**
* @}
*/
/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_PWR_ReadReg function
* @{
*/
#define LL_PWR_SR1_WUFI PWR_SR1_WUFI
#define LL_PWR_SR1_SBF PWR_SR1_SBF
#define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
#define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
#define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
#define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
#define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
#if defined(PWR_SR2_PVMO4)
#define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
#endif /* PWR_SR2_PVMO4 */
#if defined(PWR_SR2_PVMO3)
#define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
#endif /* PWR_SR2_PVMO3 */
#if defined(PWR_SR2_PVMO2)
#define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
#endif /* PWR_SR2_PVMO2 */
#if defined(PWR_SR2_PVMO1)
#define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
#endif /* PWR_SR2_PVMO1 */
#define LL_PWR_SR2_PVDO PWR_SR2_PVDO
#define LL_PWR_SR2_VOSF PWR_SR2_VOSF
#define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
#define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
/**
* @}
*/
/** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
* @{
*/
#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
/**
* @}
*/
/** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
* @{
*/
#define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
#define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
#define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
#define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
/**
* @}
*/
/** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
* @{
*/
#if defined(PWR_CR2_PVME1)
#define LL_PWR_PVM_VDDA_COMP (PWR_CR2_PVME1) /* Monitoring VDDA vs. x.xV */
#endif
#if defined(PWR_CR2_PVME2)
#define LL_PWR_PVM_VDDA_FASTDAC (PWR_CR2_PVME2) /* Monitoring VDDA vs. x.xV */
#endif
#if defined(PWR_CR2_PVME3)
#define LL_PWR_PVM_VDDA_ADC (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
#endif
#if defined(PWR_CR2_PVME4)
#define LL_PWR_PVM_VDDA_OPAMP_DAC (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1x.xV */
#endif
/**
* @}
*/
/** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
* @{
*/
#define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
#define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
#define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
#define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
#define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
#define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
#define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
#define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_LL_EC_WAKEUP WAKEUP
* @{
*/
#define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
#define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
#define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
#define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
#define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
/**
* @}
*/
/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
* @{
*/
#define LL_PWR_BATT_CHARG_RESISTOR_5K ((uint32_t)0x00000000)
#define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
/**
* @}
*/
/** @defgroup PWR_LL_EC_GPIO GPIO
* @{
*/
#define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
#define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
#define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
#define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
#define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
#define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
#define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
/**
* @}
*/
/** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
* @{
*/
#define LL_PWR_GPIO_BIT_0 ((uint32_t)0x00000001)
#define LL_PWR_GPIO_BIT_1 ((uint32_t)0x00000002)
#define LL_PWR_GPIO_BIT_2 ((uint32_t)0x00000004)
#define LL_PWR_GPIO_BIT_3 ((uint32_t)0x00000008)
#define LL_PWR_GPIO_BIT_4 ((uint32_t)0x00000010)
#define LL_PWR_GPIO_BIT_5 ((uint32_t)0x00000020)
#define LL_PWR_GPIO_BIT_6 ((uint32_t)0x00000040)
#define LL_PWR_GPIO_BIT_7 ((uint32_t)0x00000080)
#define LL_PWR_GPIO_BIT_8 ((uint32_t)0x00000100)
#define LL_PWR_GPIO_BIT_9 ((uint32_t)0x00000200)
#define LL_PWR_GPIO_BIT_10 ((uint32_t)0x00000400)
#define LL_PWR_GPIO_BIT_11 ((uint32_t)0x00000800)
#define LL_PWR_GPIO_BIT_12 ((uint32_t)0x00001000)
#define LL_PWR_GPIO_BIT_13 ((uint32_t)0x00002000)
#define LL_PWR_GPIO_BIT_14 ((uint32_t)0x00004000)
#define LL_PWR_GPIO_BIT_15 ((uint32_t)0x00008000)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
* @{
*/
/** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in PWR register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
/**
* @brief Read a value in PWR register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
* @{
*/
/** @defgroup PWR_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Switch the regulator from main mode to low-power mode
* @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
{
SET_BIT(PWR->CR1, PWR_CR1_LPR);
}
/**
* @brief Switch the regulator from low-power mode to main mode
* @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
}
/**
* @brief Check if the regulator is in low-power mode
* @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR1, PWR_CR1_LPR);
return ((temp == (PWR_CR1_LPR))?1U:0U);
}
/**
* @brief Switch from run main mode to run low-power mode.
* @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
{
LL_PWR_EnableLowPowerRunMode();
}
/**
* @brief Switch from run main mode to low-power mode.
* @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
{
LL_PWR_DisableLowPowerRunMode();
}
/**
* @brief Set the main internal regulator output voltage
* @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
* @param VoltageScaling This parameter can be one of the following values:
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
{
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
}
/**
* @brief Get the main internal regulator output voltage
* @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
* @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
*/
__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
{
return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
}
#if defined(PWR_CR5_R1MODE)
/**
* @brief Enable main regulator voltage range 1 boost mode
* @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
{
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
}
/**
* @brief Disable main regulator voltage range 1 boost mode
* @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
{
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
}
/**
* @brief Check if the main regulator voltage range 1 boost mode is enabled
* @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
* @retval Inverted state of bit (0 or 1).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR5, PWR_CR5_R1MODE);
return ((temp == (0U))?1U:0U);
}
#endif /* PWR_CR5_R1MODE */
/**
* @brief Enable access to the backup domain
* @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
{
SET_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Disable access to the backup domain
* @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
{
CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
}
/**
* @brief Check if the backup domain is enabled
* @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR1, PWR_CR1_DBP);
return ((temp == (PWR_CR1_DBP))?1U:0U);
}
/**
* @brief Set Low-Power mode
* @rmtoll CR1 LPMS LL_PWR_SetPowerMode
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
{
MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
}
/**
* @brief Get Low-Power mode
* @rmtoll CR1 LPMS LL_PWR_GetPowerMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_MODE_STOP0
* @arg @ref LL_PWR_MODE_STOP1
* @arg @ref LL_PWR_MODE_STANDBY
* @arg @ref LL_PWR_MODE_SHUTDOWN
*/
__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
{
return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
}
#if defined(PWR_CR3_UCPD_STDBY)
/**
* @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
* @note This function must be called just before entering Standby mode.
* @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
{
SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
}
/**
* @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
* @note This function must be called after exiting Standby mode and before any
* UCPD configuration update.
* @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
}
/**
* @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
* @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
{
return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL);
}
#endif /* PWR_CR3_UCPD_STDBY */
#if defined(PWR_CR3_UCPD_DBDIS)
/**
* @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
* on UCPD CC1 and CC2 pins.
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
* to disable it in all cases, either to stop this pull-down or to hand over
* control to the UCPD (which should therefore be initialized before doing the disable).
* @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
}
/**
* @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
* on UCPD CC1 and CC2 pins.
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
* to disable it in all cases, either to stop this pull-down or to hand over
* control to the UCPD (which should therefore be initialized before doing the disable).
* @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
{
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
}
/**
* @brief Check the USB Type-C and power delivery dead battery pull-down behavior
* on UCPD CC1 and CC2 pins.
* @note After exiting reset, the USB Type-C dead battery behavior is enabled,
* which may have a pull-down effect on CC1 and CC2 pins. It is recommended
* to disable it in all cases, either to stop this pull-down or to hand over
* control to the UCPD (which should therefore be initialized before doing the disable).
* @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
* @retval State of feature (1 : enabled; 0 : disabled).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
{
return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
}
#endif /* PWR_CR3_UCPD_DBDIS */
#if defined(PWR_CR2_USV)
/**
* @brief Enable VDDUSB supply
* @rmtoll CR2 USV LL_PWR_EnableVddUSB
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVddUSB(void)
{
SET_BIT(PWR->CR2, PWR_CR2_USV);
}
/**
* @brief Disable VDDUSB supply
* @rmtoll CR2 USV LL_PWR_DisableVddUSB
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVddUSB(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
}
/**
* @brief Check if VDDUSB supply is enabled
* @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR2, PWR_CR2_USV);
return ((temp == (PWR_CR2_USV))?1U:0U);
}
#endif
#if defined(PWR_CR2_IOSV)
/**
* @brief Enable VDDIO2 supply
* @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableVddIO2(void)
{
SET_BIT(PWR->CR2, PWR_CR2_IOSV);
}
/**
* @brief Disable VDDIO2 supply
* @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableVddIO2(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
}
/**
* @brief Check if VDDIO2 supply is enabled
* @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR2, PWR_CR2_IOSV);
return ((temp == (PWR_CR2_IOSV))?1U:0U);
}
#endif
/**
* @brief Enable the Power Voltage Monitoring on a peripheral
* @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
* CR2 PVME2 LL_PWR_EnablePVM\n
* CR2 PVME3 LL_PWR_EnablePVM\n
* CR2 PVME4 LL_PWR_EnablePVM
* @param PeriphVoltage This parameter can be one of the following values:
* @arg @ref LL_PWR_PVM_VDDA_COMP (*)
* @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
* @arg @ref LL_PWR_PVM_VDDA_ADC
* @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
{
SET_BIT(PWR->CR2, PeriphVoltage);
}
/**
* @brief Disable the Power Voltage Monitoring on a peripheral
* @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
* CR2 PVME2 LL_PWR_DisablePVM\n
* CR2 PVME3 LL_PWR_DisablePVM\n
* CR2 PVME4 LL_PWR_DisablePVM
* @param PeriphVoltage This parameter can be one of the following values:
* @arg @ref LL_PWR_PVM_VDDA_COMP (*)
* @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
* @arg @ref LL_PWR_PVM_VDDA_ADC
* @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
{
CLEAR_BIT(PWR->CR2, PeriphVoltage);
}
/**
* @brief Check if Power Voltage Monitoring is enabled on a peripheral
* @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
* CR2 PVME2 LL_PWR_IsEnabledPVM\n
* CR2 PVME3 LL_PWR_IsEnabledPVM\n
* CR2 PVME4 LL_PWR_IsEnabledPVM
* @param PeriphVoltage This parameter can be one of the following values:
* @arg @ref LL_PWR_PVM_VDDA_COMP (*)
* @arg @ref LL_PWR_PVM_VDDA_FASTDAC (*)
* @arg @ref LL_PWR_PVM_VDDA_ADC
* @arg @ref LL_PWR_PVM_VDDA_OPAMP_DAC
*
* (*) value not defined in all devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
{
uint32_t temp;
temp = READ_BIT(PWR->CR2, PeriphVoltage);
return ((temp == (PeriphVoltage))?1U:0U);
}
/**
* @brief Configure the voltage threshold detected by the Power Voltage Detector
* @rmtoll CR2 PLS LL_PWR_SetPVDLevel
* @param PVDLevel This parameter can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
{
MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
}
/**
* @brief Get the voltage threshold detection
* @rmtoll CR2 PLS LL_PWR_GetPVDLevel
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_PVDLEVEL_0
* @arg @ref LL_PWR_PVDLEVEL_1
* @arg @ref LL_PWR_PVDLEVEL_2
* @arg @ref LL_PWR_PVDLEVEL_3
* @arg @ref LL_PWR_PVDLEVEL_4
* @arg @ref LL_PWR_PVDLEVEL_5
* @arg @ref LL_PWR_PVDLEVEL_6
* @arg @ref LL_PWR_PVDLEVEL_7
*/
__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
{
return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
}
/**
* @brief Enable Power Voltage Detector
* @rmtoll CR2 PVDE LL_PWR_EnablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePVD(void)
{
SET_BIT(PWR->CR2, PWR_CR2_PVDE);
}
/**
* @brief Disable Power Voltage Detector
* @rmtoll CR2 PVDE LL_PWR_DisablePVD
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePVD(void)
{
CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
}
/**
* @brief Check if Power Voltage Detector is enabled
* @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR2, PWR_CR2_PVDE);
return ((temp == (PWR_CR2_PVDE))?1U:0U);
}
/**
* @brief Enable Internal Wake-up line
* @rmtoll CR3 EIWF LL_PWR_EnableInternWU
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableInternWU(void)
{
SET_BIT(PWR->CR3, PWR_CR3_EIWF);
}
/**
* @brief Disable Internal Wake-up line
* @rmtoll CR3 EIWF LL_PWR_DisableInternWU
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableInternWU(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
}
/**
* @brief Check if Internal Wake-up line is enabled
* @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
{
return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF))?1UL:0UL);
}
/**
* @brief Enable pull-up and pull-down configuration
* @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
{
SET_BIT(PWR->CR3, PWR_CR3_APC);
}
/**
* @brief Disable pull-up and pull-down configuration
* @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
}
/**
* @brief Check if pull-up and pull-down configuration is enabled
* @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR3, PWR_CR3_APC);
return ((temp == (PWR_CR3_APC))?1U:0U);
}
/**
* @brief Enable SRAM2 content retention in Standby mode
* @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
{
SET_BIT(PWR->CR3, PWR_CR3_RRS);
}
/**
* @brief Disable SRAM2 content retention in Standby mode
* @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
{
CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
}
/**
* @brief Check if SRAM2 content retention in Standby mode is enabled
* @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR3, PWR_CR3_RRS);
return ((temp == (PWR_CR3_RRS))?1U:0U);
}
/**
* @brief Enable the WakeUp PINx functionality
* @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
* CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
* CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
* CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
* CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
{
SET_BIT(PWR->CR3, WakeUpPin);
}
/**
* @brief Disable the WakeUp PINx functionality
* @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
* CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
* CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
* CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
* CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
{
CLEAR_BIT(PWR->CR3, WakeUpPin);
}
/**
* @brief Check if the WakeUp PINx functionality is enabled
* @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
* CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
* CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
* CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
* CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
{
uint32_t temp;
temp = READ_BIT(PWR->CR3, WakeUpPin);
return ((temp == (WakeUpPin))?1U:0U);
}
/**
* @brief Set the resistor impedance
* @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
* @param Resistor This parameter can be one of the following values:
* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
* @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
{
MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
}
/**
* @brief Get the resistor impedance
* @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
* @retval Returned value can be one of the following values:
* @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
* @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
*/
__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
{
return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
}
/**
* @brief Enable battery charging
* @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
{
SET_BIT(PWR->CR4, PWR_CR4_VBE);
}
/**
* @brief Disable battery charging
* @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
{
CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
}
/**
* @brief Check if battery charging is enabled
* @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
{
uint32_t temp;
temp = READ_BIT(PWR->CR4, PWR_CR4_VBE);
return ((temp == (PWR_CR4_VBE))?1U:0U);
}
/**
* @brief Set the Wake-Up pin polarity low for the event detection
* @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
* CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
* CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
* CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
* CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
{
SET_BIT(PWR->CR4, WakeUpPin);
}
/**
* @brief Set the Wake-Up pin polarity high for the event detection
* @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
* CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
* CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
* CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
* CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @retval None
*/
__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
{
CLEAR_BIT(PWR->CR4, WakeUpPin);
}
/**
* @brief Get the Wake-Up pin polarity for the event detection
* @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
* CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
* CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
* CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
* CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
* @param WakeUpPin This parameter can be one of the following values:
* @arg @ref LL_PWR_WAKEUP_PIN1
* @arg @ref LL_PWR_WAKEUP_PIN2
* @arg @ref LL_PWR_WAKEUP_PIN3
* @arg @ref LL_PWR_WAKEUP_PIN4
* @arg @ref LL_PWR_WAKEUP_PIN5
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
{
uint32_t temp;
temp = READ_BIT(PWR->CR4, WakeUpPin);
return ((temp == (WakeUpPin))?1U:0U);
}
/**
* @brief Enable GPIO pull-up state in Standby and Shutdown modes
* @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
* PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
* PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
* PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
* PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
* PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
* PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
* @param GPIO This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_A
* @arg @ref LL_PWR_GPIO_B
* @arg @ref LL_PWR_GPIO_C
* @arg @ref LL_PWR_GPIO_D
* @arg @ref LL_PWR_GPIO_E
* @arg @ref LL_PWR_GPIO_F
* @arg @ref LL_PWR_GPIO_G
*
* (*) value not defined in all devices
* @param GPIONumber This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_BIT_0
* @arg @ref LL_PWR_GPIO_BIT_1
* @arg @ref LL_PWR_GPIO_BIT_2
* @arg @ref LL_PWR_GPIO_BIT_3
* @arg @ref LL_PWR_GPIO_BIT_4
* @arg @ref LL_PWR_GPIO_BIT_5
* @arg @ref LL_PWR_GPIO_BIT_6
* @arg @ref LL_PWR_GPIO_BIT_7
* @arg @ref LL_PWR_GPIO_BIT_8
* @arg @ref LL_PWR_GPIO_BIT_9
* @arg @ref LL_PWR_GPIO_BIT_10
* @arg @ref LL_PWR_GPIO_BIT_11
* @arg @ref LL_PWR_GPIO_BIT_12
* @arg @ref LL_PWR_GPIO_BIT_13
* @arg @ref LL_PWR_GPIO_BIT_14
* @arg @ref LL_PWR_GPIO_BIT_15
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
}
/**
* @brief Disable GPIO pull-up state in Standby and Shutdown modes
* @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
* PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
* PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
* PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
* PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
* PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
* PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
* @param GPIO This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_A
* @arg @ref LL_PWR_GPIO_B
* @arg @ref LL_PWR_GPIO_C
* @arg @ref LL_PWR_GPIO_D
* @arg @ref LL_PWR_GPIO_E
* @arg @ref LL_PWR_GPIO_F
* @arg @ref LL_PWR_GPIO_G
*
* (*) value not defined in all devices
* @param GPIONumber This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_BIT_0
* @arg @ref LL_PWR_GPIO_BIT_1
* @arg @ref LL_PWR_GPIO_BIT_2
* @arg @ref LL_PWR_GPIO_BIT_3
* @arg @ref LL_PWR_GPIO_BIT_4
* @arg @ref LL_PWR_GPIO_BIT_5
* @arg @ref LL_PWR_GPIO_BIT_6
* @arg @ref LL_PWR_GPIO_BIT_7
* @arg @ref LL_PWR_GPIO_BIT_8
* @arg @ref LL_PWR_GPIO_BIT_9
* @arg @ref LL_PWR_GPIO_BIT_10
* @arg @ref LL_PWR_GPIO_BIT_11
* @arg @ref LL_PWR_GPIO_BIT_12
* @arg @ref LL_PWR_GPIO_BIT_13
* @arg @ref LL_PWR_GPIO_BIT_14
* @arg @ref LL_PWR_GPIO_BIT_15
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
}
/**
* @brief Check if GPIO pull-up state is enabled
* @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
* PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
* PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
* PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
* PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
* PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
* PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
* @param GPIO This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_A
* @arg @ref LL_PWR_GPIO_B
* @arg @ref LL_PWR_GPIO_C
* @arg @ref LL_PWR_GPIO_D
* @arg @ref LL_PWR_GPIO_E
* @arg @ref LL_PWR_GPIO_F
* @arg @ref LL_PWR_GPIO_G
*
* (*) value not defined in all devices
* @param GPIONumber This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_BIT_0
* @arg @ref LL_PWR_GPIO_BIT_1
* @arg @ref LL_PWR_GPIO_BIT_2
* @arg @ref LL_PWR_GPIO_BIT_3
* @arg @ref LL_PWR_GPIO_BIT_4
* @arg @ref LL_PWR_GPIO_BIT_5
* @arg @ref LL_PWR_GPIO_BIT_6
* @arg @ref LL_PWR_GPIO_BIT_7
* @arg @ref LL_PWR_GPIO_BIT_8
* @arg @ref LL_PWR_GPIO_BIT_9
* @arg @ref LL_PWR_GPIO_BIT_10
* @arg @ref LL_PWR_GPIO_BIT_11
* @arg @ref LL_PWR_GPIO_BIT_12
* @arg @ref LL_PWR_GPIO_BIT_13
* @arg @ref LL_PWR_GPIO_BIT_14
* @arg @ref LL_PWR_GPIO_BIT_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
{
return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
}
/**
* @brief Enable GPIO pull-down state in Standby and Shutdown modes
* @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
* PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
* PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
* PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
* PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
* PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
* PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
* @param GPIO This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_A
* @arg @ref LL_PWR_GPIO_B
* @arg @ref LL_PWR_GPIO_C
* @arg @ref LL_PWR_GPIO_D
* @arg @ref LL_PWR_GPIO_E
* @arg @ref LL_PWR_GPIO_F
* @arg @ref LL_PWR_GPIO_G
*
* (*) value not defined in all devices
* @param GPIONumber This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_BIT_0
* @arg @ref LL_PWR_GPIO_BIT_1
* @arg @ref LL_PWR_GPIO_BIT_2
* @arg @ref LL_PWR_GPIO_BIT_3
* @arg @ref LL_PWR_GPIO_BIT_4
* @arg @ref LL_PWR_GPIO_BIT_5
* @arg @ref LL_PWR_GPIO_BIT_6
* @arg @ref LL_PWR_GPIO_BIT_7
* @arg @ref LL_PWR_GPIO_BIT_8
* @arg @ref LL_PWR_GPIO_BIT_9
* @arg @ref LL_PWR_GPIO_BIT_10
* @arg @ref LL_PWR_GPIO_BIT_11
* @arg @ref LL_PWR_GPIO_BIT_12
* @arg @ref LL_PWR_GPIO_BIT_13
* @arg @ref LL_PWR_GPIO_BIT_14
* @arg @ref LL_PWR_GPIO_BIT_15
* @retval None
*/
__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
}
/**
* @brief Disable GPIO pull-down state in Standby and Shutdown modes
* @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
* PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
* PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
* PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
* PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
* PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
* PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
* @param GPIO This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_A
* @arg @ref LL_PWR_GPIO_B
* @arg @ref LL_PWR_GPIO_C
* @arg @ref LL_PWR_GPIO_D
* @arg @ref LL_PWR_GPIO_E
* @arg @ref LL_PWR_GPIO_F
* @arg @ref LL_PWR_GPIO_G
*
* (*) value not defined in all devices
* @param GPIONumber This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_BIT_0
* @arg @ref LL_PWR_GPIO_BIT_1
* @arg @ref LL_PWR_GPIO_BIT_2
* @arg @ref LL_PWR_GPIO_BIT_3
* @arg @ref LL_PWR_GPIO_BIT_4
* @arg @ref LL_PWR_GPIO_BIT_5
* @arg @ref LL_PWR_GPIO_BIT_6
* @arg @ref LL_PWR_GPIO_BIT_7
* @arg @ref LL_PWR_GPIO_BIT_8
* @arg @ref LL_PWR_GPIO_BIT_9
* @arg @ref LL_PWR_GPIO_BIT_10
* @arg @ref LL_PWR_GPIO_BIT_11
* @arg @ref LL_PWR_GPIO_BIT_12
* @arg @ref LL_PWR_GPIO_BIT_13
* @arg @ref LL_PWR_GPIO_BIT_14
* @arg @ref LL_PWR_GPIO_BIT_15
* @retval None
*/
__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
}
/**
* @brief Check if GPIO pull-down state is enabled
* @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
* PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
* PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
* PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
* PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
* PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
* PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
* @param GPIO This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_A
* @arg @ref LL_PWR_GPIO_B
* @arg @ref LL_PWR_GPIO_C
* @arg @ref LL_PWR_GPIO_D
* @arg @ref LL_PWR_GPIO_E
* @arg @ref LL_PWR_GPIO_F
* @arg @ref LL_PWR_GPIO_G
*
* (*) value not defined in all devices
* @param GPIONumber This parameter can be one of the following values:
* @arg @ref LL_PWR_GPIO_BIT_0
* @arg @ref LL_PWR_GPIO_BIT_1
* @arg @ref LL_PWR_GPIO_BIT_2
* @arg @ref LL_PWR_GPIO_BIT_3
* @arg @ref LL_PWR_GPIO_BIT_4
* @arg @ref LL_PWR_GPIO_BIT_5
* @arg @ref LL_PWR_GPIO_BIT_6
* @arg @ref LL_PWR_GPIO_BIT_7
* @arg @ref LL_PWR_GPIO_BIT_8
* @arg @ref LL_PWR_GPIO_BIT_9
* @arg @ref LL_PWR_GPIO_BIT_10
* @arg @ref LL_PWR_GPIO_BIT_11
* @arg @ref LL_PWR_GPIO_BIT_12
* @arg @ref LL_PWR_GPIO_BIT_13
* @arg @ref LL_PWR_GPIO_BIT_14
* @arg @ref LL_PWR_GPIO_BIT_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
{
return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Internal Wake-up line Flag
* @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR1, PWR_SR1_WUFI);
return ((temp == (PWR_SR1_WUFI))?1U:0U);
}
/**
* @brief Get Stand-By Flag
* @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR1, PWR_SR1_SBF);
return ((temp == (PWR_SR1_SBF))?1U:0U);
}
/**
* @brief Get Wake-up Flag 5
* @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR1, PWR_SR1_WUF5);
return ((temp == (PWR_SR1_WUF5))?1U:0U);
}
/**
* @brief Get Wake-up Flag 4
* @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR1, PWR_SR1_WUF4);
return ((temp == (PWR_SR1_WUF4))?1U:0U);
}
/**
* @brief Get Wake-up Flag 3
* @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR1, PWR_SR1_WUF3);
return ((temp == (PWR_SR1_WUF3))?1U:0U);
}
/**
* @brief Get Wake-up Flag 2
* @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR1, PWR_SR1_WUF2);
return ((temp == (PWR_SR1_WUF2))?1U:0U);
}
/**
* @brief Get Wake-up Flag 1
* @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR1, PWR_SR1_WUF1);
return ((temp == (PWR_SR1_WUF1))?1U:0U);
}
/**
* @brief Clear Stand-By Flag
* @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
}
/**
* @brief Clear Wake-up Flags
* @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
}
/**
* @brief Clear Wake-up Flag 5
* @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
}
/**
* @brief Clear Wake-up Flag 4
* @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
}
/**
* @brief Clear Wake-up Flag 3
* @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
}
/**
* @brief Clear Wake-up Flag 2
* @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
}
/**
* @brief Clear Wake-up Flag 1
* @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
* @retval None
*/
__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
{
WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
}
/**
* @brief Indicate whether VDDA voltage is below or above PVM4 threshold
* @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO4);
return ((temp == (PWR_SR2_PVMO4))?1U:0U);
}
/**
* @brief Indicate whether VDDA voltage is below or above PVM3 threshold
* @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO3);
return ((temp == (PWR_SR2_PVMO3))?1U:0U);
}
#if defined(PWR_SR2_PVMO2)
/**
* @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
* @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO2);
return ((temp == (PWR_SR2_PVMO2))?1U:0U);
}
#endif /* PWR_SR2_PVMO2 */
#if defined(PWR_SR2_PVMO1)
/**
* @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
* @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR2, PWR_SR2_PVMO1);
return ((temp == (PWR_SR2_PVMO1))?1U:0U);
}
#endif /* PWR_SR2_PVMO1 */
/**
* @brief Indicate whether VDD voltage is below or above the selected PVD threshold
* @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR2, PWR_SR2_PVDO);
return ((temp == (PWR_SR2_PVDO))?1U:0U);
}
/**
* @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
* @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR2, PWR_SR2_VOSF);
return ((temp == (PWR_SR2_VOSF))?1U:0U);
}
/**
* @brief Indicate whether the regulator is ready in main mode or is in low-power mode
* @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
* @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPF);
return ((temp == (PWR_SR2_REGLPF))?1U:0U);
}
/**
* @brief Indicate whether or not the low-power regulator is ready
* @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
{
uint32_t temp;
temp = READ_BIT(PWR->SR2, PWR_SR2_REGLPS);
return ((temp == (PWR_SR2_REGLPS))?1U:0U);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup PWR_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_PWR_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
* @{
*/
/* Old functions name kept for legacy purpose, to be replaced by the */
/* current functions name. */
#define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
#define LL_PWR_EnableUSBDeadBattery LL_PWR_EnableUCPDDeadBattery
#define LL_PWR_DisableUSBDeadBattery LL_PWR_DisableUCPDDeadBattery
#define LL_PWR_IsEnabledUSBDeadBattery LL_PWR_IsEnabledUCPDDeadBattery
#define LL_PWR_EnableDeadBatteryPD LL_PWR_EnableUCPDDeadBattery
#define LL_PWR_DisableDeadBatteryPD LL_PWR_DisableUCPDDeadBattery
#define LL_PWR_EnableUSBStandByModePD LL_PWR_EnableUCPDStandbyMode
#define LL_PWR_EnableStandByModePD LL_PWR_EnableUCPDStandbyMode
#define LL_PWR_DisableUSBStandByModePD LL_PWR_DisableUCPDStandbyMode
#define LL_PWR_DisableStandByModePD LL_PWR_DisableUCPDStandbyMode
#define LL_PWR_IsEnabledUSBStandByModePD LL_PWR_IsEnabledUCPDStandbyMode
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(PWR) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_PWR_H */
| 50,932 | C | 30.77355 | 154 | 0.578909 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smartcard_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_smartcard_ex.h
* @author MCD Application Team
* @brief Header file of SMARTCARD HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SMARTCARD_EX_H
#define STM32G4xx_HAL_SMARTCARD_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SMARTCARDEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Constants SMARTCARD Extended Exported Constants
* @{
*/
/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication
* @{
*/
#define SMARTCARD_TCBGT SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */
#define SMARTCARD_TC SMARTCARD_IT_TC /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type
* @{
*/
#define SMARTCARD_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */
#define SMARTCARD_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */
#define SMARTCARD_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */
#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */
#define SMARTCARD_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */
#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */
#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */
#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */
#define SMARTCARD_ADVFEATURE_TXCOMPLETION 0x00000100U /*!< TX completion indication before of after guard time */
/**
* @}
*/
/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
* @brief SMARTCARD FIFO mode
* @{
*/
#define SMARTCARD_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define SMARTCARD_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
* @brief SMARTCARD TXFIFO level
* @{
*/
#define SMARTCARD_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
#define SMARTCARD_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
#define SMARTCARD_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
#define SMARTCARD_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
#define SMARTCARD_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
#define SMARTCARD_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
/**
* @}
*/
/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
* @brief SMARTCARD RXFIFO level
* @{
*/
#define SMARTCARD_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
#define SMARTCARD_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
#define SMARTCARD_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
#define SMARTCARD_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
#define SMARTCARD_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
#define SMARTCARD_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define SMARTCARD_FLAG_TCBGT USART_ISR_TCBGT /*!< SMARTCARD transmission complete before guard time completion */
#define SMARTCARD_FLAG_REACK USART_ISR_REACK /*!< SMARTCARD receive enable acknowledge flag */
#define SMARTCARD_FLAG_TEACK USART_ISR_TEACK /*!< SMARTCARD transmit enable acknowledge flag */
#define SMARTCARD_FLAG_BUSY USART_ISR_BUSY /*!< SMARTCARD busy flag */
#define SMARTCARD_FLAG_EOBF USART_ISR_EOBF /*!< SMARTCARD end of block flag */
#define SMARTCARD_FLAG_RTOF USART_ISR_RTOF /*!< SMARTCARD receiver timeout flag */
#define SMARTCARD_FLAG_TXE USART_ISR_TXE_TXFNF /*!< SMARTCARD transmit data register empty */
#define SMARTCARD_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< SMARTCARD TXFIFO not full */
#define SMARTCARD_FLAG_TC USART_ISR_TC /*!< SMARTCARD transmission complete */
#define SMARTCARD_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD read data register not empty */
#define SMARTCARD_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< SMARTCARD RXFIFO not empty */
#define SMARTCARD_FLAG_IDLE USART_ISR_IDLE /*!< SMARTCARD idle line detection */
#define SMARTCARD_FLAG_ORE USART_ISR_ORE /*!< SMARTCARD overrun error */
#define SMARTCARD_FLAG_NE USART_ISR_NE /*!< SMARTCARD noise error */
#define SMARTCARD_FLAG_FE USART_ISR_FE /*!< SMARTCARD frame error */
#define SMARTCARD_FLAG_PE USART_ISR_PE /*!< SMARTCARD parity error */
#define SMARTCARD_FLAG_TXFE USART_ISR_TXFE /*!< SMARTCARD TXFIFO Empty flag */
#define SMARTCARD_FLAG_RXFF USART_ISR_RXFF /*!< SMARTCARD RXFIFO Full flag */
#define SMARTCARD_FLAG_RXFT USART_ISR_RXFT /*!< SMARTCARD RXFIFO threshold flag */
#define SMARTCARD_FLAG_TXFT USART_ISR_TXFT /*!< SMARTCARD TXFIFO threshold flag */
/**
* @}
*/
/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition
* Elements values convention: 000ZZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5 bits)
* - XX : Interrupt source register (2 bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZZ : Flag position in the ISR register(5 bits)
* @{
*/
#define SMARTCARD_IT_PE 0x0028U /*!< SMARTCARD parity error interruption */
#define SMARTCARD_IT_TXE 0x0727U /*!< SMARTCARD transmit data register empty interruption */
#define SMARTCARD_IT_TXFNF 0x0727U /*!< SMARTCARD TX FIFO not full interruption */
#define SMARTCARD_IT_TC 0x0626U /*!< SMARTCARD transmission complete interruption */
#define SMARTCARD_IT_RXNE 0x0525U /*!< SMARTCARD read data register not empty interruption */
#define SMARTCARD_IT_RXFNE 0x0525U /*!< SMARTCARD RXFIFO not empty interruption */
#define SMARTCARD_IT_IDLE 0x0424U /*!< SMARTCARD idle line detection interruption */
#define SMARTCARD_IT_ERR 0x0060U /*!< SMARTCARD error interruption */
#define SMARTCARD_IT_ORE 0x0300U /*!< SMARTCARD overrun error interruption */
#define SMARTCARD_IT_NE 0x0200U /*!< SMARTCARD noise error interruption */
#define SMARTCARD_IT_FE 0x0100U /*!< SMARTCARD frame error interruption */
#define SMARTCARD_IT_EOB 0x0C3BU /*!< SMARTCARD end of block interruption */
#define SMARTCARD_IT_RTO 0x0B3AU /*!< SMARTCARD receiver timeout interruption */
#define SMARTCARD_IT_TCBGT 0x1978U /*!< SMARTCARD transmission complete before guard time completion interruption */
#define SMARTCARD_IT_RXFF 0x183FU /*!< SMARTCARD RXFIFO full interruption */
#define SMARTCARD_IT_TXFE 0x173EU /*!< SMARTCARD TXFIFO empty interruption */
#define SMARTCARD_IT_RXFT 0x1A7CU /*!< SMARTCARD RXFIFO threshold reached interruption */
#define SMARTCARD_IT_TXFT 0x1B77U /*!< SMARTCARD TXFIFO threshold reached interruption */
/**
* @}
*/
/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags
* @{
*/
#define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< SMARTCARD parity error clear flag */
#define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< SMARTCARD framing error clear flag */
#define SMARTCARD_CLEAR_NEF USART_ICR_NECF /*!< SMARTCARD noise error detected clear flag */
#define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< SMARTCARD overrun error clear flag */
#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< SMARTCARD idle line detected clear flag */
#define SMARTCARD_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty Clear Flag */
#define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< SMARTCARD transmission complete clear flag */
#define SMARTCARD_CLEAR_TCBGTF USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */
#define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< SMARTCARD receiver time out clear flag */
#define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< SMARTCARD end of block clear flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros
* @{
*/
/** @brief Set the Transmission Completion flag
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
* AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
* to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
* @retval None
*/
#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__) \
do { \
if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION)) \
{ \
(__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC; \
} \
else \
{ \
assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \
} \
} while(0U)
/** @brief Return the transmission completion flag.
* @param __HANDLE__ specifies the SMARTCARD Handle.
* @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
* When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
* reported.
* @retval Transmission completion flag
*/
#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__) \
(((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) : (SMARTCARD_FLAG_TCBGT))
/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
* @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
* @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
*/
#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \
((__TXCOMPLETE__) == SMARTCARD_TC))
/** @brief Ensure that SMARTCARD FIFO mode is valid.
* @param __STATE__ SMARTCARD FIFO mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
* @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/* IO operation methods *******************************************************/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group1
* @{
*/
/* Peripheral Control functions ***********************************************/
void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);
void HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);
void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);
/**
* @}
*/
/** @addtogroup SMARTCARDEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);
HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SMARTCARD_EX_H */
| 18,441 | C | 53.724035 | 143 | 0.543409 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_fmac.h | /**
******************************************************************************
* @file stm32g4xx_hal_fmac.h
* @author MCD Application Team
* @brief Header for stm32g4xx_hal_fmac.c module
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_FMAC_H
#define STM32G4xx_HAL_FMAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(FMAC)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup FMAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FMAC_Exported_Types FMAC Exported Types
* @{
*/
/**
* @brief FMAC HAL State Structure definition
*/
typedef enum
{
HAL_FMAC_STATE_RESET = 0x00U, /*!< FMAC not yet initialized or disabled */
HAL_FMAC_STATE_READY = 0x20U, /*!< FMAC initialized and ready for use */
HAL_FMAC_STATE_BUSY = 0x24U, /*!< FMAC internal process is ongoing */
HAL_FMAC_STATE_BUSY_RD = 0x25U, /*!< FMAC reading configuration is ongoing */
HAL_FMAC_STATE_BUSY_WR = 0x26U, /*!< FMAC writing configuration is ongoing */
HAL_FMAC_STATE_TIMEOUT = 0xA0U, /*!< FMAC in Timeout state */
HAL_FMAC_STATE_ERROR = 0xE0U /*!< FMAC in Error state */
} HAL_FMAC_StateTypeDef;
/**
* @brief FMAC Handle Structure definition
*/
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
typedef struct __FMAC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
{
FMAC_TypeDef *Instance; /*!< Register base address */
uint32_t FilterParam; /*!< Filter configuration (operation and parameters).
Set to 0 if no valid configuration was applied. */
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
int16_t *pInput; /*!< Pointer to FMAC input data buffer */
uint16_t InputCurrentSize; /*!< Number of the input elements already written into FMAC */
uint16_t *pInputSize; /*!< Number of input elements to write (memory allocated to pInput).
In case of early interruption of the filter operation,
its value will be updated. */
int16_t *pOutput; /*!< Pointer to FMAC output data buffer */
uint16_t OutputCurrentSize; /*!< Number of the output elements already read from FMAC */
uint16_t *pOutputSize; /*!< Number of output elements to read (memory allocated to pOutput).
In case of early interruption of the filter operation,
its value will be updated. */
DMA_HandleTypeDef *hdmaIn; /*!< FMAC peripheral input data DMA handle parameters */
DMA_HandleTypeDef *hdmaOut; /*!< FMAC peripheral output data DMA handle parameters */
DMA_HandleTypeDef *hdmaPreload; /*!< FMAC peripheral preloaded data (X1, X2 and Y) DMA handle parameters */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
void (* ErrorCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC error callback */
void (* HalfGetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get half data callback */
void (* GetDataCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC get data callback */
void (* HalfOutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC half output data ready callback */
void (* OutputDataReadyCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC output data ready callback */
void (* FilterConfigCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter configuration callback */
void (* FilterPreloadCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC filter preload callback */
void (* MspInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp Init callback */
void (* MspDeInitCallback)(struct __FMAC_HandleTypeDef *hfmac); /*!< FMAC Msp DeInit callback */
#endif /* (USE_HAL_FMAC_REGISTER_CALLBACKS) */
HAL_LockTypeDef Lock; /*!< FMAC locking object */
__IO HAL_FMAC_StateTypeDef State; /*!< FMAC state related to global handle management
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
__IO HAL_FMAC_StateTypeDef RdState; /*!< FMAC state related to read operations (access to Y buffer)
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
__IO HAL_FMAC_StateTypeDef WrState; /*!< FMAC state related to write operations (access to X1 buffer)
This parameter can be a value of @ref HAL_FMAC_StateTypeDef */
__IO uint32_t ErrorCode; /*!< FMAC peripheral error code
This parameter can be a value of @ref FMAC_Error_Code */
} FMAC_HandleTypeDef;
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
/**
* @brief FMAC Callback ID enumeration definition
*/
typedef enum
{
HAL_FMAC_ERROR_CB_ID = 0x00U, /*!< FMAC error callback ID */
HAL_FMAC_HALF_GET_DATA_CB_ID = 0x01U, /*!< FMAC get half data callback ID */
HAL_FMAC_GET_DATA_CB_ID = 0x02U, /*!< FMAC get data callback ID */
HAL_FMAC_HALF_OUTPUT_DATA_READY_CB_ID = 0x03U, /*!< FMAC half output data ready callback ID */
HAL_FMAC_OUTPUT_DATA_READY_CB_ID = 0x04U, /*!< FMAC output data ready callback ID */
HAL_FMAC_FILTER_CONFIG_CB_ID = 0x05U, /*!< FMAC filter configuration callback ID */
HAL_FMAC_FILTER_PRELOAD_CB_ID = 0x06U, /*!< FMAC filter preload callback ID */
HAL_FMAC_MSPINIT_CB_ID = 0x07U, /*!< FMAC MspInit callback ID */
HAL_FMAC_MSPDEINIT_CB_ID = 0x08U, /*!< FMAC MspDeInit callback ID */
} HAL_FMAC_CallbackIDTypeDef;
/**
* @brief HAL FMAC Callback pointer definition
*/
typedef void (*pFMAC_CallbackTypeDef)(FMAC_HandleTypeDef *hfmac); /*!< pointer to an FMAC callback function */
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
/**
* @brief FMAC Filter Configuration Structure definition
*/
typedef struct
{
uint8_t InputBaseAddress; /*!< Base address of the input buffer (X1) within the internal memory (0x00 to 0xFF).
Ignored if InputBufferSize is set to 0
(previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t InputBufferSize; /*!< Number of 16-bit words allocated to the input buffer (including the optional "headroom").
0 if a previous configuration should be kept. */
uint32_t InputThreshold; /*!< Input threshold: the buffer full flag will be set if the number of free spaces
in the buffer is lower than this threshold.
This parameter can be a value
of @ref FMAC_Data_Buffer_Threshold. */
uint8_t CoeffBaseAddress; /*!< Base address of the coefficient buffer (X2) within the internal memory (0x00 to 0xFF).
Ignored if CoeffBufferSize is set to 0
(previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t CoeffBufferSize; /*!< Number of 16-bit words allocated to the coefficient buffer.
0 if a previous configuration should be kept. */
uint8_t OutputBaseAddress; /*!< Base address of the output buffer (Y) within the internal memory (0x00 to 0xFF).
Ignored if OuputBufferSize is set to 0
(previous configuration kept).
Note: the buffers can overlap or even coincide exactly. */
uint8_t OutputBufferSize; /*!< Number of 16-bit words allocated to the output buffer (including the optional "headroom").
0 if a previous configuration should be kept. */
uint32_t OutputThreshold; /*!< Output threshold: the buffer empty flag will be set if the number of unread values
in the buffer is lower than this threshold.
This parameter can be a value
of @ref FMAC_Data_Buffer_Threshold. */
int16_t *pCoeffA; /*!< [IIR only] Initialization of the coefficient vector A.
If not needed, it should be set to NULL. */
uint8_t CoeffASize; /*!< Size of the coefficient vector A. */
int16_t *pCoeffB; /*!< Initialization of the coefficient vector B.
If not needed (re-use of a previously loaded buffer),
it should be set to NULL. */
uint8_t CoeffBSize; /*!< Size of the coefficient vector B. */
uint8_t InputAccess; /*!< Access to the input buffer (internal memory area): DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint8_t OutputAccess; /*!< Access to the output buffer (internal memory area): DMA, IT, Polling, None.
This parameter can be a value of @ref FMAC_Buffer_Access. */
uint32_t Clip; /*!< Enable or disable the clipping feature. If the q1.15 range is exceeded, wrapping
is done when the clipping feature is disabled
and saturation is done when the clipping feature is enabled.
This parameter can be a value of @ref FMAC_Clip_State. */
uint32_t Filter; /*!< Filter type.
This parameter can be a value
of @ref FMAC_Functions (filter related values). */
uint8_t P; /*!< Parameter P (vector length, number of filter taps, etc.). */
uint8_t Q; /*!< Parameter Q (vector length, etc.). Ignored if not needed. */
uint8_t R; /*!< Parameter R (gain, etc.). Ignored if not needed. */
} FMAC_FilterConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FMAC_Exported_Constants FMAC Exported Constants
* @{
*/
/** @defgroup FMAC_Error_Code FMAC Error code
* @{
*/
#define HAL_FMAC_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FMAC_ERROR_SAT 0x00000001U /*!< Saturation error */
#define HAL_FMAC_ERROR_UNFL 0x00000002U /*!< Underflow error */
#define HAL_FMAC_ERROR_OVFL 0x00000004U /*!< Overflow error */
#define HAL_FMAC_ERROR_DMA 0x00000008U /*!< DMA error */
#define HAL_FMAC_ERROR_RESET 0x00000010U /*!< Reset error */
#define HAL_FMAC_ERROR_PARAM 0x00000020U /*!< Parameter error */
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
#define HAL_FMAC_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid Callback error */
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
#define HAL_FMAC_ERROR_TIMEOUT 0x00000080U /*!< Timeout error */
/**
* @}
*/
/** @defgroup FMAC_Functions FMAC Functions
* @{
*/
#define FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
#define FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
#define FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
#define FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
#define FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
/**
* @}
*/
/** @defgroup FMAC_Data_Buffer_Threshold FMAC Data Buffer Threshold
* @{
* @note This parameter sets a watermark for buffer full (input) or buffer empty (output).
*/
#define FMAC_THRESHOLD_1 0x00000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 1.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 1. */
#define FMAC_THRESHOLD_2 0x01000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 2.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 2. */
#define FMAC_THRESHOLD_4 0x02000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 4.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 4. */
#define FMAC_THRESHOLD_8 0x03000000U /*!< Input: Buffer full flag set if the number of free spaces in the buffer is less than 8.
Output: Buffer empty flag set if the number
of unread values in the buffer is less than 8. */
#define FMAC_THRESHOLD_NO_VALUE 0xFFFFFFFFU /*!< The configured threshold value shouldn't be changed */
/**
* @}
*/
/** @defgroup FMAC_Buffer_Access FMAC Buffer Access
* @{
*/
#define FMAC_BUFFER_ACCESS_NONE 0x00U /*!< Buffer handled by an external IP (ADC for instance) */
#define FMAC_BUFFER_ACCESS_DMA 0x01U /*!< Buffer accessed through DMA */
#define FMAC_BUFFER_ACCESS_POLLING 0x02U /*!< Buffer accessed through polling */
#define FMAC_BUFFER_ACCESS_IT 0x03U /*!< Buffer accessed through interruptions */
/**
* @}
*/
/** @defgroup FMAC_Clip_State FMAC Clip State
* @{
*/
#define FMAC_CLIP_DISABLED 0x00000000U /*!< Clipping disabled */
#define FMAC_CLIP_ENABLED FMAC_CR_CLIPEN /*!< Clipping enabled */
/**
* @}
*/
/** @defgroup FMAC_Flags FMAC status flags
* @{
*/
#define FMAC_FLAG_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
#define FMAC_FLAG_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
#define FMAC_FLAG_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
#define FMAC_FLAG_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
#define FMAC_FLAG_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
/**
* @}
*/
/** @defgroup FMAC_Interrupts_Enable FMAC Interrupts Enable bit
* @{
*/
#define FMAC_IT_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
#define FMAC_IT_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
#define FMAC_IT_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
#define FMAC_IT_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
#define FMAC_IT_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
/**
* @}
*/
/**
* @}
*/
/* External variables --------------------------------------------------------*/
/** @defgroup FMAC_External_variables FMAC External variables
* @{
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup FMAC_Exported_Macros FMAC Exported Macros
* @{
*/
/** @brief Reset FMAC handle state.
* @param __HANDLE__ FMAC handle.
* @retval None
*/
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_FMAC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_FMAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMAC_STATE_RESET)
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
/**
* @brief Enable the specified FMAC interrupt
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC Interrupt.
* This parameter can be any combination of the following values:
* @arg @ref FMAC_IT_RIEN Read interrupt enable
* @arg @ref FMAC_IT_WIEN Write interrupt enable
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
* @retval None
*/
#define __HAL_FMAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/**
* @brief Disable the FMAC interrupt
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC Interrupt.
* This parameter can be any combination of the following values:
* @arg @ref FMAC_IT_RIEN Read interrupt enable
* @arg @ref FMAC_IT_WIEN Write interrupt enable
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
* @retval None
*/
#define __HAL_FMAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified FMAC interrupt occurred or not.
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC interrupt to check.
* This parameter can be any combination of the following values:
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
* @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
* @arg @ref FMAC_FLAG_SAT Saturation Error Flag
* @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
*/
#define __HAL_FMAC_GET_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->SR) &= ~(__INTERRUPT__))
/** @brief Clear specified FMAC interrupt status. Dummy macro as the
interrupt status flags are read-only.
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC interrupt to clear.
* @retval None
*/
#define __HAL_FMAC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
/** @brief Check whether the specified FMAC status flag is set or not.
* @param __HANDLE__ FMAC handle.
* @param __FLAG__ FMAC flag to check.
* This parameter can be any combination of the following values:
* @arg @ref FMAC_FLAG_YEMPTY Y Buffer Empty Flag
* @arg @ref FMAC_FLAG_X1FULL X1 Buffer Full Flag
* @arg @ref FMAC_FLAG_OVFL Overflow Error Flag
* @arg @ref FMAC_FLAG_UNFL Underflow Error Flag
* @arg @ref FMAC_FLAG_SAT Saturation error Flag
* @retval SET (flag is set) or RESET (flag is reset)
*/
#define __HAL_FMAC_GET_FLAG(__HANDLE__, __FLAG__) \
((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear specified FMAC status flag. Dummy macro as no
flag can be cleared.
* @param __HANDLE__ FMAC handle.
* @param __FLAG__ FMAC flag to clear.
* @retval None
*/
#define __HAL_FMAC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
/** @brief Check whether the specified FMAC interrupt is enabled or not.
* @param __HANDLE__ FMAC handle.
* @param __INTERRUPT__ FMAC interrupt to check.
* This parameter can be one of the following values:
* @arg @ref FMAC_IT_RIEN Read interrupt enable
* @arg @ref FMAC_IT_WIEN Write interrupt enable
* @arg @ref FMAC_IT_OVFLIEN Overflow error interrupt enable
* @arg @ref FMAC_IT_UNFLIEN Underflow error interrupt enable
* @arg @ref FMAC_IT_SATIEN Saturation error interrupt enable (this helps in debugging a filter)
* @retval FlagStatus
*/
#define __HAL_FMAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CR) & (__INTERRUPT__))
/**
* @}
*/
/* Private Macros-----------------------------------------------------------*/
/** @addtogroup FMAC_Private_Macros FMAC Private Macros
* @{
*/
/**
* @brief Verify the FMAC function.
* @param __FUNCTION__ ID of the function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
#define IS_FMAC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
((__FUNCTION__) == FMAC_FUNC_LOAD_Y) || \
((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
/**
* @brief Verify the FMAC load function used for input data, output data or coefficients.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
#define IS_FMAC_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
((__FUNCTION__) == FMAC_FUNC_LOAD_X2) || \
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
/**
* @brief Verify the FMAC load function used with N values as input or output data.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
#define IS_FMAC_N_LOAD_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_LOAD_X1) || \
((__FUNCTION__) == FMAC_FUNC_LOAD_Y))
/**
* @brief Verify the FMAC load function used with N + M values as coefficients.
* @param __FUNCTION__ ID of the load function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
#define IS_FMAC_N_M_LOAD_FUNCTION(__FUNCTION__) ((__FUNCTION__) == FMAC_FUNC_LOAD_X2)
/**
* @brief Verify the FMAC filter function.
* @param __FUNCTION__ ID of the filter function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
#define IS_FMAC_FILTER_FUNCTION(__FUNCTION__) (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1))
/**
* @brief Verify the FMAC threshold.
* @param __THRESHOLD__ Value of the threshold.
* @retval SET (__THRESHOLD__ is a valid value) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_FMAC_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == FMAC_THRESHOLD_1) || \
((__THRESHOLD__) == FMAC_THRESHOLD_2) || \
((__THRESHOLD__) == FMAC_THRESHOLD_4) || \
((__THRESHOLD__) == FMAC_THRESHOLD_NO_VALUE) || \
((__THRESHOLD__) == FMAC_THRESHOLD_8))
/**
* @brief Verify the FMAC filter parameter P.
* @param __P__ Value of the filter parameter P.
* @param __FUNCTION__ ID of the filter function.
* @retval SET (__P__ is a valid value) or RESET (__P__ is invalid)
*/
#define IS_FMAC_PARAM_P(__FUNCTION__, __P__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) && \
(((__P__) >= 2U) && ((__P__) <= 127U))) || \
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
(((__P__) >= 2U) && ((__P__) <= 64U))) )
/**
* @brief Verify the FMAC filter parameter Q.
* @param __Q__ Value of the filter parameter Q.
* @param __FUNCTION__ ID of the filter function.
* @retval SET (__Q__ is a valid value) or RESET (__Q__ is invalid)
*/
#define IS_FMAC_PARAM_Q(__FUNCTION__, __Q__) ( ((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
(((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1) && \
(((__Q__) >= 1U) && ((__Q__) <= 63U))) )
/**
* @brief Verify the FMAC filter parameter R.
* @param __R__ Value of the filter parameter.
* @param __FUNCTION__ ID of the filter function.
* @retval SET (__R__ is a valid value) or RESET (__R__ is invalid)
*/
#define IS_FMAC_PARAM_R(__FUNCTION__, __R__) ( (((__FUNCTION__) == FMAC_FUNC_CONVO_FIR) || \
((__FUNCTION__) == FMAC_FUNC_IIR_DIRECT_FORM_1)) && \
((__R__) <= 7U))
/**
* @brief Verify the FMAC buffer access.
* @param __BUFFER_ACCESS__ Type of access.
* @retval SET (__BUFFER_ACCESS__ is a valid value) or RESET (__BUFFER_ACCESS__ is invalid)
*/
#define IS_FMAC_BUFFER_ACCESS(__BUFFER_ACCESS__) (((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_NONE) || \
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_DMA) || \
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_POLLING) || \
((__BUFFER_ACCESS__) == FMAC_BUFFER_ACCESS_IT))
/**
* @brief Verify the FMAC clip feature.
* @param __CLIP_STATE__ Clip state.
* @retval SET (__CLIP_STATE__ is a valid value) or RESET (__CLIP_STATE__ is invalid)
*/
#define IS_FMAC_CLIP_STATE(__CLIP_STATE__) (((__CLIP_STATE__) == FMAC_CLIP_DISABLED) || \
((__CLIP_STATE__) == FMAC_CLIP_ENABLED))
/**
* @brief Check whether the threshold is applicable.
* @param __SIZE__ Size of the matching buffer.
* @param __WM__ Watermark value.
* @param __ACCESS__ Access to the buffer (polling, it, dma, none).
* @retval THRESHOLD
*/
#define IS_FMAC_THRESHOLD_APPLICABLE(__SIZE__, __WM__, __ACCESS__) \
(( (__SIZE__) >= (((__WM__) == FMAC_THRESHOLD_1)? 1U: \
((__WM__) == FMAC_THRESHOLD_2)? 2U: \
((__WM__) == FMAC_THRESHOLD_4)? 4U:8U))&& \
((((__ACCESS__) == FMAC_BUFFER_ACCESS_DMA)&& \
((__WM__) == FMAC_THRESHOLD_1))|| \
((__ACCESS__ )!= FMAC_BUFFER_ACCESS_DMA)))
/**
* @}
*/
/* Exported functions ------------------------------------------------------- */
/** @addtogroup FMAC_Exported_Functions
* @{
*/
/** @addtogroup FMAC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac);
HAL_StatusTypeDef HAL_FMAC_DeInit(FMAC_HandleTypeDef *hfmac);
void HAL_FMAC_MspInit(FMAC_HandleTypeDef *hfmac);
void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef *hfmac);
#if (USE_HAL_FMAC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_FMAC_RegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID,
pFMAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_FMAC_UnRegisterCallback(FMAC_HandleTypeDef *hfmac, HAL_FMAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup FMAC_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_FMAC_FilterConfig(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
HAL_StatusTypeDef HAL_FMAC_FilterConfig_DMA(FMAC_HandleTypeDef *hfmac, FMAC_FilterConfigTypeDef *pConfig);
HAL_StatusTypeDef HAL_FMAC_FilterPreload(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize);
HAL_StatusTypeDef HAL_FMAC_FilterPreload_DMA(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint8_t InputSize,
int16_t *pOutput, uint8_t OutputSize);
HAL_StatusTypeDef HAL_FMAC_FilterStart(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
HAL_StatusTypeDef HAL_FMAC_AppendFilterData(FMAC_HandleTypeDef *hfmac, int16_t *pInput, uint16_t *pInputSize);
HAL_StatusTypeDef HAL_FMAC_ConfigFilterOutputBuffer(FMAC_HandleTypeDef *hfmac, int16_t *pOutput, uint16_t *pOutputSize);
HAL_StatusTypeDef HAL_FMAC_PollFilterData(FMAC_HandleTypeDef *hfmac, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMAC_FilterStop(FMAC_HandleTypeDef *hfmac);
/**
* @}
*/
/** @addtogroup FMAC_Exported_Functions_Group3
* @{
*/
/* Callback functions *********************************************************/
void HAL_FMAC_ErrorCallback(FMAC_HandleTypeDef *hfmac);
void HAL_FMAC_HalfGetDataCallback(FMAC_HandleTypeDef *hfmac);
void HAL_FMAC_GetDataCallback(FMAC_HandleTypeDef *hfmac);
void HAL_FMAC_HalfOutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
void HAL_FMAC_OutputDataReadyCallback(FMAC_HandleTypeDef *hfmac);
void HAL_FMAC_FilterConfigCallback(FMAC_HandleTypeDef *hfmac);
void HAL_FMAC_FilterPreloadCallback(FMAC_HandleTypeDef *hfmac);
/**
* @}
*/
/** @addtogroup FMAC_Exported_Functions_Group4
* @{
*/
/* IRQ handler management *****************************************************/
void HAL_FMAC_IRQHandler(FMAC_HandleTypeDef *hfmac);
/**
* @}
*/
/** @addtogroup FMAC_Exported_Functions_Group5
* @{
*/
/* Peripheral State functions *************************************************/
HAL_FMAC_StateTypeDef HAL_FMAC_GetState(FMAC_HandleTypeDef *hfmac);
uint32_t HAL_FMAC_GetError(FMAC_HandleTypeDef *hfmac);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FMAC */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_FMAC_H */
| 33,938 | C | 48.115774 | 151 | 0.515646 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h | /**
******************************************************************************
* @file stm32g4xx_hal_hrtim.h
* @author MCD Application Team
* @brief Header file of HRTIM HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_HRTIM_H
#define STM32G4xx_HAL_HRTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(HRTIM1)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup HRTIM HRTIM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
* @{
*/
/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
* @{
*/
#define MAX_HRTIM_TIMER 7U
/**
* @}
*/
/**
* @}
*/
/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
* @{
*/
/**
* @brief HRTIM Configuration Structure definition - Time base related parameters
*/
typedef struct
{
uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals.
The HRTIM instance can be configured to act as a slave (waiting for a trigger
to be synchronized) or a master (generating a synchronization signal) or both.
This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
the HRTIM instance is configured as a slave).
This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
(significant only when the HRTIM instance is configured as a master).
This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
outputs (significant only when the HRTIM instance is configured as a master).
This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
} HRTIM_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_HRTIM_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */
HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */
#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U /*!< Invalid Callback error */
#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
} HAL_HRTIM_StateTypeDef;
/**
* @brief HRTIM Timer Structure definition
*/
typedef struct
{
uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1.
When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2.
When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */
uint32_t DMARequests; /*!< DMA requests enabled for the timer. */
uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */
uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */
uint32_t DMASize; /*!< Size of the DMA transfer */
} HRTIM_TimerParamTypeDef;
/**
* @brief HRTIM Handle Structure definition
*/
#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
typedef struct __HRTIM_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
{
HRTIM_TypeDef * Instance; /*!< Register base address */
HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */
HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */
DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */
DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */
DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */
DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */
DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */
DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */
DMA_HandleTypeDef * hdmaTimerF; /*!< Timer F DMA handle parameters */
#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */
void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 2 interrupt callback function pointer */
void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 3 interrupt callback function pointer */
void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 4 interrupt callback function pointer */
void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 5 interrupt callback function pointer */
void (* Fault6Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 6 interrupt callback function pointer */
void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< System fault interrupt callback function pointer */
void (* DLLCalibrationReadyCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DLL Ready interrupt callback function pointer */
void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Burst mode period interrupt callback function pointer */
void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Sync Input interrupt callback function pointer */
void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DMA error callback function pointer */
void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Update interrupt callback function pointer */
void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Repetition interrupt callback function pointer */
void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 1 match interrupt callback function pointer */
void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 2 match interrupt callback function pointer */
void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 3 match interrupt callback function pointer */
void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 4 match interrupt callback function pointer */
void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 1 interrupts callback function pointer */
void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 2 interrupts callback function pointer */
void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer */
void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x counter reset/roll-over interrupt callback function pointer */
void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 set interrupt callback function pointer */
void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 reset interrupt callback function pointer */
void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 set interrupt callback function pointer */
void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 reset interrupt callback function pointer */
void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Burst DMA completed interrupt callback function pointer */
void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */
void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */
#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
} HRTIM_HandleTypeDef;
/**
* @brief Simple output compare mode configuration definition
*/
typedef struct
{
uint32_t Period; /*!< Specifies the timer period.
The period value must be above 3 periods of the fHRTIM clock.
Maximum value is = 0xFFDFU */
uint32_t RepetitionCounter; /*!< Specifies the timer repetition period.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
uint32_t Mode; /*!< Specifies the counter operating mode.
This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */
} HRTIM_TimeBaseCfgTypeDef;
/**
* @brief Simple output compare mode configuration definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive).
This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
The compare value must be above or equal to 3 periods of the fHRTIM clock */
uint32_t Polarity; /*!< Specifies the output polarity.
This parameter can be any value of @ref HRTIM_Output_Polarity */
uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
} HRTIM_SimpleOCChannelCfgTypeDef;
/**
* @brief Simple PWM output mode configuration definition
*/
typedef struct
{
uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
The compare value must be above or equal to 3 periods of the fHRTIM clock */
uint32_t Polarity; /*!< Specifies the output polarity.
This parameter can be any value of @ref HRTIM_Output_Polarity */
uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
} HRTIM_SimplePWMChannelCfgTypeDef;
/**
* @brief Simple capture mode configuration definition
*/
typedef struct
{
uint32_t Event; /*!< Specifies the external event triggering the capture.
This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
This parameter can be a value of @ref HRTIM_External_Event_Polarity */
uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
This parameter can be a value of @ref HRTIM_External_Event_Filter */
} HRTIM_SimpleCaptureChannelCfgTypeDef;
/**
* @brief Simple One Pulse mode configuration definition
*/
typedef struct
{
uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
The compare value must be above or equal to 3 periods of the fHRTIM clock */
uint32_t OutputPolarity; /*!< Specifies the output polarity.
This parameter can be any value of @ref HRTIM_Output_Polarity */
uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
uint32_t Event; /*!< Specifies the external event triggering the pulse generation.
This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
This parameter can be a value of @ref HRTIM_External_Event_Polarity */
uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event.
This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
This parameter can be a value of @ref HRTIM_External_Event_Filter */
} HRTIM_SimpleOnePulseChannelCfgTypeDef;
/**
* @brief Timer configuration definition
*/
typedef struct
{
uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master.
Specifies which interrupts requests must enabled for the timer.
This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
or @ref HRTIM_Timing_Unit_Interrupt_Enable */
uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master.
Specifies which DMA requests must be enabled for the timer.
This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master.
Specifies the address of the source address of the DMA transfer */
uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master.
Specifies the address of the destination address of the DMA transfer */
uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master.
Specifies the size of the DMA transfer */
uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master.
Specifies whether or not half mode is enabled
This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
uint32_t InterleavedMode; /*!< Relevant for all HRTIM timers, including the master.
Specifies whether or not half mode is enabled
This parameter can be any value of @ref HRTIM_Interleaved_Mode */
uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master.
Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master.
Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master.
Indicates whether or not the a DAC synchronization event is generated.
This parameter can be any value of @ref HRTIM_DAC_Synchronization */
uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master.
Specifies whether or not register preload is enabled.
This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master.
Specifies how the update occurs with respect to a burst DMA transaction or
update enable inputs (Slave timers only).
This parameter can be any value of @ref HRTIM_Update_Gating */
uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master.
Specifies how the timer behaves during a burst mode operation.
This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master.
Specifies whether or not registers update is triggered by the repetition event.
This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
uint32_t PushPull; /*!< Relevant for Timer A to Timer F.
Specifies whether or not the push-pull mode is enabled.
This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
uint32_t FaultEnable; /*!< Relevant for Timer A to Timer F.
Specifies which fault channels are enabled for the timer.
This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
uint32_t FaultLock; /*!< Relevant for Timer A to Timer F.
Specifies whether or not fault enabling status is write protected.
This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer F.
Specifies whether or not dead-time insertion is enabled for the timer.
This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer F.
Specifies the delayed protection mode.
This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
uint32_t BalancedIdleAutomaticResume; /*!< Indicates whether or not outputs are automatically re-enabled after a balanced idle event.
This parameters can be any value of @ref HRTIM_Output_Balanced_Idle_Auto_Resume */
uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer F.
Specifies source(s) triggering the timer registers update.
This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer F.
Specifies source(s) triggering the timer counter reset.
This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer F.
Specifies whether or not registers update is triggered when the timer counter is reset.
This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
uint32_t ReSyncUpdate; /*!< Relevant for Timer A to Timer F.
Specifies whether update source is coming from the timing unit @ref HRTIM_Timer_ReSyncUpdate */
} HRTIM_TimerCfgTypeDef;
/**
* @brief Timer control definition
*/
typedef struct
{
uint32_t UpDownMode; /*!< Relevant for Timer A to Timer F.
Specifies whether or not counter is operating in up or up-down counting mode.
This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode */
uint32_t TrigHalf; /*!< Relevant for Timer A to Timer F.
Specifies whether or not compare 2 is operating in Trigger half mode.
This parameter can be a value of @ref HRTIM_Timer_TrigHalf_Mode */
uint32_t GreaterCMP3; /*!< Relevant for Timer A to Timer F.
Specifies whether or not compare 3 is operating in compare match or greater mode.
This parameter can be a value of @ref HRTIM_Timer_GreaterCMP3_Mode */
uint32_t GreaterCMP1; /*!< Relevant for Timer A to Timer F.
Specifies whether or not compare 1 is operating in compare match or greater mode.
This parameter can be a value of @ref HRTIM_Timer_GreaterCMP1_Mode */
uint32_t DualChannelDacReset; /*!< Relevant for Timer A to Timer F.
Specifies how the hrtim_dac_reset_trgx trigger is generated.
This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Reset */
uint32_t DualChannelDacStep; /*!< Relevant for Timer A to Timer F.
Specifies how the hrtim_dac_step_trgx trigger is generated.
This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Step */
uint32_t DualChannelDacEnable; /*!< Relevant for Timer A to Timer F.
Enables or not the dual channel DAC triggering mechanism.
This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Enable */
} HRTIM_TimerCtlTypeDef;
/**
* @brief Compare unit configuration definition
*/
typedef struct
{
uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit.
The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4.
This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */
} HRTIM_CompareCfgTypeDef;
/**
* @brief Capture unit content definition
*/
typedef struct
{
uint32_t Value; /*!< Holds the counter value when the capture event occurred.
This parameter can be a number between 0x0 and 0xFFFFU */
uint32_t Dir ; /*!< Holds the counting direction value when the capture event occurred.
This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode */
} HRTIM_CaptureValueTypeDef;
/**
* @brief Capture unit configuration definition
*/
typedef struct
{
uint64_t Trigger; /*!< Specifies source(s) triggering the capture.
This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
} HRTIM_CaptureCfgTypeDef;
/**
* @brief Output configuration definition
*/
typedef struct
{
uint32_t Polarity; /*!< Specifies the output polarity.
This parameter can be any value of @ref HRTIM_Output_Polarity */
uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
This parameter can be a combination of @ref HRTIM_Output_Set_Source */
uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
} HRTIM_OutputCfgTypeDef;
/**
* @brief External event filtering in timing units configuration definition
*/
typedef struct
{
uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit.
This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
uint32_t Latch; /*!< Specifies whether or not the signal is latched.
This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
} HRTIM_TimerEventFilteringCfgTypeDef;
/**
* @brief Dead time feature configuration definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the dead-time prescaler.
This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge.
This parameter can be a number between 0x0 and 0x1FFU */
uint32_t RisingSign; /*!< Specifies whether the dead-time is positive or negative on rising edge.
This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
uint32_t RisingLock; /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected.
This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
uint32_t RisingSignLock; /*!< Specifies whether or not dead-time rising sign is write protected.
This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
uint32_t FallingValue; /*!< Specifies the dead-time following a falling edge.
This parameter can be a number between 0x0 and 0x1FFU */
uint32_t FallingSign; /*!< Specifies whether the dead-time is positive or negative on falling edge.
This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
uint32_t FallingLock; /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected.
This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
uint32_t FallingSignLock; /*!< Specifies whether or not dead-time falling sign is write protected.
This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
} HRTIM_DeadTimeCfgTypeDef;
/**
* @brief Chopper mode configuration definition
*/
typedef struct
{
uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value.
This parameter can be a value of @ref HRTIM_Chopper_Frequency */
uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value.
This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
uint32_t StartPulse; /*!< Specifies the Timer pulse width value.
This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
} HRTIM_ChopperModeCfgTypeDef;
/**
* @brief External event channel configuration definition
*/
typedef struct
{
uint32_t Source; /*!< Identifies the source of the external event.
This parameter can be a value of @ref HRTIM_External_Event_Sources */
uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
This parameter can be a value of @ref HRTIM_External_Event_Polarity */
uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event.
This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
This parameter can be a value of @ref HRTIM_External_Event_Filter */
uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event.
This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
} HRTIM_EventCfgTypeDef;
/**
* @brief Fault channel configuration definition
*/
typedef struct
{
uint32_t Source; /*!< Identifies the source of the fault.
This parameter can be a value of @ref HRTIM_Fault_Sources */
uint32_t Polarity; /*!< Specifies the polarity of the fault event.
This parameter can be a value of @ref HRTIM_Fault_Polarity */
uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
This parameter can be a value of @ref HRTIM_Fault_Filter */
uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected.
This parameter can be a value of @ref HRTIM_Fault_Lock */
} HRTIM_FaultCfgTypeDef;
typedef struct
{
uint32_t Threshold; /*!< Specifies the Fault counter Threshold.
This parameter can be a number between 0x0 and 0xF */
uint32_t ResetMode; /*!< Specifies the reset mode of a fault event counter.
This parameter can be a value of @ref HRTIM_Fault_ResetMode */
uint32_t BlankingSource;/*!< Specifies the blanking source of a fault event.
This parameter can be a value of @ref HRTIM_Fault_Blanking */
} HRTIM_FaultBlankingCfgTypeDef;
/**
* @brief Burst mode configuration definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the burst mode operating mode.
This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
uint32_t ClockSource; /*!< Specifies the burst mode clock source.
This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
uint32_t Prescaler; /*!< Specifies the burst mode prescaler.
This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation.
This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state.
This parameter can be a number between 0x0 and 0xFFFF */
uint32_t Period; /*!< Specifies burst mode repetition period.
This parameter can be a number between 0x1 and 0xFFFF */
} HRTIM_BurstModeCfgTypeDef;
/**
* @brief ADC trigger configuration definition
*/
typedef struct
{
uint32_t UpdateSource; /*!< Specifies the ADC trigger update source.
This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source */
uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion.
This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event */
} HRTIM_ADCTriggerCfgTypeDef;
/**
* @brief External Event Counter A or B configuration definition
*/
typedef struct
{
uint32_t ResetMode; /*!< Specifies the External Event Counter A or B Reset Mode.
This parameter can be a value of @ref HRTIM_Timer_External_Event_ResetMode */
uint32_t Source; /*!< Specifies the External Event Counter source selection.
This parameter can be one of @ref HRTIM_External_Event_Channels */
uint32_t Counter; /*!< Specifies the External Event Counter Threshold.
This parameter can be a number between 0x0 and 0x3F */
} HRTIM_ExternalEventCfgTypeDef;
#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
/**
* @brief HAL HRTIM Callback ID enumeration definition
*/
typedef enum {
HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */
HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */
HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */
HAL_HRTIM_FAULT4CALLBACK_CB_ID = 0x03U, /*!< Fault 4 interrupt callback ID */
HAL_HRTIM_FAULT5CALLBACK_CB_ID = 0x04U, /*!< Fault 5 interrupt callback ID */
HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID = 0x05U, /*!< System fault interrupt callback ID */
HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID = 0x06U, /*!< DLL Ready interrupt callback ID */
HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID = 0x07U, /*!< Burst mode period interrupt callback ID */
HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID */
HAL_HRTIM_ERRORCALLBACK_CB_ID = 0x09U, /*!< DMA error callback ID */
HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID = 0x10U, /*!< Timer x Update interrupt callback ID */
HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID = 0x11U, /*!< Timer x Repetition interrupt callback ID */
HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID */
HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID */
HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID */
HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID */
HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID = 0x16U, /*!< Timer x Capture 1 interrupts callback ID */
HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID = 0x17U, /*!< Timer x Capture 2 interrupts callback ID */
HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID = 0x18U, /*!< Timer x Delayed protection interrupt callback ID */
HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */
HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID = 0x1AU, /*!< Timer x output 1 set interrupt callback ID */
HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID */
HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID = 0x1CU, /*!< Timer x output 2 set interrupt callback ID */
HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID */
HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID */
HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */
HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */
HAL_HRTIM_FAULT6CALLBACK_CB_ID = 0x22U, /*!< Fault 6 interrupt callback ID */
}HAL_HRTIM_CallbackIDTypeDef;
/**
* @brief HAL HRTIM Callback function pointer definitions
*/
typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM related callback function pointer */
typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< HRTIM Timer x related callback function pointer */
uint32_t TimerIdx);
#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
* @{
*/
/** @defgroup HRTIM_Timer_Index HRTIM Timer Index
* @{
* @brief Constants defining the timer indexes
*/
#define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */
#define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */
#define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */
#define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */
#define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */
#define HRTIM_TIMERINDEX_TIMER_F 0x5U /*!< Index used to access timer F registers */
#define HRTIM_TIMERINDEX_MASTER 0x6U /*!< Index used to access master registers */
#define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */
/**
* @}
*/
/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
* @{
* @brief Constants defining timer identifiers
*/
#define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier */
#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */
#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */
#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */
#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */
#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */
#define HRTIM_TIMERID_TIMER_F (HRTIM_MCR_TFCEN) /*!< Timer F identifier */
/**
* @}
*/
/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
* @{
* @brief Constants defining compare unit identifiers
*/
#define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */
#define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */
#define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */
#define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */
/**
* @}
*/
/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
* @{
* @brief Constants defining capture unit identifiers
*/
#define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */
#define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Output HRTIM Timer Output
* @{
* @brief Constants defining timer output identifiers
*/
#define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */
#define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */
#define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */
#define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */
#define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */
#define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */
#define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */
#define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */
#define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */
#define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */
#define HRTIM_OUTPUT_TF1 0x00000400U /*!< Timer F - Output 1 identifier */
#define HRTIM_OUTPUT_TF2 0x00000800U /*!< Timer F - Output 2 identifier */
/**
* @}
*/
/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
* @{
* @brief Constants defining ADC triggers identifiers
*/
#define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */
#define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */
#define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */
#define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */
/**
* @}
*/
/** @defgroup HRTIM_ADC_Ext_Trigger HRTIM ADC Extended Trigger
* @{
* @brief Constants defining ADC Extended triggers identifiers
*/
#define HRTIM_ADCTRIGGER_5 0x00000010U /*!< ADC trigger 5 identifier */
#define HRTIM_ADCTRIGGER_6 0x00000020U /*!< ADC trigger 6 identifier */
#define HRTIM_ADCTRIGGER_7 0x00000040U /*!< ADC trigger 7 identifier */
#define HRTIM_ADCTRIGGER_8 0x00000080U /*!< ADC trigger 8 identifier */
#define HRTIM_ADCTRIGGER_9 0x00000100U /*!< ADC trigger 9 identifier */
#define HRTIM_ADCTRIGGER_10 0x00000200U /*!< ADC trigger 10 identifier */
#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
(((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_4) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_10))
#define IS_HRTIM_ADCEXTTRIGGER(ADCTRIGGER)\
(((ADCTRIGGER) == HRTIM_ADCTRIGGER_5) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_6) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_7) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_8) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_9) || \
((ADCTRIGGER) == HRTIM_ADCTRIGGER_10))
/**
* @}
*/
/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
* @{
* @brief Constants defining external event channel identifiers
*/
#define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */
#define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */
#define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */
#define HRTIM_EVENT_3 (0x00000003U) /*!< External event channel 3 identifier */
#define HRTIM_EVENT_4 (0x00000004U) /*!< External event channel 4 identifier */
#define HRTIM_EVENT_5 (0x00000005U) /*!< External event channel 5 identifier */
#define HRTIM_EVENT_6 (0x00000006U) /*!< External event channel 6 identifier */
#define HRTIM_EVENT_7 (0x00000007U) /*!< External event channel 7 identifier */
#define HRTIM_EVENT_8 (0x00000008U) /*!< External event channel 8 identifier */
#define HRTIM_EVENT_9 (0x00000009U) /*!< External event channel 9 identifier */
#define HRTIM_EVENT_10 (0x0000000AU) /*!< External event channel 10 identifier */
/**
* @}
*/
/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
* @{
* @brief Constants defining fault channel identifiers
*/
#define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */
#define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */
#define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */
#define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */
#define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */
#define HRTIM_FAULT_6 (0x20U) /*!< Fault channel 6 identifier */
/**
* @}
*/
/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
* @{
* @brief Constants defining timer high-resolution clock prescaler ratio.
*/
#define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
#define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
/**
* @}
*/
/** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
* @{
* @brief Constants defining timer counter operating mode.
*/
#define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */
#define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
/**
* @}
*/
/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
* @{
* @brief Constants defining half mode enabling status.
*/
#define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */
#define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */
/**
* @}
*/
/** @defgroup HRTIM_Interleaved_Mode HRTIM Interleaved Mode
* @{
* @brief Constants defining interleaved mode enabling status.
*/
#define HRTIM_INTERLEAVED_MODE_DISABLED 0x000U /*!< HRTIM interleaved Mode is disabled */
#define HRTIM_INTERLEAVED_MODE_DUAL 0x002U /*!< HRTIM interleaved Mode is Half */
#define HRTIM_INTERLEAVED_MODE_TRIPLE 0x003U /*!< HRTIM interleaved Mode is Triple */
#define HRTIM_INTERLEAVED_MODE_QUAD 0x004U /*!< HRTIM interleaved Mode is Quad */
/**
* @}
*/
/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
* @{
* @brief Constants defining the timer behavior following the synchronization event
*/
#define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
#define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
/**
* @}
*/
/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
* @{
* @brief Constants defining the timer behavior following the synchronization event
*/
#define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
#define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
/**
* @}
*/
/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
* @{
* @brief Constants defining on which output the DAC synchronization event is sent
*/
#define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */
#define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
#define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
#define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
/**
* @}
*/
/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
* @{
* @brief Constants defining whether a write access into a preloadable
* register is done into the active or the preload register.
*/
#define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */
#define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
/**
* @}
*/
/** @defgroup HRTIM_Update_Gating HRTIM Update Gating
* @{
* @brief Constants defining how the update occurs relatively to the burst DMA
* transaction and the external update request on update enable inputs 1 to 3.
*/
#define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
#define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
#define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
#define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
#define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
#define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */
#define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */
#define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
* @{
* @brief Constants defining how the timer behaves during a burst
mode operation.
*/
#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U /*!< Timer counter clock is maintained and the timer operates normally */
#define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
/**
* @}
*/
/** @defgroup HRTIM_Timer_UpDown_Mode HRTIM Timer UpDown Mode
* @{
* @brief Constants defining how the timer counter operates
*/
#define HRTIM_TIMERUPDOWNMODE_UP 0x00000000U /*!< Timer counter is operating in up-counting mode */
#define HRTIM_TIMERUPDOWNMODE_UPDOWN 0x00000001U /*!< Timer counter is operating in up-down counting mode */
/**
* @}
*/
/** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
* @{
* @brief Constants defining how the timer counter operates
*/
#define HRTIM_TIMERTRIGHALF_DISABLED 0x00000000U /*!< Timer Compare 2 register is behaving in standard mode */
#define HRTIM_TIMERTRIGHALF_ENABLED (HRTIM_TIMCR2_TRGHLF) /*!< Timer Compare 2 register is behaving in triggered-half mode */
/**
* @}
*/
/** @defgroup HRTIM_Timer_GreaterCMP3_Mode HRTIM Timer Greater than Compare 3 PWM Mode
* @{
* @brief Constants defining how the timer compare operates
*/
#define HRTIM_TIMERGTCMP3_EQUAL 0x00000000U /*!< Timer Compare 3 event is generated when counter is equal */
#define HRTIM_TIMERGTCMP3_GREATER (HRTIM_TIMCR2_GTCMP3) /*!< Timer Compare 3 Reset event is generated when counter is greater */
/**
* @}
*/
/** @defgroup HRTIM_Timer_GreaterCMP1_Mode HRTIM Timer Greater than Compare 1 PWM Mode
* @{
* @brief Constants defining how the timer compare operates
*/
#define HRTIM_TIMERGTCMP1_EQUAL 0x00000000U /*!< Timer Compare 1 event is generated when counter is equal */
#define HRTIM_TIMERGTCMP1_GREATER (HRTIM_TIMCR2_GTCMP1) /*!< Timer Compare 1 event is generated when counter is greater */
/**
* @}
*/
/** @defgroup HRTIM_Timer_DualChannelDac_Reset HRTIM Dual Channel Dac Reset Trigger
* @{
* @brief Constants defining when the hrtim_dac_reset_trgx trigger is generated
*/
#define HRTIM_TIMER_DCDR_COUNTER 0x00000000U /*!< the trigger is generated on counter reset or roll-over event */
#define HRTIM_TIMER_DCDR_OUT1SET (HRTIM_TIMCR2_DCDR) /*!< the trigger is generated on output 1 set event */
/**
* @}
*/
/** @defgroup HRTIM_Timer_DualChannelDac_Step HRTIM Dual Channel Dac Step Trigger
* @{
* @brief Constants defining when the hrtim_dac_step_trgx trigger is generated
is generated
*/
#define HRTIM_TIMER_DCDS_CMP2 0x00000000U /*!< the trigger is generated on compare 2 event */
#define HRTIM_TIMER_DCDS_OUT1RST (HRTIM_TIMCR2_DCDS) /*!< the trigger is generated on output 1 reset event */
/**
* @}
*/
/** @defgroup HRTIM_Timer_DualChannelDac_Enable HRTIM Dual Channel DAC Trigger Enable
* @{
* @brief Constants enabling the dual channel DAC triggering mechanism
*/
#define HRTIM_TIMER_DCDE_DISABLED 0x00000000U /*!< the Dual channel DAC trigger is disabled */
#define HRTIM_TIMER_DCDE_ENABLED (HRTIM_TIMCR2_DCDE) /*!< the Dual channel DAC trigger is enabled */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
* @{
* @brief Constants defining whether registers are updated when the timer
* repetition period is completed (either due to roll-over or
* reset events)
*/
#define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */
#define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
* @{
* @brief Constants defining whether or not the push-pull mode is enabled for
* a timer.
*/
#define HRTIM_TIMPUSHPULLMODE_DISABLED 0x00000000U /*!< Push-Pull mode disabled */
#define HRTIM_TIMPUSHPULLMODE_ENABLED (HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
* @{
* @brief Constants defining whether a fault channel is enabled for a timer
*/
#define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */
#define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */
#define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */
#define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */
#define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */
#define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */
#define HRTIM_TIMFAULTENABLE_FAULT6 (HRTIM_FLTR_FLT6EN) /*!< Fault 6 enabled */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
* @{
* @brief Constants defining whether or not fault enabling bits are write
* protected for a timer
*/
#define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */
#define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion
* @{
* @brief Constants defining whether or not fault the dead time insertion
* feature is enabled for a timer
*/
#define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */
#define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Dead-time is inserted between output 1 and output 2U */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
* @{
* @brief Constants defining all possible delayed protection modes
* for a timer. Also define the source and outputs on which the delayed
* protection schemes are applied
*/
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 delayed Idle on external Event 6U */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 2 delayed Idle on external Event 6U */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 and output 2 delayed Idle on external Event 6U */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Balanced Idle on external Event 6U */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 delayed Idle on external Event 7U */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 2 delayed Idle on external Event 7U */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Output 1 and output2 delayed Idle on external Event 7U */
#define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers F: Balanced Idle on external Event 7U */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
* @{
* @brief Constants defining whether the registers update is done synchronously
* with any other timer or master update
*/
#define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */
#define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
#define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
#define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
#define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
#define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
#define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
#define HRTIM_TIMUPDATETRIGGER_TIMER_F (HRTIM_TIMCR_TFU) /*!< Register update is triggered by the timer F update */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
* @{
* @brief Constants defining the events that can be selected to trigger the reset
* of the timer counter
*/
#define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */
#define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
#define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
#define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
#define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */
#define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */
#define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */
#define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */
#define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */
#define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */
#define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */
#define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */
#define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */
#define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
#define HRTIM_TIMRESETTRIGGER_OTHER5_CMP1 (HRTIM_RSTR_TIMFCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
#define HRTIM_TIMRESETTRIGGER_OTHER5_CMP2 (HRTIM_RSTR_TIMFCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
/**
* @}
*/
/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
* @{
* @brief Constants defining whether the register are updated upon Timerx
* counter reset or roll-over to 0 after reaching the period value
* in continuous mode
*/
#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */
#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
/**
* @}
*/
/** @defgroup HRTIM_Timer_RollOver_Mode HRTIM Timer RollOver Mode
* @{
* @brief Constants defining when the roll-over is generated upon Timerx
* event generated when the counter is equal to 0 ('VALLEY' mode) or to HRTIM_PERxR value ('CREST' mode) or BOTH
* This setting only applies when the UDM bit is set. It is not significant otherwise.
*/
#define HRTIM_TIM_FEROM_BOTH 0x00000000U /*!< Roll-over event used by */
#define HRTIM_TIM_FEROM_CREST (HRTIM_TIMCR2_FEROM_1) /*!< the Fault and */
#define HRTIM_TIM_FEROM_VALLEY (HRTIM_TIMCR2_FEROM_0) /*!< Event counters */
#define HRTIM_TIM_BMROM_BOTH 0x00000000U /*!< Roll-over event used in the Burst mode controller */
#define HRTIM_TIM_BMROM_CREST (HRTIM_TIMCR2_BMROM_1) /*!< as clock */
#define HRTIM_TIM_BMROM_VALLEY (HRTIM_TIMCR2_BMROM_0) /*!< and as burst mode trigger */
#define HRTIM_TIM_ADROM_BOTH 0x00000000U /*!< Roll-over event which triggers */
#define HRTIM_TIM_ADROM_CREST (HRTIM_TIMCR2_ADROM_1) /*!< the */
#define HRTIM_TIM_ADROM_VALLEY (HRTIM_TIMCR2_ADROM_0) /*!< ADC */
#define HRTIM_TIM_OUTROM_BOTH 0x00000000U /*!< Roll-over event which sets and/or resets the outputs */
#define HRTIM_TIM_OUTROM_CREST (HRTIM_TIMCR2_OUTROM_1) /*!< as per HRTIM_SETxyR */
#define HRTIM_TIM_OUTROM_VALLEY (HRTIM_TIMCR2_OUTROM_0) /*!< and HRTIM_RSTxyR settings */
#define HRTIM_TIM_ROM_BOTH 0x00000000U /*!< Roll-over event with the following destinations: IRQ and DMA requests,*/
#define HRTIM_TIM_ROM_CREST (HRTIM_TIMCR2_ROM_1) /*!< Update trigger (to transfer content from preload to active registers), */
#define HRTIM_TIM_ROM_VALLEY (HRTIM_TIMCR2_ROM_0) /*!< repetition counter decrement and External Event filtering */
#define IS_HRTIM_ROLLOVERMODE(ROLLOVER)\
((((ROLLOVER) == HRTIM_TIM_FEROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_FEROM_CREST) || ((ROLLOVER) == HRTIM_TIM_FEROM_VALLEY)) ||\
(((ROLLOVER) == HRTIM_TIM_ADROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ADROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ADROM_VALLEY)) ||\
(((ROLLOVER) == HRTIM_TIM_BMROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_BMROM_CREST) || ((ROLLOVER) == HRTIM_TIM_BMROM_VALLEY)) ||\
(((ROLLOVER) == HRTIM_TIM_OUTROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_OUTROM_CREST) || ((ROLLOVER) == HRTIM_TIM_OUTROM_VALLEY)) ||\
(((ROLLOVER) == HRTIM_TIM_ROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_ROM_CREST) || ((ROLLOVER) == HRTIM_TIM_ROM_VALLEY)))
/**
* @}
*/
/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
* @{
* @brief Constants defining whether the compare register is behaving in
* regular mode (compare match issued as soon as counter equal compare),
* or in auto-delayed mode
*/
#define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */
#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
/**
* @}
*/
/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
* @{
* @brief Constants defining the behavior of the output signal when the timer
operates in basic output compare mode
*/
#define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */
#define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */
#define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */
#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
(((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
/**
* @}
*/
/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
* @{
* @brief Constants defining the polarity of a timer output
*/
#define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */
#define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */
/**
* @}
*/
/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
* @{
* @brief Constants defining the events that can be selected to configure the
* set crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */
#define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
#define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
/* Timer Events mapping for Timer A */
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer B */
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer C */
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer D */
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer E */
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
/* Timer Events mapping for Timer F */
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
#define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
#define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
/**
* @}
*/
/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
* @{
* @brief Constants defining the events that can be selected to configure the
* reset crossbar of a timer output
*/
#define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */
#define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
/* Timer Events mapping for Timer A */
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer B */
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer C */
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer D */
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer E */
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
/* Timer Events mapping for Timer F */
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
#define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
/**
* @}
*/
/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
* @{
* @brief Constants defining whether or not the timer output transition to its
IDLE state when burst mode is entered
*/
#define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */
#define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
/**
* @}
*/
/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
* @{
* @brief Constants defining the output level when output is in IDLE state
*/
#define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
#define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
/**
* @}
*/
/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
* @{
* @brief Constants defining the output level when output is in FAULT state
*/
#define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */
#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
/**
* @}
*/
/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
* @{
* @brief Constants defining whether or not chopper mode is enabled for a timer
output
*/
#define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */
#define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
/**
* @}
*/
/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
* @{
* @brief Constants defining the idle mode entry is delayed by forcing a
dead-time insertion before switching the outputs to their idle state
*/
#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Dead-time is inserted on output before entering the idle mode */
/**
* @}
*/
/** @defgroup HRTIM_Output_Balanced_Idle_Auto_Resume HRTIM Output Balanced Idle Automatic Resume
* @{
* @brief Constants defining if the outputs are automatically
re-enabled after a balanced idle event.
*/
#define HRTIM_OUTPUTBIAR_DISABLED 0x00000000U /*!< output is not automatically re-enabled */
#define HRTIM_OUTPUTBIAR_ENABLED (HRTIM_OUTR_BIAR) /*!< output is automatically re-enabled */
/**
* @}
*/
/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
* @{
* @brief Constants defining the events that can be selected to trigger the
* capture of the timing unit counter
*/
#define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */
#define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
#define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
#define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
#define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
#define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
#define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
#define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */
/**
* @}
*/
/** @defgroup HRTIM_Capture_Unit_TimerF_Trigger HRTIM Capture Unit TimerF Trigger
* @{
* @brief Constants defining the events that can be selected to trigger the
* capture of the timing unit counter
*/
#define HRTIM_CAPTURETRIGGER_TF1_SET ((uint64_t)(HRTIM_CPT1CR_TF1SET ) << 32) /*!< Capture is triggered by TF1 output inactive to active transition */
#define HRTIM_CAPTURETRIGGER_TF1_RESET ((uint64_t)(HRTIM_CPT1CR_TF1RST ) << 32) /*!< Capture is triggered by TF1 output active to inactive transition */
#define HRTIM_CAPTURETRIGGER_TIMERF_CMP1 ((uint64_t)(HRTIM_CPT1CR_TIMFCMP1) << 32) /*!< Timer F Compare 1 triggers Capture */
#define HRTIM_CAPTURETRIGGER_TIMERF_CMP2 ((uint64_t)(HRTIM_CPT1CR_TIMFCMP2) << 32) /*!< Timer F Compare 2 triggers Capture */
/**
* @}
*/
/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
* @{
* @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEEVFLT_NONE (0x00000000U)
#define HRTIM_TIMEEVFLT_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
#define HRTIM_TIMEEVFLT_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
#define HRTIM_TIMEEVFLT_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
#define HRTIM_TIMEEVFLT_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
/* Blanking Filter for TIMER A */
#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER B */
#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER C */
#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER D */
#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER E */
#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
/* Blanking Filter for TIMER F */
#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
#define HRTIM_TIMEEVFLT_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
#define HRTIM_TIMEEVFLT_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
#define HRTIM_TIMEEVFLT_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
| HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
/**
* @}
*/
/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
* @{
* @brief Constants defining whether or not the external event is
* memorized (latched) and generated as soon as the blanking period
* is completed or the window ends
*/
#define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
#define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
/**
* @}
*/
/** @defgroup HRTIM_Timer_External_Event HRTIM Timer External Event Counter A or B
* @{
* @brief Constants defining the External Event Counter A or B
*/
#define HRTIM_EVENTCOUNTER_A (HRTIM_EEFR3_EEVACE) /*!< External Event Counter A */
#define HRTIM_EVENTCOUNTER_B (HRTIM_EEFR3_EEVBCE) /*!< External Event Counter B */
/**
* @}
*/
/** @defgroup HRTIM_Timer_External_Event_ResetMode HRTIM Timer External Counter Reset Mode
* @{
* @brief Constants enabling the External Event Counter A or B Reset Mode
*/
#define HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL (0x00000000U) /*!< External Event Counter is reset on each reset / roll-over event */
#define HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL (0x00000001U) /*!< External Event Counter is reset on each reset / roll-over event only
if no event occurs during last counting period */
/**
* @}
*/
/** @defgroup HRTIM_Timer_ReSyncUpdate HRTIM Timer Re-Synchronized update
* @{
* @brief Constants defining the update coming condition
*/
#define HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL (0x00000000U) /*!< update taken into account immediately */
#define HRTIM_TIMERESYNC_UPDATE_CONDITIONAL (0x00000001U) /*!< update taken into account on the following Reset/Roll-over event */
/**
* @}
*/
/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio
* @{
* @brief Constants defining division ratio between the timer clock frequency
* (fHRTIM) and the dead-time generator clock (fDTG)
*/
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */
#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */
/**
* @}
*/
/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign
* @{
* @brief Constants defining whether the dead-time is positive or negative
* (overlapping signal) on rising edge
*/
#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on rising edge */
#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative dead-time on rising edge */
/**
* @}
*/
/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock
* @{
* @brief Constants defining whether or not the dead-time (rising sign and
* value) is write protected
*/
#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Dead-time rising value and sign is writeable */
#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Dead-time rising value and sign is read-only */
/**
* @}
*/
/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock
* @{
* @brief Constants defining whether or not the dead-time rising sign is write
* protected
*/
#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time rising sign is writeable */
#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Dead-time rising sign is read-only */
/**
* @}
*/
/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign
* @{
* @brief Constants defining whether the dead-time is positive or negative
* (overlapping signal) on falling edge
*/
#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on falling edge */
#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative dead-time on falling edge */
/**
* @}
*/
/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock
* @{
* @brief Constants defining whether or not the dead-time (falling sign and
* value) is write protected
*/
#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Dead-time falling value and sign is writeable */
#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Dead-time falling value and sign is read-only */
/**
* @}
*/
/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock
* @{
* @brief Constants defining whether or not the dead-time falling sign is write
* protected
*/
#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time falling sign is writeable */
#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Dead-time falling sign is read-only */
/**
* @}
*/
/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
* @{
* @brief Constants defining the frequency of the generated high frequency carrier
*/
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
/**
* @}
*/
/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
* @{
* @brief Constants defining the duty cycle of the generated high frequency carrier
* Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
*/
#define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */
#define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */
#define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */
#define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */
#define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */
#define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */
#define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */
#define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
/**
* @}
*/
/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
* @{
* @brief Constants defining the pulse width of the first pulse of the generated
* high frequency carrier
*/
#define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */
#define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */
#define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */
#define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
#define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */
#define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
#define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
#define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
#define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */
#define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
#define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
#define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
#define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
#define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
#define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
#define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
/**
* @}
*/
/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
* @{
* @brief Constants defining the options for synchronizing multiple HRTIM
* instances, as a master unit (generating a synchronization signal)
* or as a slave (waiting for a trigger to be synchronized)
*/
#define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
#define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
#define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
/**
* @}
*/
/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
* @{
* @brief Constants defining defining the synchronization input source
*/
#define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
/**
* @}
*/
/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
* @{
* @brief Constants defining the source and event to be sent on the
* synchronization outputs
*/
#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */
#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */
#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */
/**
* @}
*/
/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
* @{
* @brief Constants defining the routing and conditioning of the synchronization output event
*/
#define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */
#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
/**
* @}
*/
/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
* @{
* @brief Constants defining available sources associated to external events
*/
#define HRTIM_EEV1SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 1 */
#define HRTIM_EEV2SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 2 */
#define HRTIM_EEV3SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 3 */
#define HRTIM_EEV4SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 4 */
#define HRTIM_EEV5SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 5 */
#define HRTIM_EEV6SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 6 */
#define HRTIM_EEV7SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 7 */
#define HRTIM_EEV8SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 8 */
#define HRTIM_EEV9SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 9 */
#define HRTIM_EEV10SRC_GPIO 0x00000000U /*!< External event source 1U for External Event 10 */
#define HRTIM_EEV1SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 1 */
#define HRTIM_EEV2SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 2 */
#define HRTIM_EEV3SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 3 */
#define HRTIM_EEV4SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 4 */
#define HRTIM_EEV5SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 5 */
#define HRTIM_EEV6SRC_COMP2_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 6 */
#define HRTIM_EEV7SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 7 */
#define HRTIM_EEV8SRC_COMP6_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 8 */
#define HRTIM_EEV9SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 9 */
#define HRTIM_EEV10SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U for External Event 10 */
#define HRTIM_EEV1SRC_TIM1_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 1 */
#define HRTIM_EEV2SRC_TIM2_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 2 */
#define HRTIM_EEV3SRC_TIM3_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 3 */
#define HRTIM_EEV4SRC_COMP5_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 4 */
#define HRTIM_EEV5SRC_COMP7_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 5 */
#define HRTIM_EEV6SRC_COMP1_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 6 */
#define HRTIM_EEV7SRC_TIM7_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 7 */
#define HRTIM_EEV8SRC_COMP3_OUT (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 8 */
#define HRTIM_EEV9SRC_TIM15_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 9 */
#define HRTIM_EEV10SRC_TIM6_TRGO (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U for External Event 10 */
#define HRTIM_EEV1SRC_ADC1_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 1 */
#define HRTIM_EEV2SRC_ADC1_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 2 */
#define HRTIM_EEV3SRC_ADC1_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 3 */
#define HRTIM_EEV4SRC_ADC2_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 4 */
#define HRTIM_EEV5SRC_ADC2_AWD2 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 5 */
#define HRTIM_EEV6SRC_ADC2_AWD3 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 6 */
#define HRTIM_EEV7SRC_ADC3_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 7 */
#define HRTIM_EEV8SRC_ADC4_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 8 */
#define HRTIM_EEV9SRC_COMP4_OUT (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 9 */
#define HRTIM_EEV10SRC_ADC5_AWD1 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 10 */
/**
* @}
*/
/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
* @{
* @brief Constants defining the polarity of an external event
*/
#define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */
#define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */
/**
* @}
*/
/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
* @{
* @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
* of an external event
*/
#define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */
#define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
#define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
/**
* @}
*/
/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
* @{
* @brief Constants defining whether or not an external event is programmed in
fast mode
*/
#define HRTIM_EVENTFASTMODE_DISABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
#define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
/**
* @}
*/
/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
* @{
* @brief Constants defining the frequency used to sample an external event 6
* input and the length (N) of the digital filter applied
*/
#define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */
#define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */
#define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */
#define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */
#define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */
#define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */
#define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */
#define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */
#define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */
#define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */
#define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */
#define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */
#define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */
#define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */
#define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */
#define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */
/**
* @}
*/
/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
* @{
* @brief Constants defining division ratio between the timer clock frequency
* fHRTIM) and the external event signal sampling clock (fEEVS)
* used by the digital filters
*/
#define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */
#define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */
#define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */
#define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */
/**
* @}
*/
/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
* @{
* @brief Constants defining whether a fault is triggered by any external
* or internal fault source
*/
#define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */
#define HRTIM_FAULTSOURCE_INTERNAL (0x00000001U) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
#define HRTIM_FAULTSOURCE_EEVINPUT (0x00000002U) /*!< Fault input is EEV pin */
/**
* @}
*/
/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
* @{
* @brief Constants defining the polarity of a fault event
*/
#define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */
#define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */
/**
* @}
*/
/** @defgroup HRTIM_Fault_Blanking HRTIM Fault Blanking Source
* @{
* @brief Constants defining the blanking source of a fault event
*/
#define HRTIM_FAULTBLANKINGMODE_RSTALIGNED (0x00000000U) /*!< Fault blanking source is Reset-aligned window */
#define HRTIM_FAULTBLANKINGMODE_MOVING (0x00000001U) /*!< Fault blanking source is Moving window */
/**
* @}
*/
/** @defgroup HRTIM_Fault_ResetMode HRTIM Fault Reset Mode
* @{
* @brief Constants defining the Counter reset mode of a fault event
*/
#define HRTIM_FAULTCOUNTERRST_UNCONDITIONAL (0x00000000U) /*!< Fault counter is reset on each reset / roll-over event */
#define HRTIM_FAULTCOUNTERRST_CONDITIONAL (0x00000001U) /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last countingperiod.*/
/**
* @}
*/
/** @defgroup HRTIM_Fault_Blanking_Control HRTIM Fault Blanking Control
* @{
* @brief Constants used to enable or disable the blanking mode of a fault channel
*/
#define HRTIM_FAULTBLANKINGCTL_DISABLED 0x00000000U /*!< No blanking on Fault */
#define HRTIM_FAULTBLANKINGCTL_ENABLED 0x00000001U /*!< Fault blanking mode */
/**
* @}
*/
/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
* @{
* @ brief Constants defining the frequency used to sample the fault input and
* the length (N) of the digital filter applied
*/
#define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */
#define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */
#define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */
#define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */
#define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */
#define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */
#define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */
#define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */
#define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */
#define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */
#define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */
#define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */
#define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */
#define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */
#define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */
#define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */
/**
* @}
*/
/** @defgroup HRTIM_Fault_Counter HRTIM Fault counter threshold value
* @{
* @ brief Constants defining the FAULT Counter threshold
*/
#define HRTIM_FAULTCOUNTER_NONE ((uint32_t)0U ) /*!< Counter threshold = 0U */
#define HRTIM_FAULTCOUNTER_1 ((uint32_t)1U ) /*!< Counter threshold = 1U */
#define HRTIM_FAULTCOUNTER_2 ((uint32_t)2U ) /*!< Counter threshold = 2U */
#define HRTIM_FAULTCOUNTER_3 ((uint32_t)3U ) /*!< Counter threshold = 3U */
#define HRTIM_FAULTCOUNTER_4 ((uint32_t)4U ) /*!< Counter threshold = 4U */
#define HRTIM_FAULTCOUNTER_5 ((uint32_t)5U ) /*!< Counter threshold = 5U */
#define HRTIM_FAULTCOUNTER_6 ((uint32_t)6U ) /*!< Counter threshold = 6U */
#define HRTIM_FAULTCOUNTER_7 ((uint32_t)7U ) /*!< Counter threshold = 7U */
#define HRTIM_FAULTCOUNTER_8 ((uint32_t)8U ) /*!< Counter threshold = 8U */
#define HRTIM_FAULTCOUNTER_9 ((uint32_t)9U ) /*!< Counter threshold = 9U */
#define HRTIM_FAULTCOUNTER_10 ((uint32_t)10U) /*!< Counter threshold = 10U */
#define HRTIM_FAULTCOUNTER_11 ((uint32_t)11U) /*!< Counter threshold = 11U */
#define HRTIM_FAULTCOUNTER_12 ((uint32_t)12U) /*!< Counter threshold = 12U */
#define HRTIM_FAULTCOUNTER_13 ((uint32_t)13U) /*!< Counter threshold = 13U */
#define HRTIM_FAULTCOUNTER_14 ((uint32_t)14U) /*!< Counter threshold = 14U */
#define HRTIM_FAULTCOUNTER_15 ((uint32_t)15U) /*!< Counter threshold = 15U */
/**
* @}
*/
/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
* @{
* @brief Constants defining whether or not the fault programming bits are
write protected
*/
#define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */
#define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
/**
* @}
*/
/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
* @{
* @brief Constants defining the division ratio between the timer clock
* frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
* by the digital filters.
*/
#define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */
#define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */
#define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */
#define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */
/**
* @}
*/
/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
* @{
* @brief Constants defining if the burst mode is entered once or if it is
* continuously operating
*/
#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */
#define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
/**
* @}
*/
/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
* @{
* @brief Constants defining the clock source for the burst mode counter
*/
#define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_F (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
/**
* @}
*/
/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
* @{
* @brief Constants defining the prescaling ratio of the fHRTIM clock
* for the burst mode controller
*/
#define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */
#define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */
#define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */
#define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */
#define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */
#define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */
#define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */
#define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */
#define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */
#define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */
#define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */
#define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/
#define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */
#define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */
#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */
#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
/**
* @}
*/
/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
* @{
* @brief Constants defining whether or not burst mode registers preload
mechanism is enabled, i.e. a write access into a preloadable register
(HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
*/
#define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */
#define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
/**
* @}
*/
/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
* @{
* @brief Constants defining the events that can be used to trig the burst
* mode operation
*/
#define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */
#define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */
#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */
#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */
#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */
#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */
#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */
#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */
#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */
#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */
#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */
#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */
#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */
#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */
#define HRTIM_BURSTMODETRIGGER_TIMERF_RESET (HRTIM_BMTRGR_TFRST) /*!< Timer F reset */
#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */
#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
#define HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION (HRTIM_BMTRGR_TFREP) /*!< Timer F repetition */
#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */
#define HRTIM_BURSTMODETRIGGER_TIMERF_CMP1 (HRTIM_BMTRGR_TFCMP1) /*!< Timer F compare 1 */
#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */
#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */
#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
#define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */
#define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/
#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */
/**
* @}
*/
/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
* @{
* @brief constants defining the source triggering the update of the
HRTIM_ADCxR register (transfer from preload to active register).
*/
#define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
#define HRTIM_ADCTRIGGERUPDATE_TIMER_F (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_1) /*!< Timer F */
/**
* @}
*/
/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
* @{
* @brief constants defining the events triggering ADC conversion.
* HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
* HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
* HRTIM_ADCTRIGGEREVENT579_*: ADC Triggers 5 and 7 and 9
* HRTIM_ADCTRIGGEREVENT6810_*: ADC Triggers 6 and 8 and 10
*/
#define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */
#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */
#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */
#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */
#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
#define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */
#define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */
#define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */
#define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */
#define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP2 (HRTIM_ADC1R_AD1TFC2) /*!< ADC Trigger on Timer F compare 2U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
#define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP3 (HRTIM_ADC1R_AD1TFC3) /*!< ADC Trigger on Timer F compare 3U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
#define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP4 (HRTIM_ADC1R_AD1TFC4) /*!< ADC Trigger on Timer F compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
#define HRTIM_ADCTRIGGEREVENT13_TIMERF_PERIOD (HRTIM_ADC1R_AD1TFPER) /*!< ADC Trigger on Timer F period */
#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
#define HRTIM_ADCTRIGGEREVENT13_TIMERF_RESET (HRTIM_ADC1R_AD1TFRST) /*!< ADC Trigger on Timer F reset */
#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */
#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
#define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */
#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */
#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */
#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */
#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
#define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */
#define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */
#define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */
#define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */
#define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP2 (HRTIM_ADC2R_AD2TFC2) /*!< ADC Trigger on Timer F compare 2U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP3 (HRTIM_ADC2R_AD2TFC3) /*!< ADC Trigger on Timer F compare 3U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP4 (HRTIM_ADC2R_AD2TFC4) /*!< ADC Trigger on Timer F compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERF_PERIOD (HRTIM_ADC2R_AD2TFPER) /*!< ADC Trigger on Timer F period */
#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */
#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
#define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP1 ((uint32_t)0x00U) /*!< ADC Trigger on master compare 1U */
#define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP2 ((uint32_t)0x01U) /*!< ADC Trigger on master compare 2U */
#define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP3 ((uint32_t)0x02U) /*!< ADC Trigger on master compare 3U */
#define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP4 ((uint32_t)0x03U) /*!< ADC Trigger on master compare 4U */
#define HRTIM_ADCTRIGGEREVENT6810_MASTER_PERIOD ((uint32_t)0x04U) /*!< ADC Trigger on master period */
#define HRTIM_ADCTRIGGEREVENT6810_EVENT_6 ((uint32_t)0x05U) /*!< ADC Trigger on external event 6U */
#define HRTIM_ADCTRIGGEREVENT6810_EVENT_7 ((uint32_t)0x06U) /*!< ADC Trigger on external event 7U */
#define HRTIM_ADCTRIGGEREVENT6810_EVENT_8 ((uint32_t)0x07U) /*!< ADC Trigger on external event 8U */
#define HRTIM_ADCTRIGGEREVENT6810_EVENT_9 ((uint32_t)0x08U) /*!< ADC Trigger on external event 9U */
#define HRTIM_ADCTRIGGEREVENT6810_EVENT_10 ((uint32_t)0x09U) /*!< ADC Trigger on external event 10U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP2 ((uint32_t)0x0AU) /*!< ADC Trigger on Timer A compare 2U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP4 ((uint32_t)0x0BU) /*!< ADC Trigger on Timer A compare 4U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERA_PERIOD ((uint32_t)0x0CU) /*!< ADC Trigger on Timer A period */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP2 ((uint32_t)0x0DU) /*!< ADC Trigger on Timer B compare 2U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP4 ((uint32_t)0x0EU) /*!< ADC Trigger on Timer B compare 4U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERB_PERIOD ((uint32_t)0x0FU) /*!< ADC Trigger on Timer B period */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP2 ((uint32_t)0x10U) /*!< ADC Trigger on Timer C compare 2U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP4 ((uint32_t)0x11U) /*!< ADC Trigger on Timer C compare 4U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERC_PERIOD ((uint32_t)0x12U) /*!< ADC Trigger on Timer C period */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERC_RESET ((uint32_t)0x13U) /*!< ADC Trigger on Timer C reset */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP2 ((uint32_t)0x14U) /*!< ADC Trigger on Timer D compare 2U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP4 ((uint32_t)0x15U) /*!< ADC Trigger on Timer D compare 4U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERD_PERIOD ((uint32_t)0x16U) /*!< ADC Trigger on Timer D period */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERD_RESET ((uint32_t)0x17U) /*!< ADC Trigger on Timer D reset */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP2 ((uint32_t)0x18U) /*!< ADC Trigger on Timer E compare 2U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP3 ((uint32_t)0x19U) /*!< ADC Trigger on Timer E compare 3U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP4 ((uint32_t)0x1AU) /*!< ADC Trigger on Timer E compare 4U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERE_RESET ((uint32_t)0x1BU) /*!< ADC Trigger on Timer E reset */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP2 ((uint32_t)0x1CU) /*!< ADC Trigger on Timer F compare 2U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP3 ((uint32_t)0x1DU) /*!< ADC Trigger on Timer F compare 3U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP4 ((uint32_t)0x1EU) /*!< ADC Trigger on Timer F compare 4U */
#define HRTIM_ADCTRIGGEREVENT6810_TIMERF_PERIOD ((uint32_t)0x1FU) /*!< ADC Trigger on Timer F period */
#define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP1 ((uint32_t)0x00U) /*!< ADC Trigger on master compare 1U */
#define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP2 ((uint32_t)0x01U) /*!< ADC Trigger on master compare 2U */
#define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP3 ((uint32_t)0x02U) /*!< ADC Trigger on master compare 3U */
#define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP4 ((uint32_t)0x03U) /*!< ADC Trigger on master compare 4U */
#define HRTIM_ADCTRIGGEREVENT579_MASTER_PERIOD ((uint32_t)0x04U) /*!< ADC Trigger on master period */
#define HRTIM_ADCTRIGGEREVENT579_EVENT_1 ((uint32_t)0x05U) /*!< ADC Trigger on external event 1U */
#define HRTIM_ADCTRIGGEREVENT579_EVENT_2 ((uint32_t)0x06U) /*!< ADC Trigger on external event 2U */
#define HRTIM_ADCTRIGGEREVENT579_EVENT_3 ((uint32_t)0x07U) /*!< ADC Trigger on external event 3U */
#define HRTIM_ADCTRIGGEREVENT579_EVENT_4 ((uint32_t)0x08U) /*!< ADC Trigger on external event 4U */
#define HRTIM_ADCTRIGGEREVENT579_EVENT_5 ((uint32_t)0x09U) /*!< ADC Trigger on external event 5U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP3 ((uint32_t)0x0AU) /*!< ADC Trigger on Timer A compare 3U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP4 ((uint32_t)0x0BU) /*!< ADC Trigger on Timer A compare 4U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERA_PERIOD ((uint32_t)0x0CU) /*!< ADC Trigger on Timer A period */
#define HRTIM_ADCTRIGGEREVENT579_TIMERA_RESET ((uint32_t)0x0DU) /*!< ADC Trigger on Timer A reset */
#define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP3 ((uint32_t)0x0EU) /*!< ADC Trigger on Timer B compare 3U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP4 ((uint32_t)0x0FU) /*!< ADC Trigger on Timer B compare 4U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERB_PERIOD ((uint32_t)0x10U) /*!< ADC Trigger on Timer B period */
#define HRTIM_ADCTRIGGEREVENT579_TIMERB_RESET ((uint32_t)0x11U) /*!< ADC Trigger on Timer B reset */
#define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP3 ((uint32_t)0x12U) /*!< ADC Trigger on Timer C compare 3U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP4 ((uint32_t)0x13U) /*!< ADC Trigger on Timer C compare 4U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERC_PERIOD ((uint32_t)0x14U) /*!< ADC Trigger on Timer C period */
#define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP3 ((uint32_t)0x15U) /*!< ADC Trigger on Timer D compare 3U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP4 ((uint32_t)0x16U) /*!< ADC Trigger on Timer D compare 4U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERD_PERIOD ((uint32_t)0x17U) /*!< ADC Trigger on Timer D period */
#define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP3 ((uint32_t)0x18U) /*!< ADC Trigger on Timer E compare 3U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP4 ((uint32_t)0x19U) /*!< ADC Trigger on Timer E compare 4U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERE_PERIOD ((uint32_t)0x1AU) /*!< ADC Trigger on Timer E period */
#define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP2 ((uint32_t)0x1BU) /*!< ADC Trigger on Timer F compare 2U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP3 ((uint32_t)0x1CU) /*!< ADC Trigger on Timer F compare 3U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP4 ((uint32_t)0x1DU) /*!< ADC Trigger on Timer F compare 4U */
#define HRTIM_ADCTRIGGEREVENT579_TIMERF_PERIOD ((uint32_t)0x1EU) /*!< ADC Trigger on Timer F period */
#define HRTIM_ADCTRIGGEREVENT579_TIMERF_RESET ((uint32_t)0x1FU) /*!< ADC Trigger on Timer F reset */
/**
* @}
*/
/** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
* @{
* @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_SINGLE_CALIBRATION 0xFFFFFFFFU /*!< Non periodic DLL calibration */
#define HRTIM_CALIBRATIONRATE_0 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
#define HRTIM_CALIBRATIONRATE_1 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
#define HRTIM_CALIBRATIONRATE_2 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
#define HRTIM_CALIBRATIONRATE_3 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
/**
* @}
*/
/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
* @{
* @brief Constants defining the registers that can be written during a burst
* DMA operation
*/
#define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_CR2 (HRTIM_BDTUPR_TIMCR2) /*!< TIMxCR2 register is updated by Burst DMA accesses */
#define HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3) /*!< EEFxR3 register is updated by Burst DMA accesses */
/**
* @}
*/
/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
* @{
* @brief Constants used to enable or disable the burst mode controller
*/
#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */
#define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */
/**
* @}
*/
/** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
* @{
* @brief Constants used to enable or disable a fault channel
*/
#define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
#define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */
/**
* @}
*/
/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
* @{
* @brief Constants used to force timer registers update
*/
#define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Force an immediate transfer from the preload to the active register in the master timer */
#define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Force an immediate transfer from the preload to the active register in the timer A */
#define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Force an immediate transfer from the preload to the active register in the timer B */
#define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Force an immediate transfer from the preload to the active register in the timer C */
#define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Force an immediate transfer from the preload to the active register in the timer D */
#define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Force an immediate transfer from the preload to the active register in the timer E */
#define HRTIM_TIMERUPDATE_F (HRTIM_CR2_TFSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer F */
/**
* @}
*/
/** @defgroup HRTIM_Software_Timer_SwapOutput HRTIM Software Timer swap Output
* @{
* @brief Constants used to swap the output of the timer registers
*/
#define HRTIM_TIMERSWAP_A (HRTIM_CR2_SWPA) /*!< Swap the output of the Timer A */
#define HRTIM_TIMERSWAP_B (HRTIM_CR2_SWPB) /*!< Swap the output of the Timer B */
#define HRTIM_TIMERSWAP_C (HRTIM_CR2_SWPC) /*!< Swap the output of the Timer C */
#define HRTIM_TIMERSWAP_D (HRTIM_CR2_SWPD) /*!< Swap the output of the Timer D */
#define HRTIM_TIMERSWAP_E (HRTIM_CR2_SWPE) /*!< Swap the output of the Timer E */
#define HRTIM_TIMERSWAP_F (HRTIM_CR2_SWPF) /*!< Swap the output of the Timer F */
/**
* @}
*/
/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
* @{
* @brief Constants used to force timer counter reset
*/
#define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Reset the master timer counter */
#define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Reset the timer A counter */
#define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Reset the timer B counter */
#define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Reset the timer C counter */
#define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Reset the timer D counter */
#define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Reset the timer E counter */
#define HRTIM_TIMERRESET_TIMER_F (HRTIM_CR2_TFRST) /*!< Reset the timer F counter */
/**
* @}
*/
/** @defgroup HRTIM_Output_Level HRTIM Output Level
* @{
* @brief Constants defining the level of a timer output
*/
#define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Force the output to its active state */
#define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */
#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
(((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
/**
* @}
*/
/** @defgroup HRTIM_Output_State HRTIM Output State
* @{
* @brief Constants defining the state of a timer output
*/
#define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or
inactive level as programmed in the crossbar unit */
#define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the
outputs are disabled by software or during a burst mode operation */
#define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on
FAULTx inputs */
/**
* @}
*/
/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
* @{
* @brief Constants defining the operating state of the burst mode controller
*/
#define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */
#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */
/**
* @}
*/
/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
* @{
* @brief Constants defining on which output the signal is currently applied
* in push-pull mode
*/
#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */
#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
/**
* @}
*/
/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
* @{
* @brief Constants defining on which output the signal was applied, in
* push-pull mode balanced fault mode or delayed idle mode, when the
* protection was triggered
*/
#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
/**
* @}
*/
/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
* @{
*/
#define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
#define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */
#define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */
#define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */
#define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */
#define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */
#define HRTIM_IT_FLT6 HRTIM_IER_FLT6 /*!< Fault 6 interrupt enable */
#define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */
#define HRTIM_IT_DLLRDY HRTIM_IER_DLLRDY /*!< DLL ready interrupt enable */
#define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */
/**
* @}
*/
/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
* @{
*/
#define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */
#define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */
#define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */
#define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */
#define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */
#define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */
#define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */
#define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */
/**
* @}
*/
/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
* @{
*/
#define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */
#define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */
#define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */
#define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */
#define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */
#define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */
#define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */
#define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */
#define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */
#define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */
#define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */
#define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */
#define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */
#define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */
#define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */
/**
* @}
*/
/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
* @{
*/
#define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */
#define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */
#define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */
#define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */
#define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */
#define HRTIM_FLAG_FLT6 HRTIM_ISR_FLT6 /*!< Fault 6 interrupt flag */
#define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */
#define HRTIM_FLAG_DLLRDY HRTIM_ISR_DLLRDY /*!< DLL ready interrupt flag */
#define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */
/**
* @}
*/
/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
* @{
*/
#define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */
#define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */
#define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */
#define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */
#define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */
#define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */
#define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */
/**
* @}
*/
/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
* @{
*/
#define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */
#define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */
#define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */
#define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */
#define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */
#define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */
#define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */
#define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */
#define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */
#define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */
#define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */
#define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */
#define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */
#define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
/**
* @}
*/
/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
* @{
*/
#define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */
#define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */
#define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */
#define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */
#define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */
#define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */
#define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */
#define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */
/**
* @}
*/
/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
* @{
*/
#define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */
#define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */
#define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */
#define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */
#define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */
#define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */
#define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */
#define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */
#define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */
#define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */
#define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */
#define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */
#define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */
#define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */
#define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */
/**
* @}
*/
/**
* @}
*/
/* Private Constants --------------------------------------------------------*/
/** @addtogroup HRTIM_Private_Constants
* @{
*/
#define HRTIM_CAPTUREFTRIGGER_NONE 0x00000000U /*!< 32bit value Capture trigger is disabled */
#define HRTIM_CAPTUREFTRIGGER_TF1_SET (HRTIM_CPT1CR_TF1SET) /*!< 32bit value Capture is triggered by TF1 output inactive to active transition */
#define HRTIM_CAPTUREFTRIGGER_TF1_RESET (HRTIM_CPT1CR_TF1RST) /*!< 32bit value Capture is triggered by TF1 output active to inactive transition */
#define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1 (HRTIM_CPT1CR_TIMFCMP1) /*!< 32bit value Timer F Compare 1 triggers Capture */
#define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2 (HRTIM_CPT1CR_TIMFCMP2) /*!< 32bit value Timer F Compare 2 triggers Capture */
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup HRTIM_Private_Macros
* @{
*/
#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
(((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F))
#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
(((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E) || \
((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F))
#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFF80FFFFU) == 0x00000000U)
#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
(((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
(((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFF000U) == 0x00000000U)
#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
(((OUTPUT) == HRTIM_OUTPUT_TA1) || \
((OUTPUT) == HRTIM_OUTPUT_TA2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
(((OUTPUT) == HRTIM_OUTPUT_TB1) || \
((OUTPUT) == HRTIM_OUTPUT_TB2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
(((OUTPUT) == HRTIM_OUTPUT_TC1) || \
((OUTPUT) == HRTIM_OUTPUT_TC2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
(((OUTPUT) == HRTIM_OUTPUT_TD1) || \
((OUTPUT) == HRTIM_OUTPUT_TD2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
(((OUTPUT) == HRTIM_OUTPUT_TE1) || \
((OUTPUT) == HRTIM_OUTPUT_TE2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \
(((OUTPUT) == HRTIM_OUTPUT_TF1) || \
((OUTPUT) == HRTIM_OUTPUT_TF2))))
#define IS_HRTIM_TIMEEVENT(EVENT)\
(((EVENT) == HRTIM_EVENTCOUNTER_A) || \
((EVENT) == HRTIM_EVENTCOUNTER_B))
#define IS_HRTIM_TIMEEVENT_RESETMODE(EVENT)\
(((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL) || \
((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL))
#define IS_HRTIM_TIMSYNCUPDATE(EVENT)\
(((EVENT) == HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL) || \
((EVENT) == HRTIM_TIMERESYNC_UPDATE_CONDITIONAL))
#define IS_HRTIM_TIMEEVENT_COUNTER(COUNTER)\
((((COUNTER) > (uint32_t)0x00U) && ((COUNTER) <= (uint32_t)0x3FU)) ||\
((COUNTER) == (uint32_t)0x00U))
#define IS_HRTIM_TIMEEVENT_SOURCE(SOURCE)\
(((SOURCE) >= (uint32_t)0x00U) && ((SOURCE) <= (uint32_t)0x9U))
#define IS_HRTIM_EVENT(EVENT)\
(((EVENT) == HRTIM_EVENT_NONE)|| \
((EVENT) == HRTIM_EVENT_1) || \
((EVENT) == HRTIM_EVENT_2) || \
((EVENT) == HRTIM_EVENT_3) || \
((EVENT) == HRTIM_EVENT_4) || \
((EVENT) == HRTIM_EVENT_5) || \
((EVENT) == HRTIM_EVENT_6) || \
((EVENT) == HRTIM_EVENT_7) || \
((EVENT) == HRTIM_EVENT_8) || \
((EVENT) == HRTIM_EVENT_9) || \
((EVENT) == HRTIM_EVENT_10))
#define IS_HRTIM_FAULT(FAULT)\
(((FAULT) == HRTIM_FAULT_1) || \
((FAULT) == HRTIM_FAULT_2) || \
((FAULT) == HRTIM_FAULT_3) || \
((FAULT) == HRTIM_FAULT_4) || \
((FAULT) == HRTIM_FAULT_5) || \
((FAULT) == HRTIM_FAULT_6))
#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
(((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
#define IS_HRTIM_MODE(MODE)\
(((MODE) == HRTIM_MODE_CONTINUOUS) || \
((MODE) == HRTIM_MODE_SINGLESHOT) || \
((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
#define IS_HRTIM_MODE_ONEPULSE(MODE)\
(((MODE) == HRTIM_MODE_SINGLESHOT) || \
((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
#define IS_HRTIM_HALFMODE(HALFMODE)\
(((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
((HALFMODE) == HRTIM_HALFMODE_ENABLED))
#define IS_HRTIM_INTERLEAVEDMODE(INTLVDMODE)\
(((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \
((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DUAL) || \
((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \
((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_TRIPLE) || \
((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED) || \
((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_QUAD))
#define IS_HRTIM_SYNCSTART(SYNCSTART)\
(((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
#define IS_HRTIM_SYNCRESET(SYNCRESET)\
(((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
#define IS_HRTIM_DACSYNC(DACSYNC)\
(((DACSYNC) == HRTIM_DACSYNC_NONE) || \
((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
#define IS_HRTIM_PRELOAD(PRELOAD)\
(((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
((PRELOAD) == HRTIM_PRELOAD_ENABLED))
#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
(((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
#define IS_HRTIM_TIMERBURSTMODE(MODE) \
(((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
#define IS_HRTIM_TIMERUPDOWNMODE(MODE) \
(((MODE) == HRTIM_TIMERUPDOWNMODE_UP) || \
((MODE) == HRTIM_TIMERUPDOWNMODE_UPDOWN))
#define IS_HRTIM_TIMERTRGHLFMODE(MODE) \
(((MODE) == HRTIM_TIMERTRIGHALF_DISABLED) || \
((MODE) == HRTIM_TIMERTRIGHALF_ENABLED))
#define IS_HRTIM_TIMERGTCMP3(MODE) \
(((MODE) == HRTIM_TIMERGTCMP3_EQUAL) || \
((MODE) == HRTIM_TIMERGTCMP3_GREATER))
#define IS_HRTIM_TIMERGTCMP1(MODE) \
(((MODE) == HRTIM_TIMERGTCMP1_EQUAL) || \
((MODE) == HRTIM_TIMERGTCMP1_GREATER))
#define IS_HRTIM_DUALDAC_RESET(DUALCHANNELDAC) \
(((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_COUNTER) || \
((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_OUT1SET))
#define IS_HRTIM_DUALDAC_STEP(DUALCHANNELDAC) \
(((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_CMP2) || \
((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_OUT1RST))
#define IS_HRTIM_DUALDAC_ENABLE(DUALCHANNELDAC) \
(((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_DISABLED) || \
((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_ENABLED ))
#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
(((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFC0U) == 0x00000000U)
#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
(((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
(((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))
#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
|| \
(((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
(((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE06FFFFU) == 0x00000000U)
#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x00000000U) == 0x00000000U)
#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
(((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
/* Auto delayed mode is only available for compare units 2 and 4U */
#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
|| \
(((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
(((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
(((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
#define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)
#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
(((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
(((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
(((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
(((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
(((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \
((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \
((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
(((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
(((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
#define IS_HRTIM_OUTPUTBALANCEDIDLE(OUTPUTBIAR)\
(((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_DISABLED) || \
((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_ENABLED))
#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \
(((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))))
#define IS_HRTIM_TIMER_CAPTUREFTRIGGER(TIMER, CAPTUREFTRIGGER) \
( ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_NONE) || \
((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_SET) || \
((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_RESET) || \
((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1) || \
((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2))
#define IS_HRTIM_TIMEVENTFILTER(TIMER,TIMEVENTFILTER)\
(((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_NONE) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP3) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP3) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGTIM) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
(((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
(((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
(((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
(((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
(((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2))) \
|| \
(((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && \
(((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4) || \
((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2))))
#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
(((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
(((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
(((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
(((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
(((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
(((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
(((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
(((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
(((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \
((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
(((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \
((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \
((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \
((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \
((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \
((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \
((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \
((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
(((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \
((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
(((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
(((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
(((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
#define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC) \
((((EVENT) == HRTIM_EVENT_1) && \
(((EVENTSRC) == HRTIM_EEV1SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT ) || \
((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO ) || \
((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 ))) \
|| \
(((EVENT) == HRTIM_EVENT_2) && \
(((EVENTSRC) == HRTIM_EEV2SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT ) || \
((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO ) || \
((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 ))) \
|| \
(((EVENT) == HRTIM_EVENT_3) && \
(((EVENTSRC) == HRTIM_EEV3SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT ) || \
((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO ) || \
((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 ))) \
|| \
(((EVENT) == HRTIM_EVENT_4) && \
(((EVENTSRC) == HRTIM_EEV4SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT ) || \
((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT ) || \
((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 ))) \
|| \
(((EVENT) == HRTIM_EVENT_5) && \
(((EVENTSRC) == HRTIM_EEV5SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT ) || \
((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT ) || \
((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 ))) \
|| \
(((EVENT) == HRTIM_EVENT_6) && \
(((EVENTSRC) == HRTIM_EEV6SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT ) || \
((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT ) || \
((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 ))) \
|| \
(((EVENT) == HRTIM_EVENT_7) && \
(((EVENTSRC) == HRTIM_EEV7SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT ) || \
((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO ) || \
((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 ))) \
|| \
(((EVENT) == HRTIM_EVENT_8) && \
(((EVENTSRC) == HRTIM_EEV8SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT ) || \
((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT ) || \
((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 ))) \
|| \
(((EVENT) == HRTIM_EVENT_9) && \
(((EVENTSRC) == HRTIM_EEV9SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT ) || \
((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO) || \
((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT ))) \
|| \
(((EVENT) == HRTIM_EVENT_10) && \
(((EVENTSRC) == HRTIM_EEV10SRC_GPIO ) || \
((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT) || \
((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO) || \
((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1))))
#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
(((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
|| \
(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
(((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
(((((EVENT) == HRTIM_EVENT_1) || \
((EVENT) == HRTIM_EVENT_2) || \
((EVENT) == HRTIM_EVENT_3) || \
((EVENT) == HRTIM_EVENT_4) || \
((EVENT) == HRTIM_EVENT_5)) && \
(((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
|| \
(((EVENT) == HRTIM_EVENT_6) || \
((EVENT) == HRTIM_EVENT_7) || \
((EVENT) == HRTIM_EVENT_8) || \
((EVENT) == HRTIM_EVENT_9) || \
((EVENT) == HRTIM_EVENT_10)))
#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
((((EVENT) == HRTIM_EVENT_1) || \
((EVENT) == HRTIM_EVENT_2) || \
((EVENT) == HRTIM_EVENT_3) || \
((EVENT) == HRTIM_EVENT_4) || \
((EVENT) == HRTIM_EVENT_5)) \
|| \
((((EVENT) == HRTIM_EVENT_6) || \
((EVENT) == HRTIM_EVENT_7) || \
((EVENT) == HRTIM_EVENT_8) || \
((EVENT) == HRTIM_EVENT_9) || \
((EVENT) == HRTIM_EVENT_10)) && \
(((FILTER) == HRTIM_EVENTFILTER_NONE) || \
((FILTER) == HRTIM_EVENTFILTER_1) || \
((FILTER) == HRTIM_EVENTFILTER_2) || \
((FILTER) == HRTIM_EVENTFILTER_3) || \
((FILTER) == HRTIM_EVENTFILTER_4) || \
((FILTER) == HRTIM_EVENTFILTER_5) || \
((FILTER) == HRTIM_EVENTFILTER_6) || \
((FILTER) == HRTIM_EVENTFILTER_7) || \
((FILTER) == HRTIM_EVENTFILTER_8) || \
((FILTER) == HRTIM_EVENTFILTER_9) || \
((FILTER) == HRTIM_EVENTFILTER_10) || \
((FILTER) == HRTIM_EVENTFILTER_11) || \
((FILTER) == HRTIM_EVENTFILTER_12) || \
((FILTER) == HRTIM_EVENTFILTER_13) || \
((FILTER) == HRTIM_EVENTFILTER_14) || \
((FILTER) == HRTIM_EVENTFILTER_15))))
#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
(((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
(((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL) || \
((FAULTSOURCE) == HRTIM_FAULTSOURCE_EEVINPUT))
#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
(((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
(((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
#define IS_HRTIM_FAULTBLANKNGMODE(FAULTBLANKINGMODE)\
(((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_RSTALIGNED) || \
((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_MOVING))
#define IS_HRTIM_FAULTBLANKING(FAULTBLANKINGCTL)\
(((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_DISABLED) || \
((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_ENABLED))
#define IS_HRTIM_FAULTCOUNTERRST(HRTIM_FAULTCOUNTERRST)\
(((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_UNCONDITIONAL) || \
((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_CONDITIONAL))
#define IS_HRTIM_FAULTBLANKINGCTL(FAULTBLANKINGCTL)\
(((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_DISABLED) || \
((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_ENABLED))
#define IS_HRTIM_FAULTCOUNTER(FAULTCOUNTER)\
(((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_NONE) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_1) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_2) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_3) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_4) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_5) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_6) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_7) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_8) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_9) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_10) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_11) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_12) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_13) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_14) || \
((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_15))
#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
(((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
((FAULTFILTER) == HRTIM_FAULTFILTER_15))
#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
(((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
(((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
#define IS_HRTIM_BURSTMODE(BURSTMODE)\
(((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
(((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_F) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \
((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
(((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
(((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
(((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_RESET) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERF_CMP1) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
(((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E) || \
((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F))
#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
(((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0) || \
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1) || \
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2) || \
((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3))
#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
|| (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)))
#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
(((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFF80U) == 0x00000000U)
#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFF80FFU) == 0x00000000U)
#define IS_HRTIM_TIMERSWAP(TIMERSWAP) (((TIMERSWAP) & 0xFFC0FFFFU) == 0x00000000U)
#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFF80U) == 0x00000000U)
#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
#define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U)
#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
* @{
*/
/**
* @brief configures the actual direction of the counter to UP counting mode
* @param __HANDLE__ : HRTIM handle.
* @param __TIMER__ : Timer index
* This parameter can be a combination of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
* @arg HRTIM_TIMERINDEX_TIMER_F for timer F
* @retval none
*/
#define __HAL_HRTIM_COUNTER_MODE_UP(__HANDLE__, __TIMERS__)\
do {\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
} while(0U)
/**
* @brief configures the actual direction of the counter to UP-DOWN counting mode
* @param __HANDLE__ : HRTIM handle.
* @param __TIMER__ : Timer index
* This parameter can be a combination of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
* @arg HRTIM_TIMERINDEX_TIMER_F for timer F
* @retval none
*/
#define __HAL_HRTIM_COUNTER_MODE_UPDOWN(__HANDLE__, __TIMERS__)\
do {\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
{\
SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
{\
SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
{\
SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
{\
SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
{\
SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
{\
SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
}\
} while(0U)
/**
* @brief swap the output of the timer
* HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
* HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
* @param __HANDLE__ : HRTIM handle.
* @param __TIMER__ : Timer index
* This parameter can be a combination of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
* @arg HRTIM_TIMERINDEX_TIMER_F for timer F
* @retval none
*/
#define __HAL_HRTIM_TIMER_OUTPUT_SWAP(__HANDLE__, __TIMERS__)\
do {\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
{\
SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
{\
SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
{\
SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
{\
SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
{\
SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
{\
SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \
}\
} while(0U)
/**
* @brief Un-swap the output of the timer
* HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
* HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
* @param __HANDLE__ : HRTIM handle.
* @param __TIMER__ : Timer index
* This parameter can be a combination of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A for timer A
* @arg HRTIM_TIMERINDEX_TIMER_B for timer B
* @arg HRTIM_TIMERINDEX_TIMER_C for timer C
* @arg HRTIM_TIMERINDEX_TIMER_D for timer D
* @arg HRTIM_TIMERINDEX_TIMER_E for timer E
* @arg HRTIM_TIMERINDEX_TIMER_F for timer F
* @retval none
*/
#define __HAL_HRTIM_TIMER_OUTPUT_NOSWAP(__HANDLE__, __TIMERS__)\
do {\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
{\
CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \
}\
} while(0U)
/** @brief Reset HRTIM handle state
* @param __HANDLE__ HRTIM handle.
* @retval None
*/
#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
#endif
/** @brief Enables or disables the timer counter(s)
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __TIMERS__ timers to enable/disable
* This parameter can be any combinations of the following values:
* @arg HRTIM_TIMERID_MASTER: Master timer identifier
* @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
* @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
* @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
* @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
* @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
* @arg HRTIM_TIMERID_TIMER_F: Timer F identifier
* @retval None
*/
#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
/* The counter of a timing unit is disabled only if all the timer outputs */
/* are disabled and no capture is configured */
#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
#define HRTIM_TFOEN_MASK (HRTIM_OENR_TF2OEN | HRTIM_OENR_TF1OEN)
#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
do {\
if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
{\
((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
{\
if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\
{\
((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
}\
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
{\
if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\
{\
((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
}\
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
{\
if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\
{\
((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
}\
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
{\
if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\
{\
((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
}\
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
{\
if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\
{\
((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
}\
}\
if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
{\
if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TFOEN_MASK) == (uint32_t)RESET)\
{\
((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_F);\
}\
}\
} while(0U)
/** @brief Enables the External Event counter
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __TIMERS__ timers to enable/disable
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
* @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
* @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
* @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
* @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
* @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
* @param Event external event Counter A or B for which timer event must be enabled
* This parameter can be one of the following values:
* @arg HRTIM_EVENTCOUNTER_A
* @arg HRTIM_EVENTCOUNTER_B
* @retval None
*/
#define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_ENABLE(__HANDLE__, __TIMER__, __EVENT__)\
do {\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
}\
}\
} while(0U)
/** @brief Disables the External Event counter
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __TIMERS__ timers to enable/disable
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
* @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
* @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
* @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
* @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
* @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
* @param Event external event A or B for which timer event must be disabled
* This parameter can be one of the following values:
* @arg HRTIM_EVENTCOUNTER_A
* @arg HRTIM_EVENTCOUNTER_B
* @retval None
*/
#define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_DISABLE(__HANDLE__, __TIMER__, __EVENT__)\
do {\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
}\
}\
} while(0U)
/** @brief Resets the External Event counter
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __TIMERS__ timers to enable/disable
* This parameter can be one of the following values:
* @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
* @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
* @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
* @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
* @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
* @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
* @param Event external event A or B for which timer event must be reset
* This parameter can be one of the following values:
* @arg HRTIM_EVENTCOUNTER_A
* @arg HRTIM_EVENTCOUNTER_B
* @retval None
*/
#define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_RESET(__HANDLE__, __TIMER__, __EVENT__)\
do {\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
}\
}\
if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
{\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
}\
if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
{\
((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
}\
}\
} while(0U)
/** @brief Enables or disables the specified HRTIM common interrupts.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
* @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
* @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
* @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
* @arg HRTIM_IT_FLT6: Fault 6 interrupt enable
* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
* @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
* @retval None
*/
#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
/** @brief Enables or disables the specified HRTIM Master timer interrupts.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
* @retval None
*/
#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
/** @brief Enables or disables the specified HRTIM Timerx interrupts.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __TIMER__ specified the timing unit (Timer A to F)
* @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
* @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
* @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
* @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
* @retval None
*/
#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
/** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __INTERRUPT__ specifies the interrupt source to check.
* This parameter can be one of the following values:
* @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
* @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
* @arg HRTIM_IT_FLT3: Fault 3 enable
* @arg HRTIM_IT_FLT4: Fault 4 enable
* @arg HRTIM_IT_FLT5: Fault 5 enable
* @arg HRTIM_IT_FLT6: Fault 6 enable
* @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
* @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
* @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __INTERRUPT__ specifies the interrupt source to check.
* This parameter can be one of the following values:
* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __TIMER__ specified the timing unit (Timer A to F)
* @param __INTERRUPT__ specifies the interrupt source to check.
* This parameter can be one of the following values:
* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
* @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
* @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
* @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Clears the specified HRTIM common pending flag.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
* @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
* @arg HRTIM_IT_FLT3: Fault 3 clear flag
* @arg HRTIM_IT_FLT4: Fault 4 clear flag
* @arg HRTIM_IT_FLT5: Fault 5 clear flag
* @arg HRTIM_IT_FLT6: Fault 6 clear flag
* @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
* @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
* @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
* @retval None
*/
#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
/** @brief Clears the specified HRTIM Master pending flag.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
* @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
* @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
* @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
* @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
* @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
* @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
* @retval None
*/
#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
/** @brief Clears the specified HRTIM Timerx pending flag.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __TIMER__ specified the timing unit (Timer A to F)
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
* @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
* @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
* @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
* @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
* @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
* @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
* @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
* @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
* @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
* @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
* @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
* @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
* @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
* @retval None
*/
#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
/* DMA HANDLING */
/** @brief Enables or disables the specified HRTIM Master timer DMA requests.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __DMA__ specifies the DMA request to enable or disable.
* This parameter can be one of the following values:
* @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable
* @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable
* @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable
* @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable
* @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable
* @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable
* @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable
* @retval None
*/
#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
/** @brief Enables or disables the specified HRTIM Timerx DMA requests.
* @param __HANDLE__ specifies the HRTIM Handle.
* @param __TIMER__ specified the timing unit (Timer A to F)
* @param __DMA__ specifies the DMA request to enable or disable.
* This parameter can be one of the following values:
* @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable
* @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable
* @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable
* @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable
* @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable
* @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable
* @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable
* @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable
* @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable
* @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable
* @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable
* @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable
* @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable
* @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable
* @retval None
*/
#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
/** @brief Sets the HRTIM timer Counter Register value on runtime
* @param __HANDLE__ HRTIM Handle.
* @param __TIMER__ HRTIM timer
* This parameter can be one of the following values:
* @arg 0x6 for master timer
* @arg 0x0 to 0x5 for timers A to F
* @param __COUNTER__ specifies the Counter Register new value.
* @retval None
*/
#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
/** @brief Gets the HRTIM timer Counter Register value on runtime
* @param __HANDLE__ HRTIM Handle.
* @param __TIMER__ HRTIM timer
* This parameter can be one of the following values:
* @arg 0x6 for master timer
* @arg 0x0 to 0x5 for timers A to F
* @retval HRTIM timer Counter Register value
*/
#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
/** @brief Sets the HRTIM timer Period value on runtime
* @param __HANDLE__ HRTIM Handle.
* @param __TIMER__ HRTIM timer
* This parameter can be one of the following values:
* @arg 0x6 for master timer
* @arg 0x0 to 0x5 for timers A to F
* @param __PERIOD__ specifies the Period Register new value.
* @retval None
*/
#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
/** @brief Gets the HRTIM timer Period Register value on runtime
* @param __HANDLE__ HRTIM Handle.
* @param __TIMER__ HRTIM timer
* This parameter can be one of the following values:
* @arg 0x6 for master timer
* @arg 0x0 to 0x5 for timers A to F
* @retval timer Period Register
*/
#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
/** @brief Sets the HRTIM timer clock prescaler value on runtime
* @param __HANDLE__ HRTIM Handle.
* @param __TIMER__ HRTIM timer
* This parameter can be one of the following values:
* @arg 0x6 for master timer
* @arg 0x0 to 0x5 for timers A to F
* @param __PRESCALER__ specifies the clock prescaler new value.
* This parameter can be one of the following values:
* @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
* @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
* @retval None
*/
#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
(MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
/** @brief Gets the HRTIM timer clock prescaler value on runtime
* @param __HANDLE__ HRTIM Handle.
* @param __TIMER__ HRTIM timer
* This parameter can be one of the following values:
* @arg 0x6 for master timer
* @arg 0x0 to 0x5 for timers A to F
* @retval timer clock prescaler value
*/
#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
/** @brief Sets the HRTIM timer Compare Register value on runtime
* @param __HANDLE__ HRTIM Handle.
* @param __TIMER__ HRTIM timer
* This parameter can be one of the following values:
* @arg 0x0 to 0x5 for timers A to F
* @param __COMPAREUNIT__ timer compare unit
* This parameter can be one of the following values:
* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
* @param __COMPARE__ specifies the Compare new value.
* @retval None
*/
#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
: \
(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
/** @brief Gets the HRTIM timer Compare Register value on runtime
* @param __HANDLE__ HRTIM Handle.
* @param __TIMER__ HRTIM timer
* This parameter can be one of the following values:
* @arg 0x0 to 0x5 for timers A to F
* @param __COMPAREUNIT__ timer compare unit
* This parameter can be one of the following values:
* @arg HRTIM_COMPAREUNIT_1: Compare unit 1
* @arg HRTIM_COMPAREUNIT_2: Compare unit 2
* @arg HRTIM_COMPAREUNIT_3: Compare unit 3
* @arg HRTIM_COMPAREUNIT_4: Compare unit 4
* @retval Compare value
*/
#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
(((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
: \
(((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
/**
* @brief Enables the Fault Counter
* @param hhrtim pointer to HAL HRTIM handle
* @param Fault fault input to enable
* This parameter can be one of the following values:
* @arg HRTIM_FAULT_1: Fault input 1
* @arg HRTIM_FAULT_2: Fault input 2
* @arg HRTIM_FAULT_3: Fault input 3
* @arg HRTIM_FAULT_4: Fault input 4
* @arg HRTIM_FAULT_5: Fault input 5
* @arg HRTIM_FAULT_6: Fault input 6
* @note This function must be called when fault is not enabled
* @retval HAL status
*/
#define __HAL_HRTIM_FAULT_BLANKING_ENABLE(__HANDLE__, __FAULT__)\
do {\
if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT1BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT2BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT3BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT4BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT5BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT6BLKE;\
}\
} while(0U)
/**
* @brief Disables the Fault Counter
* @param hhrtim pointer to HAL HRTIM handle
* @param Fault fault input to disable
* This parameter can be one of the following values:
* @arg HRTIM_FAULT_1: Fault input 1
* @arg HRTIM_FAULT_2: Fault input 2
* @arg HRTIM_FAULT_3: Fault input 3
* @arg HRTIM_FAULT_4: Fault input 4
* @arg HRTIM_FAULT_5: Fault input 5
* @arg HRTIM_FAULT_6: Fault input 6
* @retval HAL status
*/
#define __HAL_HRTIM_FAULT_BLANKING_DISABLE(__HANDLE__, __FAULT__)\
do {\
if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT1BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT2BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT3BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT4BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT5BLKE;\
}\
if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\
{\
((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT6BLKE;\
}\
} while(0U)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HRTIM_Exported_Functions
* @{
*/
/** @addtogroup HRTIM_Exported_Functions_Group1
* @{
*/
/* Initialization and Configuration functions ********************************/
HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);
HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t CalibrationRate);
HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t CalibrationRate);
HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timeout);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group2
* @{
*/
/* Simple time base related functions *****************************************/
HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t SrcAddr,
uint32_t DestAddr,
uint32_t Length);
HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group3
* @{
*/
/* Simple output compare related functions ************************************/
HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OCChannel,
HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);
HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OCChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OCChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OCChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OCChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OCChannel,
uint32_t SrcAddr,
uint32_t DestAddr,
uint32_t Length);
HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OCChannel);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group4
* @{
*/
/* Simple PWM output related functions ****************************************/
HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t PWMChannel,
HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);
HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t PWMChannel);
HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t PWMChannel);
HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t PWMChannel);
HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t PWMChannel);
HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t PWMChannel,
uint32_t SrcAddr,
uint32_t DestAddr,
uint32_t Length);
HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t PWMChannel);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group5
* @{
*/
/* Simple capture related functions *******************************************/
HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureChannel,
HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);
HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureChannel,
uint32_t SrcAddr,
uint32_t DestAddr,
uint32_t Length);
HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureChannel);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group6
* @{
*/
/* Simple one pulse related functions *****************************************/
HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OnePulseChannel,
HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);
HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OnePulseChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OnePulseChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OnePulseChannel);
HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t OnePulseChannel);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group7
* @{
*/
HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t Event,
HRTIM_EventCfgTypeDef* pEventCfg);
HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t Prescaler);
HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t Fault,
HRTIM_FaultCfgTypeDef* pFaultCfg);
HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t Prescaler);
HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef * hhrtim,
uint32_t Fault,
HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg);
HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef * hhrtim,
uint32_t Fault,
HRTIM_FaultBlankingCfgTypeDef* pFaultBlkCfg);
HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef * hhrtim,
uint32_t Fault);
HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef * hhrtim,
uint32_t Timers);
void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,
uint32_t Faults,
uint32_t Enable);
HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t ADCTrigger,
HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef * hhrtim,
uint32_t ADCTrigger,
uint32_t Postscaler);
HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t RollOverCfg);
HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef * hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef * hhrtim,
uint32_t Timers);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group8
* @{
*/
/* Waveform related functions *************************************************/
HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
HRTIM_TimerCfgTypeDef * pTimerCfg);
HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
HRTIM_TimerCtlTypeDef * pTimerCtl);
HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
HRTIM_TimerCtlTypeDef * pTimerCtl);
HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CompareUnit,
HRTIM_CompareCfgTypeDef* pCompareCfg);
HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureUnit,
HRTIM_CaptureCfgTypeDef* pCaptureCfg);
HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t Output,
HRTIM_OutputCfgTypeDef * pOutputCfg);
HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t Output,
uint32_t OutputLevel);
HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t Event,
HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t EventCounter,
HRTIM_ExternalEventCfgTypeDef* pTimerExternalEventCfg);
HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t EventCounter);
HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t EventCounter);
HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t EventCounter);
HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t RegistersToUpdate);
HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t OutputsToStart);
HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
uint32_t OutputsToStop);
HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
uint32_t Enable);
HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CaptureUnit);
HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t BurstBufferAddress,
uint32_t BurstBufferLength);
HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group9
* @{
*/
/* HRTIM peripheral state functions */
HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);
uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t CaptureUnit);
uint32_t HAL_HRTIM_GetCapturedDir(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t CaptureUnit);
HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t CaptureUnit);
uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t Output);
uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,
uint32_t TimerIdx,
uint32_t Output);
uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t Output);
uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);
uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
/**
* @}
*/
/** @addtogroup HRTIM_Exported_Functions_Group10
* @{
*/
/* IRQ handler */
void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
/* HRTIM events related callback functions */
void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
/* Timer events related callback functions */
void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx);
void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim,
HAL_HRTIM_CallbackIDTypeDef CallbackID,
pHRTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
HAL_HRTIM_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
HAL_HRTIM_CallbackIDTypeDef CallbackID,
pHRTIM_TIMxCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim,
HAL_HRTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HRTIM1 */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_HRTIM_H */
| 333,413 | C | 63.841307 | 229 | 0.606335 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_iwdg.h | /**
******************************************************************************
* @file stm32g4xx_hal_iwdg.h
* @author MCD Application Team
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_IWDG_H
#define STM32G4xx_HAL_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup IWDG IWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IWDG_Exported_Types IWDG Exported Types
* @{
*/
/**
* @brief IWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
This parameter can be a value of @ref IWDG_Prescaler */
uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
} IWDG_InitTypeDef;
/**
* @brief IWDG Handle Structure definition
*/
typedef struct
{
IWDG_TypeDef *Instance; /*!< Register base address */
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
} IWDG_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
* @{
*/
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
/** @defgroup IWDG_Window_option IWDG Window option
* @{
*/
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
* @{
*/
/**
* @brief Enable the IWDG peripheral.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
* @{
*/
/* Initialization/Start functions ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup IWDG_Private_Constants IWDG Private Constants
* @{
*/
/**
* @brief IWDG Key Register BitMask
*/
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{
*/
/**
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__ IWDG handle
* @retval None
*/
#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
/**
* @brief Check IWDG prescaler value.
* @param __PRESCALER__ IWDG prescaler value
* @retval None
*/
#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
((__PRESCALER__) == IWDG_PRESCALER_8) || \
((__PRESCALER__) == IWDG_PRESCALER_16) || \
((__PRESCALER__) == IWDG_PRESCALER_32) || \
((__PRESCALER__) == IWDG_PRESCALER_64) || \
((__PRESCALER__) == IWDG_PRESCALER_128)|| \
((__PRESCALER__) == IWDG_PRESCALER_256))
/**
* @brief Check IWDG reload value.
* @param __RELOAD__ IWDG reload value
* @retval None
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @brief Check IWDG window value.
* @param __WINDOW__ IWDG window value
* @retval None
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_IWDG_H */
| 7,156 | C | 29.071428 | 121 | 0.496227 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_adc_ex.h
* @author MCD Application Team
* @brief Header file of ADC HAL extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_ADC_EX_H
#define STM32G4xx_HAL_ADC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup ADCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
* @{
*/
/**
* @brief ADC Injected Conversion Oversampling structure definition
*/
typedef struct
{
uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
} ADC_InjOversamplingTypeDef;
/**
* @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
* @note Parameters of this structure are shared within 2 scopes:
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation
* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
* ADC state can be either:
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign', 'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
* on ADC groups regular and injected.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
*/
typedef struct
{
uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles.
Conversion time is the addition of sampling time and processing time
(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
It overwrites the last setting.
Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
Refer to device datasheet for timings values. */
uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
It overwrites the last setting.
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
of another parameter update on the fly) */
uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data.
Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */
uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data.
This parameter can be a value of @ref ADCEx_OffsetSign.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow.
This parameter value can be ENABLE or DISABLE.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
This parameter can be set to ENABLE or DISABLE.
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
To maintain JAUTO always enabled, DMA must be configured in circular mode.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
This parameter can be set to ENABLE or DISABLE.
If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
new injected context is set when queue is full, error is triggered by interruption and through function
'HAL_ADCEx_InjectedQueueOverflowCallback'.
Caution: This feature request that the sequence is fully configured before injected conversion start.
Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_injected_external_trigger_source.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
This parameter can be a value of @ref ADC_injected_external_trigger_edge.
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
This parameter can be set to ENABLE or DISABLE.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
} ADC_InjectionConfTypeDef;
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Structure definition of ADC multimode
* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
* Both Master and Slave ADCs must be disabled.
*/
typedef struct
{
uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
Delay range depends on selected resolution:
from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
} ADC_MultiModeTypeDef;
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
* @{
*/
/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
* @{
*/
/* ADC group regular trigger sources for all ADC instances */
#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_CC3 (LL_ADC_INJ_TRIG_EXT_TIM1_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T4_CC3 (LL_ADC_INJ_TRIG_EXT_TIM4_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T4_CC4 (LL_ADC_INJ_TRIG_EXT_TIM4_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T7_TRGO (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_CC2 (LL_ADC_INJ_TRIG_EXT_TIM8_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T16_CC1 (LL_ADC_INJ_TRIG_EXT_TIM16_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T20_TRGO (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T20_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T20_CC2 (LL_ADC_INJ_TRIG_EXT_TIM20_CH2) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_T20_CC4 (LL_ADC_INJ_TRIG_EXT_TIM20_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10) /*!< ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_EXT_IT3 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */
#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
* @{
*/
#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */
#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
/**
* @}
*/
/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
* @{
*/
#define ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */
#define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */
/**
* @}
*/
/** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
/**
* @}
*/
#if defined(ADC_MULTIMODE_SUPPORT)
/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
* @{
*/
#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */
#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */
#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */
#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */
#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */
#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */
#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */
/**
* @}
*/
/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
/**
* @}
*/
/**
* @}
*/
#endif /* ADC_MULTIMODE_SUPPORT */
/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
* @{
*/
#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */
#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/
#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
/**
* @}
*/
/** @defgroup ADC_CFGR_fields ADCx CFGR fields
* @{
*/
#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\
ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\
ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\
ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\
ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
/**
* @}
*/
/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
* @{
*/
#if defined(ADC_SMPR1_SMPPLUS)
#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
#else
#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
ADC_SMPR1_SMP0)
#endif /* ADC_SMPR1_SMPPLUS */
/**
* @}
*/
/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
* @{
*/
/* ADC_CFGR fields of parameters that can be updated when no conversion
(neither regular nor injected) is on-going */
#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
#if defined(ADC_MULTIMODE_SUPPORT)
/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
* @{
*/
/** @brief Force ADC instance in multimode mode independent (multimode disable).
* @note This macro must be used only in case of transition from multimode
* to mode independent and in case of unknown previous state,
* to ensure ADC configuration is in mode independent.
* @note Standard way of multimode configuration change is done from
* HAL ADC handle of ADC master using function
* "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
* Usage of this macro is not the Standard way of multimode
* configuration and can lead to have HAL ADC handles status
* misaligned. Usage of this macro must be limited to cases
* mentioned above.
* @param __HANDLE__ ADC handle.
* @retval None
*/
#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
/**
* @}
*/
#endif /* ADC_MULTIMODE_SUPPORT */
/* Private macros ------------------------------------------------------------*/
/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
* @{
*/
/* Macro reserved for internal HAL driver usage, not intended to be used in */
/* code of final user. */
/**
* @brief Test if conversion trigger of injected group is software start
* or external trigger.
* @param __HANDLE__ ADC handle.
* @retval SET (software start) or RESET (external trigger).
*/
#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
/**
* @brief Check whether or not ADC is independent.
* @param __HANDLE__ ADC handle.
* @note When multimode feature is not available, the macro always returns SET.
* @retval SET (ADC is independent) or RESET (ADC is not).
*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define ADC_IS_INDEPENDENT(__HANDLE__) \
( ( ( ((__HANDLE__)->Instance) == ADC5) \
)? \
SET \
: \
RESET \
)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define ADC_IS_INDEPENDENT(__HANDLE__) \
( ( ( ((__HANDLE__)->Instance) == ADC3) \
)? \
SET \
: \
RESET \
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
/**
* @brief Set the selected injected Channel rank.
* @param __CHANNELNB__ Channel number.
* @param __RANKNB__ Rank number.
* @retval None
*/
#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\
& ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
/**
* @brief Configure ADC injected context queue
* @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
* @retval None
*/
#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
/**
* @brief Configure ADC discontinuous conversion mode for injected group
* @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
* @retval None
*/
#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
/**
* @brief Configure ADC discontinuous conversion mode for regular group
* @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
* @retval None
*/
#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
/**
* @brief Configure the number of discontinuous conversions for regular group.
* @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
* @retval None
*/
#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
/**
* @brief Configure the ADC auto delay mode.
* @param __AUTOWAIT__ Auto delay bit enable or disable.
* @retval None
*/
#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
/**
* @brief Configure ADC continuous conversion mode.
* @param __CONTINUOUS_MODE__ Continuous mode.
* @retval None
*/
#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
/**
* @brief Configure the ADC DMA continuous request.
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
* @retval None
*/
#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Configure the ADC DMA continuous request for ADC multimode.
* @param __DMACONTREQ_MODE__ DMA continuous request mode.
* @retval None
*/
#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Shift the offset with respect to the selected ADC resolution.
* @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
* If resolution 12 bits, no shift.
* If resolution 10 bits, shift of 2 ranks on the left.
* If resolution 8 bits, shift of 4 ranks on the left.
* If resolution 6 bits, shift of 6 ranks on the left.
* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
* @param __HANDLE__ ADC handle
* @param __OFFSET__ Value to be shifted
* @retval None
*/
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
/**
* @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
* @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
* If resolution 12 bits, no shift.
* If resolution 10 bits, shift of 2 ranks on the left.
* If resolution 8 bits, shift of 4 ranks on the left.
* If resolution 6 bits, shift of 6 ranks on the left.
* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
* @param __HANDLE__ ADC handle
* @param __THRESHOLD__ Value to be shifted
* @retval None
*/
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
/**
* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
* @note Thresholds have to be left-aligned on bit 7.
* If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
* If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
* If resolution 8 bits, no shift.
* If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
* @param __HANDLE__ ADC handle
* @param __THRESHOLD__ Value to be shifted
* @retval None
*/
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
((__THRESHOLD__) << 2UL) \
)
/**
* @brief Clear Common Control Register.
* @param __HANDLE__ ADC handle.
* @retval None
*/
#if defined(ADC_MULTIMODE_SUPPORT)
#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
ADC_CCR_CKMODE | \
ADC_CCR_PRESC | \
ADC_CCR_VBATSEL | \
ADC_CCR_VSENSESEL | \
ADC_CCR_VREFEN | \
ADC_CCR_MDMA | \
ADC_CCR_DMACFG | \
ADC_CCR_DELAY | \
ADC_CCR_DUAL)
#endif /* ADC_MULTIMODE_SUPPORT */
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Set handle instance of the ADC slave associated to the ADC master.
* @param __HANDLE_MASTER__ ADC master handle.
* @param __HANDLE_SLAVE__ ADC slave handle.
* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
* @retval None
*/
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
( ((__HANDLE_MASTER__)->Instance == ADC1) ? \
((__HANDLE_SLAVE__)->Instance = ADC2) \
: \
((__HANDLE_MASTER__)->Instance == ADC3) ? \
((__HANDLE_SLAVE__)->Instance = ADC4) \
: \
((__HANDLE_SLAVE__)->Instance = NULL) \
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
/**
* @brief Set handle instance of the ADC slave associated to the ADC master.
* @param __HANDLE_MASTER__ ADC master handle.
* @param __HANDLE_SLAVE__ ADC slave handle.
* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
* @retval None
*/
#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
( ((__HANDLE_MASTER__)->Instance == ADC1) ? \
((__HANDLE_SLAVE__)->Instance = ADC2) \
: \
((__HANDLE_SLAVE__)->Instance = NULL) \
)
#endif
/**
* @brief Verify the ADC instance connected to the temperature sensor.
* @param __HANDLE__ ADC handle.
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
/**
* @brief Verify the ADC instance connected to the battery voltage VBAT.
* @param __HANDLE__ ADC handle.
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
#endif
/**
* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
* @param __HANDLE__ ADC handle.
* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
*/
#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) != ADC2)
/**
* @brief Verify the length of scheduled injected conversions group.
* @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
*/
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
/**
* @brief Calibration factor size verification (7 bits maximum).
* @param __CALIBRATION_FACTOR__ Calibration factor value.
* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
*/
#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
/**
* @brief Verify the ADC channel setting.
* @param __HANDLE__ ADC handle.
* @param __CHANNEL__ programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
((__CHANNEL__) == ADC_CHANNEL_8) || \
((__CHANNEL__) == ADC_CHANNEL_9) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15)) || \
((((__HANDLE__)->Instance) == ADC1) && \
(((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
((((__HANDLE__)->Instance) == ADC2) && \
(((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
((__CHANNEL__) == ADC_CHANNEL_17) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
((((__HANDLE__)->Instance) == ADC3) && \
(((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
((((__HANDLE__)->Instance) == ADC4) && \
(((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
((((__HANDLE__)->Instance) == ADC5) && \
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP5) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP4) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
#elif defined(STM32G471xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
((__CHANNEL__) == ADC_CHANNEL_8) || \
((__CHANNEL__) == ADC_CHANNEL_9) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15)) || \
((((__HANDLE__)->Instance) == ADC1) && \
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
((((__HANDLE__)->Instance) == ADC2) && \
(((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
((__CHANNEL__) == ADC_CHANNEL_17) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
((((__HANDLE__)->Instance) == ADC3) && \
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
((__CHANNEL__) == ADC_CHANNEL_8) || \
((__CHANNEL__) == ADC_CHANNEL_9) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15)) || \
((((__HANDLE__)->Instance) == ADC1) && \
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
((((__HANDLE__)->Instance) == ADC2) && \
(((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
((__CHANNEL__) == ADC_CHANNEL_17) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))))
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
((__CHANNEL__) == ADC_CHANNEL_8) || \
((__CHANNEL__) == ADC_CHANNEL_9) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_14) || \
((__CHANNEL__) == ADC_CHANNEL_15)) || \
((((__HANDLE__)->Instance) == ADC1) && \
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP1) || \
((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1) || \
((__CHANNEL__) == ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))) || \
((((__HANDLE__)->Instance) == ADC2) && \
(((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP2) || \
((__CHANNEL__) == ADC_CHANNEL_17) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))) || \
((((__HANDLE__)->Instance) == ADC3) && \
(((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3) || \
((__CHANNEL__) == ADC_CHANNEL_16) || \
((__CHANNEL__) == ADC_CHANNEL_VOPAMP6) || \
((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
/**
* @brief Verify the ADC channel setting in differential mode.
* @param __HANDLE__ ADC handle.
* @param __CHANNEL__ programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
((__CHANNEL__) == ADC_CHANNEL_8) || \
((__CHANNEL__) == ADC_CHANNEL_9) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_14)) || \
((((__HANDLE__)->Instance) == ADC1) && \
(((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5))) || \
((((__HANDLE__)->Instance) == ADC2) && \
(((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_13))) || \
((((__HANDLE__)->Instance) == ADC3) && \
(((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_15))) || \
((((__HANDLE__)->Instance) == ADC4) && \
(((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_15))) || \
((((__HANDLE__)->Instance) == ADC5) && \
(((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_13) || \
((__CHANNEL__) == ADC_CHANNEL_15))) )
#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
(((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
((__CHANNEL__) == ADC_CHANNEL_8) || \
((__CHANNEL__) == ADC_CHANNEL_9) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_14)) || \
((((__HANDLE__)->Instance) == ADC2) && \
(((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_13))) || \
((((__HANDLE__)->Instance) == ADC3) && \
((__CHANNEL__) == ADC_CHANNEL_15))) )
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ( ( ((__CHANNEL__) == ADC_CHANNEL_1) || \
((__CHANNEL__) == ADC_CHANNEL_2) || \
((__CHANNEL__) == ADC_CHANNEL_3) || \
((__CHANNEL__) == ADC_CHANNEL_4) || \
((__CHANNEL__) == ADC_CHANNEL_5) || \
((__CHANNEL__) == ADC_CHANNEL_6) || \
((__CHANNEL__) == ADC_CHANNEL_7) || \
((__CHANNEL__) == ADC_CHANNEL_8) || \
((__CHANNEL__) == ADC_CHANNEL_9) || \
((__CHANNEL__) == ADC_CHANNEL_10) || \
((__CHANNEL__) == ADC_CHANNEL_11) || \
((__CHANNEL__) == ADC_CHANNEL_14)) || \
((((__HANDLE__)->Instance) == ADC2) && \
(((__CHANNEL__) == ADC_CHANNEL_12) || \
((__CHANNEL__) == ADC_CHANNEL_13))) )
#endif
/**
* @brief Verify the ADC single-ended input or differential mode setting.
* @param __SING_DIFF__ programmed channel setting.
* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
*/
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
/**
* @brief Verify the ADC offset management setting.
* @param __OFFSET_NUMBER__ ADC offset management.
* @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
*/
#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
/**
* @brief Verify the ADC offset sign setting.
* @param __OFFSET_SIGN__ ADC offset sign.
* @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
*/
#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE) )
/**
* @brief Verify the ADC injected channel setting.
* @param __CHANNEL__ programmed ADC injected channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/
#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
((__CHANNEL__) == ADC_INJECTED_RANK_4) )
/**
* @brief Verify the ADC injected conversions external trigger.
* @param __HANDLE__ ADC handle.
* @param __INJTRIG__ programmed ADC injected conversions external trigger.
* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
*/
#if defined(STM32G474xx) || defined(STM32G484xx)
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
#elif defined(STM32G473xx) || defined(STM32G483xx)
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
((((__HANDLE__)->Instance == ADC3) || ((__HANDLE__)->Instance == ADC4) || ((__HANDLE__)->Instance == ADC5)) && \
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
#elif defined(STM32G471xx)
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
((((__HANDLE__)->Instance == ADC3)) && \
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT) || \
((((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)) && \
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15))) || \
(((__HANDLE__)->Instance == ADC3) && \
(((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2) || \
((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3))) || \
((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
#endif
/**
* @brief Verify the ADC edge trigger setting for injected group.
* @param __EDGE__ programmed ADC edge trigger setting.
* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
*/
#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Verify the ADC multimode setting.
* @param __MODE__ programmed ADC multimode setting.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \
((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \
((__MODE__) == ADC_DUALMODE_REGSIMULT) || \
((__MODE__) == ADC_DUALMODE_INTERL) || \
((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
/**
* @brief Verify the ADC multimode DMA access setting.
* @param __MODE__ programmed ADC multimode DMA access setting.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \
((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
/**
* @brief Verify the ADC multimode delay setting.
* @param __DELAY__ programmed ADC multimode delay setting.
* @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
*/
#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Verify the ADC analog watchdog setting.
* @param __WATCHDOG__ programmed ADC analog watchdog setting.
* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
*/
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
/**
* @brief Verify the ADC analog watchdog mode setting.
* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
*/
#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
/**
* @brief Verify the ADC analog watchdog filtering setting.
* @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
* @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
*/
#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE) || \
((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES) || \
((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES) || \
((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES) || \
((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES) || \
((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES) || \
((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES) || \
((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES) )
/**
* @brief Verify the ADC conversion (regular or injected or both).
* @param __CONVERSION__ ADC conversion group.
* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
*/
#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
((__CONVERSION__) == ADC_INJECTED_GROUP) || \
((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
/**
* @brief Verify the ADC event type.
* @param __EVENT__ ADC event.
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
*/
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
((__EVENT__) == ADC_AWD_EVENT) || \
((__EVENT__) == ADC_AWD2_EVENT) || \
((__EVENT__) == ADC_AWD3_EVENT) || \
((__EVENT__) == ADC_OVR_EVENT) || \
((__EVENT__) == ADC_JQOVF_EVENT) )
/**
* @brief Verify the ADC oversampling ratio.
* @param __RATIO__ programmed ADC oversampling ratio.
* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
*/
#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
/**
* @brief Verify the ADC oversampling shift.
* @param __SHIFT__ programmed ADC oversampling shift.
* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
*/
#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
/**
* @brief Verify the ADC oversampling triggered mode.
* @param __MODE__ programmed ADC oversampling triggered mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
/**
* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
/**
* @brief Verify the DFSDM mode configuration.
* @param __HANDLE__ ADC handle.
* @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
* this reason, the input parameter is the ADC handle and not the configuration parameter
* directly.
* @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
*/
#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
/**
* @brief Return the DFSDM configuration mode.
* @param __HANDLE__ ADC handle.
* @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
* For this reason, the input parameter is the ADC handle and not the configuration parameter
* directly.
* @retval DFSDM configuration mode
*/
#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ADCEx_Exported_Functions
* @{
*/
/** @addtogroup ADCEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
/* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
uint32_t CalibrationFactor);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
/* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
#if defined(ADC_MULTIMODE_SUPPORT)
/* ADC multimode */
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
#endif /* ADC_MULTIMODE_SUPPORT */
/* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
/* ADC group regular conversions stop */
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
#if defined(ADC_MULTIMODE_SUPPORT)
HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @addtogroup ADCEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
ADC_InjectionConfTypeDef *sConfigInjected);
#if defined(ADC_MULTIMODE_SUPPORT)
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
#endif /* ADC_MULTIMODE_SUPPORT */
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_ADC_EX_H */
| 108,288 | C | 76.682209 | 277 | 0.465148 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h | /**
******************************************************************************
* @file stm32g4xx_ll_adc.h
* @author MCD Application Team
* @brief Header file of ADC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_ADC_H
#define STM32G4xx_LL_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
/** @defgroup ADC_LL ADC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup ADC_LL_Private_Constants ADC Private Constants
* @{
*/
/* Internal mask for ADC group regular sequencer: */
/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
/* - sequencer register offset */
/* - sequencer rank bits position into the selected register */
/* Internal register offset for ADC group regular sequencer configuration */
/* (offset placed into a spare area of literal definition) */
#define ADC_SQR1_REGOFFSET (0x00000000UL)
#define ADC_SQR2_REGOFFSET (0x00000100UL)
#define ADC_SQR3_REGOFFSET (0x00000200UL)
#define ADC_SQR4_REGOFFSET (0x00000300UL)
#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
| ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
#define ADC_SQRX_REGOFFSET_POS (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */
#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
/* Definition of ADC group regular sequencer bits information to be inserted */
/* into ADC group regular sequencer ranks literals definition. */
#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS (ADC_SQR1_SQ1_Pos)
#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS (ADC_SQR1_SQ2_Pos)
#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (ADC_SQR1_SQ3_Pos)
#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (ADC_SQR1_SQ4_Pos)
#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (ADC_SQR2_SQ5_Pos)
#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (ADC_SQR2_SQ6_Pos)
#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (ADC_SQR2_SQ7_Pos)
#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (ADC_SQR2_SQ8_Pos)
#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (ADC_SQR2_SQ9_Pos)
#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
/* Internal mask for ADC group injected sequencer: */
/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
/* - data register offset */
/* - sequencer rank bits position into the selected register */
/* Internal register offset for ADC group injected data register */
/* (offset placed into a spare area of literal definition) */
#define ADC_JDR1_REGOFFSET (0x00000000UL)
#define ADC_JDR2_REGOFFSET (0x00000100UL)
#define ADC_JDR3_REGOFFSET (0x00000200UL)
#define ADC_JDR4_REGOFFSET (0x00000300UL)
#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
| ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
#define ADC_JDRX_REGOFFSET_POS (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */
/* Definition of ADC group injected sequencer bits information to be inserted */
/* into ADC group injected sequencer ranks literals definition. */
#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ1_Pos)
#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ2_Pos)
#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ3_Pos)
#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (ADC_JSQR_JSQ4_Pos)
/* Internal mask for ADC group regular trigger: */
/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
/* - regular trigger source */
/* - regular trigger edge */
#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
((ADC_CFGR_EXTSEL) << (4U * 1UL)) | \
((ADC_CFGR_EXTSEL) << (4U * 2UL)) | \
((ADC_CFGR_EXTSEL) << (4U * 3UL)) )
/* Mask containing trigger edge masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
/* Definition of ADC group regular trigger bits information. */
#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (ADC_CFGR_EXTSEL_Pos)
#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (ADC_CFGR_EXTEN_Pos)
/* Internal mask for ADC group injected trigger: */
/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
/* - injected trigger source */
/* - injected trigger edge */
#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
/* Mask containing trigger source masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL) << (4U * 0UL)) | \
((ADC_JSQR_JEXTSEL) << (4U * 1UL)) | \
((ADC_JSQR_JEXTSEL) << (4U * 2UL)) | \
((ADC_JSQR_JEXTSEL) << (4U * 3UL)) )
/* Mask containing trigger edge masks for each of possible */
/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \
((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) )
/* Definition of ADC group injected trigger bits information. */
#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (ADC_JSQR_JEXTSEL_Pos)
#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (ADC_JSQR_JEXTEN_Pos)
/* Internal mask for ADC channel: */
/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
/* - channel identifier defined by number */
/* - channel identifier defined by bitfield */
/* - channel differentiation between external channels (connected to */
/* GPIO pins) and internal channels (connected to internal paths) */
/* - channel sampling time defined by SMPRx register offset */
/* and SMPx bits positions into SMPRx register */
#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR_AWD1CH)
#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
| ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
/* Channel differentiation between external and internal channels */
#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */
#define ADC_CHANNEL_ID_INTERNAL_CH_2 (0x00080000UL) /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
/* Internal register offset for ADC channel sampling time configuration */
/* (offset placed into a spare area of literal definition) */
#define ADC_SMPR1_REGOFFSET (0x00000000UL)
#define ADC_SMPR2_REGOFFSET (0x02000000UL)
#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
#define ADC_SMPRX_REGOFFSET_POS (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
#define ADC_CHANNEL_SMPx_BITOFFSET_MASK (0x01F00000UL)
#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */
/* Definition of channels ID number information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_NUMBER (0x00000000UL)
#define ADC_CHANNEL_1_NUMBER (ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_2_NUMBER (ADC_CFGR_AWD1CH_1)
#define ADC_CHANNEL_3_NUMBER (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_4_NUMBER (ADC_CFGR_AWD1CH_2)
#define ADC_CHANNEL_5_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_6_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define ADC_CHANNEL_7_NUMBER (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_8_NUMBER (ADC_CFGR_AWD1CH_3)
#define ADC_CHANNEL_9_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_10_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
#define ADC_CHANNEL_11_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_12_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
#define ADC_CHANNEL_13_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_14_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
#define ADC_CHANNEL_15_NUMBER (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_16_NUMBER (ADC_CFGR_AWD1CH_4)
#define ADC_CHANNEL_17_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
#define ADC_CHANNEL_18_NUMBER (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
/* Definition of channels ID bitfield information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_BITFIELD (ADC_AWD2CR_AWD2CH_0)
#define ADC_CHANNEL_1_BITFIELD (ADC_AWD2CR_AWD2CH_1)
#define ADC_CHANNEL_2_BITFIELD (ADC_AWD2CR_AWD2CH_2)
#define ADC_CHANNEL_3_BITFIELD (ADC_AWD2CR_AWD2CH_3)
#define ADC_CHANNEL_4_BITFIELD (ADC_AWD2CR_AWD2CH_4)
#define ADC_CHANNEL_5_BITFIELD (ADC_AWD2CR_AWD2CH_5)
#define ADC_CHANNEL_6_BITFIELD (ADC_AWD2CR_AWD2CH_6)
#define ADC_CHANNEL_7_BITFIELD (ADC_AWD2CR_AWD2CH_7)
#define ADC_CHANNEL_8_BITFIELD (ADC_AWD2CR_AWD2CH_8)
#define ADC_CHANNEL_9_BITFIELD (ADC_AWD2CR_AWD2CH_9)
#define ADC_CHANNEL_10_BITFIELD (ADC_AWD2CR_AWD2CH_10)
#define ADC_CHANNEL_11_BITFIELD (ADC_AWD2CR_AWD2CH_11)
#define ADC_CHANNEL_12_BITFIELD (ADC_AWD2CR_AWD2CH_12)
#define ADC_CHANNEL_13_BITFIELD (ADC_AWD2CR_AWD2CH_13)
#define ADC_CHANNEL_14_BITFIELD (ADC_AWD2CR_AWD2CH_14)
#define ADC_CHANNEL_15_BITFIELD (ADC_AWD2CR_AWD2CH_15)
#define ADC_CHANNEL_16_BITFIELD (ADC_AWD2CR_AWD2CH_16)
#define ADC_CHANNEL_17_BITFIELD (ADC_AWD2CR_AWD2CH_17)
#define ADC_CHANNEL_18_BITFIELD (ADC_AWD2CR_AWD2CH_18)
/* Definition of channels sampling time information to be inserted into */
/* channels literals definition. */
#define ADC_CHANNEL_0_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */
#define ADC_CHANNEL_1_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */
#define ADC_CHANNEL_2_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */
#define ADC_CHANNEL_3_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */
#define ADC_CHANNEL_4_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */
#define ADC_CHANNEL_5_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */
#define ADC_CHANNEL_6_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */
#define ADC_CHANNEL_7_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */
#define ADC_CHANNEL_8_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */
#define ADC_CHANNEL_9_SMP (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */
#define ADC_CHANNEL_10_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */
#define ADC_CHANNEL_11_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */
#define ADC_CHANNEL_12_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */
#define ADC_CHANNEL_13_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */
#define ADC_CHANNEL_14_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */
#define ADC_CHANNEL_15_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */
#define ADC_CHANNEL_16_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */
#define ADC_CHANNEL_17_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */
#define ADC_CHANNEL_18_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */
/* Internal mask for ADC mode single or differential ended: */
/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL */
/* the relevant bits for: */
/* (concatenation of multiple bits used in different registers) */
/* - ADC calibration: calibration start, calibration factor get or set */
/* - ADC channels: set each ADC channel ending mode */
#define ADC_SINGLEDIFF_CALIB_START_MASK (ADC_CR_ADCALDIF)
#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
#define ADC_SINGLEDIFF_CHANNEL_MASK (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */
#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK (0x00010000UL) /* Selection of 1 bit to discriminate differential mode: mask of bit */
#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS (16UL) /* Selection of 1 bit to discriminate differential mode: position of bit */
#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */
/* Internal mask for ADC analog watchdog: */
/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
/* (concatenation of multiple bits used in different analog watchdogs, */
/* (feature of several watchdogs not available on all STM32 families)). */
/* - analog watchdog 1: monitored channel defined by number, */
/* selection of ADC group (ADC groups regular and-or injected). */
/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */
/* selection on groups. */
/* Internal register offset for ADC analog watchdog channel configuration */
#define ADC_AWD_CR1_REGOFFSET (0x00000000UL)
#define ADC_AWD_CR2_REGOFFSET (0x00100000UL)
#define ADC_AWD_CR3_REGOFFSET (0x00200000UL)
/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0)
#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL)
#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH)
#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */
/* Internal register offset for ADC analog watchdog threshold configuration */
#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET)
#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET)
#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */
#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate threshold high: mask of bit */
#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate threshold high: position of bit */
#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to position to perform a shift of 4 ranks */
/* Internal mask for ADC offset: */
/* Internal register offset for ADC offset number configuration */
#define ADC_OFR1_REGOFFSET (0x00000000UL)
#define ADC_OFR2_REGOFFSET (0x00000001UL)
#define ADC_OFR3_REGOFFSET (0x00000002UL)
#define ADC_OFR4_REGOFFSET (0x00000003UL)
#define ADC_OFRx_REGOFFSET_MASK (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
| ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
/* ADC registers bits positions */
#define ADC_CFGR_RES_BITOFFSET_POS (ADC_CFGR_RES_Pos)
#define ADC_CFGR_AWD1SGL_BITOFFSET_POS (ADC_CFGR_AWD1SGL_Pos)
#define ADC_CFGR_AWD1EN_BITOFFSET_POS (ADC_CFGR_AWD1EN_Pos)
#define ADC_CFGR_JAWD1EN_BITOFFSET_POS (ADC_CFGR_JAWD1EN_Pos)
#define ADC_TR1_HT1_BITOFFSET_POS (ADC_TR1_HT1_Pos)
/* ADC registers bits groups */
#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */
/* ADC internal channels related definitions */
/* Internal voltage reference VrefInt */
#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
/* Temperature sensor */
#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32G4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75CAUL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32G4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
#define TEMPSENSOR_CAL1_TEMP (30L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL2_TEMP (130L) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
#define TEMPSENSOR_CAL_VREFANALOG (3000UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup ADC_LL_Private_Macros ADC Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
*/
#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of ADC common parameters
* and multimode
* (all ADC instances belonging to the same ADC common instance).
* @note The setting of these parameters by function @ref LL_ADC_CommonInit()
* is conditioned to ADC instances state (all ADC instances
* sharing the same ADC common instance):
* All ADC instances sharing the same ADC common instance must be
* disabled.
*/
typedef struct
{
uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler.
This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
@note On this STM32 series, if ADC group injected is used, some
clock ratio constraints between ADC clock and AHB clock
must be respected. Refer to reference manual.
This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */
uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases.
This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */
#endif /* ADC_MULTIMODE_SUPPORT */
} LL_ADC_CommonInitTypeDef;
/**
* @brief Structure definition of some features of ADC instance.
* @note These parameters have an impact on ADC scope: ADC instance.
* Affects both group regular and group injected (availability
* of ADC group injected depends on STM32 families).
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Instance .
* @note The setting of these parameters by function @ref LL_ADC_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
*/
typedef struct
{
uint32_t Resolution; /*!< Set ADC resolution.
This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */
uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
uint32_t LowPowerMode; /*!< Set ADC low power mode.
This parameter can be a value of @ref ADC_LL_EC_LP_MODE
This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */
} LL_ADC_InitTypeDef;
/**
* @brief Structure definition of some features of ADC group regular.
* @note These parameters have an impact on ADC scope: ADC group regular.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "REG").
* @note The setting of these parameters by function @ref LL_ADC_REG_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
@note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
@note This parameter has an effect only if group regular sequencer is enabled
(scan length of 2 ranks or more).
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun:
data preserved or overwritten.
This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */
} LL_ADC_REG_InitTypeDef;
/**
* @brief Structure definition of some features of ADC group injected.
* @note These parameters have an impact on ADC scope: ADC group injected.
* Refer to corresponding unitary functions into
* @ref ADC_LL_EF_Configuration_ADC_Group_Regular
* (functions with prefix "INJ").
* @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
* is conditioned to ADC state:
* ADC instance must be disabled.
* This condition is applied to all ADC features, for efficiency
* and compatibility over all STM32 families. However, the different
* features can be set under different ADC state conditions
* (setting possible with ADC enabled without conversion on going,
* ADC enabled with conversion on going, ...)
* Each feature can be updated afterwards with a unitary function
* and potentially with ADC in a different state than disabled,
* refer to description of each function for setting
* conditioned to ADC state.
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
@note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge
(default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).
In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().
This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
@note This parameter has an effect only if group injected sequencer is enabled
(scan length of 2 ranks or more).
This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
} LL_ADC_INJ_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
* @{
*/
/** @defgroup ADC_LL_EC_FLAG ADC flags
* @brief Flags defines which can be used with LL_ADC_ReadReg function
* @{
*/
#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */
#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */
#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */
#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */
#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */
#define LL_ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC flag ADC group injected end of unitary conversion */
#define LL_ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC flag ADC group injected end of sequence conversions */
#define LL_ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC flag ADC group injected contexts queue overflow */
#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */
#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */
#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */
#if defined(ADC_MULTIMODE_SUPPORT)
#define LL_ADC_FLAG_ADRDY_MST ADC_CSR_ADRDY_MST /*!< ADC flag ADC multimode master instance ready */
#define LL_ADC_FLAG_ADRDY_SLV ADC_CSR_ADRDY_SLV /*!< ADC flag ADC multimode slave instance ready */
#define LL_ADC_FLAG_EOC_MST ADC_CSR_EOC_MST /*!< ADC flag ADC multimode master group regular end of unitary conversion */
#define LL_ADC_FLAG_EOC_SLV ADC_CSR_EOC_SLV /*!< ADC flag ADC multimode slave group regular end of unitary conversion */
#define LL_ADC_FLAG_EOS_MST ADC_CSR_EOS_MST /*!< ADC flag ADC multimode master group regular end of sequence conversions */
#define LL_ADC_FLAG_EOS_SLV ADC_CSR_EOS_SLV /*!< ADC flag ADC multimode slave group regular end of sequence conversions */
#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR_MST /*!< ADC flag ADC multimode master group regular overrun */
#define LL_ADC_FLAG_OVR_SLV ADC_CSR_OVR_SLV /*!< ADC flag ADC multimode slave group regular overrun */
#define LL_ADC_FLAG_EOSMP_MST ADC_CSR_EOSMP_MST /*!< ADC flag ADC multimode master group regular end of sampling phase */
#define LL_ADC_FLAG_EOSMP_SLV ADC_CSR_EOSMP_SLV /*!< ADC flag ADC multimode slave group regular end of sampling phase */
#define LL_ADC_FLAG_JEOC_MST ADC_CSR_JEOC_MST /*!< ADC flag ADC multimode master group injected end of unitary conversion */
#define LL_ADC_FLAG_JEOC_SLV ADC_CSR_JEOC_SLV /*!< ADC flag ADC multimode slave group injected end of unitary conversion */
#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOS_MST /*!< ADC flag ADC multimode master group injected end of sequence conversions */
#define LL_ADC_FLAG_JEOS_SLV ADC_CSR_JEOS_SLV /*!< ADC flag ADC multimode slave group injected end of sequence conversions */
#define LL_ADC_FLAG_JQOVF_MST ADC_CSR_JQOVF_MST /*!< ADC flag ADC multimode master group injected contexts queue overflow */
#define LL_ADC_FLAG_JQOVF_SLV ADC_CSR_JQOVF_SLV /*!< ADC flag ADC multimode slave group injected contexts queue overflow */
#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1_MST /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
#define LL_ADC_FLAG_AWD1_SLV ADC_CSR_AWD1_SLV /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */
#define LL_ADC_FLAG_AWD2_MST ADC_CSR_AWD2_MST /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */
#define LL_ADC_FLAG_AWD2_SLV ADC_CSR_AWD2_SLV /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */
#define LL_ADC_FLAG_AWD3_MST ADC_CSR_AWD3_MST /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */
#define LL_ADC_FLAG_AWD3_SLV ADC_CSR_AWD3_SLV /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
* @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
* @{
*/
#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */
#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */
#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */
#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */
#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */
#define LL_ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC interruption ADC group injected end of unitary conversion */
#define LL_ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC interruption ADC group injected end of sequence conversions */
#define LL_ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC interruption ADC group injected contexts queue overflow */
#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */
#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */
#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
* @{
*/
/* List of ADC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
#if defined(ADC_MULTIMODE_SUPPORT)
#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source
* @{
*/
#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock without prescaler */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CCR_CKMODE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */
#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */
#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */
#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */
#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4 */
#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6 */
#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8 */
#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10 */
#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12 */
#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16 */
#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */
#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64 */
#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128 */
#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
* @{
*/
/* Note: Other measurement paths to internal channels may be available */
/* (connections to other peripherals). */
/* If they are not listed below, they do not require any specific */
/* path enable. In this case, Access to measurement path is done */
/* only by selecting the corresponding ADC internal channel. */
#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */
#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */
#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_VSENSESEL) /*!< ADC measurement path to internal channel temperature sensor */
#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATSEL) /*!< ADC measurement path to internal channel Vbat */
/**
* @}
*/
/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
* @{
*/
#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */
#define LL_ADC_RESOLUTION_10B ( ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */
#define LL_ADC_RESOLUTION_8B (ADC_CFGR_RES_1 ) /*!< ADC resolution 8 bits */
#define LL_ADC_RESOLUTION_6B (ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 6 bits */
/**
* @}
*/
/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
* @{
*/
#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/
/**
* @}
*/
/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode
* @{
*/
#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */
#define LL_ADC_LP_AUTOWAIT (ADC_CFGR_AUTDLY) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OFFSET_NB ADC instance - Offset number
* @{
*/
#define LL_ADC_OFFSET_1 ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define LL_ADC_OFFSET_2 ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define LL_ADC_OFFSET_3 ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
#define LL_ADC_OFFSET_4 ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
* @{
*/
#define LL_ADC_OFFSET_DISABLE (0x00000000UL) /*!< ADC offset disabled (among ADC selected offset number 1, 2, 3 or 4) */
#define LL_ADC_OFFSET_ENABLE (ADC_OFR1_OFFSET1_EN) /*!< ADC offset enabled (among ADC selected offset number 1, 2, 3 or 4) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
* @{
*/
#define LL_ADC_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< ADC offset is negative (among ADC selected offset number 1, 2, 3 or 4) */
#define LL_ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive (among ADC selected offset number 1, 2, 3 or 4) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
* @{
*/
#define LL_ADC_OFFSET_SATURATION_DISABLE (0x00000000UL) /*!< ADC offset saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */
#define LL_ADC_OFFSET_SATURATION_ENABLE (ADC_OFR1_SATEN) /*!< ADC offset saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
* @{
*/
#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
#define LL_ADC_GROUP_INJECTED (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/
#define LL_ADC_GROUP_REGULAR_INJECTED (0x00000003UL) /*!< ADC both groups regular and injected */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
* @{
*/
#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */
#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On this STM32 series, ADC channel available on all instances but ADC2. */
#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC1 instance. */
#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (LL_ADC_CHANNEL_4 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 availaibility */
#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On this STM32 series, ADC channel available on all ADC instances but ADC2 & ADC4. Refer to device datasheet for ADC4 availaibility */
#define LL_ADC_CHANNEL_VOPAMP1 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP1 output. On this STM32 series, ADC channel available only on ADC1 instance. */
#define LL_ADC_CHANNEL_VOPAMP2 (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2 output. On this STM32 series, ADC channel available only on ADC2 instance. */
#define LL_ADC_CHANNEL_VOPAMP3_ADC2 (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC2 instance. */
#define LL_ADC_CHANNEL_VOPAMP3_ADC3 (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3 output. On this STM32 series, ADC channel available only on ADC3 instance. Refer to device datasheet for ADC3 availability */
#define LL_ADC_CHANNEL_VOPAMP4 (LL_ADC_CHANNEL_5 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP4 availability */
#define LL_ADC_CHANNEL_VOPAMP5 (LL_ADC_CHANNEL_3 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance. Refer to device datasheet for ADC5 & OPAMP5 availability */
#define LL_ADC_CHANNEL_VOPAMP6 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP6 output. On this STM32 series, ADC channel available only on ADC4 instance. Refer to device datasheet for ADC4 & OPAMP6 availability */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
* @{
*/
#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!<
ADC group regular conversion trigger internal: SW start. */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM2_CH1 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_REG_TRIG_EXT_TIM3_CH4 (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM4_CH1 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2 (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_TIM20_CH1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM20 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_TIM20_CH2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_TIM20_CH3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: TIM20 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances, and TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10 (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: external interrupt line 2. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group regular conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
* @{
*/
#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */
#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */
#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE ADC group regular - Sampling mode
* @{
*/
#define LL_ADC_REG_SAMPLING_MODE_NORMAL (0x00000000UL) /*!< ADC conversions sampling phase duration is defined using @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
#define LL_ADC_REG_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts immediately after end of conversion, and stops upon trigger event.
Note: First conversion is using minimal sampling time (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled by trigger events:
Trigger rising edge = start sampling
Trigger falling edge = stop sampling and start conversion */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
* @{
*/
#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */
#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
* @{
*/
#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */
#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */
#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
/**
* @}
*/
#if defined(ADC_SMPR1_SMPPLUS)
/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
* @{
*/
#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT (0x00000000UL) /*!< ADC sampling time let to default settings. */
#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped with selection sampling time 2.5 ADC clock cycles, whatever channels mapped on ADC groups regular or injected). */
/**
* @}
*/
#endif
/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data
* @{
*/
#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */
#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
* @{
*/
#define LL_ADC_REG_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
* @{
*/
#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */
#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
/**
* @}
*/
/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
* @{
*/
#define LL_ADC_REG_RANK_1 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
#define LL_ADC_REG_RANK_2 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
#define LL_ADC_REG_RANK_3 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
#define LL_ADC_REG_RANK_4 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
#define LL_ADC_REG_RANK_5 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
#define LL_ADC_REG_RANK_6 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
#define LL_ADC_REG_RANK_10 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
#define LL_ADC_REG_RANK_11 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
#define LL_ADC_REG_RANK_12 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
#define LL_ADC_REG_RANK_13 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
#define LL_ADC_REG_RANK_14 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
#define LL_ADC_REG_RANK_15 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
#define LL_ADC_REG_RANK_16 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
* @{
*/
#define LL_ADC_INJ_TRIG_SOFTWARE (0x00000000UL) /*!<
ADC group injected conversion trigger internal: SW start.. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM7 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */
#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances */
#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM20 TRGO. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM20 TRGO2. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM20 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: TIM20 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting).
Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 1 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 2 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 3 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances, and HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 4 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 5 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 6 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 7 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 8 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 9 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10 (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: HRTIMER ADC trigger 10 event. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, HRTIM is not available on all devices. Refer to device datasheet for more details */
#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: external interrupt line 3. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC3/4/5 instances. Refer to device datasheet for ADCx availaibility */
#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting).
Note: On this STM32 series, this trigger is available only on ADC1/2 instances. */
#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
ADC group injected conversion trigger from external peripheral: LPTIMER OUT event. Trigger edge set to rising edge (default setting). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
* @{
*/
#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */
#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_JSQR_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */
#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
* @{
*/
#define LL_ADC_INJ_TRIG_INDEPENDENT (0x00000000UL) /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CFGR_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE ADC group injected - Context queue mode
* @{
*/
#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */
#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY (ADC_CFGR_JQM) /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */
#define LL_ADC_INJ_QUEUE_DISABLE (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
* @{
*/
#define LL_ADC_INJ_SEQ_SCAN_DISABLE (0x00000000UL) /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
* @{
*/
#define LL_ADC_INJ_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group injected sequencer discontinuous mode disable */
#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
/**
* @}
*/
/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
* @{
*/
#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */
#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */
#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */
#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
* @{
*/
#define LL_ADC_SAMPLINGTIME_2CYCLES_5 (0x00000000UL) /*!< Sampling time 2.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_6CYCLES_5 ( ADC_SMPR2_SMP10_0) /*!< Sampling time 6.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_12CYCLES_5 ( ADC_SMPR2_SMP10_1 ) /*!< Sampling time 12.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_24CYCLES_5 ( ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_47CYCLES_5 (ADC_SMPR2_SMP10_2 ) /*!< Sampling time 47.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_92CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_247CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 ) /*!< Sampling time 247.5 ADC clock cycles */
#define LL_ADC_SAMPLINGTIME_640CYCLES_5 (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
/**
* @}
*/
/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
* @{
*/
#define LL_ADC_SINGLE_ENDED ( ADC_CALFACT_CALFACT_S) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */
#define LL_ADC_DIFFERENTIAL_ENDED (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */
#define LL_ADC_BOTH_SINGLE_DIFF_ENDED (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
* @{
*/
#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
* @{
*/
#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */
#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
#define LL_ADC_AWD_ALL_CHANNELS_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */
#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */
#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group regular only */
#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by group injected only */
#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC1 internal channel connected to Temperature sensor, converted by either group regular or injected */
#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group regular only */
#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by group injected only */
#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC5 internal channel connected to Temperature sensor, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */
#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */
#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */
#define LL_ADC_AWD_CH_VOPAMP1_REG ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group regular only */
#define LL_ADC_AWD_CH_VOPAMP1_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by group injected only */
#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ ((LL_ADC_CHANNEL_VOPAMP1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP1 output, channel specific to ADC1, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VOPAMP2_REG ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group regular only */
#define LL_ADC_AWD_CH_VOPAMP2_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by group injected only */
#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP2 output, channel specific to ADC2, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group regular only */
#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by group injected only */
#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC2, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group regular only */
#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by group injected only */
#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP3 output, channel specific to ADC3, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VOPAMP4_REG ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group regular only */
#define LL_ADC_AWD_CH_VOPAMP4_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by group injected only */
#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ ((LL_ADC_CHANNEL_VOPAMP4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP4 output, channel specific to ADC5, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VOPAMP5_REG ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group regular only */
#define LL_ADC_AWD_CH_VOPAMP5_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by group injected only */
#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ ((LL_ADC_CHANNEL_VOPAMP5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP5 output, channel specific to ADC5, converted by either group regular or injected */
#define LL_ADC_AWD_CH_VOPAMP6_REG ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group regular only */
#define LL_ADC_AWD_CH_VOPAMP6_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by group injected only */
#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ ((LL_ADC_CHANNEL_VOPAMP6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to OPAMP6 output, channel specific to ADC4, converted by either group regular or injected */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
* @{
*/
#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR1_HT1 ) /*!< ADC analog watchdog threshold high */
#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR1_LT1) /*!< ADC analog watchdog threshold low */
#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR1_HT1 | ADC_TR1_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */
/**
* @}
*/
/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG Analog watchdog - filtering config
* @{
*/
#define LL_ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC analog wathdog no filtering, one out-of-window sample is needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_2SAMPLES ( ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 2 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_3SAMPLES ( ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 3 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_4SAMPLES ( ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 4 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_5SAMPLES (ADC_TR1_AWDFILT_2 ) /*!< ADC analog wathdog 5 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_6SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 6 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_7SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 ) /*!< ADC analog wathdog 7 consecutives out-of-window samples are needed to raise flag or interrupt */
#define LL_ADC_AWD_FILTERING_8SAMPLES (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog wathdog 8 consecutives out-of-window samples are needed to raise flag or interrupt */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope
* @{
*/
#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */
#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */
#define LL_ADC_OVS_GRP_REGULAR_RESUMED (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
#define LL_ADC_OVS_GRP_INJECTED ( ADC_CFGR2_JOVSE ) /*!< ADC oversampling on conversions of ADC group injected. */
#define LL_ADC_OVS_GRP_INJ_REG_RESUMED ( ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode
* @{
*/
#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */
#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio
* @{
*/
#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
/**
* @}
*/
/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift
* @{
*/
#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */
#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */
/**
* @}
*/
#if defined(ADC_MULTIMODE_SUPPORT)
/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
* @{
*/
#define LL_ADC_MULTI_INDEPENDENT (0x00000000UL) /*!< ADC dual mode disabled (ADC independent mode) */
#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */
#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */
#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_DUAL_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */
/**
* @}
*/
/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer
* @{
*/
#define LL_ADC_MULTI_REG_DMA_EACH_ADC (0x00000000UL) /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */
#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B ( ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 12 and 10 bits */
#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B ( ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting for ADC resolution of 8 and 6 bits */
#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 12 and 10 bits */
#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. Setting for ADC resolution of 8 and 6 bits */
/**
* @}
*/
/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
* @{
*/
#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE (0x00000000UL) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */
#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */
#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */
/**
* @}
*/
/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
* @{
*/
#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */
#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */
#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
/**
* @}
*/
#endif /* ADC_MULTIMODE_SUPPORT */
/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
* @note Only ADC peripheral HW delays are defined in ADC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */
/* not timeout values. */
/* Timeout values for ADC operations are dependent to device clock */
/* configuration (system clock versus ADC clock), */
/* and therefore must be defined in user application. */
/* Indications for estimation of ADC timeout delays, for this */
/* STM32 series: */
/* - ADC calibration time: maximum delay is 112/fADC. */
/* (refer to device datasheet, parameter "tCAL") */
/* - ADC enable time: maximum delay is 1 conversion cycle. */
/* (refer to device datasheet, parameter "tSTAB") */
/* - ADC disable time: maximum delay should be a few ADC clock cycles */
/* - ADC stop conversion time: maximum delay should be a few ADC clock */
/* cycles */
/* - ADC conversion time: duration depending on ADC clock and ADC */
/* configuration. */
/* (refer to device reference manual, section "Timing") */
/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tADCVREG_STUP"). */
/* Unit: us */
#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */
/* Delay for internal voltage reference stabilization time. */
/* Delay set to maximum value (refer to device datasheet, */
/* parameter "tstart_vrefint"). */
/* Unit: us */
#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */
/* Delay for temperature sensor stabilization time. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time */
/* Delay required between ADC end of calibration and ADC enable. */
/* Note: On this STM32 series, a minimum number of ADC clock cycles */
/* are required between ADC end of calibration and ADC enable. */
/* Wait time can be computed in user application by waiting for the */
/* equivalent number of CPU cycles, by taking into account */
/* ratio of CPU clock versus ADC clock prescalers. */
/* Unit: ADC clock cycles. */
#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4UL) /*!< Delay required between ADC end of calibration and ADC enable */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
* @{
*/
/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in ADC register
* @param __INSTANCE__ ADC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in ADC register
* @param __INSTANCE__ ADC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
* @{
*/
/**
* @brief Helper macro to get ADC channel number in decimal format
* from literals LL_ADC_CHANNEL_x.
* @note Example:
* __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
* will return decimal number "4".
* @note The input can be a value from functions where a channel
* number is returned, either defined with number
* or with bitfield (only one bit must be set).
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval Value between Min_Data=0 and Max_Data=18
*/
#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \
( \
((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
) \
: \
( \
(uint32_t)POSITION_VAL((__CHANNEL__)) \
) \
)
/**
* @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
* from number in decimal format.
* @note Example:
* __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
* will return a data equivalent to "LL_ADC_CHANNEL_4".
* @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
(((__DECIMAL_NB__) <= 9UL) ? \
( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
) \
: \
( \
((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
(ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__)) | \
(ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
) \
)
/**
* @brief Helper macro to determine whether the selected channel
* corresponds to literal definitions of driver.
* @note The different literal definitions of ADC channels are:
* - ADC internal channel:
* LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
* - ADC external channel (channel connected to a GPIO pin):
* LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
* @note The channel parameter must be a value defined from literal
* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
* LL_ADC_CHANNEL_TEMPSENSOR, ...),
* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
* must not be a value from functions where a channel number is
* returned from ADC registers,
* because internal and external channels share the same channel
* number in ADC registers. The differentiation is made only with
* parameters definitions of driver.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/
#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
(((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
/**
* @brief Helper macro to convert a channel defined from parameter
* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
* LL_ADC_CHANNEL_TEMPSENSOR, ...),
* to its equivalent parameter definition of a ADC external channel
* (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
* @note The channel parameter can be, additionally to a value
* defined from parameter definition of a ADC internal channel
* (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
* a value defined from parameter definition of
* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
* or a value from functions where a channel number is returned
* from ADC registers.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
*/
#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
/**
* @brief Helper macro to determine whether the internal channel
* selected is available on the ADC instance selected.
* @note The channel parameter must be a value defined from parameter
* definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
* LL_ADC_CHANNEL_TEMPSENSOR, ...),
* must not be a value defined from parameter definition of
* ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
* or a value from functions where a channel number is
* returned from ADC registers,
* because internal and external channels share the same channel
* number in ADC registers. The differentiation is made only with
* parameters definitions of driver.
* @param __ADC_INSTANCE__ ADC instance
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
* Value "1" if the internal channel selected is available on the ADC instance selected.
*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC1) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC2) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC3) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC4) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC5) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5) || \
((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
)
#elif defined(STM32G471xx)
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC1) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC2) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC3) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC1) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC2) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
) \
) \
)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
((((__ADC_INSTANCE__) == ADC1) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1) || \
((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC2) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2) \
) \
) \
|| \
(((__ADC_INSTANCE__) == ADC3) \
&&( \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6) || \
((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) \
) \
) \
)
#endif
/**
* @brief Helper macro to define ADC analog watchdog parameter:
* define a single channel to monitor with analog watchdog
* from sequencer channel and groups definition.
* @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
* Example:
* LL_ADC_SetAnalogWDMonitChannels(
* ADC1, LL_ADC_AWD1,
* __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
* @param __GROUP__ This parameter can be one of the following values:
* @arg @ref LL_ADC_GROUP_REGULAR
* @arg @ref LL_ADC_GROUP_INJECTED
* @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
* @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
* @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
* @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
* @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
*
* (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
*/
#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
(((__GROUP__) == LL_ADC_GROUP_REGULAR) \
? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
: \
((__GROUP__) == LL_ADC_GROUP_INJECTED) \
? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL) \
: \
(((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) \
)
/**
* @brief Helper macro to set the value of ADC analog watchdog threshold high
* or low in function of ADC resolution, when ADC resolution is
* different of 12 bits.
* @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
* or @ref LL_ADC_SetAnalogWDThresholds().
* Example, with a ADC resolution of 8 bits, to set the value of
* analog watchdog threshold high (on 8 bits):
* LL_ADC_SetAnalogWDThresholds
* (< ADCx param >,
* __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
* );
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
/**
* @brief Helper macro to get the value of ADC analog watchdog threshold high
* or low in function of ADC resolution, when ADC resolution is
* different of 12 bits.
* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
* Example, with a ADC resolution of 8 bits, to get the value of
* analog watchdog threshold high (on 8 bits):
* < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
* (LL_ADC_RESOLUTION_8B,
* LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
* );
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
/**
* @brief Helper macro to get the ADC analog watchdog threshold high
* or low from raw value containing both thresholds concatenated.
* @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
* Example, to get analog watchdog threshold high from the register raw value:
* __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
* @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
* @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \
(((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) & LL_ADC_AWD_THRESHOLD_LOW)
/**
* @brief Helper macro to set the ADC calibration value with both single ended
* and differential modes calibration factors concatenated.
* @note To be used with function @ref LL_ADC_SetCalibrationFactor().
* Example, to set calibration factors single ended to 0x55
* and differential ended to 0x2A:
* LL_ADC_SetCalibrationFactor(
* ADC1,
* __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
* @param __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
* @param __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__) \
(((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Helper macro to get the ADC multimode conversion data of ADC master
* or ADC slave from raw value with both ADC conversion data concatenated.
* @note This macro is intended to be used when multimode transfer by DMA
* is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
* In this case the transferred data need to processed with this macro
* to separate the conversion data of ADC master and ADC slave.
* @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_MASTER
* @arg @ref LL_ADC_MULTI_SLAVE
* @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
(((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
#endif /* ADC_MULTIMODE_SUPPORT */
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Helper macro to select, from a ADC instance, to which ADC instance
* it has a dependence in multimode (ADC master of the corresponding
* ADC common instance).
* @note In case of device with multimode available and a mix of
* ADC instances compliant and not compliant with multimode feature,
* ADC instances not compliant with multimode feature are
* considered as master instances (do not depend to
* any other ADC instance).
* @param __ADCx__ ADC instance
* @retval __ADCx__ ADC instance master of the corresponding ADC common instance
*/
#if defined(ADC5)
#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
( ( ((__ADCx__) == ADC2) \
)? \
(ADC1) \
: \
( ( ((__ADCx__) == ADC4) \
)? \
(ADC3) \
: \
(__ADCx__) \
) \
)
#else
#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
( ( ((__ADCx__) == ADC2) \
)? \
(ADC1) \
: \
(__ADCx__) \
)
#endif /* ADC5 */
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @brief Helper macro to select the ADC common instance
* to which is belonging the selected ADC instance.
* @note ADC common register instance can be used for:
* - Set parameters common to several ADC instances
* - Multimode (for devices with several ADC instances)
* Refer to functions having argument "ADCxy_COMMON" as parameter.
* @param __ADCx__ ADC instance
* @retval ADC common register instance
*/
#if defined(ADC345_COMMON)
#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
? ( \
(ADC12_COMMON) \
) \
: \
( \
(ADC345_COMMON) \
) \
)
#else
#define __LL_ADC_COMMON_INSTANCE(__ADCx__) (ADC12_COMMON)
#endif /* ADC345_COMMON */
/**
* @brief Helper macro to check if all ADC instances sharing the same
* ADC common instance are disabled.
* @note This check is required by functions with setting conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* Refer to functions having argument "ADCxy_COMMON" as parameter.
* @note On devices with only 1 ADC common instance, parameter of this macro
* is useless and can be ignored (parameter kept for compatibility
* with devices featuring several ADC common instances).
* @param __ADCXY_COMMON__ ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Value "0" if all ADC instances sharing the same ADC common instance
* are disabled.
* Value "1" if at least one ADC instance sharing the same ADC common instance
* is enabled.
*/
#if defined(ADC345_COMMON)
#if defined(ADC4) && defined(ADC5)
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(((__ADCXY_COMMON__) == ADC12_COMMON) \
? ( \
(LL_ADC_IsEnabled(ADC1) | \
LL_ADC_IsEnabled(ADC2) ) \
) \
: \
( \
(LL_ADC_IsEnabled(ADC3) | \
LL_ADC_IsEnabled(ADC4) | \
LL_ADC_IsEnabled(ADC5) ) \
) \
)
#else
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(((__ADCXY_COMMON__) == ADC12_COMMON) \
? ( \
(LL_ADC_IsEnabled(ADC1) | \
LL_ADC_IsEnabled(ADC2) ) \
) \
: \
(LL_ADC_IsEnabled(ADC3)) \
)
#endif /* ADC4 && ADC5 */
#else
#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
(LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
#endif
/**
* @brief Helper macro to define the ADC conversion data full-scale digital
* value corresponding to the selected ADC resolution.
* @note ADC conversion data full-scale corresponds to voltage range
* determined by analog voltage references Vref+ and Vref-
* (refer to reference manual).
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
*/
#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
(0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
/**
* @brief Helper macro to convert the ADC conversion data from
* a resolution to another resolution.
* @param __DATA__ ADC conversion data to be converted
* @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
* This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
* This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval ADC conversion data to the requested resolution
*/
#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__) \
(((__DATA__) \
<< ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))) \
>> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)) \
)
/**
* @brief Helper macro to calculate the voltage (unit: mVolt)
* corresponding to a ADC conversion data (unit: digital value).
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
* (unit: digital value).
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\
__ADC_RESOLUTION__) \
((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
)
/**
* @brief Helper macro to calculate analog reference voltage (Vref+)
* (unit: mVolt) from ADC conversion data of internal voltage
* reference VrefInt.
* @note Computation is using VrefInt calibration value
* stored in system memory for each device during production.
* @note This voltage depends on user board environment: voltage level
* connected to pin Vref+.
* On devices with small package, the pin Vref+ is not present
* and internally bonded to pin Vdda.
* @note On this STM32 series, calibration data of internal voltage reference
* VrefInt corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* internal voltage reference VrefInt.
* Otherwise, this macro performs the processing to scale
* ADC conversion data to 12 bits.
* @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
* of internal voltage reference VrefInt (unit: digital value).
* @param __ADC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval Analog reference voltage (unit: mV)
*/
#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
__ADC_RESOLUTION__) \
(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_12B) \
)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
* from ADC conversion data of internal temperature sensor.
* @note Computation is using temperature sensor calibration values
* stored in system memory for each device during production.
* @note Calculation formula:
* Temperature = ((TS_ADC_DATA - TS_CAL1)
* * (TS_CAL2_TEMP - TS_CAL1_TEMP))
* / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
* with TS_ADC_DATA = temperature sensor raw data measured by ADC
* Avg_Slope = (TS_CAL2 - TS_CAL1)
* / (TS_CAL2_TEMP - TS_CAL1_TEMP)
* TS_CAL1 = equivalent TS_ADC_DATA at temperature
* TEMP_DEGC_CAL1 (calibrated in factory)
* TS_CAL2 = equivalent TS_ADC_DATA at temperature
* TEMP_DEGC_CAL2 (calibrated in factory)
* Caution: Calculation relevancy under reserve that calibration
* parameters are correct (address and data).
* To calculate temperature using temperature sensor
* datasheet typical values (generic values less, therefore
* less accurate than calibrated values),
* use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
* @note As calculation input, the analog reference voltage (Vref+) must be
* defined as it impacts the ADC LSB equivalent voltage.
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @note On this STM32 series, calibration data of temperature sensor
* corresponds to a resolution of 12 bits,
* this is the recommended ADC resolution to convert voltage of
* temperature sensor.
* Otherwise, this macro performs the processing to scale
* ADC conversion data to 12 bits.
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
* temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature
* sensor voltage has been measured.
* This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval Temperature (unit: degree Celsius)
*/
#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \
(((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
(__ADC_RESOLUTION__), \
LL_ADC_RESOLUTION_12B) \
* (__VREFANALOG_VOLTAGE__)) \
/ TEMPSENSOR_CAL_VREFANALOG) \
- (int32_t) *TEMPSENSOR_CAL1_ADDR) \
) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
) + TEMPSENSOR_CAL1_TEMP \
)
/**
* @brief Helper macro to calculate the temperature (unit: degree Celsius)
* from ADC conversion data of internal temperature sensor.
* @note Computation is using temperature sensor typical values
* (refer to device datasheet).
* @note Calculation formula:
* Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
* / Avg_Slope + CALx_TEMP
* with TS_ADC_DATA = temperature sensor raw data measured by ADC
* (unit: digital value)
* Avg_Slope = temperature sensor slope
* (unit: uV/Degree Celsius)
* TS_TYP_CALx_VOLT = temperature sensor digital value at
* temperature CALx_TEMP (unit: mV)
* Caution: Calculation relevancy under reserve the temperature sensor
* of the current device has characteristics in line with
* datasheet typical values.
* If temperature sensor calibration values are available on
* on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
* temperature calculation will be more accurate using
* helper macro @ref __LL_ADC_CALC_TEMPERATURE().
* @note As calculation input, the analog reference voltage (Vref+) must be
* defined as it impacts the ADC LSB equivalent voltage.
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @note ADC measurement data must correspond to a resolution of 12 bits
* (full scale digital value 4095). If not the case, the data must be
* preliminarily rescaled to an equivalent resolution of 12 bits.
* @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
* On STM32G4, refer to device datasheet parameter "Avg_Slope".
* @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
* On STM32G4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).
* @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
* @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
* @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
* @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
* This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval Temperature (unit: degree Celsius)
*/
#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
__TEMPSENSOR_TYP_CALX_V__,\
__TEMPSENSOR_CALX_TEMP__,\
__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \
(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
* 1000UL) \
- \
(int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
* 1000UL) \
) \
) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \
) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \
)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
* @{
*/
/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
* @{
*/
/* Note: LL ADC functions to set DMA transfer are located into sections of */
/* configuration of ADC instance, groups and multimode (if available): */
/* @ref LL_ADC_REG_SetDMATransfer(), ... */
/**
* @brief Function to help to configure DMA transfer from ADC: retrieve the
* ADC register address from ADC instance and a list of ADC registers
* intended to be used (most commonly) with DMA transfer.
* @note These ADC registers are data registers:
* when ADC conversion data is available in ADC data registers,
* ADC generates a DMA transfer request.
* @note This macro is intended to be used with LL DMA driver, refer to
* function "LL_DMA_ConfigAddresses()".
* Example:
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
* (uint32_t)&< array or variable >,
* LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
* @note For devices with several ADC: in multimode, some devices
* use a different data register outside of ADC instance scope
* (common data register). This macro manages this register difference,
* only ADC instance has to be set as parameter.
* @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n
* CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n
* CDR RDATA_SLV LL_ADC_DMA_GetRegAddr
* @param ADCx ADC instance
* @param Register This parameter can be one of the following values:
* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
* @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
*
* (1) Available on devices with several ADC instances.
* @retval ADC register address
*/
#if defined(ADC_MULTIMODE_SUPPORT)
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
uint32_t data_reg_addr;
if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
{
/* Retrieve address of register DR */
data_reg_addr = (uint32_t) &(ADCx->DR);
}
else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
{
/* Retrieve address of register CDR */
data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
}
return data_reg_addr;
}
#else
__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
{
/* Prevent unused argument(s) compilation warning */
(void)(Register);
/* Retrieve address of register DR */
return (uint32_t) &(ADCx->DR);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
* @{
*/
/**
* @brief Set parameter common to several ADC: Clock source and prescaler.
* @note On this STM32 series, if ADC group injected is used, some
* clock ratio constraints between ADC clock and AHB clock
* must be respected.
* Refer to reference manual.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR CKMODE LL_ADC_SetCommonClock\n
* CCR PRESC LL_ADC_SetCommonClock
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param CommonClock This parameter can be one of the following values:
* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
}
/**
* @brief Get parameter common to several ADC: Clock source and prescaler.
* @rmtoll CCR CKMODE LL_ADC_GetCommonClock\n
* CCR PRESC LL_ADC_GetCommonClock
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
* @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
}
/**
* @brief Set parameter common to several ADC: measurement path to
* internal channels (VrefInt, temperature sensor, ...).
* Configure all paths (overwrite current configuration).
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
* The values not selected are removed from configuration.
* @note Stabilization time of measurement path to internal channel:
* After enabling internal paths, before starting ADC conversion,
* a delay is required for internal voltage reference and
* temperature sensor stabilization time.
* Refer to device datasheet.
* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
* @note ADC internal channel sampling time constraint:
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n
* CCR VSENSESEL LL_ADC_SetCommonPathInternalCh\n
* CCR VBATSEL LL_ADC_SetCommonPathInternalCh
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param PathInternal This parameter can be a combination of the following values:
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
}
/**
* @brief Set parameter common to several ADC: measurement path to
* internal channels (VrefInt, temperature sensor, ...).
* Add paths to the current configuration.
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
* @note Stabilization time of measurement path to internal channel:
* After enabling internal paths, before starting ADC conversion,
* a delay is required for internal voltage reference and
* temperature sensor stabilization time.
* Refer to device datasheet.
* Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
* Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
* @note ADC internal channel sampling time constraint:
* For ADC conversion of internal channels,
* a sampling time minimum value is required.
* Refer to device datasheet.
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n
* CCR VSENSESEL LL_ADC_SetCommonPathInternalChAdd\n
* CCR VBATSEL LL_ADC_SetCommonPathInternalChAdd
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param PathInternal This parameter can be a combination of the following values:
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
SET_BIT(ADCxy_COMMON->CCR, PathInternal);
}
/**
* @brief Set parameter common to several ADC: measurement path to
* internal channels (VrefInt, temperature sensor, ...).
* Remove paths to the current configuration.
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
* @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n
* CCR VSENSESEL LL_ADC_SetCommonPathInternalChRem\n
* CCR VBATSEL LL_ADC_SetCommonPathInternalChRem
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param PathInternal This parameter can be a combination of the following values:
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
}
/**
* @brief Get parameter common to several ADC: measurement path to internal
* channels (VrefInt, temperature sensor, ...).
* @note One or several values can be selected.
* Example: (LL_ADC_PATH_INTERNAL_VREFINT |
* LL_ADC_PATH_INTERNAL_TEMPSENSOR)
* @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n
* CCR VSENSESEL LL_ADC_GetCommonPathInternalCh\n
* CCR VBATSEL LL_ADC_GetCommonPathInternalCh
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be a combination of the following values:
* @arg @ref LL_ADC_PATH_INTERNAL_NONE
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
* @{
*/
/**
* @brief Set ADC calibration factor in the mode single-ended
* or differential (for devices with differential mode available).
* @note This function is intended to set calibration parameters
* without having to perform a new calibration using
* @ref LL_ADC_StartCalibration().
* @note For devices with differential mode available:
* Calibration of offset is specific to each of
* single-ended and differential modes
* (calibration factor must be specified for each of these
* differential modes, if used afterwards and if the application
* requires their calibration).
* @note In case of setting calibration factors of both modes single ended
* and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
* both calibration factors must be concatenated.
* To perform this processing, use helper macro
* @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled, without calibration on going, without conversion
* on going on group regular.
* @rmtoll CALFACT CALFACT_S LL_ADC_SetCalibrationFactor\n
* CALFACT CALFACT_D LL_ADC_SetCalibrationFactor
* @param ADCx ADC instance
* @param SingleDiff This parameter can be one of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
* @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
{
MODIFY_REG(ADCx->CALFACT,
SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
}
/**
* @brief Get ADC calibration factor in the mode single-ended
* or differential (for devices with differential mode available).
* @note Calibration factors are set by hardware after performing
* a calibration run using function @ref LL_ADC_StartCalibration().
* @note For devices with differential mode available:
* Calibration of offset is specific to each of
* single-ended and differential modes
* @rmtoll CALFACT CALFACT_S LL_ADC_GetCalibrationFactor\n
* CALFACT CALFACT_D LL_ADC_GetCalibrationFactor
* @param ADCx ADC instance
* @param SingleDiff This parameter can be one of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval Value between Min_Data=0x00 and Max_Data=0x7F
*/
__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)
{
/* Retrieve bits with position in register depending on parameter */
/* "SingleDiff". */
/* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because */
/* containing other bits reserved for other purpose. */
return (uint32_t)(READ_BIT(ADCx->CALFACT,
(SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
}
/**
* @brief Set ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR RES LL_ADC_SetResolution
* @param ADCx ADC instance
* @param Resolution This parameter can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
}
/**
* @brief Get ADC resolution.
* Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
* @rmtoll CFGR RES LL_ADC_GetResolution
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_RESOLUTION_12B
* @arg @ref LL_ADC_RESOLUTION_10B
* @arg @ref LL_ADC_RESOLUTION_8B
* @arg @ref LL_ADC_RESOLUTION_6B
*/
__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
}
/**
* @brief Set ADC conversion data alignment.
* @note Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR ALIGN LL_ADC_SetDataAlignment
* @param ADCx ADC instance
* @param DataAlignment This parameter can be one of the following values:
* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
* @arg @ref LL_ADC_DATA_ALIGN_LEFT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
}
/**
* @brief Get ADC conversion data alignment.
* @note Refer to reference manual for alignments formats
* dependencies to ADC resolutions.
* @rmtoll CFGR ALIGN LL_ADC_GetDataAlignment
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_DATA_ALIGN_RIGHT
* @arg @ref LL_ADC_DATA_ALIGN_LEFT
*/
__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
}
/**
* @brief Set ADC low power mode.
* @note Description of ADC low power modes:
* - ADC low power mode "auto wait": Dynamic low power mode,
* ADC conversions occurrences are limited to the minimum necessary
* in order to reduce power consumption.
* New ADC conversion starts only when the previous
* unitary conversion data (for ADC group regular)
* or previous sequence conversions data (for ADC group injected)
* has been retrieved by user software.
* In the meantime, ADC remains idle: does not performs any
* other conversion.
* This mode allows to automatically adapt the ADC conversions
* triggers to the speed of the software that reads the data.
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
* - It is not recommended to use with interruption or DMA
* since these modes have to clear immediately the EOC flag
* (by CPU to free the IRQ pending event or by DMA).
* Auto wait will work but fort a very short time, discarding
* its intended benefit (except specific case of high load of CPU
* or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
* retrieve ADC conversion data. This will trig another
* ADC conversion start.
* - ADC low power mode "auto power-off" (feature available on
* this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
* the ADC automatically powers-off after a conversion and
* automatically wakes up when a new conversion is triggered
* (with startup time between trigger and start of sampling).
* This feature can be combined with low power mode "auto wait".
* @note With ADC low power mode "auto wait", the ADC conversion data read
* is corresponding to previous ADC conversion start, independently
* of delay during which ADC was idle.
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR AUTDLY LL_ADC_SetLowPowerMode
* @param ADCx ADC instance
* @param LowPowerMode This parameter can be one of the following values:
* @arg @ref LL_ADC_LP_MODE_NONE
* @arg @ref LL_ADC_LP_AUTOWAIT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
}
/**
* @brief Get ADC low power mode:
* @note Description of ADC low power modes:
* - ADC low power mode "auto wait": Dynamic low power mode,
* ADC conversions occurrences are limited to the minimum necessary
* in order to reduce power consumption.
* New ADC conversion starts only when the previous
* unitary conversion data (for ADC group regular)
* or previous sequence conversions data (for ADC group injected)
* has been retrieved by user software.
* In the meantime, ADC remains idle: does not performs any
* other conversion.
* This mode allows to automatically adapt the ADC conversions
* triggers to the speed of the software that reads the data.
* Moreover, this avoids risk of overrun for low frequency
* applications.
* How to use this low power mode:
* - It is not recommended to use with interruption or DMA
* since these modes have to clear immediately the EOC flag
* (by CPU to free the IRQ pending event or by DMA).
* Auto wait will work but fort a very short time, discarding
* its intended benefit (except specific case of high load of CPU
* or DMA transfers which can justify usage of auto wait).
* - Do use with polling: 1. Start conversion,
* 2. Later on, when conversion data is needed: poll for end of
* conversion to ensure that conversion is completed and
* retrieve ADC conversion data. This will trig another
* ADC conversion start.
* - ADC low power mode "auto power-off" (feature available on
* this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
* the ADC automatically powers-off after a conversion and
* automatically wakes up when a new conversion is triggered
* (with startup time between trigger and start of sampling).
* This feature can be combined with low power mode "auto wait".
* @note With ADC low power mode "auto wait", the ADC conversion data read
* is corresponding to previous ADC conversion start, independently
* of delay during which ADC was idle.
* Therefore, the ADC conversion data may be outdated: does not
* correspond to the current voltage level on the selected
* ADC channel.
* @rmtoll CFGR AUTDLY LL_ADC_GetLowPowerMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_LP_MODE_NONE
* @arg @ref LL_ADC_LP_AUTOWAIT
*/
__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
}
/**
* @brief Set ADC selected offset number 1, 2, 3 or 4.
* @note This function set the 2 items of offset configuration:
* - ADC channel to which the offset programmed will be applied
* (independently of channel mapped on ADC group regular
* or group injected)
* - Offset level (offset to be subtracted from the raw
* converted data).
* @note Caution: Offset format is dependent to ADC resolution:
* offset has to be left-aligned on bit 11, the LSB (right bits)
* are set to 0.
* @note This function enables the offset, by default. It can be forced
* to disable state using function LL_ADC_SetOffsetState().
* @note If a channel is mapped on several offsets numbers, only the offset
* with the lowest value is considered for the subtraction.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @note On STM32G4, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN1..5).
* @rmtoll OFR1 OFFSET1_CH LL_ADC_SetOffset\n
* OFR1 OFFSET1 LL_ADC_SetOffset\n
* OFR1 OFFSET1_EN LL_ADC_SetOffset\n
* OFR2 OFFSET2_CH LL_ADC_SetOffset\n
* OFR2 OFFSET2 LL_ADC_SetOffset\n
* OFR2 OFFSET2_EN LL_ADC_SetOffset\n
* OFR3 OFFSET3_CH LL_ADC_SetOffset\n
* OFR3 OFFSET3 LL_ADC_SetOffset\n
* OFR3 OFFSET3_EN LL_ADC_SetOffset\n
* OFR4 OFFSET4_CH LL_ADC_SetOffset\n
* OFR4 OFFSET4 LL_ADC_SetOffset\n
* OFR4 OFFSET4_EN LL_ADC_SetOffset
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
}
/**
* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
* Channel to which the offset programmed will be applied
* (independently of channel mapped on ADC group regular
* or group injected)
* @note Usage of the returned channel number:
* - To reinject this channel into another function LL_ADC_xxx:
* the returned channel number is only partly formatted on definition
* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
* with parts of literals LL_ADC_CHANNEL_x or using
* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Then the selected literal LL_ADC_CHANNEL_x can be used
* as parameter for another function.
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* @note On STM32G4, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN1..5).
* @rmtoll OFR1 OFFSET1_CH LL_ADC_GetOffsetChannel\n
* OFR2 OFFSET2_CH LL_ADC_GetOffsetChannel\n
* OFR3 OFFSET3_CH LL_ADC_GetOffsetChannel\n
* OFR4 OFFSET4_CH LL_ADC_GetOffsetChannel
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
}
/**
* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
* Offset level (offset to be subtracted from the raw
* converted data).
* @note Caution: Offset format is dependent to ADC resolution:
* offset has to be left-aligned on bit 11, the LSB (right bits)
* are set to 0.
* @rmtoll OFR1 OFFSET1 LL_ADC_GetOffsetLevel\n
* OFR2 OFFSET2 LL_ADC_GetOffsetLevel\n
* OFR3 OFFSET3 LL_ADC_GetOffsetLevel\n
* OFR4 OFFSET4 LL_ADC_GetOffsetLevel
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
}
/**
* @brief Set for the ADC selected offset number 1, 2, 3 or 4:
* force offset state disable or enable
* without modifying offset channel or offset value.
* @note This function should be needed only in case of offset to be
* enabled-disabled dynamically, and should not be needed in other cases:
* function LL_ADC_SetOffset() automatically enables the offset.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll OFR1 OFFSET1_EN LL_ADC_SetOffsetState\n
* OFR2 OFFSET2_EN LL_ADC_SetOffsetState\n
* OFR3 OFFSET3_EN LL_ADC_SetOffsetState\n
* OFR4 OFFSET4_EN LL_ADC_SetOffsetState
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @param OffsetState This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_OFFSET1_EN,
OffsetState);
}
/**
* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
* offset state disabled or enabled.
* @rmtoll OFR1 OFFSET1_EN LL_ADC_GetOffsetState\n
* OFR2 OFFSET2_EN LL_ADC_GetOffsetState\n
* OFR3 OFFSET3_EN LL_ADC_GetOffsetState\n
* OFR4 OFFSET4_EN LL_ADC_GetOffsetState
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
}
/**
* @brief Set for the ADC selected offset number 1, 2, 3 or 4:
* choose offset sign.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll OFR1 OFFSETPOS LL_ADC_SetOffsetSign\n
* OFR2 OFFSETPOS LL_ADC_SetOffsetSign\n
* OFR3 OFFSETPOS LL_ADC_SetOffsetSign\n
* OFR4 OFFSETPOS LL_ADC_SetOffsetSign
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @param OffsetSign This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_OFFSETPOS,
OffsetSign);
}
/**
* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
* offset sign if positive or negative.
* @rmtoll OFR1 OFFSETPOS LL_ADC_GetOffsetSign\n
* OFR2 OFFSETPOS LL_ADC_GetOffsetSign\n
* OFR3 OFFSETPOS LL_ADC_GetOffsetSign\n
* OFR4 OFFSETPOS LL_ADC_GetOffsetSign
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
}
/**
* @brief Set for the ADC selected offset number 1, 2, 3 or 4:
* choose offset saturation mode.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll OFR1 SATEN LL_ADC_SetOffsetSaturation\n
* OFR2 SATEN LL_ADC_SetOffsetSaturation\n
* OFR3 SATEN LL_ADC_SetOffsetSaturation\n
* OFR4 SATEN LL_ADC_SetOffsetSaturation
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @param OffsetSaturation This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
{
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
MODIFY_REG(*preg,
ADC_OFR1_SATEN,
OffsetSaturation);
}
/**
* @brief Get for the ADC selected offset number 1, 2, 3 or 4:
* offset saturation if enabled or disabled.
* @rmtoll OFR1 SATEN LL_ADC_GetOffsetSaturation\n
* OFR2 SATEN LL_ADC_GetOffsetSaturation\n
* OFR3 SATEN LL_ADC_GetOffsetSaturation\n
* OFR4 SATEN LL_ADC_GetOffsetSaturation
* @param ADCx ADC instance
* @param Offsety This parameter can be one of the following values:
* @arg @ref LL_ADC_OFFSET_1
* @arg @ref LL_ADC_OFFSET_2
* @arg @ref LL_ADC_OFFSET_3
* @arg @ref LL_ADC_OFFSET_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
}
/**
* @brief Set ADC gain compensation.
* @note This function set the gain compensation coefficient
* that is applied to raw converted data using the formula:
* DATA = DATA(raw) * (gain compensation coef) / 4096
* @note This function enables the gain compensation if given
* coefficient is above 0, otherwise it disables it.
* @note Gain compensation when enabled is applied to all channels.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll GCOMP GCOMPCOEFF LL_ADC_SetGainCompensation\n
* CFGR2 GCOMP LL_ADC_SetGainCompensation
* @param ADCx ADC instance
* @param GainCompensation This parameter can be:
* 0 Gain compensation will be disabled and value set to 0
* 1 -> 16393 Gain compensation will be enabled with specified value
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
{
MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
}
/**
* @brief Get the ADC gain compensation value
* @rmtoll GCOMP GCOMPCOEFF LL_ADC_GetGainCompensation\n
* CFGR2 GCOMP LL_ADC_GetGainCompensation
* @param ADCx ADC instance
* @retval Returned value can be:
* 0 Gain compensation is disabled
* 1 -> 16393 Gain compensation is enabled with returned value
*/
__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ? READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
}
#if defined(ADC_SMPR1_SMPPLUS)
/**
* @brief Set ADC sampling time common configuration impacting
* settings of sampling time channel wise.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll SMPR1 SMPPLUS LL_ADC_SetSamplingTimeCommonConfig
* @param ADCx ADC instance
* @param SamplingTimeCommonConfig This parameter can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
{
MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
}
/**
* @brief Get ADC sampling time common configuration impacting
* settings of sampling time channel wise.
* @rmtoll SMPR1 SMPPLUS LL_ADC_GetSamplingTimeCommonConfig
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
*/
__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
}
#endif /* ADC_SMPR1_SMPPLUS */
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
* @{
*/
/**
* @brief Set ADC group regular conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
* In case of need to modify trigger edge, use
* function @ref LL_ADC_REG_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR EXTSEL LL_ADC_REG_SetTriggerSource\n
* CFGR EXTEN LL_ADC_REG_SetTriggerSource
* @param ADCx ADC instance
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
*
* (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
* (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
}
/**
* @brief Get ADC group regular conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note To determine whether group regular trigger source is
* internal (SW start) or external, without detail
* of which peripheral is selected as external trigger,
* (equivalent to
* "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
* use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CFGR EXTSEL LL_ADC_REG_GetTriggerSource\n
* CFGR EXTEN LL_ADC_REG_GetTriggerSource
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_SOFTWARE
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
* @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (1)
* @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2 (2)
* @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
*
* (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
* (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
{
__IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}. */
uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL */
/* to match with triggers literals definition. */
return ((TriggerSource
& (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)
| ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)
);
}
/**
* @brief Get ADC group regular conversion trigger source internal (SW start)
* or external.
* @note In case of group regular trigger source set to external trigger,
* to determine which peripheral is selected as external trigger,
* use function @ref LL_ADC_REG_GetTriggerSource().
* @rmtoll CFGR EXTEN LL_ADC_REG_IsTriggerSourceSWStart
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
}
/**
* @brief Set ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR EXTEN LL_ADC_REG_SetTriggerEdge
* @param ADCx ADC instance
* @param ExternalTriggerEdge This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
}
/**
* @brief Get ADC group regular conversion trigger polarity.
* @note Applicable only for trigger source set to external trigger.
* @rmtoll CFGR EXTEN LL_ADC_REG_GetTriggerEdge
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_TRIG_EXT_RISING
* @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
* @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
}
/**
* @brief Set ADC sampling mode.
* @note This function set the ADC conversion sampling mode
* @note This mode applies to regular group only.
* @note Set sampling mode is applied to all conversion of regular group.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR2 BULB LL_ADC_REG_SetSamplingMode\n
* CFGR2 SMPTRIG LL_ADC_REG_SetSamplingMode
* @param ADCx ADC instance
* @param SamplingMode This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
* @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
* @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
{
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
}
/**
* @brief Get the ADC sampling mode
* @rmtoll CFGR2 BULB LL_ADC_REG_GetSamplingMode\n
* CFGR2 SMPTRIG LL_ADC_REG_GetSamplingMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
* @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
* @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
}
/**
* @brief Set ADC group regular sequencer length and scan direction.
* @note Description of ADC group regular sequencer features:
* - For devices with sequencer fully configurable
* (function "LL_ADC_REG_SetSequencerRanks()" available):
* sequencer length and each rank affectation to a channel
* are configurable.
* This function performs configuration of:
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerRanks()".
* - For devices with sequencer not fully configurable
* (function "LL_ADC_REG_SetSequencerChannels()" available):
* sequencer length and each rank affectation to a channel
* are defined by channel number.
* This function performs configuration of:
* - Sequence length: Number of ranks in the scan sequence is
* defined by number of channels set in the sequence,
* rank of each channel is fixed by channel HW number.
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from lowest channel number to
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
* @param ADCx ADC instance
* @param SequencerNbRanks This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
}
/**
* @brief Get ADC group regular sequencer length and scan direction.
* @note Description of ADC group regular sequencer features:
* - For devices with sequencer fully configurable
* (function "LL_ADC_REG_SetSequencerRanks()" available):
* sequencer length and each rank affectation to a channel
* are configurable.
* This function retrieves:
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerRanks()".
* - For devices with sequencer not fully configurable
* (function "LL_ADC_REG_SetSequencerChannels()" available):
* sequencer length and each rank affectation to a channel
* are defined by channel number.
* This function retrieves:
* - Sequence length: Number of ranks in the scan sequence is
* defined by number of channels set in the sequence,
* rank of each channel is fixed by channel HW number.
* (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from lowest channel number to
* highest channel number).
* Sequencer ranks are selected using
* function "LL_ADC_REG_SetSequencerChannels()".
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @rmtoll SQR1 L LL_ADC_REG_GetSequencerLength
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
* @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
}
/**
* @brief Set ADC group regular sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
* number of ranks.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
* @note It is not possible to enable both ADC auto-injected mode
* and ADC group regular sequencer discontinuous mode.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR DISCEN LL_ADC_REG_SetSequencerDiscont\n
* CFGR DISCNUM LL_ADC_REG_SetSequencerDiscont
* @param ADCx ADC instance
* @param SeqDiscont This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
}
/**
* @brief Get ADC group regular sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
* number of ranks.
* @rmtoll CFGR DISCEN LL_ADC_REG_GetSequencerDiscont\n
* CFGR DISCNUM LL_ADC_REG_GetSequencerDiscont
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
* @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
* @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
}
/**
* @brief Set ADC group regular sequence: channel on the selected
* scan sequence rank.
* @note This function performs configuration of:
* - Channels ordering into each rank of scan sequence:
* whatever channel can be placed into whatever rank.
* @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll SQR1 SQ1 LL_ADC_REG_SetSequencerRanks\n
* SQR1 SQ2 LL_ADC_REG_SetSequencerRanks\n
* SQR1 SQ3 LL_ADC_REG_SetSequencerRanks\n
* SQR1 SQ4 LL_ADC_REG_SetSequencerRanks\n
* SQR2 SQ5 LL_ADC_REG_SetSequencerRanks\n
* SQR2 SQ6 LL_ADC_REG_SetSequencerRanks\n
* SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
* SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
* SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
* SQR3 SQ10 LL_ADC_REG_SetSequencerRanks\n
* SQR3 SQ11 LL_ADC_REG_SetSequencerRanks\n
* SQR3 SQ12 LL_ADC_REG_SetSequencerRanks\n
* SQR3 SQ13 LL_ADC_REG_SetSequencerRanks\n
* SQR3 SQ14 LL_ADC_REG_SetSequencerRanks\n
* SQR4 SQ15 LL_ADC_REG_SetSequencerRanks\n
* SQR4 SQ16 LL_ADC_REG_SetSequencerRanks
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_RANK_1
* @arg @ref LL_ADC_REG_RANK_2
* @arg @ref LL_ADC_REG_RANK_3
* @arg @ref LL_ADC_REG_RANK_4
* @arg @ref LL_ADC_REG_RANK_5
* @arg @ref LL_ADC_REG_RANK_6
* @arg @ref LL_ADC_REG_RANK_7
* @arg @ref LL_ADC_REG_RANK_8
* @arg @ref LL_ADC_REG_RANK_9
* @arg @ref LL_ADC_REG_RANK_10
* @arg @ref LL_ADC_REG_RANK_11
* @arg @ref LL_ADC_REG_RANK_12
* @arg @ref LL_ADC_REG_RANK_13
* @arg @ref LL_ADC_REG_RANK_14
* @arg @ref LL_ADC_REG_RANK_15
* @arg @ref LL_ADC_REG_RANK_16
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
/**
* @brief Get ADC group regular sequence: channel on the selected
* scan sequence rank.
* @note On this STM32 series, ADC group regular sequencer is
* fully configurable: sequencer length and each rank
* affectation to a channel are configurable.
* Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note Usage of the returned channel number:
* - To reinject this channel into another function LL_ADC_xxx:
* the returned channel number is only partly formatted on definition
* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
* with parts of literals LL_ADC_CHANNEL_x or using
* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Then the selected literal LL_ADC_CHANNEL_x can be used
* as parameter for another function.
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* @rmtoll SQR1 SQ1 LL_ADC_REG_GetSequencerRanks\n
* SQR1 SQ2 LL_ADC_REG_GetSequencerRanks\n
* SQR1 SQ3 LL_ADC_REG_GetSequencerRanks\n
* SQR1 SQ4 LL_ADC_REG_GetSequencerRanks\n
* SQR2 SQ5 LL_ADC_REG_GetSequencerRanks\n
* SQR2 SQ6 LL_ADC_REG_GetSequencerRanks\n
* SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
* SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
* SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
* SQR3 SQ10 LL_ADC_REG_GetSequencerRanks\n
* SQR3 SQ11 LL_ADC_REG_GetSequencerRanks\n
* SQR3 SQ12 LL_ADC_REG_GetSequencerRanks\n
* SQR3 SQ13 LL_ADC_REG_GetSequencerRanks\n
* SQR3 SQ14 LL_ADC_REG_GetSequencerRanks\n
* SQR4 SQ15 LL_ADC_REG_GetSequencerRanks\n
* SQR4 SQ16 LL_ADC_REG_GetSequencerRanks
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_RANK_1
* @arg @ref LL_ADC_REG_RANK_2
* @arg @ref LL_ADC_REG_RANK_3
* @arg @ref LL_ADC_REG_RANK_4
* @arg @ref LL_ADC_REG_RANK_5
* @arg @ref LL_ADC_REG_RANK_6
* @arg @ref LL_ADC_REG_RANK_7
* @arg @ref LL_ADC_REG_RANK_8
* @arg @ref LL_ADC_REG_RANK_9
* @arg @ref LL_ADC_REG_RANK_10
* @arg @ref LL_ADC_REG_RANK_11
* @arg @ref LL_ADC_REG_RANK_12
* @arg @ref LL_ADC_REG_RANK_13
* @arg @ref LL_ADC_REG_RANK_14
* @arg @ref LL_ADC_REG_RANK_15
* @arg @ref LL_ADC_REG_RANK_16
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
return (uint32_t)((READ_BIT(*preg,
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
);
}
/**
* @brief Set ADC continuous conversion mode on ADC group regular.
* @note Description of ADC continuous conversion mode:
* - single mode: one conversion per trigger
* - continuous mode: after the first trigger, following
* conversions launched successively automatically.
* @note It is not possible to enable both ADC group regular
* continuous mode and sequencer discontinuous mode.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR CONT LL_ADC_REG_SetContinuousMode
* @param ADCx ADC instance
* @param Continuous This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_CONV_SINGLE
* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
}
/**
* @brief Get ADC continuous conversion mode on ADC group regular.
* @note Description of ADC continuous conversion mode:
* - single mode: one conversion per trigger
* - continuous mode: after the first trigger, following
* conversions launched successively automatically.
* @rmtoll CFGR CONT LL_ADC_REG_GetContinuousMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_CONV_SINGLE
* @arg @ref LL_ADC_REG_CONV_CONTINUOUS
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
}
/**
* @brief Set ADC group regular conversion data transfer: no transfer or
* transfer by DMA, and DMA requests mode.
* @note If transfer by DMA selected, specifies the DMA requests
* mode:
* - Limited mode (One shot mode): DMA transfer requests are stopped
* when number of DMA data transfers (number of
* ADC conversions) is reached.
* This ADC mode is intended to be used with DMA mode non-circular.
* - Unlimited mode: DMA transfer requests are unlimited,
* whatever number of DMA data transfers (number of
* ADC conversions).
* This ADC mode is intended to be used with DMA mode circular.
* @note If ADC DMA requests mode is set to unlimited and DMA is set to
* mode non-circular:
* when DMA transfers size will be reached, DMA will stop transfers of
* ADC conversions data ADC will raise an overrun error
* (overrun flag and interruption if enabled).
* @note For devices with several ADC instances: ADC multimode DMA
* settings are available using function @ref LL_ADC_SetMultiDMATransfer().
* @note To configure DMA source address (peripheral address),
* use function @ref LL_ADC_DMA_GetRegAddr().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR DMAEN LL_ADC_REG_SetDMATransfer\n
* CFGR DMACFG LL_ADC_REG_SetDMATransfer
* @param ADCx ADC instance
* @param DMATransfer This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
}
/**
* @brief Get ADC group regular conversion data transfer: no transfer or
* transfer by DMA, and DMA requests mode.
* @note If transfer by DMA selected, specifies the DMA requests
* mode:
* - Limited mode (One shot mode): DMA transfer requests are stopped
* when number of DMA data transfers (number of
* ADC conversions) is reached.
* This ADC mode is intended to be used with DMA mode non-circular.
* - Unlimited mode: DMA transfer requests are unlimited,
* whatever number of DMA data transfers (number of
* ADC conversions).
* This ADC mode is intended to be used with DMA mode circular.
* @note If ADC DMA requests mode is set to unlimited and DMA is set to
* mode non-circular:
* when DMA transfers size will be reached, DMA will stop transfers of
* ADC conversions data ADC will raise an overrun error
* (overrun flag and interruption if enabled).
* @note For devices with several ADC instances: ADC multimode DMA
* settings are available using function @ref LL_ADC_GetMultiDMATransfer().
* @note To configure DMA source address (peripheral address),
* use function @ref LL_ADC_DMA_GetRegAddr().
* @rmtoll CFGR DMAEN LL_ADC_REG_GetDMATransfer\n
* CFGR DMACFG LL_ADC_REG_GetDMATransfer
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
* @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
* @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
}
/**
* @brief Set ADC group regular behavior in case of overrun:
* data preserved or overwritten.
* @note Compatibility with devices without feature overrun:
* other devices without this feature have a behavior
* equivalent to data overwritten.
* The default setting of overrun is data preserved.
* Therefore, for compatibility with all devices, parameter
* overrun should be set to data overwritten.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @rmtoll CFGR OVRMOD LL_ADC_REG_SetOverrun
* @param ADCx ADC instance
* @param Overrun This parameter can be one of the following values:
* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
}
/**
* @brief Get ADC group regular behavior in case of overrun:
* data preserved or overwritten.
* @rmtoll CFGR OVRMOD LL_ADC_REG_GetOverrun
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
* @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
*/
__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
* @{
*/
/**
* @brief Set ADC group injected conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note On this STM32 series, setting trigger source to external trigger
* also set trigger polarity to rising edge
* (default setting for compatibility with some ADC on other
* STM32 families having this setting set by HW default value).
* In case of need to modify trigger edge, use
* function @ref LL_ADC_INJ_SetTriggerEdge().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JEXTSEL LL_ADC_INJ_SetTriggerSource\n
* JSQR JEXTEN LL_ADC_INJ_SetTriggerSource
* @param ADCx ADC instance
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
*
* (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
* (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
{
MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
}
/**
* @brief Get ADC group injected conversion trigger source:
* internal (SW start) or from external peripheral (timer event,
* external interrupt line).
* @note To determine whether group injected trigger source is
* internal (SW start) or external, without detail
* of which peripheral is selected as external trigger,
* (equivalent to
* "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
* use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll JSQR JEXTSEL LL_ADC_INJ_GetTriggerSource\n
* JSQR JEXTEN LL_ADC_INJ_GetTriggerSource
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
*
* (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
* (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
{
__IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
/* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
/* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}. */
uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
/* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL */
/* to match with triggers literals definition. */
return ((TriggerSource
& (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)
| ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)
);
}
/**
* @brief Get ADC group injected conversion trigger source internal (SW start)
or external
* @note In case of group injected trigger source set to external trigger,
* to determine which peripheral is selected as external trigger,
* use function @ref LL_ADC_INJ_GetTriggerSource.
* @rmtoll JSQR JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
}
/**
* @brief Set ADC group injected conversion trigger polarity.
* Applicable only for trigger source set to external trigger.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JEXTEN LL_ADC_INJ_SetTriggerEdge
* @param ADCx ADC instance
* @param ExternalTriggerEdge This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
{
MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
}
/**
* @brief Get ADC group injected conversion trigger polarity.
* Applicable only for trigger source set to external trigger.
* @rmtoll JSQR JEXTEN LL_ADC_INJ_GetTriggerEdge
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
}
/**
* @brief Set ADC group injected sequencer length and scan direction.
* @note This function performs configuration of:
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
* @param ADCx ADC instance
* @param SequencerNbRanks This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
{
MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
}
/**
* @brief Get ADC group injected sequencer length and scan direction.
* @note This function retrieves:
* - Sequence length: Number of ranks in the scan sequence.
* - Sequence direction: Unless specified in parameters, sequencer
* scan direction is forward (from rank 1 to rank n).
* @note Sequencer disabled is equivalent to sequencer of 1 rank:
* ADC conversion on only 1 channel.
* @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
}
/**
* @brief Set ADC group injected sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
* number of ranks.
* @note It is not possible to enable both ADC group injected
* auto-injected mode and sequencer discontinuous mode.
* @rmtoll CFGR JDISCEN LL_ADC_INJ_SetSequencerDiscont
* @param ADCx ADC instance
* @param SeqDiscont This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
}
/**
* @brief Get ADC group injected sequencer discontinuous mode:
* sequence subdivided and scan conversions interrupted every selected
* number of ranks.
* @rmtoll CFGR JDISCEN LL_ADC_INJ_GetSequencerDiscont
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
}
/**
* @brief Set ADC group injected sequence: channel on the selected
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32G4, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN1..5).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
* JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
* JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
* JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
/* Set bits with content of parameter "Channel" with bits position */
/* in register depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
MODIFY_REG(ADCx->JSQR,
(ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
}
/**
* @brief Get ADC group injected sequence: channel on the selected
* sequence rank.
* @note Depending on devices and packages, some channels may not be available.
* Refer to device datasheet for channels availability.
* @note Usage of the returned channel number:
* - To reinject this channel into another function LL_ADC_xxx:
* the returned channel number is only partly formatted on definition
* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
* with parts of literals LL_ADC_CHANNEL_x or using
* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Then the selected literal LL_ADC_CHANNEL_x can be used
* as parameter for another function.
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* @rmtoll JSQR JSQ1 LL_ADC_INJ_GetSequencerRanks\n
* JSQR JSQ2 LL_ADC_INJ_GetSequencerRanks\n
* JSQR JSQ3 LL_ADC_INJ_GetSequencerRanks\n
* JSQR JSQ4 LL_ADC_INJ_GetSequencerRanks
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
return (uint32_t)((READ_BIT(ADCx->JSQR,
(ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
>> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
);
}
/**
* @brief Set ADC group injected conversion trigger:
* independent or from ADC group regular.
* @note This mode can be used to extend number of data registers
* updated after one ADC conversion trigger and with data
* permanently kept (not erased by successive conversions of scan of
* ADC sequencer ranks), up to 5 data registers:
* 1 data register on ADC group regular, 4 data registers
* on ADC group injected.
* @note If ADC group injected injected trigger source is set to an
* external trigger, this feature must be must be set to
* independent trigger.
* ADC group injected automatic trigger is compliant only with
* group injected trigger source set to SW start, without any
* further action on ADC group injected conversion start or stop:
* in this case, ADC group injected is controlled only
* from ADC group regular.
* @note It is not possible to enable both ADC group injected
* auto-injected mode and sequencer discontinuous mode.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR JAUTO LL_ADC_INJ_SetTrigAuto
* @param ADCx ADC instance
* @param TrigAuto This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
}
/**
* @brief Get ADC group injected conversion trigger:
* independent or from ADC group regular.
* @rmtoll CFGR JAUTO LL_ADC_INJ_GetTrigAuto
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
* @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
}
/**
* @brief Set ADC group injected contexts queue mode.
* @note A context is a setting of group injected sequencer:
* - group injected trigger
* - sequencer length
* - sequencer ranks
* If contexts queue is disabled:
* - only 1 sequence can be configured
* and is active perpetually.
* If contexts queue is enabled:
* - up to 2 contexts can be queued
* and are checked in and out as a FIFO stack (first-in, first-out).
* - If a new context is set when queues is full, error is triggered
* by interruption "Injected Queue Overflow".
* - Two behaviors are possible when all contexts have been processed:
* the contexts queue can maintain the last context active perpetually
* or can be empty and injected group triggers are disabled.
* - Triggers can be only external (not internal SW start)
* - Caution: The sequence must be fully configured in one time
* (one write of register JSQR makes a check-in of a new context
* into the queue).
* Therefore functions to set separately injected trigger and
* sequencer channels cannot be used, register JSQR must be set
* using function @ref LL_ADC_INJ_ConfigQueueContext().
* @note This parameter can be modified only when no conversion is on going
* on either groups regular or injected.
* @note A modification of the context mode (bit JQDIS) causes the contexts
* queue to be flushed and the register JSQR is cleared.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR JQM LL_ADC_INJ_SetQueueMode\n
* CFGR JQDIS LL_ADC_INJ_SetQueueMode
* @param ADCx ADC instance
* @param QueueMode This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_QUEUE_DISABLE
* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
{
MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
}
/**
* @brief Get ADC group injected context queue mode.
* @rmtoll CFGR JQM LL_ADC_INJ_GetQueueMode\n
* CFGR JQDIS LL_ADC_INJ_GetQueueMode
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_INJ_QUEUE_DISABLE
* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
* @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
}
/**
* @brief Set one context on ADC group injected that will be checked in
* contexts queue.
* @note A context is a setting of group injected sequencer:
* - group injected trigger
* - sequencer length
* - sequencer ranks
* This function is intended to be used when contexts queue is enabled,
* because the sequence must be fully configured in one time
* (functions to set separately injected trigger and sequencer channels
* cannot be used):
* Refer to function @ref LL_ADC_INJ_SetQueueMode().
* @note In the contexts queue, only the active context can be read.
* The parameters of this function can be read using functions:
* @arg @ref LL_ADC_INJ_GetTriggerSource()
* @arg @ref LL_ADC_INJ_GetTriggerEdge()
* @arg @ref LL_ADC_INJ_GetSequencerRanks()
* @note On this STM32 series, to measure internal channels (VrefInt,
* TempSensor, ...), measurement paths to internal channels must be
* enabled separately.
* This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
* @note On STM32G4, some fast channels are available: fast analog inputs
* coming from GPIO pads (ADC_IN1..5).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must not be disabled. Can be enabled with or without conversion
* on going on either groups regular or injected.
* @rmtoll JSQR JEXTSEL LL_ADC_INJ_ConfigQueueContext\n
* JSQR JEXTEN LL_ADC_INJ_ConfigQueueContext\n
* JSQR JL LL_ADC_INJ_ConfigQueueContext\n
* JSQR JSQ1 LL_ADC_INJ_ConfigQueueContext\n
* JSQR JSQ2 LL_ADC_INJ_ConfigQueueContext\n
* JSQR JSQ3 LL_ADC_INJ_ConfigQueueContext\n
* JSQR JSQ4 LL_ADC_INJ_ConfigQueueContext
* @param ADCx ADC instance
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
* @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3 (2)
* @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (1)
* @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
*
* (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
* (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
* On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* @param ExternalTriggerEdge This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
* @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
* @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
*
* Note: This parameter is discarded in case of SW start:
* parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
* @param SequencerNbRanks This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
* @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
* @param Rank1_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @param Rank2_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @param Rank3_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @param Rank4_Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
uint32_t TriggerSource,
uint32_t ExternalTriggerEdge,
uint32_t SequencerNbRanks,
uint32_t Rank1_Channel,
uint32_t Rank2_Channel,
uint32_t Rank3_Channel,
uint32_t Rank4_Channel)
{
/* Set bits with content of parameter "Rankx_Channel" with bits position */
/* in register depending on literal "LL_ADC_INJ_RANK_x". */
/* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks */
/* because containing other bits reserved for other purpose. */
/* If parameter "TriggerSource" is set to SW start, then parameter */
/* "ExternalTriggerEdge" is discarded. */
uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
MODIFY_REG(ADCx->JSQR,
ADC_JSQR_JEXTSEL |
ADC_JSQR_JEXTEN |
ADC_JSQR_JSQ4 |
ADC_JSQR_JSQ3 |
ADC_JSQR_JSQ2 |
ADC_JSQR_JSQ1 |
ADC_JSQR_JL,
(TriggerSource & ADC_JSQR_JEXTSEL) |
(ExternalTriggerEdge * (is_trigger_not_sw)) |
(((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
(((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
SequencerNbRanks
);
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
* @{
*/
/**
* @brief Set sampling time of the selected ADC channel
* Unit: ADC clock cycles.
* @note On this device, sampling time is on channel scope: independently
* of channel mapped on ADC group regular or injected.
* @note In case of internal channel (VrefInt, TempSensor, ...) to be
* converted:
* sampling time constraints must be respected (sampling time can be
* adjusted in function of ADC clock frequency and sampling time
* setting).
* Refer to device datasheet for timings values (parameters TS_vrefint,
* TS_temp, ...).
* @note Conversion time is the addition of sampling time and processing time.
* On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
* - 6.5 ADC clock cycles at ADC resolution 6 bits
* @note In case of ADC conversion of internal channel (VrefInt,
* temperature sensor, ...), a sampling time minimum value
* is required.
* Refer to device datasheet.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll SMPR1 SMP0 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP1 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP2 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP3 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP4 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP5 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP6 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP7 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP8 LL_ADC_SetChannelSamplingTime\n
* SMPR1 SMP9 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP10 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP11 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP12 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP13 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP14 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP15 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP16 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP17 LL_ADC_SetChannelSamplingTime\n
* SMPR2 SMP18 LL_ADC_SetChannelSamplingTime
* @param ADCx ADC instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @param SamplingTime This parameter can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
* @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
*
* (1) On some devices, ADC sampling time 2.5 ADC clock cycles
* can be replaced by 3.5 ADC clock cycles.
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
/**
* @brief Get sampling time of the selected ADC channel
* Unit: ADC clock cycles.
* @note On this device, sampling time is on channel scope: independently
* of channel mapped on ADC group regular or injected.
* @note Conversion time is the addition of sampling time and processing time.
* On this STM32 series, ADC processing time is:
* - 12.5 ADC clock cycles at ADC resolution 12 bits
* - 10.5 ADC clock cycles at ADC resolution 10 bits
* - 8.5 ADC clock cycles at ADC resolution 8 bits
* - 6.5 ADC clock cycles at ADC resolution 6 bits
* @rmtoll SMPR1 SMP0 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP1 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP2 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP3 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP4 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP5 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP6 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP7 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP8 LL_ADC_GetChannelSamplingTime\n
* SMPR1 SMP9 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP10 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP11 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP12 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP13 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP14 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP15 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP16 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP17 LL_ADC_GetChannelSamplingTime\n
* SMPR2 SMP18 LL_ADC_GetChannelSamplingTime
* @param ADCx ADC instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_0
* @arg @ref LL_ADC_CHANNEL_1 (8)
* @arg @ref LL_ADC_CHANNEL_2 (8)
* @arg @ref LL_ADC_CHANNEL_3 (8)
* @arg @ref LL_ADC_CHANNEL_4 (8)
* @arg @ref LL_ADC_CHANNEL_5 (8)
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @arg @ref LL_ADC_CHANNEL_16
* @arg @ref LL_ADC_CHANNEL_17
* @arg @ref LL_ADC_CHANNEL_18
* @arg @ref LL_ADC_CHANNEL_VREFINT (7)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1 (1)
* @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5 (5)
* @arg @ref LL_ADC_CHANNEL_VBAT (6)
* @arg @ref LL_ADC_CHANNEL_VOPAMP1 (1)
* @arg @ref LL_ADC_CHANNEL_VOPAMP2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2 (2)
* @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3 (3)
* @arg @ref LL_ADC_CHANNEL_VOPAMP4 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP5 (5)
* @arg @ref LL_ADC_CHANNEL_VOPAMP6 (4)
*
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to convert in 12-bit resolution.
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles (fADC) to convert in 12-bit resolution.\n
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5 (1)
* @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
* @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
*
* (1) On some devices, ADC sampling time 2.5 ADC clock cycles
* can be replaced by 3.5 ADC clock cycles.
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
>> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
);
}
/**
* @brief Set mode single-ended or differential input of the selected
* ADC channel.
* @note Channel ending is on channel scope: independently of channel mapped
* on ADC group regular or injected.
* In differential mode: Differential measurement is carried out
* between the selected channel 'i' (positive input) and
* channel 'i+1' (negative input). Only channel 'i' has to be
* configured, channel 'i+1' is configured automatically.
* @note Refer to Reference Manual to ensure the selected channel is
* available in differential mode.
* For example, internal channels (VrefInt, TempSensor, ...) are
* not available in differential mode.
* @note When configuring a channel 'i' in differential mode,
* the channel 'i+1' is not usable separately.
* @note On STM32G4, some channels are internally fixed to single-ended inputs
* configuration:
* - ADC1: Channels 12, 15, 16, 17 and 18
* - ADC2: Channels 15, 17 and 18
* - ADC3: Channels 12, 16, 17 and 18 (1)
* - ADC4: Channels 16, 17 and 18 (1)
* - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
* (1) ADC3/4/5 are not available on all devices, refer to device datasheet
* for more details.
* @note For ADC channels configured in differential mode, both inputs
* should be biased at (Vref+)/2 +/-200mV.
* (Vref+ is the analog voltage reference)
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @note One or several values can be selected.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll DIFSEL DIFSEL LL_ADC_SetChannelSingleDiff
* @param ADCx ADC instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @param SingleDiff This parameter can be a combination of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
/* Bits for single or differential mode selection for each channel are set */
/* to 1 only when the differential mode is selected, and to 0 when the */
/* single mode is selected. */
if (SingleDiff == LL_ADC_DIFFERENTIAL_ENDED)
{
SET_BIT(ADCx->DIFSEL,
Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
}
else
{
CLEAR_BIT(ADCx->DIFSEL,
Channel & ADC_SINGLEDIFF_CHANNEL_MASK);
}
}
/**
* @brief Get mode single-ended or differential input of the selected
* ADC channel.
* @note When configuring a channel 'i' in differential mode,
* the channel 'i+1' is not usable separately.
* Therefore, to ensure a channel is configured in single-ended mode,
* the configuration of channel itself and the channel 'i-1' must be
* read back (to ensure that the selected channel channel has not been
* configured in differential mode by the previous channel).
* @note Refer to Reference Manual to ensure the selected channel is
* available in differential mode.
* For example, internal channels (VrefInt, TempSensor, ...) are
* not available in differential mode.
* @note When configuring a channel 'i' in differential mode,
* the channel 'i+1' is not usable separately.
* @note On STM32G4, some channels are internally fixed to single-ended inputs
* configuration:
* - ADC1: Channels 12, 15, 16, 17 and 18
* - ADC2: Channels 15, 17 and 18
* - ADC3: Channels 12, 16, 17 and 18 (1)
* - ADC4: Channels 16, 17 and 18 (1)
* - ADC5: Channels 2, 3, 4, 16, 17 and 18 (1)
* (1) ADC3/4/5 are not available on all devices, refer to device datasheet
* for more details.
* @note One or several values can be selected. In this case, the value
* returned is null if all channels are in single ended-mode.
* Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
* @rmtoll DIFSEL DIFSEL LL_ADC_GetChannelSingleDiff
* @param ADCx ADC instance
* @param Channel This parameter can be a combination of the following values:
* @arg @ref LL_ADC_CHANNEL_1
* @arg @ref LL_ADC_CHANNEL_2
* @arg @ref LL_ADC_CHANNEL_3
* @arg @ref LL_ADC_CHANNEL_4
* @arg @ref LL_ADC_CHANNEL_5
* @arg @ref LL_ADC_CHANNEL_6
* @arg @ref LL_ADC_CHANNEL_7
* @arg @ref LL_ADC_CHANNEL_8
* @arg @ref LL_ADC_CHANNEL_9
* @arg @ref LL_ADC_CHANNEL_10
* @arg @ref LL_ADC_CHANNEL_11
* @arg @ref LL_ADC_CHANNEL_12
* @arg @ref LL_ADC_CHANNEL_13
* @arg @ref LL_ADC_CHANNEL_14
* @arg @ref LL_ADC_CHANNEL_15
* @retval 0: channel in single-ended mode, else: channel in differential mode
*/
__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)
{
return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
* @{
*/
/**
* @brief Set ADC analog watchdog monitored channels:
* a single channel, multiple channels or all channels,
* on ADC groups regular and-or injected.
* @note Once monitored channels are selected, analog watchdog
* is enabled.
* @note In case of need to define a single channel to monitor
* with analog watchdog from sequencer channel definition,
* use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
* @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC groups regular and-or injected.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* - AWD flexible (instances AWD2, AWD3):
* - channels monitored: flexible on channels monitored, selection is
* channel wise, from from 1 to all channels.
* Specificity of this analog watchdog: Multiple channels can
* be selected. For example:
* (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
* - groups monitored: not selection possible (monitoring on both
* groups regular and injected).
* Channels selected are monitored on groups regular and injected:
* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
* CFGR AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
* CFGR AWD1EN LL_ADC_SetAnalogWDMonitChannels\n
* CFGR JAWD1EN LL_ADC_SetAnalogWDMonitChannels\n
* AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n
* AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDChannelGroup This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG (0)
* @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (0)
* @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG (0)(5)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ (0)(5)
* @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG (0)(6)
* @arg @ref LL_ADC_AWD_CH_VBAT_INJ (0)(6)
* @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (6)
* @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG (0)(1)
* @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ (0)(1)
* @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ (1)
* @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ (0)(2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ (2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG (0)(2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ (0)(2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ (2)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG (0)(3)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ (0)(3)
* @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ (3)
* @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG (0)(5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ (0)(5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ (5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG (0)(5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ (0)(5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ (5)
* @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG (0)(4)
* @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ (0)(4)
* @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ (4)
*
* (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
* (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
* (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
* (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
* (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
* (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
* (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
* (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
* - On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for more details.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
{
/* Set bits with content of parameter "AWDChannelGroup" with bits position */
/* in register and register position depending on parameter "AWDy". */
/* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */
/* containing other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
MODIFY_REG(*preg,
(AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
AWDChannelGroup & AWDy);
}
/**
* @brief Get ADC analog watchdog monitored channel.
* @note Usage of the returned channel number:
* - To reinject this channel into another function LL_ADC_xxx:
* the returned channel number is only partly formatted on definition
* of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
* with parts of literals LL_ADC_CHANNEL_x or using
* helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Then the selected literal LL_ADC_CHANNEL_x can be used
* as parameter for another function.
* - To get the channel number in decimal format:
* process the returned value with the helper macro
* @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
* Applicable only when the analog watchdog is set to monitor
* one channel.
* @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC groups regular and-or injected.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* - AWD flexible (instances AWD2, AWD3):
* - channels monitored: flexible on channels monitored, selection is
* channel wise, from from 1 to all channels.
* Specificity of this analog watchdog: Multiple channels can
* be selected. For example:
* (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
* - groups monitored: not selection possible (monitoring on both
* groups regular and injected).
* Channels selected are monitored on groups regular and injected:
* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
* CFGR AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
* CFGR AWD1EN LL_ADC_GetAnalogWDMonitChannels\n
* CFGR JAWD1EN LL_ADC_GetAnalogWDMonitChannels\n
* AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n
* AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2 (1)
* @arg @ref LL_ADC_AWD3 (1)
*
* (1) On this AWD number, monitored channel can be retrieved
* if only 1 channel is programmed (or none or all channels).
* This function cannot retrieve monitored channel if
* multiple channels are programmed simultaneously
* by bitfield.
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_AWD_DISABLE
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ (0)
* @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_INJ (0)
* @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
*
* (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+ ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));
uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & ADC_AWD_CR_ALL_CHANNEL_MASK);
/* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */
/* (parameter value LL_ADC_AWD_DISABLE). */
/* Else, the selected AWD is enabled and is monitoring a group of channels */
/* or a single channel. */
if (AnalogWDMonitChannels != 0UL)
{
if (AWDy == LL_ADC_AWD1)
{
if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)
{
/* AWD monitoring a group of channels */
AnalogWDMonitChannels = ((AnalogWDMonitChannels
| (ADC_AWD_CR23_CHANNEL_MASK)
)
& (~(ADC_CFGR_AWD1CH))
);
}
else
{
/* AWD monitoring a single channel */
AnalogWDMonitChannels = (AnalogWDMonitChannels
| (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))
);
}
}
else
{
if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
{
/* AWD monitoring a group of channels */
AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
| ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
);
}
else
{
/* AWD monitoring a single channel */
/* AWD monitoring a group of channels */
AnalogWDMonitChannels = (AnalogWDMonitChannels
| (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
| (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)
);
}
}
}
return AnalogWDMonitChannels;
}
/**
* @brief Set ADC analog watchdog thresholds value of both thresholds
* high and low.
* @note If value of only one threshold high or low must be set,
* use function @ref LL_ADC_SetAnalogWDThresholds().
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
* @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC groups regular and-or injected.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* - AWD flexible (instances AWD2, AWD3):
* - channels monitored: flexible on channels monitored, selection is
* channel wise, from from 1 to all channels.
* Specificity of this analog watchdog: Multiple channels can
* be selected. For example:
* (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
* - groups monitored: not selection possible (monitoring on both
* groups regular and injected).
* Channels selected are monitored on groups regular and injected:
* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
* @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
* impacted: the comparison of analog watchdog thresholds is done on
* oversampling final computation (after ratio and shift application):
* ADC data register bitfield [15:4] (12 most significant bits).
* @rmtoll TR1 HT1 LL_ADC_ConfigAnalogWDThresholds\n
* TR2 HT2 LL_ADC_ConfigAnalogWDThresholds\n
* TR3 HT3 LL_ADC_ConfigAnalogWDThresholds\n
* TR1 LT1 LL_ADC_ConfigAnalogWDThresholds\n
* TR2 LT2 LL_ADC_ConfigAnalogWDThresholds\n
* TR3 LT3 LL_ADC_ConfigAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
uint32_t AWDThresholdLowValue)
{
/* Set bits with content of parameter "AWDThresholdxxxValue" with bits */
/* position in register and register position depending on parameter */
/* "AWDy". */
/* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
/* containing other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1, ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
ADC_TR1_HT1 | ADC_TR1_LT1,
(AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
}
/**
* @brief Set ADC analog watchdog threshold value of threshold
* high or low.
* @note If values of both thresholds high or low must be set,
* use function @ref LL_ADC_ConfigAnalogWDThresholds().
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
* @note On this STM32 series, there are 2 kinds of analog watchdog
* instance:
* - AWD standard (instance AWD1):
* - channels monitored: can monitor 1 channel or all channels.
* - groups monitored: ADC groups regular and-or injected.
* - resolution: resolution is not limited (corresponds to
* ADC resolution configured).
* - AWD flexible (instances AWD2, AWD3):
* - channels monitored: flexible on channels monitored, selection is
* channel wise, from from 1 to all channels.
* Specificity of this analog watchdog: Multiple channels can
* be selected. For example:
* (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
* - groups monitored: not selection possible (monitoring on both
* groups regular and injected).
* Channels selected are monitored on groups regular and injected:
* LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
* LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
* - resolution: resolution is limited to 8 bits: if ADC resolution is
* 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
* the 2 LSB are ignored.
* @note If ADC oversampling is enabled, ADC analog watchdog thresholds are
* impacted: the comparison of analog watchdog thresholds is done on
* oversampling final computation (after ratio and shift application):
* ADC data register bitfield [15:4] (12 most significant bits).
* @note On this STM32 series, setting of this feature is not conditioned to
* ADC state:
* ADC can be disabled, enabled with or without conversion on going
* on either ADC groups regular or injected.
* @rmtoll TR1 HT1 LL_ADC_SetAnalogWDThresholds\n
* TR2 HT2 LL_ADC_SetAnalogWDThresholds\n
* TR3 HT3 LL_ADC_SetAnalogWDThresholds\n
* TR1 LT1 LL_ADC_SetAnalogWDThresholds\n
* TR2 LT2 LL_ADC_SetAnalogWDThresholds\n
* TR3 LT3 LL_ADC_SetAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDThresholdsHighLow This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
* @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
uint32_t AWDThresholdValue)
{
/* Set bits with content of parameter "AWDThresholdValue" with bits */
/* position in register and register position depending on parameters */
/* "AWDThresholdsHighLow" and "AWDy". */
/* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */
/* containing other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
MODIFY_REG(*preg,
AWDThresholdsHighLow,
AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
}
/**
* @brief Get ADC analog watchdog threshold value of threshold high,
* threshold low or raw data with ADC thresholds high and low
* concatenated.
* @note If raw data with ADC thresholds high and low is retrieved,
* the data of each threshold high or low can be isolated
* using helper macro:
* @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
* @note In case of ADC resolution different of 12 bits,
* analog watchdog thresholds data require a specific shift.
* Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
* @rmtoll TR1 HT1 LL_ADC_GetAnalogWDThresholds\n
* TR2 HT2 LL_ADC_GetAnalogWDThresholds\n
* TR3 HT3 LL_ADC_GetAnalogWDThresholds\n
* TR1 LT1 LL_ADC_GetAnalogWDThresholds\n
* TR2 LT2 LL_ADC_GetAnalogWDThresholds\n
* TR3 LT3 LL_ADC_GetAnalogWDThresholds
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @arg @ref LL_ADC_AWD2
* @arg @ref LL_ADC_AWD3
* @param AWDThresholdsHighLow This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
* @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
(AWDThresholdsHighLow | ADC_TR1_LT1))
>> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
& ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
}
/**
* @brief Set ADC analog watchdog filtering configuration
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @note On this STM32 series, this feature is only available on first
* analog watchdog (AWD1)
* @rmtoll TR1 AWDFILT LL_ADC_SetAWDFilteringConfiguration
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @param FilteringConfig This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD_FILTERING_NONE
* @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
{
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
}
/**
* @brief Get ADC analog watchdog filtering configuration
* @note On this STM32 series, this feature is only available on first
* analog watchdog (AWD1)
* @rmtoll TR1 AWDFILT LL_ADC_GetAWDFilteringConfiguration
* @param ADCx ADC instance
* @param AWDy This parameter can be one of the following values:
* @arg @ref LL_ADC_AWD1
* @retval Returned value can be:
* @arg @ref LL_ADC_AWD_FILTERING_NONE
* @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
* @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
*/
__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy)
{
/* Prevent unused argument(s) compilation warning */
(void)(AWDy);
return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
* @{
*/
/**
* @brief Set ADC oversampling scope: ADC groups regular and-or injected
* (availability of ADC group injected depends on STM32 families).
* @note If both groups regular and injected are selected,
* specify behavior of ADC group injected interrupting
* group regular: when ADC group injected is triggered,
* the oversampling on ADC group regular is either
* temporary stopped and continued, or resumed from start
* (oversampler buffer reset).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR2 ROVSE LL_ADC_SetOverSamplingScope\n
* CFGR2 JOVSE LL_ADC_SetOverSamplingScope\n
* CFGR2 ROVSM LL_ADC_SetOverSamplingScope
* @param ADCx ADC instance
* @param OvsScope This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_DISABLE
* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
* @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
* @arg @ref LL_ADC_OVS_GRP_INJECTED
* @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
{
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
}
/**
* @brief Get ADC oversampling scope: ADC groups regular and-or injected
* (availability of ADC group injected depends on STM32 families).
* @note If both groups regular and injected are selected,
* specify behavior of ADC group injected interrupting
* group regular: when ADC group injected is triggered,
* the oversampling on ADC group regular is either
* temporary stopped and continued, or resumed from start
* (oversampler buffer reset).
* @rmtoll CFGR2 ROVSE LL_ADC_GetOverSamplingScope\n
* CFGR2 JOVSE LL_ADC_GetOverSamplingScope\n
* CFGR2 ROVSM LL_ADC_GetOverSamplingScope
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OVS_DISABLE
* @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
* @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
* @arg @ref LL_ADC_OVS_GRP_INJECTED
* @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
}
/**
* @brief Set ADC oversampling discontinuous mode (triggered mode)
* on the selected ADC group.
* @note Number of oversampled conversions are done either in:
* - continuous mode (all conversions of oversampling ratio
* are done from 1 trigger)
* - discontinuous mode (each conversion of oversampling ratio
* needs a trigger)
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on group regular.
* @note On this STM32 series, oversampling discontinuous mode
* (triggered mode) can be used only when oversampling is
* set on group regular only and in resumed mode.
* @rmtoll CFGR2 TROVS LL_ADC_SetOverSamplingDiscont
* @param ADCx ADC instance
* @param OverSamplingDiscont This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_REG_CONT
* @arg @ref LL_ADC_OVS_REG_DISCONT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
{
MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
}
/**
* @brief Get ADC oversampling discontinuous mode (triggered mode)
* on the selected ADC group.
* @note Number of oversampled conversions are done either in:
* - continuous mode (all conversions of oversampling ratio
* are done from 1 trigger)
* - discontinuous mode (each conversion of oversampling ratio
* needs a trigger)
* @rmtoll CFGR2 TROVS LL_ADC_GetOverSamplingDiscont
* @param ADCx ADC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_OVS_REG_CONT
* @arg @ref LL_ADC_OVS_REG_DISCONT
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
}
/**
* @brief Set ADC oversampling
* (impacting both ADC groups regular and injected)
* @note This function set the 2 items of oversampling configuration:
* - ratio
* - shift
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be disabled or enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n
* CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift
* @param ADCx ADC instance
* @param Ratio This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_RATIO_2
* @arg @ref LL_ADC_OVS_RATIO_4
* @arg @ref LL_ADC_OVS_RATIO_8
* @arg @ref LL_ADC_OVS_RATIO_16
* @arg @ref LL_ADC_OVS_RATIO_32
* @arg @ref LL_ADC_OVS_RATIO_64
* @arg @ref LL_ADC_OVS_RATIO_128
* @arg @ref LL_ADC_OVS_RATIO_256
* @param Shift This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_SHIFT_NONE
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
* @retval None
*/
__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
{
MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
}
/**
* @brief Get ADC oversampling ratio
* (impacting both ADC groups regular and injected)
* @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio
* @param ADCx ADC instance
* @retval Ratio This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_RATIO_2
* @arg @ref LL_ADC_OVS_RATIO_4
* @arg @ref LL_ADC_OVS_RATIO_8
* @arg @ref LL_ADC_OVS_RATIO_16
* @arg @ref LL_ADC_OVS_RATIO_32
* @arg @ref LL_ADC_OVS_RATIO_64
* @arg @ref LL_ADC_OVS_RATIO_128
* @arg @ref LL_ADC_OVS_RATIO_256
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
}
/**
* @brief Get ADC oversampling shift
* (impacting both ADC groups regular and injected)
* @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift
* @param ADCx ADC instance
* @retval Shift This parameter can be one of the following values:
* @arg @ref LL_ADC_OVS_SHIFT_NONE
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
* @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
*/
__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
* @{
*/
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Set ADC multimode configuration to operate in independent mode
* or multimode (for devices with several ADC instances).
* @note If multimode configuration: the selected ADC instance is
* either master or slave depending on hardware.
* Refer to reference manual.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR DUAL LL_ADC_SetMultimode
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param Multimode This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_INDEPENDENT
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
}
/**
* @brief Get ADC multimode configuration to operate in independent mode
* or multimode (for devices with several ADC instances).
* @note If multimode configuration: the selected ADC instance is
* either master or slave depending on hardware.
* Refer to reference manual.
* @rmtoll CCR DUAL LL_ADC_GetMultimode
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_MULTI_INDEPENDENT
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
* @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
* @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
}
/**
* @brief Set ADC multimode conversion data transfer: no transfer
* or transfer by DMA.
* @note If ADC multimode transfer by DMA is not selected:
* each ADC uses its own DMA channel, with its individual
* DMA transfer settings.
* If ADC multimode transfer by DMA is selected:
* One DMA channel is used for both ADC (DMA of ADC master)
* Specifies the DMA requests mode:
* - Limited mode (One shot mode): DMA transfer requests are stopped
* when number of DMA data transfers (number of
* ADC conversions) is reached.
* This ADC mode is intended to be used with DMA mode non-circular.
* - Unlimited mode: DMA transfer requests are unlimited,
* whatever number of DMA data transfers (number of
* ADC conversions).
* This ADC mode is intended to be used with DMA mode circular.
* @note If ADC DMA requests mode is set to unlimited and DMA is set to
* mode non-circular:
* when DMA transfers size will be reached, DMA will stop transfers of
* ADC conversions data ADC will raise an overrun error
* (overrun flag and interruption if enabled).
* @note How to retrieve multimode conversion data:
* Whatever multimode transfer by DMA setting: using function
* @ref LL_ADC_REG_ReadMultiConversionData32().
* If ADC multimode transfer by DMA is selected: conversion data
* is a raw data with ADC master and slave concatenated.
* A macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled
* or enabled without conversion on going on group regular.
* @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n
* CCR DMACFG LL_ADC_SetMultiDMATransfer
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param MultiDMATransfer This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
}
/**
* @brief Get ADC multimode conversion data transfer: no transfer
* or transfer by DMA.
* @note If ADC multimode transfer by DMA is not selected:
* each ADC uses its own DMA channel, with its individual
* DMA transfer settings.
* If ADC multimode transfer by DMA is selected:
* One DMA channel is used for both ADC (DMA of ADC master)
* Specifies the DMA requests mode:
* - Limited mode (One shot mode): DMA transfer requests are stopped
* when number of DMA data transfers (number of
* ADC conversions) is reached.
* This ADC mode is intended to be used with DMA mode non-circular.
* - Unlimited mode: DMA transfer requests are unlimited,
* whatever number of DMA data transfers (number of
* ADC conversions).
* This ADC mode is intended to be used with DMA mode circular.
* @note If ADC DMA requests mode is set to unlimited and DMA is set to
* mode non-circular:
* when DMA transfers size will be reached, DMA will stop transfers of
* ADC conversions data ADC will raise an overrun error
* (overrun flag and interruption if enabled).
* @note How to retrieve multimode conversion data:
* Whatever multimode transfer by DMA setting: using function
* @ref LL_ADC_REG_ReadMultiConversionData32().
* If ADC multimode transfer by DMA is selected: conversion data
* is a raw data with ADC master and slave concatenated.
* A macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
* @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n
* CCR DMACFG LL_ADC_GetMultiDMATransfer
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
* @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
}
/**
* @brief Set ADC multimode delay between 2 sampling phases.
* @note The sampling delay range depends on ADC resolution:
* - ADC resolution 12 bits can have maximum delay of 12 cycles.
* - ADC resolution 10 bits can have maximum delay of 10 cycles.
* - ADC resolution 8 bits can have maximum delay of 8 cycles.
* - ADC resolution 6 bits can have maximum delay of 6 cycles.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* All ADC instances of the ADC common group must be disabled.
* This check can be done with function @ref LL_ADC_IsEnabled() for each
* ADC instance or by using helper macro helper macro
* @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
* @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param MultiTwoSamplingDelay This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
*
* (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
* (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
* (3) Parameter available only if ADC resolution is 12 bits.
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
{
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
}
/**
* @brief Get ADC multimode delay between 2 sampling phases.
* @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval Returned value can be one of the following values:
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES (1)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
* @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
*
* (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
* (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
* (3) Parameter available only if ADC resolution is 12 bits.
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
* @{
*/
/**
* @brief Put ADC instance in deep power down state.
* @note In case of ADC calibration necessary: When ADC is in deep-power-down
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_EnableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_DEEPPWD);
}
/**
* @brief Disable ADC deep power down mode.
* @note In case of ADC calibration necessary: When ADC is in deep-power-down
* state, the internal analog calibration is lost. After exiting from
* deep power down, calibration must be relaunched or calibration factor
* (preliminarily saved) must be set back into calibration register.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
}
/**
* @brief Get the selected ADC instance deep power down state.
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
}
/**
* @brief Enable ADC instance internal voltage regulator.
* @note On this STM32 series, after ADC internal voltage regulator enable,
* a delay for ADC internal voltage regulator stabilization
* is required before performing a ADC calibration or ADC enable.
* Refer to device datasheet, parameter tADCVREG_STUP.
* Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
/**
* @brief Disable ADC internal voltage regulator.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
}
/**
* @brief Get the selected ADC instance internal voltage regulator state.
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
}
/**
* @brief Enable the selected ADC instance.
* @note On this STM32 series, after ADC enable, a delay for
* ADC internal analog stabilization is required before performing a
* ADC conversion start.
* Refer to device datasheet, parameter tSTAB.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled and ADC internal voltage regulator enabled.
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADEN);
}
/**
* @brief Disable the selected ADC instance.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be not disabled. Must be enabled without conversion on going
* on either groups regular or injected.
* @rmtoll CR ADDIS LL_ADC_Disable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADDIS);
}
/**
* @brief Get the selected ADC instance enable state.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
}
/**
* @brief Get the selected ADC instance disable state.
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
}
/**
* @brief Start ADC calibration in the mode single-ended
* or differential (for devices with differential mode available).
* @note On this STM32 series, a minimum number of ADC clock cycles
* are required between ADC end of calibration and ADC enable.
* Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
* @note For devices with differential mode available:
* Calibration of offset is specific to each of
* single-ended and differential modes
* (calibration run must be performed for each of these
* differential modes, if used afterwards and if the application
* requires their calibration).
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be ADC disabled.
* @rmtoll CR ADCAL LL_ADC_StartCalibration\n
* CR ADCALDIF LL_ADC_StartCalibration
* @param ADCx ADC instance
* @param SingleDiff This parameter can be one of the following values:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
}
/**
* @brief Get ADC calibration state.
* @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing
* @param ADCx ADC instance
* @retval 0: calibration complete, 1: calibration in progress.
*/
__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
* @{
*/
/**
* @brief Start ADC group regular conversion.
* @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
* without ADC disable command on going.
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTART);
}
/**
* @brief Stop ADC group regular conversion.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group regular,
* without ADC disable command on going.
* @rmtoll CR ADSTP LL_ADC_REG_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTP);
}
/**
* @brief Get ADC group regular conversion state.
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
}
/**
* @brief Get ADC group regular command of conversion stop state
* @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing
* @param ADCx ADC instance
* @retval 0: no command of conversion stop is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
}
/**
* @brief Start ADC sampling phase for sampling time trigger mode
* @note This function is relevant only when
* - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
* using @ref LL_ADC_REG_SetSamplingMode
* - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
* without ADC disable command on going.
* @rmtoll CFGR2 SWTRIG LL_ADC_REG_StartSamplingPhase
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
}
/**
* @brief Stop ADC sampling phase for sampling time trigger mode and start conversion
* @note This function is relevant only when
* - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
* using @ref LL_ADC_REG_SetSamplingMode
* - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
* - @ref LL_ADC_REG_StartSamplingPhase has been called to start
* the sampling phase
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group regular,
* without conversion stop command on going on group regular,
* without ADC disable command on going.
* @rmtoll CFGR2 SWTRIG LL_ADC_REG_StopSamplingPhase
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
}
/**
* @brief Get ADC group regular conversion data, range fit for
* all ADC configurations: all ADC resolutions and
* all oversampling increased data width (for devices
* with feature oversampling).
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
{
return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 12 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
* @param ADCx ADC instance
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
{
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 10 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10
* @param ADCx ADC instance
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)
{
return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 8 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)
{
return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
/**
* @brief Get ADC group regular conversion data, range fit for
* ADC resolution 6 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_REG_ReadConversionData32.
* @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6
* @param ADCx ADC instance
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)
{
return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
}
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Get ADC multimode conversion data of ADC master, ADC slave
* or raw data with ADC master and slave concatenated.
* @note If raw data with ADC master and slave concatenated is retrieved,
* a macro is available to get the conversion data of
* ADC master or ADC slave: see helper macro
* @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
* (however this macro is mainly intended for multimode
* transfer by DMA, because this function can do the same
* by getting multimode conversion data of ADC master or ADC slave
* separately).
* @rmtoll CDR RDATA_MST LL_ADC_REG_ReadMultiConversionData32\n
* CDR RDATA_SLV LL_ADC_REG_ReadMultiConversionData32
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @param ConversionData This parameter can be one of the following values:
* @arg @ref LL_ADC_MULTI_MASTER
* @arg @ref LL_ADC_MULTI_SLAVE
* @arg @ref LL_ADC_MULTI_MASTER_SLAVE
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
{
return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
ConversionData)
>> (POSITION_VAL(ConversionData) & 0x1FUL)
);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
* @{
*/
/**
* @brief Start ADC group injected conversion.
* @note On this STM32 series, this function is relevant for both
* internal trigger (SW start) and external trigger:
* - If ADC trigger has been set to software start, ADC conversion
* starts immediately.
* - If ADC trigger has been set to external trigger, ADC conversion
* will start at next trigger event (on the selected trigger edge)
* following the ADC start conversion command.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled without conversion on going on group injected,
* without conversion stop command on going on group injected,
* without ADC disable command on going.
* @rmtoll CR JADSTART LL_ADC_INJ_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_JADSTART);
}
/**
* @brief Stop ADC group injected conversion.
* @note On this STM32 series, setting of this feature is conditioned to
* ADC state:
* ADC must be enabled with conversion on going on group injected,
* without ADC disable command on going.
* @rmtoll CR JADSTP LL_ADC_INJ_StopConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
{
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_JADSTP);
}
/**
* @brief Get ADC group injected conversion state.
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
}
/**
* @brief Get ADC group injected command of conversion stop state
* @rmtoll CR JADSTP LL_ADC_INJ_IsStopConversionOngoing
* @param ADCx ADC instance
* @retval 0: no command of conversion stop is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
}
/**
* @brief Get ADC group injected conversion data, range fit for
* all ADC configurations: all ADC resolutions and
* all oversampling increased data width (for devices
* with feature oversampling).
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
* JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
* JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
* JDR4 JDATA LL_ADC_INJ_ReadConversionData32
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint32_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
);
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 12 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
* JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
* JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
* JDR4 JDATA LL_ADC_INJ_ReadConversionData12
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
);
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 10 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n
* JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n
* JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n
* JDR4 JDATA LL_ADC_INJ_ReadConversionData10
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint16_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
);
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 8 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n
* JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n
* JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n
* JDR4 JDATA LL_ADC_INJ_ReadConversionData8
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
);
}
/**
* @brief Get ADC group injected conversion data, range fit for
* ADC resolution 6 bits.
* @note For devices with feature oversampling: Oversampling
* can increase data width, function for extended range
* may be needed: @ref LL_ADC_INJ_ReadConversionData32.
* @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n
* JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n
* JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n
* JDR4 JDATA LL_ADC_INJ_ReadConversionData6
* @param ADCx ADC instance
* @param Rank This parameter can be one of the following values:
* @arg @ref LL_ADC_INJ_RANK_1
* @arg @ref LL_ADC_INJ_RANK_2
* @arg @ref LL_ADC_INJ_RANK_3
* @arg @ref LL_ADC_INJ_RANK_4
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
*/
__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)
{
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
return (uint8_t)(READ_BIT(*preg,
ADC_JDR1_JDATA)
);
}
/**
* @}
*/
/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
* @{
*/
/**
* @brief Get flag ADC ready.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group regular end of unitary conversion.
* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group regular end of sequence conversions.
* @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group regular overrun.
* @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group regular end of sampling phase.
* @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group injected end of unitary conversion.
* @rmtoll ISR JEOC LL_ADC_IsActiveFlag_JEOC
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group injected end of sequence conversions.
* @rmtoll ISR JEOS LL_ADC_IsActiveFlag_JEOS
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC group injected contexts queue overflow.
* @rmtoll ISR JQOVF LL_ADC_IsActiveFlag_JQOVF
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC analog watchdog 1 flag
* @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC analog watchdog 2.
* @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
}
/**
* @brief Get flag ADC analog watchdog 3.
* @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
}
/**
* @brief Clear flag ADC ready.
* @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
* is enabled and when conversion clock is active.
* (not only core clock: this ADC has a dual clock domain)
* @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
}
/**
* @brief Clear flag ADC group regular end of unitary conversion.
* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
}
/**
* @brief Clear flag ADC group regular end of sequence conversions.
* @rmtoll ISR EOS LL_ADC_ClearFlag_EOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
}
/**
* @brief Clear flag ADC group regular overrun.
* @rmtoll ISR OVR LL_ADC_ClearFlag_OVR
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
}
/**
* @brief Clear flag ADC group regular end of sampling phase.
* @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
}
/**
* @brief Clear flag ADC group injected end of unitary conversion.
* @rmtoll ISR JEOC LL_ADC_ClearFlag_JEOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
}
/**
* @brief Clear flag ADC group injected end of sequence conversions.
* @rmtoll ISR JEOS LL_ADC_ClearFlag_JEOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
}
/**
* @brief Clear flag ADC group injected contexts queue overflow.
* @rmtoll ISR JQOVF LL_ADC_ClearFlag_JQOVF
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
}
/**
* @brief Clear flag ADC analog watchdog 1.
* @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
}
/**
* @brief Clear flag ADC analog watchdog 2.
* @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
}
/**
* @brief Clear flag ADC analog watchdog 3.
* @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
{
WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
}
#if defined(ADC_MULTIMODE_SUPPORT)
/**
* @brief Get flag multimode ADC ready of the ADC master.
* @rmtoll CSR ADRDY_MST LL_ADC_IsActiveFlag_MST_ADRDY
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC ready of the ADC slave.
* @rmtoll CSR ADRDY_SLV LL_ADC_IsActiveFlag_SLV_ADRDY
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group regular end of unitary conversion of the ADC master.
* @rmtoll CSR EOC_MST LL_ADC_IsActiveFlag_MST_EOC
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
* @rmtoll CSR EOC_SLV LL_ADC_IsActiveFlag_SLV_EOC
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
* @rmtoll CSR EOS_MST LL_ADC_IsActiveFlag_MST_EOS
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
* @rmtoll CSR EOS_SLV LL_ADC_IsActiveFlag_SLV_EOS
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group regular overrun of the ADC master.
* @rmtoll CSR OVR_MST LL_ADC_IsActiveFlag_MST_OVR
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group regular overrun of the ADC slave.
* @rmtoll CSR OVR_SLV LL_ADC_IsActiveFlag_SLV_OVR
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group regular end of sampling of the ADC master.
* @rmtoll CSR EOSMP_MST LL_ADC_IsActiveFlag_MST_EOSMP
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group regular end of sampling of the ADC slave.
* @rmtoll CSR EOSMP_SLV LL_ADC_IsActiveFlag_SLV_EOSMP
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group injected end of unitary conversion of the ADC master.
* @rmtoll CSR JEOC_MST LL_ADC_IsActiveFlag_MST_JEOC
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
* @rmtoll CSR JEOC_SLV LL_ADC_IsActiveFlag_SLV_JEOC
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
* @rmtoll CSR JEOS_MST LL_ADC_IsActiveFlag_MST_JEOS
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
* @rmtoll CSR JEOS_SLV LL_ADC_IsActiveFlag_SLV_JEOS
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group injected context queue overflow of the ADC master.
* @rmtoll CSR JQOVF_MST LL_ADC_IsActiveFlag_MST_JQOVF
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC group injected context queue overflow of the ADC slave.
* @rmtoll CSR JQOVF_SLV LL_ADC_IsActiveFlag_SLV_JQOVF
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
* @rmtoll CSR AWD1_MST LL_ADC_IsActiveFlag_MST_AWD1
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode analog watchdog 1 of the ADC slave.
* @rmtoll CSR AWD1_SLV LL_ADC_IsActiveFlag_SLV_AWD1
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC analog watchdog 2 of the ADC master.
* @rmtoll CSR AWD2_MST LL_ADC_IsActiveFlag_MST_AWD2
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC analog watchdog 2 of the ADC slave.
* @rmtoll CSR AWD2_SLV LL_ADC_IsActiveFlag_SLV_AWD2
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC analog watchdog 3 of the ADC master.
* @rmtoll CSR AWD3_MST LL_ADC_IsActiveFlag_MST_AWD3
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
}
/**
* @brief Get flag multimode ADC analog watchdog 3 of the ADC slave.
* @rmtoll CSR AWD3_SLV LL_ADC_IsActiveFlag_SLV_AWD3
* @param ADCxy_COMMON ADC common instance
* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)
{
return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
}
#endif /* ADC_MULTIMODE_SUPPORT */
/**
* @}
*/
/** @defgroup ADC_LL_EF_IT_Management ADC IT management
* @{
*/
/**
* @brief Enable ADC ready.
* @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
}
/**
* @brief Enable interruption ADC group regular end of unitary conversion.
* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
}
/**
* @brief Enable interruption ADC group regular end of sequence conversions.
* @rmtoll IER EOSIE LL_ADC_EnableIT_EOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
}
/**
* @brief Enable ADC group regular interruption overrun.
* @rmtoll IER OVRIE LL_ADC_EnableIT_OVR
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
}
/**
* @brief Enable interruption ADC group regular end of sampling.
* @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
}
/**
* @brief Enable interruption ADC group injected end of unitary conversion.
* @rmtoll IER JEOCIE LL_ADC_EnableIT_JEOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
}
/**
* @brief Enable interruption ADC group injected end of sequence conversions.
* @rmtoll IER JEOSIE LL_ADC_EnableIT_JEOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
}
/**
* @brief Enable interruption ADC group injected context queue overflow.
* @rmtoll IER JQOVFIE LL_ADC_EnableIT_JQOVF
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
}
/**
* @brief Enable interruption ADC analog watchdog 1.
* @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
}
/**
* @brief Enable interruption ADC analog watchdog 2.
* @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
}
/**
* @brief Enable interruption ADC analog watchdog 3.
* @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
{
SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
}
/**
* @brief Disable interruption ADC ready.
* @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
}
/**
* @brief Disable interruption ADC group regular end of unitary conversion.
* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
}
/**
* @brief Disable interruption ADC group regular end of sequence conversions.
* @rmtoll IER EOSIE LL_ADC_DisableIT_EOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
}
/**
* @brief Disable interruption ADC group regular overrun.
* @rmtoll IER OVRIE LL_ADC_DisableIT_OVR
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
}
/**
* @brief Disable interruption ADC group regular end of sampling.
* @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
}
/**
* @brief Disable interruption ADC group regular end of unitary conversion.
* @rmtoll IER JEOCIE LL_ADC_DisableIT_JEOC
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
}
/**
* @brief Disable interruption ADC group injected end of sequence conversions.
* @rmtoll IER JEOSIE LL_ADC_DisableIT_JEOS
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
}
/**
* @brief Disable interruption ADC group injected context queue overflow.
* @rmtoll IER JQOVFIE LL_ADC_DisableIT_JQOVF
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
}
/**
* @brief Disable interruption ADC analog watchdog 1.
* @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
}
/**
* @brief Disable interruption ADC analog watchdog 2.
* @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
}
/**
* @brief Disable interruption ADC analog watchdog 3.
* @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
{
CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
}
/**
* @brief Get state of interruption ADC ready
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group regular end of unitary conversion
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group regular end of sequence conversions
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group regular overrun
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group regular end of sampling
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group injected end of unitary conversion
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER JEOCIE LL_ADC_IsEnabledIT_JEOC
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group injected end of sequence conversions
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER JEOSIE LL_ADC_IsEnabledIT_JEOS
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC group injected context queue overflow interrupt state
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER JQOVFIE LL_ADC_IsEnabledIT_JQOVF
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption ADC analog watchdog 1
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption Get ADC analog watchdog 2
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
}
/**
* @brief Get state of interruption Get ADC analog watchdog 3
* (0: interrupt disabled, 1: interrupt enabled).
* @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3
* @param ADCx ADC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
/* Initialization of some features of ADC common parameters and multimode */
ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
/* De-initialization of ADC instance, ADC group regular and ADC group injected */
/* (availability of ADC group injected depends on STM32 families) */
ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
/* Initialization of some features of ADC instance */
ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
/* Initialization of some features of ADC instance and ADC group regular */
ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
/* Initialization of some features of ADC instance and ADC group injected */
ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_ADC_H */
| 492,347 | C | 59.159824 | 468 | 0.597089 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h | /**
******************************************************************************
* @file stm32g4xx_ll_comp.h
* @author MCD Application Team
* @brief Header file of COMP LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_COMP_H
#define STM32G4xx_LL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
/** @defgroup COMP_LL COMP
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup COMP_LL_Private_Macros COMP Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of COMP instance.
*/
typedef struct
{
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */
uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */
uint32_t OutputPolarity; /*!< Set comparator output polarity.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */
uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */
} LL_COMP_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
* @{
*/
#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL) /*!< Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
/**
* @}
*/
/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
* @{
*/
#define LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
/**
* @}
*/
/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
* @{
*/
#define LL_COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
#define LL_COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0) /*!< Hysteresis level 10mV */
#define LL_COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 ) /*!< Hysteresis level 20mV */
#define LL_COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 30mV */
#define LL_COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 ) /*!< Hysteresis level 40mV */
#define LL_COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0) /*!< Hysteresis level 50mV */
#define LL_COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 ) /*!< Hysteresis level 60mV */
#define LL_COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 70mV */
#define LL_COMP_HYSTERESIS_LOW LL_COMP_HYSTERESIS_10MV /*!< Hysteresis level low */
#define LL_COMP_HYSTERESIS_MEDIUM LL_COMP_HYSTERESIS_40MV /*!< Hysteresis level medium */
#define LL_COMP_HYSTERESIS_HIGH LL_COMP_HYSTERESIS_70MV /*!< Hysteresis level high */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
* @{
*/
#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
* @{
*/
#define LL_COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM20 OC5 (Common to all COMP instances). Note: For TIM20 instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM15 OC1 (Common to all COMP instances). */
#define LL_COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM4 OC3 (Common to all COMP instances). */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
* @{
*/
#define LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
#define LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
/**
* @}
*/
/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
* @note Only COMP peripheral HW delays are defined in COMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for comparator startup time. */
/* Note: Delay required to reach propagation delay specification. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
#define LL_COMP_DELAY_STARTUP_US ( 5UL) /*!< Delay for COMP startup time */
/* Delay for comparator voltage scaler stabilization time. */
/* Note: Voltage scaler is used when selecting comparator input */
/* based on VrefInt: VrefInt or subdivision of VrefInt. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART_SCALER"). */
/* Unit: us */
#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL) /*!< Delay for COMP voltage scaler stabilization time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
* @{
*/
/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
* @{
*/
/**
* @brief Write a value in COMP register
* @param __INSTANCE__ comparator instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in COMP register
* @param __INSTANCE__ comparator instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
* @{
*/
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
* @{
*/
/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
* @{
*/
/**
* @brief Set comparator inputs minus (inverting) and plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
* subdivision of VrefInt).
* - For scaler bridge power consumption values,
* refer to device datasheet, parameter "IDDA(SCALER)".
* - Voltage scaler requires a delay for voltage stabilization.
* Refer to device datasheet, parameter "tSTART_SCALER".
* - Scaler bridge is common for all comparator instances,
* therefore if at least one of the comparator instance
* is requiring the scaler bridge, it remains enabled.
* @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n
* CSR INPSEL LL_COMP_ConfigInputs\n
* CSR BRGEN LL_COMP_ConfigInputs\n
* CSR SCALEN LL_COMP_ConfigInputs
* @param COMPx Comparator instance
* @param InputMinus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
* @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2 (6)
* (a,b...) Only available for COMPa, COMPb...
* For COMPx & DACx instances availability, please refer to datasheet
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
* @param InputPlus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
* @retval None
*/
__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
{
MODIFY_REG(COMPx->CSR,
COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
InputMinus | InputPlus);
}
/**
* @brief Set comparator input plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INPSEL LL_COMP_SetInputPlus
* @param COMPx Comparator instance
* @param InputPlus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
}
/**
* @brief Get comparator input plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INPSEL LL_COMP_GetInputPlus
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
}
/**
* @brief Set comparator input minus (inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
* subdivision of VrefInt).
* - For scaler bridge power consumption values,
* refer to device datasheet, parameter "IDDA(SCALER)".
* - Voltage scaler requires a delay for voltage stabilization.
* Refer to device datasheet, parameter "tSTART_SCALER".
* - Scaler bridge is common for all comparator instances,
* therefore if at least one of the comparator instance
* is requiring the scaler bridge, it remains enabled.
* @rmtoll CSR INMSEL LL_COMP_SetInputMinus\n
* CSR BRGEN LL_COMP_SetInputMinus\n
* CSR SCALEN LL_COMP_SetInputMinus
* @param COMPx Comparator instance
* @param InputMinus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
* @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2 (6)
* (a,b...) Only available for COMPa, COMPb...
* For COMPx & DACx instances availability, please refer to datasheet
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
}
/**
* @brief Get comparator input minus (inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INMSEL LL_COMP_GetInputMinus\n
* CSR BRGEN LL_COMP_GetInputMinus\n
* CSR SCALEN LL_COMP_GetInputMinus
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
* @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2 (6)
* (a,b...) Only available for COMPa, COMPb...
* For COMPx & DACx instances availability, please refer to datasheet
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
}
/**
* @brief Set comparator instance hysteresis mode of the input minus (inverting input).
* @rmtoll CSR HYST LL_COMP_SetInputHysteresis
* @param COMPx Comparator instance
* @param InputHysteresis This parameter can be one of the following values:
* @arg @ref LL_COMP_HYSTERESIS_NONE
* @arg @ref LL_COMP_HYSTERESIS_10MV
* @arg @ref LL_COMP_HYSTERESIS_20MV
* @arg @ref LL_COMP_HYSTERESIS_30MV
* @arg @ref LL_COMP_HYSTERESIS_40MV
* @arg @ref LL_COMP_HYSTERESIS_50MV
* @arg @ref LL_COMP_HYSTERESIS_60MV
* @arg @ref LL_COMP_HYSTERESIS_70MV
* @arg @ref LL_COMP_HYSTERESIS_LOW
* @arg @ref LL_COMP_HYSTERESIS_MEDIUM
* @arg @ref LL_COMP_HYSTERESIS_HIGH
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
}
/**
* @brief Get comparator instance hysteresis mode of the minus (inverting) input.
* @rmtoll CSR HYST LL_COMP_GetInputHysteresis
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_HYSTERESIS_NONE
* @arg @ref LL_COMP_HYSTERESIS_10MV
* @arg @ref LL_COMP_HYSTERESIS_20MV
* @arg @ref LL_COMP_HYSTERESIS_30MV
* @arg @ref LL_COMP_HYSTERESIS_40MV
* @arg @ref LL_COMP_HYSTERESIS_50MV
* @arg @ref LL_COMP_HYSTERESIS_60MV
* @arg @ref LL_COMP_HYSTERESIS_70MV
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
}
/**
* @}
*/
/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
* @{
*/
/**
* @brief Set comparator instance output polarity.
* @rmtoll CSR POLARITY LL_COMP_SetOutputPolarity
* @param COMPx Comparator instance
* @param OutputPolarity This parameter can be one of the following values:
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
}
/**
* @brief Get comparator instance output polarity.
* @rmtoll CSR POLARITY LL_COMP_GetOutputPolarity
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
*/
__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
}
/**
* @brief Set comparator instance blanking source.
* @note Blanking source may be specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note Availability of parameters of blanking source from timer
* depends on timers availability on the selected device.
* @rmtoll CSR BLANKING LL_COMP_SetOutputBlankingSource
* @param COMPx Comparator instance
* @param BlankingSource This parameter can be one of the following values:
* @arg @ref LL_COMP_BLANKINGSRC_NONE
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM20_OC5
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
* @arg @ref LL_COMP_BLANKINGSRC_TIM4_OC3
*
* On STM32G4 series, blanking sources are linked to COMP instance (except
* those without COMPx suffix that are common to all instances)
* Note: For COMPx & TIMx instances availability, please refer to datasheet
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
}
/**
* @brief Get comparator instance blanking source.
* @note Availability of parameters of blanking source from timer
* depends on timers availability on the selected device.
* @note Blanking source may be specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR BLANKING LL_COMP_GetOutputBlankingSource
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_BLANKINGSRC_NONE
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM20_OC5
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
* @arg @ref LL_COMP_BLANKINGSRC_TIM4_OC3
*
* On STM32G4 series, blanking sources are linked to COMP instance (except
* those without COMPx suffix that are common to all instances)
* Note: For COMPx & TIMx instances availability, please refer to datasheet
*/
__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
}
/**
* @}
*/
/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
* @{
*/
/**
* @brief Enable comparator instance.
* @note After enable from off state, comparator requires a delay
* to reach reach propagation delay specification.
* Refer to device datasheet, parameter "tSTART".
* @rmtoll CSR EN LL_COMP_Enable
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
{
SET_BIT(COMPx->CSR, COMP_CSR_EN);
}
/**
* @brief Disable comparator instance.
* @rmtoll CSR EN LL_COMP_Disable
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
{
CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
}
/**
* @brief Get comparator enable state
* (0: COMP is disabled, 1: COMP is enabled)
* @rmtoll CSR EN LL_COMP_IsEnabled
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
}
/**
* @brief Lock comparator instance.
* @note Once locked, comparator configuration can be accessed in read-only.
* @note The only way to unlock the comparator is a device hardware reset.
* @rmtoll CSR LOCK LL_COMP_Lock
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
{
SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
}
/**
* @brief Get comparator lock state
* (0: COMP is unlocked, 1: COMP is locked).
* @note Once locked, comparator configuration can be accessed in read-only.
* @note The only way to unlock the comparator is a device hardware reset.
* @rmtoll CSR LOCK LL_COMP_IsLocked
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
}
/**
* @brief Read comparator instance output level.
* @note On this STM32 series, comparator 'value' is taken before
* polarity and blanking are applied, thus:
* - Comparator output is low when the input plus
* is at a lower voltage than the input minus
* - Comparator output is high when the input plus
* is at a higher voltage than the input minus
* @rmtoll CSR VALUE LL_COMP_ReadOutputLevel
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
* @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
*/
__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
>> COMP_CSR_VALUE_Pos);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);
void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_COMP_H */
| 41,212 | C | 53.370712 | 393 | 0.610259 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_irda.h | /**
******************************************************************************
* @file stm32g4xx_hal_irda.h
* @author MCD Application Team
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_IRDA_H
#define STM32G4xx_HAL_IRDA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup IRDA
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup IRDA_Exported_Types IRDA Exported Types
* @{
*/
/**
* @brief IRDA Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the IRDA communication baud rate.
The baud rate register is computed using the following formula:
Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))
where usart_ker_ckpres is the IRDA input clock divided by a prescaler */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref IRDAEx_Word_Length */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref IRDA_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref IRDA_Transfer_Mode */
uint8_t Prescaler; /*!< Specifies the Prescaler value for dividing the UART/USART source clock
to achieve low-power frequency.
@note Prescaler value 0 is forbidden */
uint16_t PowerMode; /*!< Specifies the IRDA power mode.
This parameter can be a value of @ref IRDA_Low_Power */
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the IRDA clock source.
This parameter can be a value of @ref IRDA_ClockPrescaler. */
} IRDA_InitTypeDef;
/**
* @brief HAL IRDA State definition
* @note HAL IRDA State value is a combination of 2 different substates:
* gState and RxState (see @ref IRDA_State_Definition).
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (Peripheral busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 Peripheral initialization status
* 0 : Reset (Peripheral not initialized)
* 1 : Init done (Peripheral initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef uint32_t HAL_IRDA_StateTypeDef;
/**
* @brief IRDA clock sources definition
*/
typedef enum
{
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
IRDA_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */
IRDA_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */
} IRDA_ClockSourceTypeDef;
/**
* @brief IRDA handle Structure definition
*/
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
typedef struct __IRDA_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
{
USART_TypeDef *Instance; /*!< USART registers base address */
IRDA_InitTypeDef Init; /*!< IRDA communication parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */
uint16_t TxXferSize; /*!< IRDA Tx Transfer size */
__IO uint16_t TxXferCount; /*!< IRDA Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to IRDA Rx transfer Buffer */
uint16_t RxXferSize; /*!< IRDA Rx Transfer size */
__IO uint16_t RxXferCount; /*!< IRDA Rx Transfer Counter */
uint16_t Mask; /*!< USART RX RDR register mask */
DMA_HandleTypeDef *hdmatx; /*!< IRDA Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< IRDA Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_IRDA_StateTypeDef gState; /*!< IRDA state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO HAL_IRDA_StateTypeDef RxState; /*!< IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO uint32_t ErrorCode; /*!< IRDA Error code */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Half Complete Callback */
void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Half Complete Callback */
void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Rx Complete Callback */
void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Error Callback */
void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Complete Callback */
void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */
void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Receive Complete Callback */
void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp Init callback */
void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Msp DeInit callback */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
} IRDA_HandleTypeDef;
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/**
* @brief HAL IRDA Callback ID enumeration definition
*/
typedef enum
{
HAL_IRDA_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< IRDA Tx Half Complete Callback ID */
HAL_IRDA_TX_COMPLETE_CB_ID = 0x01U, /*!< IRDA Tx Complete Callback ID */
HAL_IRDA_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< IRDA Rx Half Complete Callback ID */
HAL_IRDA_RX_COMPLETE_CB_ID = 0x03U, /*!< IRDA Rx Complete Callback ID */
HAL_IRDA_ERROR_CB_ID = 0x04U, /*!< IRDA Error Callback ID */
HAL_IRDA_ABORT_COMPLETE_CB_ID = 0x05U, /*!< IRDA Abort Complete Callback ID */
HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< IRDA Abort Transmit Complete Callback ID */
HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< IRDA Abort Receive Complete Callback ID */
HAL_IRDA_MSPINIT_CB_ID = 0x08U, /*!< IRDA MspInit callback ID */
HAL_IRDA_MSPDEINIT_CB_ID = 0x09U /*!< IRDA MspDeInit callback ID */
} HAL_IRDA_CallbackIDTypeDef;
/**
* @brief HAL IRDA Callback pointer definition
*/
typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer to an IRDA callback function */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup IRDA_Exported_Constants IRDA Exported Constants
* @{
*/
/** @defgroup IRDA_State_Definition IRDA State Code Definition
* @{
*/
#define HAL_IRDA_STATE_RESET 0x00000000U /*!< Peripheral is not initialized
Value is allowed for gState and RxState */
#define HAL_IRDA_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
#define HAL_IRDA_STATE_BUSY 0x00000024U /*!< An internal process is ongoing
Value is allowed for gState only */
#define HAL_IRDA_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing
Value is allowed for gState only */
#define HAL_IRDA_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing
Value is allowed for RxState only */
#define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between
gState and RxState values */
#define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state
Value is allowed for gState only */
#define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error
Value is allowed for gState only */
/**
* @}
*/
/** @defgroup IRDA_Error_Definition IRDA Error Code Definition
* @{
*/
#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */
#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE 0x00000000U /*!< No parity */
#define IRDA_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
#define IRDA_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode
* @{
*/
#define IRDA_MODE_RX USART_CR1_RE /*!< RX mode */
#define IRDA_MODE_TX USART_CR1_TE /*!< TX mode */
#define IRDA_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
#define IRDA_POWERMODE_NORMAL 0x00000000U /*!< IRDA normal power mode */
#define IRDA_POWERMODE_LOWPOWER USART_CR3_IRLP /*!< IRDA low power mode */
/**
* @}
*/
/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
* @{
*/
#define IRDA_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
#define IRDA_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
#define IRDA_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
#define IRDA_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
#define IRDA_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
#define IRDA_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
#define IRDA_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
#define IRDA_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
#define IRDA_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
#define IRDA_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
#define IRDA_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
#define IRDA_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
/**
* @}
*/
/** @defgroup IRDA_State IRDA State
* @{
*/
#define IRDA_STATE_DISABLE 0x00000000U /*!< IRDA disabled */
#define IRDA_STATE_ENABLE USART_CR1_UE /*!< IRDA enabled */
/**
* @}
*/
/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
#define IRDA_MODE_DISABLE 0x00000000U /*!< Associated UART disabled in IRDA mode */
#define IRDA_MODE_ENABLE USART_CR3_IREN /*!< Associated UART enabled in IRDA mode */
/**
* @}
*/
/** @defgroup IRDA_One_Bit IRDA One Bit Sampling
* @{
*/
#define IRDA_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disabled */
#define IRDA_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enabled */
/**
* @}
*/
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
* @{
*/
#define IRDA_DMA_TX_DISABLE 0x00000000U /*!< IRDA DMA TX disabled */
#define IRDA_DMA_TX_ENABLE USART_CR3_DMAT /*!< IRDA DMA TX enabled */
/**
* @}
*/
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
* @{
*/
#define IRDA_DMA_RX_DISABLE 0x00000000U /*!< IRDA DMA RX disabled */
#define IRDA_DMA_RX_ENABLE USART_CR3_DMAR /*!< IRDA DMA RX enabled */
/**
* @}
*/
/** @defgroup IRDA_Request_Parameters IRDA Request Parameters
* @{
*/
#define IRDA_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */
#define IRDA_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
#define IRDA_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
/** @defgroup IRDA_Flags IRDA Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define IRDA_FLAG_REACK USART_ISR_REACK /*!< IRDA receive enable acknowledge flag */
#define IRDA_FLAG_TEACK USART_ISR_TEACK /*!< IRDA transmit enable acknowledge flag */
#define IRDA_FLAG_BUSY USART_ISR_BUSY /*!< IRDA busy flag */
#define IRDA_FLAG_ABRF USART_ISR_ABRF /*!< IRDA auto Baud rate flag */
#define IRDA_FLAG_ABRE USART_ISR_ABRE /*!< IRDA auto Baud rate error */
#define IRDA_FLAG_TXE USART_ISR_TXE_TXFNF /*!< IRDA transmit data register empty */
#define IRDA_FLAG_TC USART_ISR_TC /*!< IRDA transmission complete */
#define IRDA_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< IRDA read data register not empty */
#define IRDA_FLAG_ORE USART_ISR_ORE /*!< IRDA overrun error */
#define IRDA_FLAG_NE USART_ISR_NE /*!< IRDA noise error */
#define IRDA_FLAG_FE USART_ISR_FE /*!< IRDA frame error */
#define IRDA_FLAG_PE USART_ISR_PE /*!< IRDA parity error */
/**
* @}
*/
/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define IRDA_IT_PE 0x0028U /*!< IRDA Parity error interruption */
#define IRDA_IT_TXE 0x0727U /*!< IRDA Transmit data register empty interruption */
#define IRDA_IT_TC 0x0626U /*!< IRDA Transmission complete interruption */
#define IRDA_IT_RXNE 0x0525U /*!< IRDA Read data register not empty interruption */
#define IRDA_IT_IDLE 0x0424U /*!< IRDA Idle interruption */
/* Elements values convention: 000000000XXYYYYYb
- YYYYY : Interrupt source position in the XX register (5bits)
- XX : Interrupt source register (2bits)
- 01: CR1 register
- 10: CR2 register
- 11: CR3 register */
#define IRDA_IT_ERR 0x0060U /*!< IRDA Error interruption */
/* Elements values convention: 0000ZZZZ00000000b
- ZZZZ : Flag position in the ISR register(4bits) */
#define IRDA_IT_ORE 0x0300U /*!< IRDA Overrun error interruption */
#define IRDA_IT_NE 0x0200U /*!< IRDA Noise error interruption */
#define IRDA_IT_FE 0x0100U /*!< IRDA Frame error interruption */
/**
* @}
*/
/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags
* @{
*/
#define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define IRDA_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
#define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
/**
* @}
*/
/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask
* @{
*/
#define IRDA_IT_MASK 0x001FU /*!< IRDA Interruptions flags mask */
#define IRDA_CR_MASK 0x00E0U /*!< IRDA control register mask */
#define IRDA_CR_POS 5U /*!< IRDA control register position */
#define IRDA_ISR_MASK 0x1F00U /*!< IRDA ISR register mask */
#define IRDA_ISR_POS 8U /*!< IRDA ISR register position */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
* @{
*/
/** @brief Reset IRDA handle state.
* @param __HANDLE__ IRDA handle.
* @retval None
*/
#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_IRDA_STATE_RESET; \
(__HANDLE__)->RxState = HAL_IRDA_STATE_RESET; \
} while(0U)
#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS */
/** @brief Flush the IRDA DR register.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
} while(0U)
/** @brief Clear the specified IRDA pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref IRDA_CLEAR_PEF
* @arg @ref IRDA_CLEAR_FEF
* @arg @ref IRDA_CLEAR_NEF
* @arg @ref IRDA_CLEAR_OREF
* @arg @ref IRDA_CLEAR_TCF
* @arg @ref IRDA_CLEAR_IDLEF
* @retval None
*/
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the IRDA PE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
/** @brief Clear the IRDA FE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
/** @brief Clear the IRDA NE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
/** @brief Clear the IRDA ORE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
/** @brief Clear the IRDA IDLE pending flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
/** @brief Check whether the specified IRDA flag is set or not.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
* @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref IRDA_FLAG_BUSY Busy flag
* @arg @ref IRDA_FLAG_ABRF Auto Baud rate detection flag
* @arg @ref IRDA_FLAG_ABRE Auto Baud rate detection error flag
* @arg @ref IRDA_FLAG_TXE Transmit data register empty flag
* @arg @ref IRDA_FLAG_TC Transmission Complete flag
* @arg @ref IRDA_FLAG_RXNE Receive data register not empty flag
* @arg @ref IRDA_FLAG_ORE OverRun Error flag
* @arg @ref IRDA_FLAG_NE Noise Error flag
* @arg @ref IRDA_FLAG_FE Framing Error flag
* @arg @ref IRDA_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Enable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
((__HANDLE__)->Instance->CR1 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))):\
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
((__HANDLE__)->Instance->CR2 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))):\
((__HANDLE__)->Instance->CR3 |= (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \
((__HANDLE__)->Instance->CR1 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))): \
((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \
((__HANDLE__)->Instance->CR2 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << \
((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_ORE OverRun Error interrupt
* @arg @ref IRDA_IT_NE Noise Error interrupt
* @arg @ref IRDA_IT_FE Framing Error interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \
((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified IRDA interrupt source is enabled or not.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
* @arg @ref IRDA_IT_TC Transmission complete interrupt
* @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt
* @arg @ref IRDA_IT_IDLE Idle line detection interrupt
* @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt
* @arg @ref IRDA_IT_PE Parity Error interrupt
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \
& IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \
& (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
* @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag
* @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag
* @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag
* @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific IRDA request flag.
* @param __HANDLE__ specifies the IRDA Handle.
* @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
* @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
* @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
* @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request
* @retval None
*/
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the IRDA one bit sample method.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the IRDA one bit sample method.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
&= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART/USART associated to IRDA Handle.
* @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @addtogroup IRDA_Private_Macros
* @{
*/
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value.
* @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
* @retval True or False
*/
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
/** @brief Ensure that IRDA prescaler value is strictly larger than 0.
* @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
* @retval True or False
*/
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
/** @brief Ensure that IRDA frame parity is valid.
* @param __PARITY__ IRDA frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
*/
#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
((__PARITY__) == IRDA_PARITY_EVEN) || \
((__PARITY__) == IRDA_PARITY_ODD))
/** @brief Ensure that IRDA communication mode is valid.
* @param __MODE__ IRDA communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
& (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
/** @brief Ensure that IRDA power mode is valid.
* @param __MODE__ IRDA power mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
((__MODE__) == IRDA_POWERMODE_NORMAL))
/** @brief Ensure that IRDA clock Prescaler is valid.
* @param __CLOCKPRESCALER__ IRDA clock Prescaler value.
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
*/
#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
/** @brief Ensure that IRDA state is valid.
* @param __STATE__ IRDA state mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
((__STATE__) == IRDA_STATE_ENABLE))
/** @brief Ensure that IRDA associated UART/USART mode is valid.
* @param __MODE__ IRDA associated UART/USART mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_IRDA_MODE(__MODE__) (((__MODE__) == IRDA_MODE_DISABLE) || \
((__MODE__) == IRDA_MODE_ENABLE))
/** @brief Ensure that IRDA sampling rate is valid.
* @param __ONEBIT__ IRDA sampling rate.
* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
*/
#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))
/** @brief Ensure that IRDA DMA TX mode is valid.
* @param __DMATX__ IRDA DMA TX mode.
* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
*/
#define IS_IRDA_DMA_TX(__DMATX__) (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
((__DMATX__) == IRDA_DMA_TX_ENABLE))
/** @brief Ensure that IRDA DMA RX mode is valid.
* @param __DMARX__ IRDA DMA RX mode.
* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
*/
#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
((__DMARX__) == IRDA_DMA_RX_ENABLE))
/** @brief Ensure that IRDA request is valid.
* @param __PARAM__ IRDA request.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \
((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
/**
* @}
*/
/* Include IRDA HAL Extended module */
#include "stm32g4xx_hal_irda_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
* @{
*/
/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
pIRDA_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);
HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);
void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_IRDA_H */
| 42,906 | C | 47.048152 | 119 | 0.529879 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h | /**
******************************************************************************
* @file stm32g4xx_ll_dac.h
* @author MCD Application Team
* @brief Header file of DAC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_DAC_H
#define STM32G4xx_LL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
/** @defgroup DAC_LL DAC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DAC_LL_Private_Constants DAC Private Constants
* @{
*/
/* Internal masks for DAC channels definition */
/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR, STMODR */
/* - channel bits position into register SWTRIG */
/* - channel bits position into register SWTRIGB */
/* - channel register offset of data holding register DHRx */
/* - channel register offset of data output register DORx */
/* - channel register offset of sample-and-hold sample time register SHSRx */
/* - channel register offset of sawtooth register STRx */
#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
#define DAC_SWTRB_CH1 (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/
#define DAC_SWTRB_CH2 (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
#define DAC_SWTRB_CHX_MASK (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
DHR12Rx channel 1 (shifted left of 20 bits) */
#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
DHR12Rx channel 1 (shifted left of 24 bits) */
#define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus
DHR12Rx channel 1 (shifted left of 28 bits) */
#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
DHR12Rx channel 1 (shifted left of 20 bits) */
#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
DHR12Rx channel 1 (shifted left of 24 bits) */
#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
| DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
#define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus
DORx channel 2 (shifted left of 5 bits) */
#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
#define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */
#define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus
SHSRx channel 2 (shifted left of 6 bits) */
#define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
#define DAC_REG_STR1_REGOFFSET 0x00000000UL /* Register STRx channel 1 taken as reference */
#define DAC_REG_STR2_REGOFFSET 0x00000080UL /* Register offset of STRx channel 1 versus
STRx channel 2 (shifted left of 7 bits) */
#define DAC_REG_STRX_REGOFFSET_MASK (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
to position 0 */
#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
to position 0 */
#define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of STRx registers offset when shifted
to position 0 */
#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 28 bits) */
#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 20 bits) */
#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
channel 1 or 2 versus DHR12Rx channel 1
(shifted left of 24 bits) */
#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx
channel 1 or 2 versus DORx channel 1
(shifted left of 5 bits) */
#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx
channel 1 or 2 versus SHSRx channel 1
(shifted left of 6 bits) */
#define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS 7UL /* Position of bits register offset of STRx
channel 1 or 2 versus STRx channel 1
(shifted left of 7 bits) */
/* DAC registers bits positions */
#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
/* Miscellaneous data */
#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
bits (voltage range determined by analog voltage
references Vref+ and Vref-, refer to reference manual) */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DAC_LL_Private_Macros DAC Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
* @retval Pointer to register address
*/
#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of DAC instance.
*/
typedef struct
{
uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel:
internal (SW start) or from external peripheral
(timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetTriggerSource().
@note If waveform automatic generation mode is set to sawtooth,
this parameter is used as sawtooth RESET trigger */
uint32_t TriggerSource2; /*!< Set the conversion secondary trigger source for the selected DAC channel:
internal (SW start) or from external peripheral
(timer event, external interrupt line).
This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetTriggerSource2().
@note If waveform automatic generation mode is set to sawtooth,
this parameter is used as sawtooth step trigger */
uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetWaveAutoGeneration(). */
uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel.
If waveform automatic generation mode is set to noise, this parameter
can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
If waveform automatic generation mode is set to triangle,
this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
If waveform automatic generation mode is set to sawtooth, this parameter
host the sawtooth configuration: polarity, reset data, increment data.
Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to set this parameter value.
@note If waveform automatic generation mode is disabled,
this parameter is discarded.
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetWaveNoiseLFSR(),
@ref LL_DAC_SetWaveTriangleAmplitude(),
@ref LL_DAC_SetWaveSawtoothPolarity(),
@ref LL_DAC_SetWaveSawtoothResetData()
or @ref LL_DAC_SetWaveSawtoothStepData(),
depending on the wave automatic generation selected. */
uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetOutputBuffer(). */
uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel.
This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetOutputConnection(). */
uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC
channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
This feature can be modified afterwards using unitary
function @ref LL_DAC_SetOutputMode(). */
} LL_DAC_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
* @brief Flags defines which can be used with LL_DAC_ReadReg function
* @{
*/
/* DAC channel 1 flags */
#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */
#define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
#define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */
#define LL_DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY) /*!< DAC channel 1 flag ready */
#define LL_DAC_FLAG_DORSTAT1 (DAC_SR_DORSTAT1) /*!< DAC channel 1 flag output register */
/* DAC channel 2 flags */
#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */
#define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
#define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */
#define LL_DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY) /*!< DAC channel 2 flag ready */
#define LL_DAC_FLAG_DORSTAT2 (DAC_SR_DORSTAT2) /*!< DAC channel 2 flag output register */
/**
* @}
*/
/** @defgroup DAC_LL_EC_IT DAC interruptions
* @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions
* @{
*/
#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
/**
* @}
*/
/** @defgroup DAC_LL_EC_CHANNEL DAC channels
* @{
*/
#define LL_DAC_CHANNEL_1 (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1) /*!< DAC channel 1 */
#define LL_DAC_CHANNEL_2 (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2) /*!< DAC channel 2 */
/**
* @}
*/
/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
* @brief High frequency interface mode defines that can be used
* with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
* @{
*/
#define LL_DAC_HIGH_FREQ_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
#define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
* @{
*/
#define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */
#define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */
/**
* @}
*/
/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
* @{
*/
#define LL_DAC_TRIG_SOFTWARE 0x00000000UL /*!< DAC (all) channel conversion trigger internal (SW start) */
#define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: TIM1 TRGO. */
#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO. */
#define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM15 TRGO. */
#define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM2 TRGO. */
#define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM4 TRGO. */
#define LL_DAC_TRIG_EXT_EXTI_LINE9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger */
#define LL_DAC_TRIG_EXT_EXTI_LINE10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */
#define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM6 TRGO. */
#define LL_DAC_TRIG_EXT_TIM3_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM3 TRGO. */
#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
#define LL_DAC_TRIG_EXT_HRTIM_TRGO3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
* @{
*/
#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */
#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
#define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated sawtooth waveform. */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
* @{
*/
#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
/**
* @}
*/
/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
* @{
*/
#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
/**
* @}
*/
/** @defgroup DAC_LL_EC_SAWTOOTH_POLARITY_MODE DAC wave generation - Sawtooth polarity mode
* @{
*/
#define LL_DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */
#define LL_DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
* @{
*/
#define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */
#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
* @{
*/
#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
/**
* @}
*/
/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
* @{
*/
#define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */
#define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
/**
* @}
*/
/** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
* @{
*/
#define LL_DAC_SIGNED_FORMAT_DISABLE 0x00000000UL /*!< The selected DAC channel data format is not signed */
#define LL_DAC_SIGNED_FORMAT_ENABLE (DAC_MCR_SINFORMAT1) /*!< The selected DAC channel data format is signed */
/**
* @}
*/
/** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution
* @{
*/
#define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */
#define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */
/**
* @}
*/
/** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose
* @{
*/
/* List of DAC registers intended to be used (most commonly) with */
/* DMA transfer. */
/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */
/**
* @}
*/
/** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays
* @note Only DAC peripheral HW delays are defined in DAC LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for DAC channel voltage settling time from DAC channel startup */
/* (transition from disable to enable). */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
/* The delay below is specified under conditions: */
/* - voltage maximum transition (lowest to highest value) */
/* - until voltage reaches final value +-1LSB */
/* - DAC channel output buffer enabled */
/* - load impedance of 5kOhm (min), 50pF (max) */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Delay for DAC channel voltage settling time. */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
/* The delay below is specified under conditions: */
/* - voltage maximum transition (lowest to highest value) */
/* - until voltage reaches final value +-1LSB */
/* - DAC channel output buffer enabled */
/* - load impedance of 5kOhm min, 50pF max */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSETTLING"). */
/* Unit: us */
#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
* @{
*/
/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
* @{
*/
/**
* @brief Write a value in DAC register
* @param __INSTANCE__ DAC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in DAC register
* @param __INSTANCE__ DAC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
* @{
*/
/**
* @brief Helper macro to get DAC channel number in decimal format
* from literals LL_DAC_CHANNEL_x.
* Example:
* __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
* will return decimal number "1".
* @note The input can be a value from functions where a channel
* number is returned.
* @param __CHANNEL__ This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval 1...2
*/
#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
((__CHANNEL__) & DAC_SWTR_CHX_MASK)
/**
* @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
* from number in decimal format.
* Example:
* __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
* will return a data equivalent to "LL_DAC_CHANNEL_1".
* @note If the input parameter does not correspond to a DAC channel,
* this macro returns value '0'.
* @param __DECIMAL_NB__ 1...2
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
*/
#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
(((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
/**
* @brief Helper macro to define the DAC conversion data full-scale digital
* value corresponding to the selected DAC resolution.
* @note DAC conversion data full-scale corresponds to voltage range
* determined by analog voltage references Vref+ and Vref-
* (refer to reference manual).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_DAC_RESOLUTION_12B
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval ADC conversion data equivalent voltage value (unit: mVolt)
*/
#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
/**
* @brief Helper macro to calculate the DAC conversion data (unit: digital
* value) corresponding to a voltage (unit: mVolt).
* @note This helper macro is intended to provide input data in voltage
* rather than digital value,
* to be used with LL DAC functions such as
* @ref LL_DAC_ConvertData12RightAligned().
* @note Analog reference voltage (Vref+) must be either known from
* user board environment or can be calculated using ADC measurement
* and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
* @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
* @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel
* (unit: mVolt).
* @param __DAC_RESOLUTION__ This parameter can be one of the following values:
* @arg @ref LL_DAC_RESOLUTION_12B
* @arg @ref LL_DAC_RESOLUTION_8B
* @retval DAC conversion data (unit: digital value)
*/
#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\
__DAC_VOLTAGE__,\
__DAC_RESOLUTION__) \
((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
/ (__VREFANALOG_VOLTAGE__) \
)
/**
* @brief Helper macro to format sawtooth wave generation configuration
* value to be filled into WaveAutoGenerationConfig parameter of @ref LL_DAC_InitTypeDef.
* @note This helper will format information to fit in DAC_STRx register.
* @param __POLARITY__ sawtooth wave polarity (must be value of @ref DAC_LL_EC_SAWTOOTH_POLARITY_MODE)
* @param __RESET_DATA__ sawtooth reset data.
* @param __STEP_DATA__ sawtooth step data
* @retval Sawtooth configuration organized in DAC_STRx compatible format.
*/
#define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__,\
__RESET_DATA__,\
__STEP_DATA__) \
( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk) \
| ((__POLARITY__) & DAC_STR1_STDIR1_Msk) \
| (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk) \
)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
* @{
*/
/** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
* @{
*/
/**
* @brief Set the high frequency interface mode for the selected DAC instance
* @rmtoll MCR HFSEL LL_DAC_SetHighFrequencyMode
* @param DACx DAC instance
* @param HighFreqMode This parameter can be one of the following values:
* @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
{
MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
}
/**
* @brief Get the high frequency interface mode for the selected DAC instance
* @rmtoll MCR HFSEL LL_DAC_GetHighFrequencyMode
* @param DACx DAC instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
* @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
*/
__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(DAC_TypeDef *DACx)
{
return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
* @{
*/
/**
* @brief Set the operating mode for the selected DAC channel:
* calibration or normal operating mode.
* @rmtoll CR CEN1 LL_DAC_SetMode\n
* CR CEN2 LL_DAC_SetMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param ChannelMode This parameter can be one of the following values:
* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
* @arg @ref LL_DAC_MODE_CALIBRATION
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
{
MODIFY_REG(DACx->CR,
DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the operating mode for the selected DAC channel:
* calibration or normal operating mode.
* @rmtoll CR CEN1 LL_DAC_GetMode\n
* CR CEN2 LL_DAC_GetMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_MODE_NORMAL_OPERATION
* @arg @ref LL_DAC_MODE_CALIBRATION
*/
__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the offset trimming value for the selected DAC channel.
* Trimming has an impact when output buffer is enabled
* and is intended to replace factory calibration default values.
* @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n
* CCR OTRIM2 LL_DAC_SetTrimmingValue
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
{
MODIFY_REG(DACx->CCR,
DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the offset trimming value for the selected DAC channel.
* Trimming has an impact when output buffer is enabled
* and is intended to replace factory calibration default values.
* @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n
* CCR OTRIM2 LL_DAC_GetTrimmingValue
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
*/
__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the conversion trigger source for the selected DAC channel.
* @note For conversion trigger source to be effective, DAC trigger
* must be enabled using function @ref LL_DAC_EnableTrigger().
* @note To set conversion trigger source, DAC channel must be disabled.
* Otherwise, the setting is discarded.
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n
* CR TSEL2 LL_DAC_SetTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
*
* (1) On this STM32 series, parameter only available on DAC3.
* (2) On this STM32 series, parameter only available on DAC1/2/4.
* (3) On this STM32 series, parameter only available on DAC1&4.
* (4) On this STM32 series, parameter only available on DAC2.
* Refer to device datasheet for DACx instances availability.
* (5) On this STM32 series, parameter not available on all devices.
* Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
{
MODIFY_REG(DACx->CR,
DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the conversion trigger source for the selected DAC channel.
* @note For conversion trigger source to be effective, DAC trigger
* must be enabled using function @ref LL_DAC_EnableTrigger().
* @note Availability of parameters of trigger sources from timer
* depends on timers availability on the selected device.
* @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n
* CR TSEL2 LL_DAC_GetTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
*
* (1) On this STM32 series, parameter only available on DAC3.
* (2) On this STM32 series, parameter only available on DAC1/2/4.
* (3) On this STM32 series, parameter only available on DAC1&4.
* (4) On this STM32 series, parameter only available on DAC2.
* Refer to device datasheet for DACx instances availability.
* (5) On this STM32 series, parameter not available on all devices.
* Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
*/
__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the waveform automatic generation mode
* for the selected DAC channel.
* @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n
* CR WAVE2 LL_DAC_SetWaveAutoGeneration
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param WaveAutoGeneration This parameter can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
{
MODIFY_REG(DACx->CR,
DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the waveform automatic generation mode
* for the selected DAC channel.
* @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n
* CR WAVE2 LL_DAC_GetWaveAutoGeneration
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
* @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register).
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_SetWaveNoiseLFSR
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param NoiseLFSRMask This parameter can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
{
MODIFY_REG(DACx->CR,
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the noise waveform generation for the selected DAC channel:
* Noise mode and parameters LFSR (linear feedback shift register).
* @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n
* CR MAMP2 LL_DAC_GetWaveNoiseLFSR
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
* @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude.
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_SetWaveTriangleAmplitude
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param TriangleAmplitude This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
uint32_t TriangleAmplitude)
{
MODIFY_REG(DACx->CR,
DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the triangle waveform generation for the selected DAC channel:
* triangle mode and amplitude.
* @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n
* CR MAMP2 LL_DAC_GetWaveTriangleAmplitude
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
* @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the swatooth waveform generation polarity.
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll STR1 STDIR1 LL_DAC_SetWaveSawtoothPolarity\n
* STR2 STDIR2 LL_DAC_SetWaveSawtoothPolarity
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
* @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_STR1_STDIR1,
Polarity);
}
/**
* @brief Get the sawtooth waveform generation polarity.
* @rmtoll STR1 STDIR1 LL_DAC_GetWaveSawtoothPolarity\n
* STR2 STDIR2 LL_DAC_GetWaveSawtoothPolarity
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
* @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t) READ_BIT(*preg, DAC_STR1_STDIR1);
}
/**
* @brief Set the swatooth waveform generation reset data.
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll STR1 STRSTDATA1 LL_DAC_SetWaveSawtoothResetData\n
* STR2 STRSTDATA2 LL_DAC_SetWaveSawtoothResetData
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param ResetData This parameter is the sawtooth reset value.
* Range is from 0 to DAC full range 4095 (0xFFF)
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_STR1_STRSTDATA1,
ResetData << DAC_STR1_STRSTDATA1_Pos);
}
/**
* @brief Get the sawtooth waveform generation reset data.
* @rmtoll STR1 STRSTDATA1 LL_DAC_GetWaveSawtoothResetData\n
* STR2 STRSTDATA2 LL_DAC_GetWaveSawtoothResetData
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value is the sawtooth reset value.
* Range is from 0 to DAC full range 4095 (0xFFF)
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t)(READ_BIT(*preg, DAC_STR1_STRSTDATA1) >> DAC_STR1_STRSTDATA1_Pos);
}
/**
* @brief Set the swatooth waveform generation step data.
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll STR1 STINCDATA1 LL_DAC_SetWaveSawtoothStepData\n
* STR2 STINCDATA2 LL_DAC_SetWaveSawtoothStepData
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param StepData This parameter is the sawtooth step value.
* 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
* Step value step is 1/16 = 0.0625
* Step value range is 0.0000 to 4095.9375 (0xFFF.F)
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg,
DAC_STR1_STINCDATA1,
StepData << DAC_STR1_STINCDATA1_Pos);
}
/**
* @brief Get the sawtooth waveform generation step data.
* @rmtoll STR1 STINCDATA1 LL_DAC_GetWaveSawtoothStepData\n
* STR2 STINCDATA2 LL_DAC_GetWaveSawtoothStepData
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value is the sawtooth step value.
* 12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
* Step value step is 1/16 = 0.0625
* Step value range is 0.0000 to 4095.9375 (0xFFF.F)
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1, (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t)(READ_BIT(*preg, DAC_STR1_STINCDATA1) >> DAC_STR1_STINCDATA1_Pos);
}
/**
* @brief Set the swatooth waveform generation reset trigger source.
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll STMODR STRSTTRIGSEL1 LL_DAC_SetWaveSawtoothResetTriggerSource\n
* STMODR STRSTTRIGSEL2 LL_DAC_SetWaveSawtoothResetTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
*
* (1) On this STM32 series, parameter only available on DAC3.
* (2) On this STM32 series, parameter only available on DAC1/2/4.
* (3) On this STM32 series, parameter only available on DAC1&4.
* (4) On this STM32 series, parameter only available on DAC2.
* Refer to device datasheet for DACx instances availability.
* (5) On this STM32 series, parameter not available on all devices.
* Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
uint32_t TriggerSource)
{
MODIFY_REG(DACx->STMODR,
DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the sawtooth waveform generation reset trigger source.
* @rmtoll STMODR STRSTTRIGSEL1 LL_DAC_GetWaveSawtoothResetTriggerSource\n
* STMODR STRSTTRIGSEL2 LL_DAC_GetWaveSawtoothResetTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6 (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (3) (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (4) (5)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3 (1) (5)
*
* (1) On this STM32 series, parameter only available on DAC3.
* (2) On this STM32 series, parameter only available on DAC1/2/4.
* (3) On this STM32 series, parameter only available on DAC1&4.
* (4) On this STM32 series, parameter only available on DAC2.
* Refer to device datasheet for DACx instances availability.
* (5) On this STM32 series, parameter not available on all devices.
* Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)((READ_BIT(DACx->STMODR,
DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
)
>> (DAC_STMODR_STRSTTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
) << DAC_CR_TSEL1_Pos);
}
/**
* @brief Set the swatooth waveform generation step trigger source.
* @note For wave generation to be effective, DAC channel
* wave generation mode must be enabled using
* function @ref LL_DAC_SetWaveAutoGeneration().
* @note This setting can be set when the selected DAC channel is disabled
* (otherwise, the setting operation is ignored).
* @rmtoll STMODR STINCTRIGSEL1 LL_DAC_SetWaveSawtoothStepTriggerSource\n
* STMODR STINCTRIGSEL2 LL_DAC_SetWaveSawtoothStepTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param TriggerSource This parameter can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
*
* (1) On this STM32 series, parameter only available on DAC3.
* (2) On this STM32 series, parameter only available on DAC1/2/4.
* Refer to device datasheet for DACx instances availability.
* (3) On this STM32 series, parameter not available on all devices.
* Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
uint32_t TriggerSource)
{
MODIFY_REG(DACx->STMODR,
DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the sawtooth waveform generation step trigger source.
* @rmtoll STMODR STINCTRIGSEL1 LL_DAC_GetWaveSawtoothStepTriggerSource\n
* STMODR STINCTRIGSEL2 LL_DAC_GetWaveSawtoothStepTriggerSource
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_TRIG_SOFTWARE
* @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO (1)
* @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO (2)
* @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
* @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
* @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
* @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5 (3)
* @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6 (3)
*
* (1) On this STM32 series, parameter only available on DAC3.
* (2) On this STM32 series, parameter only available on DAC1/2/4.
* Refer to device datasheet for DACx instances availability.
* (3) On this STM32 series, parameter not available on all devices.
* Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
*/
__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)((READ_BIT(DACx->STMODR,
DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
)
>> (DAC_STMODR_STINCTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
) << DAC_CR_TSEL1_Pos);
}
/**
* @brief Set the output for the selected DAC channel.
* @note This function set several features:
* - mode normal or sample-and-hold
* - buffer
* - connection to GPIO or internal path.
* These features can also be set individually using
* dedicated functions:
* - @ref LL_DAC_SetOutputBuffer()
* - @ref LL_DAC_SetOutputMode()
* - @ref LL_DAC_SetOutputConnection()
* @note On this STM32 series, output connection depends on output mode
* (normal or sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
* output connection is also connected to GPIO pin
* (both connections to GPIO pin and internal path).
* - if output connection is set to GPIO pin, output buffer
* is disabled, output mode set to sample and hold:
* output connection is also connected to internal path
* (both connections to GPIO pin and internal path).
* @note Mode sample-and-hold requires an external capacitor
* to be connected between DAC channel output and ground.
* Capacitor value depends on load on DAC channel output and
* sample-and-hold timings configured.
* As indication, capacitor typical value is 100nF
* (refer to device datasheet, parameter "CSH").
* @rmtoll CR MODE1 LL_DAC_ConfigOutput\n
* CR MODE2 LL_DAC_ConfigOutput
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param OutputMode This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
* @param OutputBuffer This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
* @param OutputConnection This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
uint32_t OutputBuffer, uint32_t OutputConnection)
{
MODIFY_REG(DACx->MCR,
(DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
(OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Set the output mode normal or sample-and-hold
* for the selected DAC channel.
* @note Mode sample-and-hold requires an external capacitor
* to be connected between DAC channel output and ground.
* Capacitor value depends on load on DAC channel output and
* sample-and-hold timings configured.
* As indication, capacitor typical value is 100nF
* (refer to device datasheet, parameter "CSH").
* @rmtoll CR MODE1 LL_DAC_SetOutputMode\n
* CR MODE2 LL_DAC_SetOutputMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param OutputMode This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
{
MODIFY_REG(DACx->MCR,
(uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the output mode normal or sample-and-hold for the selected DAC channel.
* @rmtoll CR MODE1 LL_DAC_GetOutputMode\n
* CR MODE2 LL_DAC_GetOutputMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
* @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
*/
__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the output buffer for the selected DAC channel.
* @note On this STM32 series, when buffer is enabled, its offset can be
* trimmed: factory calibration default values can be
* replaced by user trimming values, using function
* @ref LL_DAC_SetTrimmingValue().
* @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n
* CR MODE2 LL_DAC_SetOutputBuffer
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param OutputBuffer This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
{
MODIFY_REG(DACx->MCR,
(uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the output buffer state for the selected DAC channel.
* @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n
* CR MODE2 LL_DAC_GetOutputBuffer
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
* @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
*/
__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the output connection for the selected DAC channel.
* @note On this STM32 series, output connection depends on output mode (normal or
* sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
* output connection is also connected to GPIO pin
* (both connections to GPIO pin and internal path).
* - if output connection is set to GPIO pin, output buffer
* is disabled, output mode set to sample and hold:
* output connection is also connected to internal path
* (both connections to GPIO pin and internal path).
* @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n
* CR MODE2 LL_DAC_SetOutputConnection
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param OutputConnection This parameter can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
{
MODIFY_REG(DACx->MCR,
(uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the output connection for the selected DAC channel.
* @note On this STM32 series, output connection depends on output mode (normal or
* sample and hold) and output buffer state.
* - if output connection is set to internal path and output buffer
* is enabled (whatever output mode):
* output connection is also connected to GPIO pin
* (both connections to GPIO pin and internal path).
* - if output connection is set to GPIO pin, output buffer
* is disabled, output mode set to sample and hold:
* output connection is also connected to internal path
* (both connections to GPIO pin and internal path).
* @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n
* CR MODE2 LL_DAC_GetOutputConnection
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
* @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
*/
__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the sample-and-hold timing for the selected DAC channel:
* sample time
* @note Sample time must be set when DAC channel is disabled
* or during DAC operation when DAC channel flag BWSTx is reset,
* otherwise the setting is ignored.
* Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
* @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n
* SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
}
/**
* @brief Get the sample-and-hold timing for the selected DAC channel:
* sample time
* @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n
* SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
}
/**
* @brief Set the sample-and-hold timing for the selected DAC channel:
* hold time
* @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n
* SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
{
MODIFY_REG(DACx->SHHR,
DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the sample-and-hold timing for the selected DAC channel:
* hold time
* @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n
* SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Value between Min_Data=0x000 and Max_Data=0x3FF
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the sample-and-hold timing for the selected DAC channel:
* refresh time
* @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n
* SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
{
MODIFY_REG(DACx->SHRR,
DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the sample-and-hold timing for the selected DAC channel:
* refresh time
* @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n
* SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @brief Set the signed format for the selected DAC channel.
* @note On this STM32 series, signed format can be used to inject
* Q1.15, Q1.11, Q1.7 signed format data to DAC.
* Ex when using 12bits data format (Q1.11 is used):
* 0x800 will output 0v level
* 0xFFF will output mid-scale level
* 0x000 will output mid-scale level
* 0x7FF will output full-scale level
* @rmtoll MCR SINFORMAT1 LL_DAC_SetSignedFormat\n
* MCR SINFORMAT2 LL_DAC_SetSignedFormat
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param SignedFormat This parameter can be one of the following values:
* @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
* @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
{
MODIFY_REG(DACx->MCR,
DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get the signed format state for the selected DAC channel.
* @rmtoll MCR SINFORMAT1 LL_DAC_GetSignedFormat\n
* MCR SINFORMAT2 LL_DAC_GetSignedFormat
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Returned value can be one of the following values:
* @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
* @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
*/
__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
>> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
);
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable DAC DMA transfer request of the selected channel.
* @note To configure DMA source address (peripheral address),
* use function @ref LL_DAC_DMA_GetRegAddr().
* @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n
* CR DMAEN2 LL_DAC_EnableDMAReq
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC DMA transfer request of the selected channel.
* @note To configure DMA source address (peripheral address),
* use function @ref LL_DAC_DMA_GetRegAddr().
* @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n
* CR DMAEN2 LL_DAC_DisableDMAReq
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC DMA transfer request state of the selected channel.
* (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
* @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n
* CR DMAEN2 LL_DAC_IsDMAReqEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Enable DAC DMA Double data mode of the selected channel.
* @rmtoll MCR DMADOUBLE1 LL_DAC_EnableDMADoubleDataMode\n
* MCR DMADOUBLE2 LL_DAC_EnableDMADoubleDataMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->MCR,
DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC DMA Double data mode of the selected channel.
* @rmtoll MCR DMADOUBLE1 LL_DAC_DisableDMADoubleDataMode\n
* MCR DMADOUBLE2 LL_DAC_DisableDMADoubleDataMode
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->MCR,
DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC DMA double data mode state of the selected channel.
* (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
* @rmtoll MCR DMADOUBLE1 LL_DAC_IsDMADoubleDataModeEnabled\n
* MCR DMADOUBLE2 LL_DAC_IsDMADoubleDataModeEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->MCR,
DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Function to help to configure DMA transfer to DAC: retrieve the
* DAC register address from DAC instance and a list of DAC registers
* intended to be used (most commonly) with DMA transfer.
* @note These DAC registers are data holding registers:
* when DAC conversion is requested, DAC generates a DMA transfer
* request to have data available in DAC data holding registers.
* @note This macro is intended to be used with LL DMA driver, refer to
* function "LL_DMA_ConfigAddresses()".
* Example:
* LL_DMA_ConfigAddresses(DMA1,
* LL_DMA_CHANNEL_1,
* (uint32_t)&< array or variable >,
* LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
* LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
* LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
* @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n
* DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
* DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n
* DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param Register This parameter can be one of the following values:
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
* @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
* @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
* @retval DAC register address
*/
__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
{
/* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
/* DAC channel selected. */
return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
* @{
*/
/**
* @brief Enable DAC selected channel.
* @rmtoll CR EN1 LL_DAC_Enable\n
* CR EN2 LL_DAC_Enable
* @note After enable from off state, DAC channel requires a delay
* for output voltage to reach accuracy +/- 1 LSB.
* Refer to device datasheet, parameter "tWAKEUP".
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC selected channel.
* @rmtoll CR EN1 LL_DAC_Disable\n
* CR EN2 LL_DAC_Disable
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC enable state of the selected channel.
* (0: DAC channel is disabled, 1: DAC channel is enabled)
* @rmtoll CR EN1 LL_DAC_IsEnabled\n
* CR EN2 LL_DAC_IsEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Get DAC ready for conversion state of the selected channel.
* (0: DAC channel is not ready, 1: DAC channel is ready)
* @rmtoll SR DAC1RDY LL_DAC_IsReady\n
* SR DAC2RDY LL_DAC_IsReady
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsReady(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->SR,
DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Enable DAC trigger of the selected channel.
* @note - If DAC trigger is disabled, DAC conversion is performed
* automatically once the data holding register is updated,
* using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
* @ref LL_DAC_ConvertData12RightAligned(), ...
* - If DAC trigger is enabled, DAC conversion is performed
* only when a hardware of software trigger event is occurring.
* Select trigger source using
* function @ref LL_DAC_SetTriggerSource().
* @rmtoll CR TEN1 LL_DAC_EnableTrigger\n
* CR TEN2 LL_DAC_EnableTrigger
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Disable DAC trigger of the selected channel.
* @rmtoll CR TEN1 LL_DAC_DisableTrigger\n
* CR TEN2 LL_DAC_DisableTrigger
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
CLEAR_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
}
/**
* @brief Get DAC trigger state of the selected channel.
* (0: DAC trigger is disabled, 1: DAC trigger is enabled)
* @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n
* CR TEN2 LL_DAC_IsTriggerEnabled
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
return ((READ_BIT(DACx->CR,
DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
== (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
}
/**
* @brief Trig DAC conversion by software for the selected DAC channel.
* @note Preliminarily, DAC trigger must be set to software trigger
* using function
* @ref LL_DAC_Init()
* @ref LL_DAC_SetTriggerSource()
* @ref LL_DAC_SetWaveSawtoothResetTriggerSource() (1)
* with parameter "LL_DAC_TRIGGER_SOFTWARE".
* and DAC trigger must be enabled using
* function @ref LL_DAC_EnableTrigger().
*
* (1) In case, Sawtooth wave generation has been configured.
* @note For devices featuring DAC with 2 channels: this function
* can perform a SW start of both DAC channels simultaneously.
* Two channels can be selected as parameter.
* Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
* @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n
* SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion
* @param DACx DAC instance
* @param DAC_Channel This parameter can a combination of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->SWTRIGR,
(DAC_Channel & DAC_SWTR_CHX_MASK));
}
/**
* @brief Trig DAC conversion by secondary software trigger for the selected DAC channel.
* @note Preliminarily, DAC secondary trigger must be set to software trigger
* using function
* @ref LL_DAC_Init()
* @ref LL_DAC_SetWaveSawtoothStepTriggerSource() (1)
* with parameter "LL_DAC_TRIGGER_SOFTWARE".
* and DAC trigger must be enabled using
* function @ref LL_DAC_EnableTrigger().
*
* (1) In case, Sawtooth wave generation has been configured.
* @note For devices featuring DAC with 2 channels: this function
* can perform a SW start of both DAC channels simultaneously.
* Two channels can be selected as parameter.
* Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
* @rmtoll SWTRIGR SWTRIGB1 LL_DAC_TrigSWConversion2\n
* SWTRIGR SWTRIGB2 LL_DAC_TrigSWConversion2
* @param DACx DAC instance
* @param DAC_Channel This parameter can a combination of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
__STATIC_INLINE void LL_DAC_TrigSWConversion2(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
SET_BIT(DACx->SWTRIGR,
(DAC_Channel & DAC_SWTRB_CHX_MASK));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (LSB aligned on bit 0),
* for the selected DAC channel.
* @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n
* DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (MSB aligned on bit 15),
* for the selected DAC channel.
* @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n
* DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 8 bits left alignment (LSB aligned on bit 0),
* for the selected DAC channel.
* @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n
* DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
{
__IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (LSB aligned on bit 0),
* for both DAC channels.
* @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n
* DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR12RD,
(DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 12 bits left alignment (MSB aligned on bit 15),
* for both DAC channels.
* @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n
* DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
* @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
/* Note: Data of DAC channel 2 shift value subtracted of 4 because */
/* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
/* the 4 LSB must be taken into account for the shift value. */
MODIFY_REG(DACx->DHR12LD,
(DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
}
/**
* @brief Set the data to be loaded in the data holding register
* in format 8 bits left alignment (LSB aligned on bit 0),
* for both DAC channels.
* @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n
* DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned
* @param DACx DAC instance
* @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
* @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
uint32_t DataChannel2)
{
MODIFY_REG(DACx->DHR8RD,
(DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
}
/**
* @brief Retrieve output data currently generated for the selected DAC channel.
* @note Whatever alignment and resolution settings
* (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
* @ref LL_DAC_ConvertData12RightAligned(), ...),
* output data format is 12 bits right aligned (LSB aligned on bit 0).
* @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n
* DOR2 DACC2DOR LL_DAC_RetrieveOutputData
* @param DACx DAC instance
* @param DAC_Channel This parameter can be one of the following values:
* @arg @ref LL_DAC_CHANNEL_1
* @arg @ref LL_DAC_CHANNEL_2 (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)
{
__IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
& DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Get DAC calibration offset flag for DAC channel 1
* @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
}
/**
* @brief Get DAC calibration offset flag for DAC channel 2
* @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
}
/**
* @brief Get DAC busy writing sample time flag for DAC channel 1
* @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
}
/**
* @brief Get DAC busy writing sample time flag for DAC channel 2
* @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
}
/**
* @brief Get DAC ready status flag for DAC channel 1
* @rmtoll SR DAC1RDY LL_DAC_IsActiveFlag_DAC1RDY
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
}
/**
* @brief Get DAC ready status flag for DAC channel 2
* @rmtoll SR DAC2RDY LL_DAC_IsActiveFlag_DAC2RDY
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
}
/**
* @brief Get DAC output register status flag for DAC channel 1
* @rmtoll SR DORSTAT1 LL_DAC_IsActiveFlag_DORSTAT1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
}
/**
* @brief Get DAC output register status flag for DAC channel 2
* @rmtoll SR DORSTAT2 LL_DAC_IsActiveFlag_DORSTAT2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
}
/**
* @brief Get DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
}
/**
* @brief Get DAC underrun flag for DAC channel 2
* @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
}
/**
* @brief Clear DAC underrun flag for DAC channel 1
* @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
{
WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
}
/**
* @brief Clear DAC underrun flag for DAC channel 2
* @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
{
WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
}
/**
* @}
*/
/** @defgroup DAC_LL_EF_IT_Management IT management
* @{
*/
/**
* @brief Enable DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
{
SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
}
/**
* @brief Enable DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
{
SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
}
/**
* @brief Disable DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
{
CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
}
/**
* @brief Disable DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2
* @param DACx DAC instance
* @retval None
*/
__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
{
CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
}
/**
* @brief Get DMA underrun interrupt for DAC channel 1
* @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
}
/**
* @brief Get DMA underrun interrupt for DAC channel 2
* @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2
* @param DACx DAC instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)
{
return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);
ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);
void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_DAC_H */
| 134,938 | C | 49.614779 | 460 | 0.606493 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart.h | /**
******************************************************************************
* @file stm32g4xx_hal_usart.h
* @author MCD Application Team
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_USART_H
#define STM32G4xx_HAL_USART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup USART
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup USART_Exported_Types USART Exported Types
* @{
*/
/**
* @brief USART Init Structure definition
*/
typedef struct
{
uint32_t BaudRate; /*!< This member configures the Usart communication baud rate.
The baud rate is computed using the following formula:
Baud Rate Register[15:4] = ((2 * fclk_pres) /
((huart->Init.BaudRate)))[15:4]
Baud Rate Register[3] = 0
Baud Rate Register[2:0] = (((2 * fclk_pres) /
((huart->Init.BaudRate)))[3:0]) >> 1
where fclk_pres is the USART input clock frequency (fclk)
divided by a prescaler.
@note Oversampling by 8 is systematically applied to
achieve high baud rates. */
uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USARTEx_Word_Length. */
uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits. */
uint32_t Parity; /*!< Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode. */
uint32_t CLKPolarity; /*!< Specifies the steady state of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity. */
uint32_t CLKPhase; /*!< Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase. */
uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit. */
uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the USART clock source.
This parameter can be a value of @ref USART_ClockPrescaler. */
} USART_InitTypeDef;
/**
* @brief HAL USART State structures definition
*/
typedef enum
{
HAL_USART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized */
HAL_USART_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_USART_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_USART_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
HAL_USART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_USART_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission Reception process is ongoing */
HAL_USART_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_USART_STATE_ERROR = 0x04U /*!< Error */
} HAL_USART_StateTypeDef;
/**
* @brief USART clock sources definitions
*/
typedef enum
{
USART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
USART_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
USART_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
USART_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
USART_CLOCKSOURCE_LSE = 0x08U, /*!< LSE clock source */
USART_CLOCKSOURCE_UNDEFINED = 0x10U /*!< Undefined clock source */
} USART_ClockSourceTypeDef;
/**
* @brief USART handle Structure definition
*/
typedef struct __USART_HandleTypeDef
{
USART_TypeDef *Instance; /*!< USART registers base address */
USART_InitTypeDef Init; /*!< USART communication parameters */
const uint8_t *pTxBuffPtr; /*!< Pointer to USART Tx transfer Buffer */
uint16_t TxXferSize; /*!< USART Tx Transfer size */
__IO uint16_t TxXferCount; /*!< USART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to USART Rx transfer Buffer */
uint16_t RxXferSize; /*!< USART Rx Transfer size */
__IO uint16_t RxXferCount; /*!< USART Rx Transfer Counter */
uint16_t Mask; /*!< USART Rx RDR register mask */
uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */
uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */
uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value
of @ref USARTEx_Slave_Mode */
uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value
of @ref USARTEx_FIFO_mode. */
void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */
void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */
DMA_HandleTypeDef *hdmatx; /*!< USART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< USART Rx DMA Handle parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_USART_StateTypeDef State; /*!< USART communication state */
__IO uint32_t ErrorCode; /*!< USART Error code */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Half Complete Callback */
void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Complete Callback */
void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Half Complete Callback */
void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Complete Callback */
void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Rx Complete Callback */
void (* ErrorCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Error Callback */
void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Abort Complete Callback */
void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Rx Fifo Full Callback */
void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Tx Fifo Empty Callback */
void (* MspInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp Init callback */
void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart); /*!< USART Msp DeInit callback */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
} USART_HandleTypeDef;
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
/**
* @brief HAL USART Callback ID enumeration definition
*/
typedef enum
{
HAL_USART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< USART Tx Half Complete Callback ID */
HAL_USART_TX_COMPLETE_CB_ID = 0x01U, /*!< USART Tx Complete Callback ID */
HAL_USART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< USART Rx Half Complete Callback ID */
HAL_USART_RX_COMPLETE_CB_ID = 0x03U, /*!< USART Rx Complete Callback ID */
HAL_USART_TX_RX_COMPLETE_CB_ID = 0x04U, /*!< USART Tx Rx Complete Callback ID */
HAL_USART_ERROR_CB_ID = 0x05U, /*!< USART Error Callback ID */
HAL_USART_ABORT_COMPLETE_CB_ID = 0x06U, /*!< USART Abort Complete Callback ID */
HAL_USART_RX_FIFO_FULL_CB_ID = 0x07U, /*!< USART Rx Fifo Full Callback ID */
HAL_USART_TX_FIFO_EMPTY_CB_ID = 0x08U, /*!< USART Tx Fifo Empty Callback ID */
HAL_USART_MSPINIT_CB_ID = 0x09U, /*!< USART MspInit callback ID */
HAL_USART_MSPDEINIT_CB_ID = 0x0AU /*!< USART MspDeInit callback ID */
} HAL_USART_CallbackIDTypeDef;
/**
* @brief HAL USART Callback pointer definition
*/
typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< pointer to an USART callback function */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USART_Exported_Constants USART Exported Constants
* @{
*/
/** @defgroup USART_Error_Definition USART Error Definition
* @{
*/
#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */
#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */
#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */
#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */
#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */
/**
* @}
*/
/** @defgroup USART_Stop_Bits USART Number of Stop Bits
* @{
*/
#define USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< USART frame with 0.5 stop bit */
#define USART_STOPBITS_1 0x00000000U /*!< USART frame with 1 stop bit */
#define USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */
#define USART_STOPBITS_2 USART_CR2_STOP_1 /*!< USART frame with 2 stop bits */
/**
* @}
*/
/** @defgroup USART_Parity USART Parity
* @{
*/
#define USART_PARITY_NONE 0x00000000U /*!< No parity */
#define USART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */
#define USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */
/**
* @}
*/
/** @defgroup USART_Mode USART Mode
* @{
*/
#define USART_MODE_RX USART_CR1_RE /*!< RX mode */
#define USART_MODE_TX USART_CR1_TE /*!< TX mode */
#define USART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */
/**
* @}
*/
/** @defgroup USART_Clock USART Clock
* @{
*/
#define USART_CLOCK_DISABLE 0x00000000U /*!< USART clock disable */
#define USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< USART clock enable */
/**
* @}
*/
/** @defgroup USART_Clock_Polarity USART Clock Polarity
* @{
*/
#define USART_POLARITY_LOW 0x00000000U /*!< Driver enable signal is active high */
#define USART_POLARITY_HIGH USART_CR2_CPOL /*!< Driver enable signal is active low */
/**
* @}
*/
/** @defgroup USART_Clock_Phase USART Clock Phase
* @{
*/
#define USART_PHASE_1EDGE 0x00000000U /*!< USART frame phase on first clock transition */
#define USART_PHASE_2EDGE USART_CR2_CPHA /*!< USART frame phase on second clock transition */
/**
* @}
*/
/** @defgroup USART_Last_Bit USART Last Bit
* @{
*/
#define USART_LASTBIT_DISABLE 0x00000000U /*!< USART frame last data bit clock pulse not output to SCLK pin */
#define USART_LASTBIT_ENABLE USART_CR2_LBCL /*!< USART frame last data bit clock pulse output to SCLK pin */
/**
* @}
*/
/** @defgroup USART_ClockPrescaler USART Clock Prescaler
* @{
*/
#define USART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */
#define USART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */
#define USART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */
#define USART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */
#define USART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */
#define USART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */
#define USART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */
#define USART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */
#define USART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */
#define USART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */
#define USART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */
#define USART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */
/**
* @}
*/
/** @defgroup USART_Request_Parameters USART Request Parameters
* @{
*/
#define USART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */
#define USART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */
/**
* @}
*/
/** @defgroup USART_Flags USART Flags
* Elements values convention: 0xXXXX
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define USART_FLAG_TXFT USART_ISR_TXFT /*!< USART TXFIFO threshold flag */
#define USART_FLAG_RXFT USART_ISR_RXFT /*!< USART RXFIFO threshold flag */
#define USART_FLAG_RXFF USART_ISR_RXFF /*!< USART RXFIFO Full flag */
#define USART_FLAG_TXFE USART_ISR_TXFE /*!< USART TXFIFO Empty flag */
#define USART_FLAG_REACK USART_ISR_REACK /*!< USART receive enable acknowledge flag */
#define USART_FLAG_TEACK USART_ISR_TEACK /*!< USART transmit enable acknowledge flag */
#define USART_FLAG_BUSY USART_ISR_BUSY /*!< USART busy flag */
#define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */
#define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */
#define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */
#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */
#define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */
#define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */
#define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */
#define USART_FLAG_IDLE USART_ISR_IDLE /*!< USART idle flag */
#define USART_FLAG_ORE USART_ISR_ORE /*!< USART overrun error */
#define USART_FLAG_NE USART_ISR_NE /*!< USART noise error */
#define USART_FLAG_FE USART_ISR_FE /*!< USART frame error */
#define USART_FLAG_PE USART_ISR_PE /*!< USART parity error */
/**
* @}
*/
/** @defgroup USART_Interrupt_definition USART Interrupts Definition
* Elements values convention: 0000ZZZZ0XXYYYYYb
* - YYYYY : Interrupt source position in the XX register (5bits)
* - XX : Interrupt source register (2bits)
* - 01: CR1 register
* - 10: CR2 register
* - 11: CR3 register
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define USART_IT_PE 0x0028U /*!< USART parity error interruption */
#define USART_IT_TXE 0x0727U /*!< USART transmit data register empty interruption */
#define USART_IT_TXFNF 0x0727U /*!< USART TX FIFO not full interruption */
#define USART_IT_TC 0x0626U /*!< USART transmission complete interruption */
#define USART_IT_RXNE 0x0525U /*!< USART read data register not empty interruption */
#define USART_IT_RXFNE 0x0525U /*!< USART RXFIFO not empty interruption */
#define USART_IT_IDLE 0x0424U /*!< USART idle interruption */
#define USART_IT_ERR 0x0060U /*!< USART error interruption */
#define USART_IT_ORE 0x0300U /*!< USART overrun error interruption */
#define USART_IT_NE 0x0200U /*!< USART noise error interruption */
#define USART_IT_FE 0x0100U /*!< USART frame error interruption */
#define USART_IT_RXFF 0x183FU /*!< USART RXFIFO full interruption */
#define USART_IT_TXFE 0x173EU /*!< USART TXFIFO empty interruption */
#define USART_IT_RXFT 0x1A7CU /*!< USART RXFIFO threshold reached interruption */
#define USART_IT_TXFT 0x1B77U /*!< USART TXFIFO threshold reached interruption */
/**
* @}
*/
/** @defgroup USART_IT_CLEAR_Flags USART Interruption Clear Flags
* @{
*/
#define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
#define USART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
#define USART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */
#define USART_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */
#define USART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
#define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
#define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */
#define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */
#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */
/**
* @}
*/
/** @defgroup USART_Interruption_Mask USART Interruption Flags Mask
* @{
*/
#define USART_IT_MASK 0x001FU /*!< USART interruptions flags mask */
#define USART_CR_MASK 0x00E0U /*!< USART control register mask */
#define USART_CR_POS 5U /*!< USART control register position */
#define USART_ISR_MASK 0x1F00U /*!< USART ISR register mask */
#define USART_ISR_POS 8U /*!< USART ISR register position */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup USART_Exported_Macros USART Exported Macros
* @{
*/
/** @brief Reset USART handle state.
* @param __HANDLE__ USART handle.
* @retval None
*/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_USART_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/** @brief Check whether the specified USART flag is set or not.
* @param __HANDLE__ specifies the USART Handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref USART_FLAG_TXFT TXFIFO threshold flag
* @arg @ref USART_FLAG_RXFT RXFIFO threshold flag
* @arg @ref USART_FLAG_RXFF RXFIFO Full flag
* @arg @ref USART_FLAG_TXFE TXFIFO Empty flag
* @arg @ref USART_FLAG_REACK Receive enable acknowledge flag
* @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag
* @arg @ref USART_FLAG_BUSY Busy flag
* @arg @ref USART_FLAG_UDR SPI slave underrun error flag
* @arg @ref USART_FLAG_TXE Transmit data register empty flag
* @arg @ref USART_FLAG_TXFNF TXFIFO not full flag
* @arg @ref USART_FLAG_TC Transmission Complete flag
* @arg @ref USART_FLAG_RXNE Receive data register not empty flag
* @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag
* @arg @ref USART_FLAG_RTOF Receiver Timeout flag
* @arg @ref USART_FLAG_IDLE Idle Line detection flag
* @arg @ref USART_FLAG_ORE OverRun Error flag
* @arg @ref USART_FLAG_NE Noise Error flag
* @arg @ref USART_FLAG_FE Framing Error flag
* @arg @ref USART_FLAG_PE Parity Error flag
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified USART pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
* @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag
* @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag
* @retval None
*/
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the USART PE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)
/** @brief Clear the USART FE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)
/** @brief Clear the USART NE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)
/** @brief Clear the USART ORE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)
/** @brief Clear the USART IDLE pending flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)
/** @brief Clear the USART TX FIFO empty clear flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_TXFECF(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)
/** @brief Clear SPI slave underrun error flag.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)
/** @brief Enable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref USART_IT_RXFF RXFIFO Full interrupt
* @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disable the specified USART interrupt.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref USART_IT_RXFF RXFIFO Full interrupt
* @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error)
* @retval None
*/
#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\
(((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\
((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\
((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Check whether the specified USART interrupt has occurred or not.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref USART_IT_RXFF RXFIFO Full interrupt
* @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_ORE OverRun Error interrupt
* @arg @ref USART_IT_NE Noise Error interrupt
* @arg @ref USART_IT_FE Framing Error interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
& (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\
USART_ISR_POS))) != 0U) ? SET : RESET)
/** @brief Check whether the specified USART interrupt source is enabled or not.
* @param __HANDLE__ specifies the USART Handle.
* @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref USART_IT_RXFF RXFIFO Full interrupt
* @arg @ref USART_IT_TXFE TXFIFO Empty interrupt
* @arg @ref USART_IT_RXFT RXFIFO threshold interrupt
* @arg @ref USART_IT_TXFT TXFIFO threshold interrupt
* @arg @ref USART_IT_TXE Transmit Data Register empty interrupt
* @arg @ref USART_IT_TXFNF TX FIFO not full interrupt
* @arg @ref USART_IT_TC Transmission complete interrupt
* @arg @ref USART_IT_RXNE Receive Data register not empty interrupt
* @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt
* @arg @ref USART_IT_IDLE Idle line detection interrupt
* @arg @ref USART_IT_ORE OverRun Error interrupt
* @arg @ref USART_IT_NE Noise Error interrupt
* @arg @ref USART_IT_FE Framing Error interrupt
* @arg @ref USART_IT_PE Parity Error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\
(__HANDLE__)->Instance->CR1 : \
(((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\
(__HANDLE__)->Instance->CR2 : \
(__HANDLE__)->Instance->CR3)) & (0x01U <<\
(((uint16_t)(__INTERRUPT__)) &\
USART_IT_MASK))) != 0U) ? SET : RESET)
/** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt.
* This parameter can be one of the following values:
* @arg @ref USART_CLEAR_PEF Parity Error Clear Flag
* @arg @ref USART_CLEAR_FEF Framing Error Clear Flag
* @arg @ref USART_CLEAR_NEF Noise detected Clear Flag
* @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag
* @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag
* @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag
* @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag
* @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag
* @retval None
*/
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific USART request flag.
* @param __HANDLE__ specifies the USART Handle.
* @param __REQ__ specifies the request flag to set.
* This parameter can be one of the following values:
* @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request
* @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request
*
* @retval None
*/
#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable the USART one bit sample method.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disable the USART one bit sample method.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
/** @brief Enable USART.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART.
* @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup USART_Private_Macros USART Private Macros
* @{
*/
/** @brief Get USART clock division factor from clock prescaler value.
* @param __CLOCKPRESCALER__ USART prescaler value.
* @retval USART clock division factor
*/
#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
(((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) ? 1U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) ? 2U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) ? 4U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) ? 6U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) ? 8U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) ? 10U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) ? 12U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
* @param __PCLK__ USART clock.
* @param __BAUD__ Baud rate set by the user.
* @param __CLOCKPRESCALER__ USART prescaler value.
* @retval Division result
*/
#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\
(((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+ ((__BAUD__)/2U)) / (__BAUD__))
/** @brief Report the USART clock source.
* @param __HANDLE__ specifies the USART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0)
/** @brief Check USART Baud rate.
* @param __BAUDRATE__ Baudrate specified by the user.
* The maximum Baud Rate is derived from the maximum clock on G4 (i.e. 150 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) */
#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 18750000U)
/**
* @brief Ensure that USART frame number of stop bits is valid.
* @param __STOPBITS__ USART frame number of stop bits.
* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
*/
#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \
((__STOPBITS__) == USART_STOPBITS_1) || \
((__STOPBITS__) == USART_STOPBITS_1_5) || \
((__STOPBITS__) == USART_STOPBITS_2))
/**
* @brief Ensure that USART frame parity is valid.
* @param __PARITY__ USART frame parity.
* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
*/
#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \
((__PARITY__) == USART_PARITY_EVEN) || \
((__PARITY__) == USART_PARITY_ODD))
/**
* @brief Ensure that USART communication mode is valid.
* @param __MODE__ USART communication mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))
/**
* @brief Ensure that USART clock state is valid.
* @param __CLOCK__ USART clock state.
* @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)
*/
#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \
((__CLOCK__) == USART_CLOCK_ENABLE))
/**
* @brief Ensure that USART frame polarity is valid.
* @param __CPOL__ USART frame polarity.
* @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
*/
#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))
/**
* @brief Ensure that USART frame phase is valid.
* @param __CPHA__ USART frame phase.
* @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)
*/
#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))
/**
* @brief Ensure that USART frame last bit clock pulse setting is valid.
* @param __LASTBIT__ USART frame last bit clock pulse setting.
* @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)
*/
#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \
((__LASTBIT__) == USART_LASTBIT_ENABLE))
/**
* @brief Ensure that USART request parameter is valid.
* @param __PARAM__ USART request parameter.
* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
*/
#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \
((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))
/**
* @brief Ensure that USART Prescaler is valid.
* @param __CLOCKPRESCALER__ USART Prescaler value.
* @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
*/
#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \
((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))
/**
* @}
*/
/* Include USART HAL Extended module */
#include "stm32g4xx_hal_usart_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USART_Exported_Functions USART Exported Functions
* @{
*/
/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
void HAL_USART_MspInit(USART_HandleTypeDef *husart);
void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
pUSART_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_USART_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData,
uint16_t Size);
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
/* Transfer Abort functions */
HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_USART_H */
| 51,778 | C | 51.567513 | 132 | 0.517536 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_spi.h | /**
******************************************************************************
* @file stm32g4xx_ll_spi.h
* @author MCD Application Team
* @brief Header file of SPI LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_SPI_H
#define STM32G4xx_LL_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4)
/** @defgroup SPI_LL SPI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure
* @{
*/
/**
* @brief SPI Init structures definition
*/
typedef struct
{
uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/
uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
This parameter can be a value of @ref SPI_LL_EC_MODE.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/
uint32_t DataWidth; /*!< Specifies the SPI data width.
This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/
uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_LL_EC_POLARITY.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/
uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_LL_EC_PHASE.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/
uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/
uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
@note The communication clock is derived from the master clock. The slave clock does not need to be set.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/
uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/
uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF.
This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/
} LL_SPI_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
* @{
*/
/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_SPI_ReadReg function
* @{
*/
#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */
#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */
#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */
#define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */
#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */
#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */
#define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */
/**
* @}
*/
/** @defgroup SPI_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
* @{
*/
#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */
/**
* @}
*/
/** @defgroup SPI_LL_EC_MODE Operation Mode
* @{
*/
#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */
#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */
/**
* @}
*/
/** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol
* @{
*/
#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */
#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */
/**
* @}
*/
/** @defgroup SPI_LL_EC_PHASE Clock Phase
* @{
*/
#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */
#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */
/**
* @}
*/
/** @defgroup SPI_LL_EC_POLARITY Clock Polarity
* @{
*/
#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */
#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */
/**
* @}
*/
/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
* @{
*/
#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */
#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */
#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */
#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */
#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */
#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */
#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */
#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */
/**
* @}
*/
/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order
* @{
*/
#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */
#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */
/**
* @}
*/
/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
* @{
*/
#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */
#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */
#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */
#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */
/**
* @}
*/
/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode
* @{
*/
#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */
#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */
#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */
/**
* @}
*/
/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth
* @{
*/
#define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */
#define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */
#define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */
#define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */
#define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */
#define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */
#define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */
#define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */
#define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */
#define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */
#define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */
#define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */
#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
* @{
*/
#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */
#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length
* @{
*/
#define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */
#define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */
/**
* @}
*/
/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
* @{
*/
#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */
/**
* @}
*/
/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
* @{
*/
#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */
#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */
#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */
#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */
/**
* @}
*/
/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level
* @{
*/
#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */
#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */
#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */
#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */
/**
* @}
*/
/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity
* @{
*/
#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */
#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
* @{
*/
/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in SPI register
* @param __INSTANCE__ SPI Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in SPI register
* @param __INSTANCE__ SPI Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
* @{
*/
/** @defgroup SPI_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable SPI peripheral
* @rmtoll CR1 SPE LL_SPI_Enable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
* @brief Disable SPI peripheral
* @note When disabling the SPI, follow the procedure described in the Reference Manual.
* @rmtoll CR1 SPE LL_SPI_Disable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
* @brief Check if SPI peripheral is enabled
* @rmtoll CR1 SPE LL_SPI_IsEnabled
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
}
/**
* @brief Set SPI operation mode to Master or Slave
* @note This bit should not be changed when communication is ongoing.
* @rmtoll CR1 MSTR LL_SPI_SetMode\n
* CR1 SSI LL_SPI_SetMode
* @param SPIx SPI Instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
}
/**
* @brief Get SPI operation mode (Master or Slave)
* @rmtoll CR1 MSTR LL_SPI_GetMode\n
* CR1 SSI LL_SPI_GetMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_MODE_MASTER
* @arg @ref LL_SPI_MODE_SLAVE
*/
__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
}
/**
* @brief Set serial protocol used
* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
* @rmtoll CR2 FRF LL_SPI_SetStandard
* @param SPIx SPI Instance
* @param Standard This parameter can be one of the following values:
* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
* @arg @ref LL_SPI_PROTOCOL_TI
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
{
MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
}
/**
* @brief Get serial protocol used
* @rmtoll CR2 FRF LL_SPI_GetStandard
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_PROTOCOL_MOTOROLA
* @arg @ref LL_SPI_PROTOCOL_TI
*/
__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
}
/**
* @brief Set clock phase
* @note This bit should not be changed when communication is ongoing.
* This bit is not used in SPI TI mode.
* @rmtoll CR1 CPHA LL_SPI_SetClockPhase
* @param SPIx SPI Instance
* @param ClockPhase This parameter can be one of the following values:
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
}
/**
* @brief Get clock phase
* @rmtoll CR1 CPHA LL_SPI_GetClockPhase
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_PHASE_1EDGE
* @arg @ref LL_SPI_PHASE_2EDGE
*/
__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
}
/**
* @brief Set clock polarity
* @note This bit should not be changed when communication is ongoing.
* This bit is not used in SPI TI mode.
* @rmtoll CR1 CPOL LL_SPI_SetClockPolarity
* @param SPIx SPI Instance
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
}
/**
* @brief Get clock polarity
* @rmtoll CR1 CPOL LL_SPI_GetClockPolarity
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_POLARITY_LOW
* @arg @ref LL_SPI_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
}
/**
* @brief Set baud rate prescaler
* @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler.
* @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler
* @param SPIx SPI Instance
* @param BaudRate This parameter can be one of the following values:
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
}
/**
* @brief Get baud rate prescaler
* @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
* @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
*/
__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
}
/**
* @brief Set transfer bit order
* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
* @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder
* @param SPIx SPI Instance
* @param BitOrder This parameter can be one of the following values:
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
}
/**
* @brief Get transfer bit order
* @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_LSB_FIRST
* @arg @ref LL_SPI_MSB_FIRST
*/
__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
}
/**
* @brief Set transfer direction mode
* @note For Half-Duplex mode, Rx Direction is set by default.
* In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex.
* @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n
* CR1 BIDIMODE LL_SPI_SetTransferDirection\n
* CR1 BIDIOE LL_SPI_SetTransferDirection
* @param SPIx SPI Instance
* @param TransferDirection This parameter can be one of the following values:
* @arg @ref LL_SPI_FULL_DUPLEX
* @arg @ref LL_SPI_SIMPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
}
/**
* @brief Get transfer direction mode
* @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n
* CR1 BIDIMODE LL_SPI_GetTransferDirection\n
* CR1 BIDIOE LL_SPI_GetTransferDirection
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_FULL_DUPLEX
* @arg @ref LL_SPI_SIMPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_RX
* @arg @ref LL_SPI_HALF_DUPLEX_TX
*/
__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
}
/**
* @brief Set frame data width
* @rmtoll CR2 DS LL_SPI_SetDataWidth
* @param SPIx SPI Instance
* @param DataWidth This parameter can be one of the following values:
* @arg @ref LL_SPI_DATAWIDTH_4BIT
* @arg @ref LL_SPI_DATAWIDTH_5BIT
* @arg @ref LL_SPI_DATAWIDTH_6BIT
* @arg @ref LL_SPI_DATAWIDTH_7BIT
* @arg @ref LL_SPI_DATAWIDTH_8BIT
* @arg @ref LL_SPI_DATAWIDTH_9BIT
* @arg @ref LL_SPI_DATAWIDTH_10BIT
* @arg @ref LL_SPI_DATAWIDTH_11BIT
* @arg @ref LL_SPI_DATAWIDTH_12BIT
* @arg @ref LL_SPI_DATAWIDTH_13BIT
* @arg @ref LL_SPI_DATAWIDTH_14BIT
* @arg @ref LL_SPI_DATAWIDTH_15BIT
* @arg @ref LL_SPI_DATAWIDTH_16BIT
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
{
MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth);
}
/**
* @brief Get frame data width
* @rmtoll CR2 DS LL_SPI_GetDataWidth
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_DATAWIDTH_4BIT
* @arg @ref LL_SPI_DATAWIDTH_5BIT
* @arg @ref LL_SPI_DATAWIDTH_6BIT
* @arg @ref LL_SPI_DATAWIDTH_7BIT
* @arg @ref LL_SPI_DATAWIDTH_8BIT
* @arg @ref LL_SPI_DATAWIDTH_9BIT
* @arg @ref LL_SPI_DATAWIDTH_10BIT
* @arg @ref LL_SPI_DATAWIDTH_11BIT
* @arg @ref LL_SPI_DATAWIDTH_12BIT
* @arg @ref LL_SPI_DATAWIDTH_13BIT
* @arg @ref LL_SPI_DATAWIDTH_14BIT
* @arg @ref LL_SPI_DATAWIDTH_15BIT
* @arg @ref LL_SPI_DATAWIDTH_16BIT
*/
__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS));
}
/**
* @brief Set threshold of RXFIFO that triggers an RXNE event
* @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold
* @param SPIx SPI Instance
* @param Threshold This parameter can be one of the following values:
* @arg @ref LL_SPI_RX_FIFO_TH_HALF
* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
{
MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold);
}
/**
* @brief Get threshold of RXFIFO that triggers an RXNE event
* @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_RX_FIFO_TH_HALF
* @arg @ref LL_SPI_RX_FIFO_TH_QUARTER
*/
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH));
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_CRC_Management CRC Management
* @{
*/
/**
* @brief Enable CRC
* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
* @rmtoll CR1 CRCEN LL_SPI_EnableCRC
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
}
/**
* @brief Disable CRC
* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
* @rmtoll CR1 CRCEN LL_SPI_DisableCRC
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
}
/**
* @brief Check if CRC is enabled
* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
* @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
}
/**
* @brief Set CRC Length
* @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation.
* @rmtoll CR1 CRCL LL_SPI_SetCRCWidth
* @param SPIx SPI Instance
* @param CRCLength This parameter can be one of the following values:
* @arg @ref LL_SPI_CRC_8BIT
* @arg @ref LL_SPI_CRC_16BIT
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength);
}
/**
* @brief Get CRC Length
* @rmtoll CR1 CRCL LL_SPI_GetCRCWidth
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_CRC_8BIT
* @arg @ref LL_SPI_CRC_16BIT
*/
__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL));
}
/**
* @brief Set CRCNext to transfer CRC on the line
* @note This bit has to be written as soon as the last data is written in the SPIx_DR register.
* @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
}
/**
* @brief Set polynomial for CRC calculation
* @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial
* @param SPIx SPI Instance
* @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
{
WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
}
/**
* @brief Get polynomial for CRC calculation
* @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->CRCPR));
}
/**
* @brief Get Rx CRC
* @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->RXCRCR));
}
/**
* @brief Get Tx CRC
* @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
* @param SPIx SPI Instance
* @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_REG(SPIx->TXCRCR));
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management
* @{
*/
/**
* @brief Set NSS mode
* @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode.
* @rmtoll CR1 SSM LL_SPI_SetNSSMode\n
* @rmtoll CR2 SSOE LL_SPI_SetNSSMode
* @param SPIx SPI Instance
* @param NSS This parameter can be one of the following values:
* @arg @ref LL_SPI_NSS_SOFT
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
{
MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
}
/**
* @brief Get NSS mode
* @rmtoll CR1 SSM LL_SPI_GetNSSMode\n
* @rmtoll CR2 SSOE LL_SPI_GetNSSMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_NSS_SOFT
* @arg @ref LL_SPI_NSS_HARD_INPUT
* @arg @ref LL_SPI_NSS_HARD_OUTPUT
*/
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
{
uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
return (Ssm | Ssoe);
}
/**
* @brief Enable NSS pulse management
* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
* @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_NSSP);
}
/**
* @brief Disable NSS pulse management
* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
* @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP);
}
/**
* @brief Check if NSS pulse is enabled
* @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode.
* @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Check if Rx buffer is not empty
* @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
}
/**
* @brief Check if Tx buffer is empty
* @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
}
/**
* @brief Get CRC error flag
* @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
}
/**
* @brief Get mode fault error flag
* @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
}
/**
* @brief Get overrun error flag
* @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
}
/**
* @brief Get busy flag
* @note The BSY flag is cleared under any one of the following conditions:
* -When the SPI is correctly disabled
* -When a fault is detected in Master mode (MODF bit set to 1)
* -In Master mode, when it finishes a data transmission and no new data is ready to be
* sent
* -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between
* each data transfer.
* @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
}
/**
* @brief Get frame format error flag
* @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
}
/**
* @brief Get FIFO reception Level
* @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_RX_FIFO_EMPTY
* @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL
* @arg @ref LL_SPI_RX_FIFO_HALF_FULL
* @arg @ref LL_SPI_RX_FIFO_FULL
*/
__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL));
}
/**
* @brief Get FIFO Transmission Level
* @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_TX_FIFO_EMPTY
* @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL
* @arg @ref LL_SPI_TX_FIFO_HALF_FULL
* @arg @ref LL_SPI_TX_FIFO_FULL
*/
__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL));
}
/**
* @brief Clear CRC error flag
* @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
}
/**
* @brief Clear mode fault error flag
* @note Clearing this flag is done by a read access to the SPIx_SR
* register followed by a write access to the SPIx_CR1 register
* @rmtoll SR MODF LL_SPI_ClearFlag_MODF
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
{
__IO uint32_t tmpreg_sr;
tmpreg_sr = SPIx->SR;
(void) tmpreg_sr;
CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
}
/**
* @brief Clear overrun error flag
* @note Clearing this flag is done by a read access to the SPIx_DR
* register followed by a read access to the SPIx_SR register
* @rmtoll SR OVR LL_SPI_ClearFlag_OVR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
{
__IO uint32_t tmpreg;
tmpreg = SPIx->DR;
(void) tmpreg;
tmpreg = SPIx->SR;
(void) tmpreg;
}
/**
* @brief Clear frame format error flag
* @note Clearing this flag is done by reading SPIx_SR register
* @rmtoll SR FRE LL_SPI_ClearFlag_FRE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
{
__IO uint32_t tmpreg;
tmpreg = SPIx->SR;
(void) tmpreg;
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_IT_Management Interrupt Management
* @{
*/
/**
* @brief Enable error interrupt
* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
* @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
}
/**
* @brief Enable Rx buffer not empty interrupt
* @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
}
/**
* @brief Enable Tx buffer empty interrupt
* @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
}
/**
* @brief Disable error interrupt
* @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode).
* @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
}
/**
* @brief Disable Rx buffer not empty interrupt
* @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
}
/**
* @brief Disable Tx buffer empty interrupt
* @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
}
/**
* @brief Check if error interrupt is enabled
* @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Rx buffer not empty interrupt is enabled
* @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Tx buffer empty interrupt
* @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Enable DMA Rx
* @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
}
/**
* @brief Disable DMA Rx
* @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
}
/**
* @brief Check if DMA Rx is enabled
* @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Enable DMA Tx
* @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
}
/**
* @brief Disable DMA Tx
* @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
}
/**
* @brief Check if DMA Tx is enabled
* @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Set parity of Last DMA reception
* @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX
* @param SPIx SPI Instance
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_SPI_DMA_PARITY_ODD
* @arg @ref LL_SPI_DMA_PARITY_EVEN
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity)
{
MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos));
}
/**
* @brief Get parity configuration for Last DMA reception
* @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_DMA_PARITY_ODD
* @arg @ref LL_SPI_DMA_PARITY_EVEN
*/
__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos);
}
/**
* @brief Set parity of Last DMA transmission
* @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX
* @param SPIx SPI Instance
* @param Parity This parameter can be one of the following values:
* @arg @ref LL_SPI_DMA_PARITY_ODD
* @arg @ref LL_SPI_DMA_PARITY_EVEN
* @retval None
*/
__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity)
{
MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos));
}
/**
* @brief Get parity configuration for Last DMA transmission
* @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_SPI_DMA_PARITY_ODD
* @arg @ref LL_SPI_DMA_PARITY_EVEN
*/
__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos);
}
/**
* @brief Get the data register address used for DMA transfer
* @rmtoll DR DR LL_SPI_DMA_GetRegAddr
* @param SPIx SPI Instance
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx)
{
return (uint32_t) &(SPIx->DR);
}
/**
* @}
*/
/** @defgroup SPI_LL_EF_DATA_Management DATA Management
* @{
*/
/**
* @brief Read 8-Bits in the data register
* @rmtoll DR DR LL_SPI_ReceiveData8
* @param SPIx SPI Instance
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
{
return (*((__IO uint8_t *)&SPIx->DR));
}
/**
* @brief Read 16-Bits in the data register
* @rmtoll DR DR LL_SPI_ReceiveData16
* @param SPIx SPI Instance
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
{
return (uint16_t)(READ_REG(SPIx->DR));
}
/**
* @brief Write 8-Bits in the data register
* @rmtoll DR DR LL_SPI_TransmitData8
* @param SPIx SPI Instance
* @param TxData Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
{
#if defined (__GNUC__)
__IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
*spidr = TxData;
#else
*((__IO uint8_t *)&SPIx->DR) = TxData;
#endif /* __GNUC__ */
}
/**
* @brief Write 16-Bits in the data register
* @rmtoll DR DR LL_SPI_TransmitData16
* @param SPIx SPI Instance
* @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
#if defined (__GNUC__)
__IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
*spidr = TxData;
#else
SPIx->DR = TxData;
#endif /* __GNUC__ */
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#if defined(SPI_I2S_SUPPORT)
/** @defgroup I2S_LL I2S
* @{
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
* @{
*/
/**
* @brief I2S Init structure definition
*/
typedef struct
{
uint32_t Mode; /*!< Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_LL_EC_MODE
This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/
uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_STANDARD
This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/
uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/
uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity
and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/
uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_LL_EC_POLARITY
This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/
} LL_I2S_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
* @{
*/
/** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_I2S_ReadReg function
* @{
*/
#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */
#define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */
#define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */
#define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */
#define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */
#define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */
/**
* @}
*/
/** @defgroup SPI_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
* @{
*/
#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */
#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */
#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */
/**
* @}
*/
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
* @{
*/
#define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel length 16bit */
#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel length 32bit */
#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel length 32bit */
#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel length 32bit */
/**
* @}
*/
/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
* @{
*/
#define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */
#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */
/**
* @}
*/
/** @defgroup I2S_LL_EC_STANDARD I2s Standard
* @{
*/
#define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */
#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */
#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */
#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */
#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */
/**
* @}
*/
/** @defgroup I2S_LL_EC_MODE Operation Mode
* @{
*/
#define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */
#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */
#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */
#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */
/**
* @}
*/
/** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor
* @{
*/
#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */
#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
* @{
*/
#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */
#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */
/**
* @}
*/
/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
* @{
*/
#define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */
#define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */
#define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */
#define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */
#define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */
#define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */
#define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */
#define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */
#define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */
#define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
* @{
*/
/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in I2S register
* @param __INSTANCE__ I2S Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in I2S register
* @param __INSTANCE__ I2S Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
* @{
*/
/** @defgroup I2S_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Select I2S mode and Enable I2S peripheral
* @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
* I2SCFGR I2SE LL_I2S_Enable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
}
/**
* @brief Disable I2S peripheral
* @rmtoll I2SCFGR I2SE LL_I2S_Disable
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
}
/**
* @brief Check if I2S peripheral is enabled
* @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
}
/**
* @brief Set I2S data frame length
* @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
* I2SCFGR CHLEN LL_I2S_SetDataFormat
* @param SPIx SPI Instance
* @param DataFormat This parameter can be one of the following values:
* @arg @ref LL_I2S_DATAFORMAT_16B
* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
* @arg @ref LL_I2S_DATAFORMAT_24B
* @arg @ref LL_I2S_DATAFORMAT_32B
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
{
MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
}
/**
* @brief Get I2S data frame length
* @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
* I2SCFGR CHLEN LL_I2S_GetDataFormat
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_DATAFORMAT_16B
* @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
* @arg @ref LL_I2S_DATAFORMAT_24B
* @arg @ref LL_I2S_DATAFORMAT_32B
*/
__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
}
/**
* @brief Set I2S clock polarity
* @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
* @param SPIx SPI Instance
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_I2S_POLARITY_LOW
* @arg @ref LL_I2S_POLARITY_HIGH
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
{
SET_BIT(SPIx->I2SCFGR, ClockPolarity);
}
/**
* @brief Get I2S clock polarity
* @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_POLARITY_LOW
* @arg @ref LL_I2S_POLARITY_HIGH
*/
__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
}
/**
* @brief Set I2S standard protocol
* @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
* I2SCFGR PCMSYNC LL_I2S_SetStandard
* @param SPIx SPI Instance
* @param Standard This parameter can be one of the following values:
* @arg @ref LL_I2S_STANDARD_PHILIPS
* @arg @ref LL_I2S_STANDARD_MSB
* @arg @ref LL_I2S_STANDARD_LSB
* @arg @ref LL_I2S_STANDARD_PCM_SHORT
* @arg @ref LL_I2S_STANDARD_PCM_LONG
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
{
MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
}
/**
* @brief Get I2S standard protocol
* @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
* I2SCFGR PCMSYNC LL_I2S_GetStandard
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_STANDARD_PHILIPS
* @arg @ref LL_I2S_STANDARD_MSB
* @arg @ref LL_I2S_STANDARD_LSB
* @arg @ref LL_I2S_STANDARD_PCM_SHORT
* @arg @ref LL_I2S_STANDARD_PCM_LONG
*/
__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
}
/**
* @brief Set I2S transfer mode
* @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
* @param SPIx SPI Instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_I2S_MODE_SLAVE_TX
* @arg @ref LL_I2S_MODE_SLAVE_RX
* @arg @ref LL_I2S_MODE_MASTER_TX
* @arg @ref LL_I2S_MODE_MASTER_RX
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
{
MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
}
/**
* @brief Get I2S transfer mode
* @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_MODE_SLAVE_TX
* @arg @ref LL_I2S_MODE_SLAVE_RX
* @arg @ref LL_I2S_MODE_MASTER_TX
* @arg @ref LL_I2S_MODE_MASTER_RX
*/
__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
}
/**
* @brief Set I2S linear prescaler
* @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear
* @param SPIx SPI Instance
* @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
{
MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
}
/**
* @brief Get I2S linear prescaler
* @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear
* @param SPIx SPI Instance
* @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
}
/**
* @brief Set I2S parity prescaler
* @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity
* @param SPIx SPI Instance
* @param PrescalerParity This parameter can be one of the following values:
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
* @retval None
*/
__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
{
MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
}
/**
* @brief Get I2S parity prescaler
* @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity
* @param SPIx SPI Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
* @arg @ref LL_I2S_PRESCALER_PARITY_ODD
*/
__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
{
return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
}
/**
* @brief Enable the master clock output (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
}
/**
* @brief Disable the master clock output (Pin MCK)
* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
}
/**
* @brief Check if the master clock output (Pin MCK) is enabled
* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
}
#if defined(SPI_I2SCFGR_ASTRTEN)
/**
* @brief Enable asynchronous start
* @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
{
SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
}
/**
* @brief Disable asynchronous start
* @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
{
CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
}
/**
* @brief Check if asynchronous start is enabled
* @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
}
#endif /* SPI_I2SCFGR_ASTRTEN */
/**
* @}
*/
/** @defgroup I2S_LL_EF_FLAG FLAG Management
* @{
*/
/**
* @brief Check if Rx buffer is not empty
* @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_RXNE(SPIx);
}
/**
* @brief Check if Tx buffer is empty
* @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_TXE(SPIx);
}
/**
* @brief Get busy flag
* @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_BSY(SPIx);
}
/**
* @brief Get overrun error flag
* @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_OVR(SPIx);
}
/**
* @brief Get underrun error flag
* @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
}
/**
* @brief Get frame format error flag
* @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
{
return LL_SPI_IsActiveFlag_FRE(SPIx);
}
/**
* @brief Get channel side flag.
* @note 0: Channel Left has to be transmitted or has been received\n
* 1: Channel Right has to be transmitted or has been received\n
* It has no significance in PCM mode.
* @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx)
{
return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
}
/**
* @brief Clear overrun error flag
* @rmtoll SR OVR LL_I2S_ClearFlag_OVR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
{
LL_SPI_ClearFlag_OVR(SPIx);
}
/**
* @brief Clear underrun error flag
* @rmtoll SR UDR LL_I2S_ClearFlag_UDR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
{
__IO uint32_t tmpreg;
tmpreg = SPIx->SR;
(void)tmpreg;
}
/**
* @brief Clear frame format error flag
* @rmtoll SR FRE LL_I2S_ClearFlag_FRE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
{
LL_SPI_ClearFlag_FRE(SPIx);
}
/**
* @}
*/
/** @defgroup I2S_LL_EF_IT Interrupt Management
* @{
*/
/**
* @brief Enable error IT
* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
* @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
{
LL_SPI_EnableIT_ERR(SPIx);
}
/**
* @brief Enable Rx buffer not empty IT
* @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
{
LL_SPI_EnableIT_RXNE(SPIx);
}
/**
* @brief Enable Tx buffer empty IT
* @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
{
LL_SPI_EnableIT_TXE(SPIx);
}
/**
* @brief Disable error IT
* @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode).
* @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
{
LL_SPI_DisableIT_ERR(SPIx);
}
/**
* @brief Disable Rx buffer not empty IT
* @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
{
LL_SPI_DisableIT_RXNE(SPIx);
}
/**
* @brief Disable Tx buffer empty IT
* @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
{
LL_SPI_DisableIT_TXE(SPIx);
}
/**
* @brief Check if ERR IT is enabled
* @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_ERR(SPIx);
}
/**
* @brief Check if RXNE IT is enabled
* @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_RXNE(SPIx);
}
/**
* @brief Check if TXE IT is enabled
* @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledIT_TXE(SPIx);
}
/**
* @}
*/
/** @defgroup I2S_LL_EF_DMA DMA Management
* @{
*/
/**
* @brief Enable DMA Rx
* @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
{
LL_SPI_EnableDMAReq_RX(SPIx);
}
/**
* @brief Disable DMA Rx
* @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
{
LL_SPI_DisableDMAReq_RX(SPIx);
}
/**
* @brief Check if DMA Rx is enabled
* @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_RX(SPIx);
}
/**
* @brief Enable DMA Tx
* @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
{
LL_SPI_EnableDMAReq_TX(SPIx);
}
/**
* @brief Disable DMA Tx
* @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX
* @param SPIx SPI Instance
* @retval None
*/
__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
{
LL_SPI_DisableDMAReq_TX(SPIx);
}
/**
* @brief Check if DMA Tx is enabled
* @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
* @param SPIx SPI Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
{
return LL_SPI_IsEnabledDMAReq_TX(SPIx);
}
/**
* @}
*/
/** @defgroup I2S_LL_EF_DATA DATA Management
* @{
*/
/**
* @brief Read 16-Bits in data register
* @rmtoll DR DR LL_I2S_ReceiveData16
* @param SPIx SPI Instance
* @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
{
return LL_SPI_ReceiveData16(SPIx);
}
/**
* @brief Write 16-Bits in data register
* @rmtoll DR DR LL_I2S_TransmitData16
* @param SPIx SPI Instance
* @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
{
LL_SPI_TransmitData16(SPIx, TxData);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* SPI_I2S_SUPPORT */
#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_SPI_H */
| 76,127 | C | 32.316411 | 173 | 0.591131 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_wwdg.h | /**
******************************************************************************
* @file stm32g4xx_hal_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_WWDG_H
#define STM32G4xx_HAL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup WWDG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Types WWDG Exported Types
* @{
*/
/**
* @brief WWDG Init structure definition
*/
typedef struct
{
uint32_t Prescaler; /*!< Specifies the prescaler value of the WWDG.
This parameter can be a value of @ref WWDG_Prescaler */
uint32_t Window; /*!< Specifies the WWDG window value to be compared to the downcounter.
This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t Counter; /*!< Specifies the WWDG free-running downcounter value.
This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
uint32_t EWIMode ; /*!< Specifies if WWDG Early Wakeup Interrupt is enable or not.
This parameter can be a value of @ref WWDG_EWI_Mode */
} WWDG_InitTypeDef;
/**
* @brief WWDG handle Structure definition
*/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
typedef struct __WWDG_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
{
WWDG_TypeDef *Instance; /*!< Register base address */
WWDG_InitTypeDef Init; /*!< WWDG required parameters */
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
void (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Early WakeUp Interrupt callback */
void (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
} WWDG_HandleTypeDef;
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
/**
* @brief HAL WWDG common Callback ID enumeration definition
*/
typedef enum
{
HAL_WWDG_EWI_CB_ID = 0x00U, /*!< WWDG EWI callback ID */
HAL_WWDG_MSPINIT_CB_ID = 0x01U, /*!< WWDG MspInit callback ID */
} HAL_WWDG_CallbackIDTypeDef;
/**
* @brief HAL WWDG Callback pointer definition
*/
typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer to a WWDG common callback functions */
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
* @{
*/
#define WWDG_IT_EWI WWDG_CFR_EWI /*!< Early wakeup interrupt */
/**
* @}
*/
/** @defgroup WWDG_Flag_definition WWDG Flag definition
* @brief WWDG Flag definition
* @{
*/
#define WWDG_FLAG_EWIF WWDG_SR_EWIF /*!< Early wakeup interrupt flag */
/**
* @}
*/
/** @defgroup WWDG_Prescaler WWDG Prescaler
* @{
*/
#define WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/8 */
#define WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */
#define WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */
#define WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */
#define WWDG_PRESCALER_128 WWDG_CFR_WDGTB /*!< WWDG counter clock = (PCLK1/4096)/128 */
/**
* @}
*/
/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode
* @{
*/
#define WWDG_EWI_DISABLE 0x00000000u /*!< EWI Disable */
#define WWDG_EWI_ENABLE WWDG_CFR_EWI /*!< EWI Enable */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup WWDG_Private_Macros WWDG Private Macros
* @{
*/
#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
((__PRESCALER__) == WWDG_PRESCALER_2) || \
((__PRESCALER__) == WWDG_PRESCALER_4) || \
((__PRESCALER__) == WWDG_PRESCALER_8) || \
((__PRESCALER__) == WWDG_PRESCALER_16) || \
((__PRESCALER__) == WWDG_PRESCALER_32) || \
((__PRESCALER__) == WWDG_PRESCALER_64) || \
((__PRESCALER__) == WWDG_PRESCALER_128))
#define IS_WWDG_WINDOW(__WINDOW__) (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))
#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))
#define IS_WWDG_EWI_MODE(__MODE__) (((__MODE__) == WWDG_EWI_ENABLE) || \
((__MODE__) == WWDG_EWI_DISABLE))
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
* @{
*/
/**
* @brief Enable the WWDG peripheral.
* @param __HANDLE__ WWDG handle
* @retval None
*/
#define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
/**
* @brief Enable the WWDG early wakeup interrupt.
* @param __HANDLE__: WWDG handle
* @param __INTERRUPT__ specifies the interrupt to enable.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early wakeup interrupt
* @note Once enabled this interrupt cannot be disabled except by a system reset.
* @retval None
*/
#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))
/**
* @brief Check whether the selected WWDG interrupt has occurred or not.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the it to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))
/** @brief Clear the WWDG interrupt pending bits.
* bits to clear the selected interrupt pending bits.
* @param __HANDLE__ WWDG handle
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
*/
#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
/**
* @brief Check whether the specified WWDG flag is set or not.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval The new state of WWDG_FLAG (SET or RESET).
*/
#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clear the WWDG's pending flags.
* @param __HANDLE__ WWDG handle
* @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
* @retval None
*/
#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Check whether the specified WWDG interrupt source is enabled or not.
* @param __HANDLE__ WWDG Handle.
* @param __INTERRUPT__ specifies the WWDG interrupt source to check.
* This parameter can be one of the following values:
* @arg WWDG_IT_EWI: Early Wakeup Interrupt
* @retval state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\
& (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup WWDG_Exported_Functions
* @{
*/
/** @addtogroup WWDG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID,
pWWDG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_WWDG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup WWDG_Exported_Functions_Group2
* @{
*/
/* I/O operation functions ******************************************************/
HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_WWDG_H */
| 11,044 | C | 34.977199 | 130 | 0.531873 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h | /**
******************************************************************************
* @file stm32g4xx_hal_dac.h
* @author MCD Application Team
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_DAC_H
#define STM32G4xx_HAL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Types DAC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
} HAL_DAC_StateTypeDef;
/**
* @brief DAC handle Structure definition
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
typedef struct __DAC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
{
DAC_TypeDef *Instance; /*!< Register base address */
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac);
void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
/**
* @brief DAC Configuration sample and hold Channel structure definition
*/
typedef struct
{
uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
} DAC_SampleAndHoldConfTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode
This parameter can be a value of @ref DAC_HighFrequency */
FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel.
This parameter can be ENABLE or DISABLE */
FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel.
This parameter can be ENABLE or DISABLE */
uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
This parameter can be a value of @ref DAC_SampleAndHold */
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection.
Note: In case of sawtooth wave generation, this
trigger corresponds to the reset trigger. */
uint32_t DAC_Trigger2; /*!< Specifies the external secondary trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection.
Note: In case of sawtooth wave generation, this
trigger corresponds to the step trigger.*/
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref DAC_UserTrimming
DAC_UserTrimming is either factory or user trimming */
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DAC Callback ID enumeration definition
*/
typedef enum
{
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
} HAL_DAC_CallbackIDTypeDef;
/**
* @brief HAL DAC Callback pointer definition
*/
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
#define DAC_TRIGGER_NONE 0x00000000UL /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger */
#define DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */
#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
#define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
/**
* @}
*/
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
/**
* @}
*/
/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
#define DAC_CHANNEL_2 0x00000010U
/**
* @}
*/
/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R 0x00000000U
#define DAC_ALIGN_12B_L 0x00000004U
#define DAC_ALIGN_8B_R 0x00000008U
/**
* @}
*/
/** @defgroup DAC_flags_definition DAC flags definition
* @{
*/
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
#define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
/**
* @}
*/
/** @defgroup DAC_IT_definition DAC IT definition
* @{
*/
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
/**
* @}
*/
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
* @{
*/
#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0)
#define DAC_CHIPCONNECT_INTERNAL (1UL << 1)
#define DAC_CHIPCONNECT_BOTH (1UL << 2)
/**
* @}
*/
/** @defgroup DAC_UserTrimming DAC User Trimming
* @{
*/
#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */
/**
* @}
*/
/** @defgroup DAC_SampleAndHold DAC power mode
* @{
*/
#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
/**
* @}
*/
/** @defgroup DAC_HighFrequency DAC high frequency interface mode
* @{
*/
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Macros DAC Exported Macros
* @{
*/
/** @brief Reset DAC handle state.
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** @brief Enable the DAC channel.
* @param __HANDLE__ specifies the DAC handle.
* @param __DAC_Channel__ specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Disable the DAC channel.
* @param __HANDLE__ specifies the DAC handle
* @param __DAC_Channel__ specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Set DHR12R1 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified DAC interrupt source is enabled or not.
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval State of interruption (SET or RESET)
*/
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
& (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to get.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
* @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
* @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
(((DACX) == DAC2) ? \
((CHANNEL) == DAC_CHANNEL_1) \
: \
(((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2)))
#else
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
(((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#endif
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
/**
* @}
*/
/* Include DAC HAL Extended module */
#include "stm32g4xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
/** @defgroup DAC_Private_Functions DAC Private Functions
* @{
*/
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_DAC_H */
| 30,939 | C | 49.308943 | 474 | 0.594428 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash_ramfunc.h | /**
******************************************************************************
* @file stm32g4xx_hal_flash_ramfunc.h
* @author MCD Application Team
* @brief Header file of FLASH RAMFUNC driver.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_FLASH_RAMFUNC_H
#define STM32G4xx_FLASH_RAMFUNC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH_RAMFUNC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions
* @{
*/
/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
* @{
*/
/* Peripheral Control functions ************************************************/
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_EnableRunPowerDown(void);
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableRunPowerDown(void);
#if defined (FLASH_OPTR_DBANK)
__RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_OB_DBankConfig(uint32_t DBankConfig);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_FLASH_RAMFUNC_H */
| 1,917 | C | 24.573333 | 82 | 0.468962 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_flash.h | /**
******************************************************************************
* @file stm32g4xx_hal_flash.h
* @author MCD Application Team
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_FLASH_H
#define STM32G4xx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH Erase structure definition
*/
typedef struct
{
uint32_t TypeErase; /*!< Mass erase or page erase.
This parameter can be a value of @ref FLASH_Type_Erase */
uint32_t Banks; /*!< Select bank to erase.
This parameter must be a value of @ref FLASH_Banks
(FLASH_BANK_BOTH should be used only for mass erase) */
uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled.
This parameter must be a value between 0 and (max number of pages in the bank - 1)
(eg : 127 for 512KB dual bank) */
uint32_t NbPages; /*!< Number of pages to be erased.
This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/
} FLASH_EraseInitTypeDef;
/**
* @brief FLASH Option Bytes Program structure definition
*/
typedef struct
{
uint32_t OptionType; /*!< Option byte to be configured.
This parameter can be a combination of the values of @ref FLASH_OB_Type */
uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
Only one WRP area could be programmed at the same time.
This parameter can be value of @ref FLASH_OB_WRP_Area */
uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
This parameter must be a value between 0 and (max number of pages in the bank - 1) */
uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP).
This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
uint32_t RDPLevel; /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
This parameter can be a value of @ref FLASH_OB_Read_Protection */
uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASH_OB_USER_Type */
uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER).
This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
@ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
@ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW,
@ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY,
@ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2 (*),
@ref FLASH_OB_USER_nBOOT1, @ref FLASH_OB_USER_SRAM_PE,
@ref FLASH_OB_USER_CCMSRAM_RST
@note (*) availability depends on devices */
uint32_t PCROPConfig; /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH)
and @ref FLASH_OB_PCROP_RDP */
uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
This parameter must be a value between begin and end of bank
=> Be careful of the bank swapping for the address */
uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP).
This parameter must be a value between PCROP Start address and end of bank */
uint32_t BootEntryPoint; /*!< Set the Boot Lock (used for OPTIONBYTE_BOOT_LOCK).
This parameter can be a value of @ref FLASH_OB_Boot_Lock */
uint32_t SecBank; /*!< Bank of securable memory area to be programmed (used for OPTIONBYTE_SEC).
Only one securable memory area could be programmed at the same time.
This parameter can be one of the following values:
FLASH_BANK_1: Securable memory area to be programmed in bank 1
FLASH_BANK_2: Securable memory area to be programmed in bank 2 (*)
@note (*) availability depends on devices */
uint32_t SecSize; /*!< Size of securable memory area to be programmed (used for OPTIONBYTE_SEC),
in number of pages. Securable memory area is starting from first page of the bank.
Only one securable memory could be programmed at the same time.
This parameter must be a value between 0 and (max number of pages in the bank - 1) */
} FLASH_OBProgramInitTypeDef;
/**
* @brief FLASH Procedure structure definition
*/
typedef enum
{
FLASH_PROC_NONE = 0,
FLASH_PROC_PAGE_ERASE,
FLASH_PROC_MASS_ERASE,
FLASH_PROC_PROGRAM,
FLASH_PROC_PROGRAM_LAST
} FLASH_ProcedureTypeDef;
/**
* @brief FLASH Cache structure definition
*/
typedef enum
{
FLASH_CACHE_DISABLED = 0,
FLASH_CACHE_ICACHE_ENABLED,
FLASH_CACHE_DCACHE_ENABLED,
FLASH_CACHE_ICACHE_DCACHE_ENABLED
} FLASH_CacheTypeDef;
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
HAL_LockTypeDef Lock; /* FLASH locking object */
__IO uint32_t ErrorCode; /* FLASH error code */
__IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */
__IO uint32_t Address; /* Internal variable to save address selected for program in IT context */
__IO uint32_t Bank; /* Internal variable to save current bank selected during erase in IT context */
__IO uint32_t Page; /* Internal variable to define the current page which is erasing in IT context */
__IO uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */
__IO FLASH_CacheTypeDef CacheToReactivate; /* Internal variable to indicate which caches should be reactivated */
} FLASH_ProcessTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASH_Error FLASH Error
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00000000U
#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR
#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR
#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR
#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR
#define HAL_FLASH_ERROR_MIS FLASH_FLAG_MISERR
#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC
#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
#if defined (FLASH_OPTR_DBANK)
#define HAL_FLASH_ERROR_ECCC2 FLASH_FLAG_ECCC2
#define HAL_FLASH_ERROR_ECCD2 FLASH_FLAG_ECCD2
#endif
/**
* @}
*/
/** @defgroup FLASH_Type_Erase FLASH Erase Type
* @{
*/
#define FLASH_TYPEERASE_PAGES 0x00U /*!<Pages erase only*/
#define FLASH_TYPEERASE_MASSERASE 0x01U /*!<Flash mass erase activation*/
/**
* @}
*/
/** @defgroup FLASH_Banks FLASH Banks
* @{
*/
#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */
#if defined (FLASH_OPTR_DBANK)
#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */
#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */
#else
#define FLASH_BANK_BOTH FLASH_BANK_1 /*!< Bank 1 */
#endif
/**
* @}
*/
/** @defgroup FLASH_Type_Program FLASH Program Type
* @{
*/
#define FLASH_TYPEPROGRAM_DOUBLEWORD 0x00U /*!< Program a double-word (64-bit) at a specified address.*/
#define FLASH_TYPEPROGRAM_FAST 0x01U /*!< Fast program a 32 row double-word (64-bit) at a specified address.
And another 32 row double-word (64-bit) will be programmed */
#define FLASH_TYPEPROGRAM_FAST_AND_LAST 0x02U /*!< Fast program a 32 row double-word (64-bit) at a specified address.
And this is the last 32 row double-word (64-bit) programmed */
/**
* @}
*/
/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
* @{
*/
#define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */
#define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */
#define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */
#define OPTIONBYTE_BOOT_LOCK 0x10U /*!< Boot lock option byte configuration */
#define OPTIONBYTE_SEC 0x20U /*!< Securable memory option byte configuration */
/**
* @}
*/
/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
* @{
*/
#define OB_WRPAREA_BANK1_AREAA 0x00U /*!< Flash Bank 1 Area A */
#define OB_WRPAREA_BANK1_AREAB 0x01U /*!< Flash Bank 1 Area B */
#if defined (FLASH_OPTR_DBANK)
#define OB_WRPAREA_BANK2_AREAA 0x02U /*!< Flash Bank 2 Area A */
#define OB_WRPAREA_BANK2_AREAB 0x04U /*!< Flash Bank 2 Area B */
#endif
/**
* @}
*/
/** @defgroup FLASH_OB_Boot_Lock FLASH Boot Lock
* @{
*/
#define OB_BOOT_LOCK_DISABLE 0x00000000U /*!< Boot Lock Disable */
#define OB_BOOT_LOCK_ENABLE FLASH_SEC1R_BOOT_LOCK /*!< Boot Lock Enable */
/**
* @}
*/
/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 0xAAU
#define OB_RDP_LEVEL_1 0xBBU
#define OB_RDP_LEVEL_2 0xCCU /*!< Warning: When enabling read protection level 2
it's no more possible to go back to level 1 or 0 */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
* @{
*/
#define OB_USER_BOR_LEV 0x00000001U /*!< BOR reset Level */
#define OB_USER_nRST_STOP 0x00000002U /*!< Reset generated when entering the stop mode */
#define OB_USER_nRST_STDBY 0x00000004U /*!< Reset generated when entering the standby mode */
#define OB_USER_IWDG_SW 0x00000008U /*!< Independent watchdog selection */
#define OB_USER_IWDG_STOP 0x00000010U /*!< Independent watchdog counter freeze in stop mode */
#define OB_USER_IWDG_STDBY 0x00000020U /*!< Independent watchdog counter freeze in standby mode */
#define OB_USER_WWDG_SW 0x00000040U /*!< Window watchdog selection */
#if defined (FLASH_OPTR_DBANK)
#define OB_USER_BFB2 0x00000080U /*!< Dual-bank boot */
#define OB_USER_DBANK 0x00000100U /*!< Single bank with 128-bits data or two banks with 64-bits data */
#endif
#if defined (FLASH_OPTR_PB4_PUPEN)
#define OB_USER_PB4_PUPEN 0x00000100U /*!< USB power delivery dead-battery/TDI pull-up */
#endif
#define OB_USER_nBOOT1 0x00000200U /*!< Boot configuration */
#define OB_USER_SRAM_PE 0x00000400U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
#define OB_USER_CCMSRAM_RST 0x00000800U /*!< CCMSRAM Erase when system reset */
#define OB_USER_nRST_SHDW 0x00001000U /*!< Reset generated when entering the shutdown mode */
#define OB_USER_nSWBOOT0 0x00002000U /*!< Software BOOT0 */
#define OB_USER_nBOOT0 0x00004000U /*!< nBOOT0 option bit */
#define OB_USER_NRST_MODE 0x00008000U /*!< Reset pin configuration */
#define OB_USER_IRHEN 0x00010000U /*!< Internal Reset Holder enable */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
* @{
*/
#define OB_BOR_LEVEL_0 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 1.7V */
#define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.0V */
#define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.2V */
#define OB_BOR_LEVEL_3 FLASH_OPTR_BOR_LEV_3 /*!< Reset level threshold is around 2.5V */
#define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_4 /*!< Reset level threshold is around 2.8V */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
* @{
*/
#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */
#define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
* @{
*/
#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */
#define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
* @{
*/
#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */
#define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
* @{
*/
#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
#define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
* @{
*/
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */
#define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
* @{
*/
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */
#define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
* @{
*/
#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
#define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */
/**
* @}
*/
#if defined (FLASH_OPTR_DBANK)
/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
* @{
*/
#define OB_BFB2_DISABLE 0x00000000U /*!< Dual-bank boot disable */
#define OB_BFB2_ENABLE FLASH_OPTR_BFB2 /*!< Dual-bank boot enable */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_DBANK FLASH Option Bytes User DBANK Type
* @{
*/
#define OB_DBANK_128_BITS 0x00000000U /*!< Single-bank with 128-bits data */
#define OB_DBANK_64_BITS FLASH_OPTR_DBANK /*!< Dual-bank with 64-bits data */
/**
* @}
*/
#endif
#if defined (FLASH_OPTR_PB4_PUPEN)
/** @defgroup FLASH_OB_USER_PB4_PUPEN FLASH Option Bytes User PB4 PUPEN bit
* @{
*/
#define OB_PB4_PUPEN_DISABLE 0x00000000U /*!< USB power delivery dead-battery enabled/ TDI pull-up deactivated */
#define OB_PB4_PUPEN_ENABLE FLASH_OPTR_PB4_PUPEN /*!< USB power delivery dead-battery disabled/ TDI pull-up activated */
/**
* @}
*/
#endif
/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
* @{
*/
#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
#define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_SRAM_PE FLASH Option Bytes User SRAM Parity Check Type
* @{
*/
#define OB_SRAM_PARITY_ENABLE 0x00000000U /*!< SRAM parity check enable (first 32kB of SRAM1 + CCM SRAM) */
#define OB_SRAM_PARITY_DISABLE FLASH_OPTR_SRAM_PE /*!< SRAM parity check disable (first 32kB of SRAM1 + CCM SRAM) */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_CCMSRAM_RST FLASH Option Bytes User CCMSRAM Erase On Reset Type
* @{
*/
#define OB_CCMSRAM_RST_ERASE 0x00000000U /*!< CCMSRAM erased when a system reset occurs */
#define OB_CCMSRAM_RST_NOT_ERASE FLASH_OPTR_CCMSRAM_RST /*!< CCMSRAM is not erased when a system reset occurs */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
* @{
*/
#define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */
#define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PB8/BOOT0 pin */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
* @{
*/
#define OB_nBOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */
#define OB_nBOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_NRST_MODE FLASH Option Bytes User NRST mode bit
* @{
*/
#define OB_NRST_MODE_INPUT_ONLY FLASH_OPTR_NRST_MODE_0 /*!< Reset pin is in Reset input mode only */
#define OB_NRST_MODE_GPIO FLASH_OPTR_NRST_MODE_1 /*!< Reset pin is in GPIO mode only */
#define OB_NRST_MODE_INPUT_OUTPUT FLASH_OPTR_NRST_MODE /*!< Reset pin is in reset input and output mode */
/**
* @}
*/
/** @defgroup FLASH_OB_USER_INTERNAL_RESET_HOLDER FLASH Option Bytes User internal reset holder bit
* @{
*/
#define OB_IRH_DISABLE 0x00000000U /*!< Internal Reset holder disable */
#define OB_IRH_ENABLE FLASH_OPTR_IRHEN /*!< Internal Reset holder enable */
/**
* @}
*/
/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
* @{
*/
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
is decreased from Level 1 to Level 0 */
#define OB_PCROP_RDP_ERASE FLASH_PCROP1ER_PCROP_RDP /*!< PCROP area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */
/**
* @}
*/
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait state */
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait state */
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait states */
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait state */
#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait state */
#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait states */
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait states */
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait states */
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait states */
/**
* @}
*/
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_KEY1 0x45670123U /*!< Flash key1 */
#define FLASH_KEY2 0xCDEF89ABU /*!< Flash key2: used with FLASH_KEY1
to unlock the FLASH registers access */
#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
#define FLASH_OPTKEY1 0x08192A3BU /*!< Flash option byte key1 */
#define FLASH_OPTKEY2 0x4C5D6E7FU /*!< Flash option byte key2: used with FLASH_OPTKEY1
to allow option bytes operations */
/**
* @}
*/
/** @defgroup FLASH_Flags FLASH Flags Definition
* @{
*/
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of operation flag */
#define FLASH_FLAG_OPERR FLASH_SR_OPERR /*!< FLASH Operation error flag */
#define FLASH_FLAG_PROGERR FLASH_SR_PROGERR /*!< FLASH Programming error flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protection error flag */
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming alignment error flag */
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Programming sequence error flag */
#define FLASH_FLAG_MISERR FLASH_SR_MISERR /*!< FLASH Fast programming data miss error flag */
#define FLASH_FLAG_FASTERR FLASH_SR_FASTERR /*!< FLASH Fast programming error flag */
#define FLASH_FLAG_RDERR FLASH_SR_RDERR /*!< FLASH PCROP read error flag */
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option validity error flag */
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction in 64 LSB bits */
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection in 64 LSB bits */
#if defined (FLASH_OPTR_DBANK)
#define FLASH_FLAG_ECCC2 FLASH_ECCR_ECCC2 /*!< FLASH ECC correction in 64 MSB bits (mode 128 bits only) */
#define FLASH_FLAG_ECCD2 FLASH_ECCR_ECCD2 /*!< FLASH ECC detection in 64 MSB bits (mode 128 bits only) */
#endif
#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
FLASH_FLAG_OPTVERR)
#if defined (FLASH_OPTR_DBANK)
#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD | FLASH_FLAG_ECCC2 | FLASH_FLAG_ECCD2)
#else
#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
#endif
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
/**
* @}
*/
/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
* @brief FLASH Interrupt definition
* @{
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_OPERR FLASH_CR_ERRIE /*!< Error Interrupt source */
#define FLASH_IT_RDERR FLASH_CR_RDERRIE /*!< PCROP Read Error Interrupt source*/
#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24U) /*!< ECC Correction Interrupt source */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @brief macros to control FLASH features
* @{
*/
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__ FLASH Latency.
* This parameter can be one of the following values :
* @arg FLASH_LATENCY_0: FLASH Zero wait state
* @arg FLASH_LATENCY_1: FLASH One wait state
* @arg FLASH_LATENCY_2: FLASH Two wait states
* @arg FLASH_LATENCY_3: FLASH Three wait states
* @arg FLASH_LATENCY_4: FLASH Four wait states
* @arg FLASH_LATENCY_5: FLASH Five wait states
* @arg FLASH_LATENCY_6: FLASH Six wait states
* @arg FLASH_LATENCY_7: FLASH Seven wait states
* @arg FLASH_LATENCY_8: FLASH Eight wait states
* @arg FLASH_LATENCY_9: FLASH Nine wait states
* @arg FLASH_LATENCY_10: FLASH Ten wait state
* @arg FLASH_LATENCY_11: FLASH Eleven wait state
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
* @retval None
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH_Latency.
* This parameter can be one of the following values :
* @arg FLASH_LATENCY_0: FLASH Zero wait state
* @arg FLASH_LATENCY_1: FLASH One wait state
* @arg FLASH_LATENCY_2: FLASH Two wait states
* @arg FLASH_LATENCY_3: FLASH Three wait states
* @arg FLASH_LATENCY_4: FLASH Four wait states
* @arg FLASH_LATENCY_5: FLASH Five wait states
* @arg FLASH_LATENCY_6: FLASH Six wait states
* @arg FLASH_LATENCY_7: FLASH Seven wait states
* @arg FLASH_LATENCY_8: FLASH Eight wait states
* @arg FLASH_LATENCY_9: FLASH Nine wait states
* @arg FLASH_LATENCY_10: FLASH Ten wait state
* @arg FLASH_LATENCY_11: FLASH Eleven wait state
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
*/
#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
/**
* @brief Enable the FLASH prefetch buffer.
* @retval None
*/
#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
/**
* @brief Disable the FLASH prefetch buffer.
* @retval None
*/
#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
/**
* @brief Enable the FLASH instruction cache.
* @retval none
*/
#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
/**
* @brief Disable the FLASH instruction cache.
* @retval none
*/
#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
/**
* @brief Enable the FLASH data cache.
* @retval none
*/
#define __HAL_FLASH_DATA_CACHE_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
/**
* @brief Disable the FLASH data cache.
* @retval none
*/
#define __HAL_FLASH_DATA_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
/**
* @brief Reset the FLASH instruction Cache.
* @note This function must be used only when the Instruction Cache is disabled.
* @retval None
*/
#define __HAL_FLASH_INSTRUCTION_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
} while (0)
/**
* @brief Reset the FLASH data Cache.
* @note This function must be used only when the data Cache is disabled.
* @retval None
*/
#define __HAL_FLASH_DATA_CACHE_RESET() do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
} while (0)
/**
* @brief Enable the FLASH power down during Low-power run mode.
* @note Writing this bit to 1, automatically the keys are
* lost and a new unlock sequence is necessary to re-write it to 0.
*/
#define __HAL_FLASH_POWER_DOWN_ENABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
} while (0)
/**
* @brief Disable the FLASH power down during Low-power run mode.
* @note Writing this bit to 0, automatically the keys are
* lost and a new unlock sequence is necessary to re-write it to 1.
*/
#define __HAL_FLASH_POWER_DOWN_DISABLE() do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
} while (0)
/**
* @brief Enable the FLASH power down during Low-Power sleep mode
* @retval none
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
/**
* @brief Disable the FLASH power down during Low-Power sleep mode
* @retval none
*/
#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
/**
* @}
*/
/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
* @brief macros to handle FLASH interrupts
* @{
*/
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_OPERR: Error Interrupt
* @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
* @arg FLASH_IT_ECCC: ECC Correction Interrupt
* @retval none
*/
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
} while (0)
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_OPERR: Error Interrupt
* @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
* @arg FLASH_IT_ECCC: ECC Correction Interrupt
* @retval none
*/
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
} while (0)
/**
* @brief Check whether the specified FLASH flag is set or not.
* @param __FLAG__ specifies the FLASH flag to check.
* This parameter can be one of the following values:
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR: FLASH Operation error flag
* @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
* @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
* @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
* @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
* @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
* @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
* @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
* @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
* @note (*) availability depends on devices
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) ? \
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
/**
* @brief Clear the FLASH's pending flags.
* @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP: FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR: FLASH Operation error flag
* @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
* @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag
* @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
* @arg FLASH_FLAG_SIZERR: FLASH Size error flag
* @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
* @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
* @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
* @arg FLASH_FLAG_RDERR: FLASH PCROP read error flag
* @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
* @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected in 64 LSB bits
* @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected in 64 LSB bits
* @arg FLASH_FLAG_ECCC2(*): FLASH one ECC error has been detected and corrected in 64 MSB bits (mode 128 bits only)
* @arg FLASH_FLAG_ECCD2(*): FLASH two ECC errors have been detected in 64 MSB bits (mode 128 bits only)
* @arg FLASH_FLAG_SR_ERRORS: FLASH All SR errors flags
* @arg FLASH_FLAG_ECCR_ERRORS: FLASH All ECCR errors flags
* @note (*) availability depends on devices
* @retval None
*/
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
} while (0)
/**
* @}
*/
/* Include FLASH HAL Extended module */
#include "stm32g4xx_hal_flash_ex.h"
#include "stm32g4xx_hal_flash_ramfunc.h"
/* Exported variables --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Variables FLASH Exported Variables
* @{
*/
extern FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/* Program operation functions ***********************************************/
/** @addtogroup FLASH_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
/* FLASH IRQ handler method */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
/* Peripheral Control functions **********************************************/
/** @addtogroup FLASH_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
/* Option bytes control */
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
/**
* @}
*/
/* Peripheral State functions ************************************************/
/** @addtogroup FLASH_Exported_Functions_Group3
* @{
*/
uint32_t HAL_FLASH_GetError(void);
/**
* @}
*/
/**
* @}
*/
/** @addtogroup FLASH_Private_Functions
* @{
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
#define FLASH_SIZE_DATA_REGISTER FLASHSIZE_BASE
#if defined (FLASH_OPTR_DBANK)
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x200UL << 10U) : \
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
#define FLASH_BANK_SIZE (FLASH_SIZE >> 1)
#define FLASH_PAGE_NB 128U
#define FLASH_PAGE_SIZE_128_BITS 0x1000U /* 4 KB */
#else
#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? (0x80UL << 10U) : \
(((*((uint32_t *)FLASH_SIZE_DATA_REGISTER)) & 0xFFFFUL) << 10U))
#define FLASH_BANK_SIZE (FLASH_SIZE)
#define FLASH_PAGE_NB ((FLASH_SIZE == 0x00080000U) ? 256U : \
((FLASH_SIZE == 0x00040000U) ? 128U : 64U))
#endif
#define FLASH_PAGE_SIZE 0x800U /* 2 KB */
#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \
((VALUE) == FLASH_TYPEERASE_MASSERASE))
#if defined (FLASH_OPTR_DBANK)
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2))
#else
#define IS_FLASH_BANK(BANK) ((BANK) == FLASH_BANK_1)
#define IS_FLASH_BANK_EXCLUSIVE(BANK) ((BANK) == FLASH_BANK_1)
#endif
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))
#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= 0x1FFF7000U) && ((ADDRESS) <= 0x1FFF73FFU))
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB)
#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \
OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_SEC)))
#if defined (FLASH_OPTR_DBANK)
#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
#else
#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB))
#endif
#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_ENABLE) || ((VALUE) == OB_BOOT_LOCK_DISABLE))
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1) ||\
((LEVEL) == OB_RDP_LEVEL_2))
#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFU) && ((TYPE) != 0U))
#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
((LEVEL) == OB_BOR_LEVEL_4))
#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
#if defined (FLASH_OPTR_DBANK)
#define IS_OB_USER_BFB2(VALUE) (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
#define IS_OB_USER_DBANK(VALUE) (((VALUE) == OB_DBANK_128_BITS) || ((VALUE) == OB_DBANK_64_BITS))
#endif
#if defined (FLASH_OPTR_PB4_PUPEN)
#define IS_OB_USER_PB4_PUPEN(VALUE) (((VALUE) == OB_PB4_PUPEN_DISABLE) || ((VALUE) == OB_PB4_PUPEN_ENABLE))
#endif
#define IS_OB_USER_BOOT1(VALUE) (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
#define IS_OB_USER_SRAM_PARITY(VALUE) (((VALUE) == OB_SRAM_PARITY_ENABLE) || ((VALUE) == OB_SRAM_PARITY_DISABLE))
#define IS_OB_USER_CCMSRAM_RST(VALUE) (((VALUE) == OB_CCMSRAM_RST_ERASE) || ((VALUE) == OB_CCMSRAM_RST_NOT_ERASE))
#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN))
#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_nBOOT0_RESET) || ((VALUE) == OB_nBOOT0_SET))
#define IS_OB_USER_NRST_MODE(VALUE) (((VALUE) == OB_NRST_MODE_GPIO) || ((VALUE) == OB_NRST_MODE_INPUT_ONLY) || \
((VALUE) == OB_NRST_MODE_INPUT_OUTPUT))
#define IS_OB_USER_IRHEN(VALUE) (((VALUE) == OB_IRH_ENABLE) || ((VALUE) == OB_IRH_DISABLE))
#define IS_OB_PCROP_RDP(VALUE) (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
#define IS_OB_SECMEM_SIZE(VALUE) ((VALUE) <= FLASH_PAGE_NB)
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \
((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \
((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \
((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \
((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \
((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_FLASH_H */
| 46,573 | C | 44.750491 | 172 | 0.564748 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dma.h | /**
******************************************************************************
* @file stm32g4xx_ll_dma.h
* @author MCD Application Team
* @brief Header file of DMA LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_DMA_H
#define __STM32G4xx_LL_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
#include "stm32g4xx_ll_dmamux.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (DMA1) || defined (DMA2)
/** @defgroup DMA_LL DMA
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup DMA_LL_Private_Variables DMA Private Variables
* @{
*/
/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
static const uint8_t CHANNEL_OFFSET_TAB[] =
{
(uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
(uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
(uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
(uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
(uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
(uint8_t)(DMA1_Channel6_BASE - DMA1_BASE)
#if defined (DMA1_Channel7)
,
(uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
,
(uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
#endif /* DMA1_Channel8 */
};
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DMA_LL_Private_Constants DMA Private Constants
* @{
*/
/* Define used to get CSELR register offset */
#define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
/* Defines used for the bit position in the register and perform offsets */
#define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DMA_LL_Private_Macros DMA Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
* @{
*/
typedef struct
{
uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
or as Source base address in case of memory to memory transfer direction.
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
or as Destination base address in case of memory to memory transfer direction.
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
This parameter can be a value of @ref DMA_LL_EC_DIRECTION
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
uint32_t Mode; /*!< Specifies the normal or circular operation mode.
This parameter can be a value of @ref DMA_LL_EC_MODE
@note: The circular buffer mode cannot be used if the memory to memory
data transfer direction is configured on the selected Channel
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
is incremented or not.
This parameter can be a value of @ref DMA_LL_EC_PERIPH
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
is incremented or not.
This parameter can be a value of @ref DMA_LL_EC_MEMORY
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
in case of memory to memory transfer direction.
This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
in case of memory to memory transfer direction.
This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
The data unit is equal to the source buffer configuration set in PeripheralSize
or MemorySize parameters depending in the transfer direction.
This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
uint32_t Priority; /*!< Specifies the channel priority level.
This parameter can be a value of @ref DMA_LL_EC_PRIORITY
This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
} LL_DMA_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
* @{
*/
/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_DMA_WriteReg function
* @{
*/
#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
#define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
#define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
#define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
#define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
#define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
#define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
#define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
#define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
#define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
#define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
#define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
#define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
#if defined (DMA1_Channel7)
#define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
#define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
#define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
#define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
#define LL_DMA_IFCR_CGIF8 DMA_IFCR_CGIF8 /*!< Channel 8 global flag */
#define LL_DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8 /*!< Channel 8 transfer complete flag */
#define LL_DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8 /*!< Channel 8 half transfer flag */
#define LL_DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8 /*!< Channel 8 transfer error flag */
#endif /* DMA1_Channel8 */
/**
* @}
*/
/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_DMA_ReadReg function
* @{
*/
#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
#define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
#define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
#define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
#define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
#define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
#define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
#define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
#define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
#define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
#define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
#define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
#define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
#if defined (DMA1_Channel7)
#define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
#define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
#define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
#define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
#define LL_DMA_ISR_GIF8 DMA_ISR_GIF8 /*!< Channel 8 global flag */
#define LL_DMA_ISR_TCIF8 DMA_ISR_TCIF8 /*!< Channel 8 transfer complete flag */
#define LL_DMA_ISR_HTIF8 DMA_ISR_HTIF8 /*!< Channel 8 half transfer flag */
#define LL_DMA_ISR_TEIF8 DMA_ISR_TEIF8 /*!< Channel 8 transfer error flag */
#endif /* DMA1_Channel8 */
/**
* @}
*/
/** @defgroup DMA_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
* @{
*/
#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
/**
* @}
*/
/** @defgroup DMA_LL_EC_CHANNEL CHANNEL
* @{
*/
#define LL_DMA_CHANNEL_1 0x00000000U /*!< DMA Channel 1 */
#define LL_DMA_CHANNEL_2 0x00000001U /*!< DMA Channel 2 */
#define LL_DMA_CHANNEL_3 0x00000002U /*!< DMA Channel 3 */
#define LL_DMA_CHANNEL_4 0x00000003U /*!< DMA Channel 4 */
#define LL_DMA_CHANNEL_5 0x00000004U /*!< DMA Channel 5 */
#define LL_DMA_CHANNEL_6 0x00000005U /*!< DMA Channel 6 */
#if defined (DMA1_Channel7)
#define LL_DMA_CHANNEL_7 0x00000006U /*!< DMA Channel 7 */
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
#define LL_DMA_CHANNEL_8 0x00000007U /*!< DMA Channel 8 */
#endif /* DMA1_Channel8 */
#if defined(USE_FULL_LL_DRIVER)
#define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
* @{
*/
#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
/**
* @}
*/
/** @defgroup DMA_LL_EC_MODE Transfer mode
* @{
*/
#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
/**
* @}
*/
/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
* @{
*/
#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_LL_EC_MEMORY Memory increment mode
* @{
*/
#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
/**
* @}
*/
/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
* @{
*/
#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
* @{
*/
#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
/**
* @}
*/
/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
* @{
*/
#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
* @{
*/
/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
* @{
*/
/**
* @brief Write a value in DMA register
* @param __INSTANCE__ DMA Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in DMA register
* @param __INSTANCE__ DMA Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
* @{
*/
/**
* @brief Convert DMAx_Channely into DMAx
* @param __CHANNEL_INSTANCE__ DMAx_Channely
* @retval DMAx
*/
#if defined (DMA1_Channel8)
#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel8)) ? DMA2 : DMA1)
#else
#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ? DMA2 : DMA1)
#endif /* DMA1_Channel8 */
/**
* @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
* @param __CHANNEL_INSTANCE__ DMAx_Channely
* @retval LL_DMA_CHANNEL_y
*/
#if defined (DMA1_Channel8)
#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel7)) ? LL_DMA_CHANNEL_7 : \
LL_DMA_CHANNEL_8)
#else
#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
LL_DMA_CHANNEL_6)
#endif /* DMA1_Channel8 */
/**
* @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
* @param __DMA_INSTANCE__ DMAx
* @param __CHANNEL__ LL_DMA_CHANNEL_y
* @retval DMAx_Channely
*/
#if defined (DMA1_Channel8)
#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA2_Channel7 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) ? DMA1_Channel8 : \
DMA2_Channel8)
#else
#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
DMA2_Channel6)
#endif /* DMA1_Channel8 */
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
* @{
*/
/** @defgroup DMA_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable DMA channel.
* @rmtoll CCR EN LL_DMA_EnableChannel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
}
/**
* @brief Disable DMA channel.
* @rmtoll CCR EN LL_DMA_DisableChannel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_EN);
}
/**
* @brief Check if DMA channel is enabled or disabled.
* @rmtoll CCR EN LL_DMA_IsEnabledChannel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
}
/**
* @brief Configure all parameters link to DMA transfer.
* @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
* CCR MEM2MEM LL_DMA_ConfigTransfer\n
* CCR CIRC LL_DMA_ConfigTransfer\n
* CCR PINC LL_DMA_ConfigTransfer\n
* CCR MINC LL_DMA_ConfigTransfer\n
* CCR PSIZE LL_DMA_ConfigTransfer\n
* CCR MSIZE LL_DMA_ConfigTransfer\n
* CCR PL LL_DMA_ConfigTransfer
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param Configuration This parameter must be a combination of all the following values:
* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
* @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
* @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
* @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
* @retval None
*/
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
Configuration);
}
/**
* @brief Set Data transfer direction (read from peripheral or from memory).
* @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
* CCR MEM2MEM LL_DMA_SetDataTransferDirection
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
}
/**
* @brief Get Data transfer direction (read from peripheral or from memory).
* @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
* CCR MEM2MEM LL_DMA_GetDataTransferDirection
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
*/
__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
}
/**
* @brief Set DMA mode circular or normal.
* @note The circular buffer mode cannot be used if the memory-to-memory
* data transfer is configured on the selected Channel.
* @rmtoll CCR CIRC LL_DMA_SetMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_DMA_MODE_NORMAL
* @arg @ref LL_DMA_MODE_CIRCULAR
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_CIRC,
Mode);
}
/**
* @brief Get DMA mode circular or normal.
* @rmtoll CCR CIRC LL_DMA_GetMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_MODE_NORMAL
* @arg @ref LL_DMA_MODE_CIRCULAR
*/
__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_CIRC));
}
/**
* @brief Set Peripheral increment mode.
* @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
* @arg @ref LL_DMA_PERIPH_INCREMENT
* @arg @ref LL_DMA_PERIPH_NOINCREMENT
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PINC,
PeriphOrM2MSrcIncMode);
}
/**
* @brief Get Peripheral increment mode.
* @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_PERIPH_INCREMENT
* @arg @ref LL_DMA_PERIPH_NOINCREMENT
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_PINC));
}
/**
* @brief Set Memory increment mode.
* @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
* @arg @ref LL_DMA_MEMORY_INCREMENT
* @arg @ref LL_DMA_MEMORY_NOINCREMENT
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MINC,
MemoryOrM2MDstIncMode);
}
/**
* @brief Get Memory increment mode.
* @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_MEMORY_INCREMENT
* @arg @ref LL_DMA_MEMORY_NOINCREMENT
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_MINC));
}
/**
* @brief Set Peripheral size.
* @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
* @arg @ref LL_DMA_PDATAALIGN_BYTE
* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
* @arg @ref LL_DMA_PDATAALIGN_WORD
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PSIZE,
PeriphOrM2MSrcDataSize);
}
/**
* @brief Get Peripheral size.
* @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_PDATAALIGN_BYTE
* @arg @ref LL_DMA_PDATAALIGN_HALFWORD
* @arg @ref LL_DMA_PDATAALIGN_WORD
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_PSIZE));
}
/**
* @brief Set Memory size.
* @rmtoll CCR MSIZE LL_DMA_SetMemorySize
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
* @arg @ref LL_DMA_MDATAALIGN_BYTE
* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
* @arg @ref LL_DMA_MDATAALIGN_WORD
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_MSIZE,
MemoryOrM2MDstDataSize);
}
/**
* @brief Get Memory size.
* @rmtoll CCR MSIZE LL_DMA_GetMemorySize
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_MDATAALIGN_BYTE
* @arg @ref LL_DMA_MDATAALIGN_HALFWORD
* @arg @ref LL_DMA_MDATAALIGN_WORD
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_MSIZE));
}
/**
* @brief Set Channel priority level.
* @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param Priority This parameter can be one of the following values:
* @arg @ref LL_DMA_PRIORITY_LOW
* @arg @ref LL_DMA_PRIORITY_MEDIUM
* @arg @ref LL_DMA_PRIORITY_HIGH
* @arg @ref LL_DMA_PRIORITY_VERYHIGH
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_PL,
Priority);
}
/**
* @brief Get Channel priority level.
* @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMA_PRIORITY_LOW
* @arg @ref LL_DMA_PRIORITY_MEDIUM
* @arg @ref LL_DMA_PRIORITY_HIGH
* @arg @ref LL_DMA_PRIORITY_VERYHIGH
*/
__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_PL));
}
/**
* @brief Set Number of data to transfer.
* @note This action has no effect if
* channel is enabled.
* @rmtoll CNDTR NDT LL_DMA_SetDataLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
DMA_CNDTR_NDT, NbData);
}
/**
* @brief Get Number of data to transfer.
* @note Once the channel is enabled, the return value indicate the
* remaining bytes to be transmitted.
* @rmtoll CNDTR NDT LL_DMA_GetDataLength
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CNDTR,
DMA_CNDTR_NDT));
}
/**
* @brief Configure the Source and Destination addresses.
* @note This API must not be called when the DMA channel is enabled.
* @note Each IP using DMA provides an API to get directly the register address (LL_PPP_DMA_GetRegAddr).
* @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
* CMAR MA LL_DMA_ConfigAddresses
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
* @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
* @param Direction This parameter can be one of the following values:
* @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
* @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
* @retval None
*/
__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
uint32_t DstAddress, uint32_t Direction)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
/* Direction Memory to Periph */
if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
{
WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, SrcAddress);
WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, DstAddress);
}
/* Direction Periph to Memory and Memory to Memory */
else
{
WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, SrcAddress);
WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, DstAddress);
}
}
/**
* @brief Set the Memory address.
* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
* @note This API must not be called when the DMA channel is enabled.
* @rmtoll CMAR MA LL_DMA_SetMemoryAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
}
/**
* @brief Set the Peripheral address.
* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
* @note This API must not be called when the DMA channel is enabled.
* @rmtoll CPAR PA LL_DMA_SetPeriphAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, PeriphAddress);
}
/**
* @brief Get Memory address.
* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
* @rmtoll CMAR MA LL_DMA_GetMemoryAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
}
/**
* @brief Get Peripheral address.
* @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
* @rmtoll CPAR PA LL_DMA_GetPeriphAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
}
/**
* @brief Set the Memory to Memory Source address.
* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
* @note This API must not be called when the DMA channel is enabled.
* @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR, MemoryAddress);
}
/**
* @brief Set the Memory to Memory Destination address.
* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
* @note This API must not be called when the DMA channel is enabled.
* @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR, MemoryAddress);
}
/**
* @brief Get the Memory to Memory Source address.
* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
* @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CPAR));
}
/**
* @brief Get the Memory to Memory Destination address.
* @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
* @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CMAR));
}
/**
* @brief Set DMA request for DMA instance on Channel x.
* @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
* @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
* CSELR C2S LL_DMA_SetPeriphRequest\n
* CSELR C3S LL_DMA_SetPeriphRequest\n
* CSELR C4S LL_DMA_SetPeriphRequest\n
* CSELR C5S LL_DMA_SetPeriphRequest\n
* CSELR C6S LL_DMA_SetPeriphRequest\n
* CSELR C7S LL_DMA_SetPeriphRequest
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @param PeriphRequest This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_MEM2MEM
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR1
* @arg @ref LL_DMAMUX_REQ_GENERATOR2
* @arg @ref LL_DMAMUX_REQ_GENERATOR3
* @arg @ref LL_DMAMUX_REQ_ADC1
* @arg @ref LL_DMAMUX_REQ_DAC1_CH1
* @arg @ref LL_DMAMUX_REQ_DAC1_CH2
* @arg @ref LL_DMAMUX_REQ_TIM6_UP
* @arg @ref LL_DMAMUX_REQ_TIM7_UP
* @arg @ref LL_DMAMUX_REQ_SPI1_RX
* @arg @ref LL_DMAMUX_REQ_SPI1_TX
* @arg @ref LL_DMAMUX_REQ_SPI2_RX
* @arg @ref LL_DMAMUX_REQ_SPI2_TX
* @arg @ref LL_DMAMUX_REQ_SPI3_RX
* @arg @ref LL_DMAMUX_REQ_SPI3_TX
* @arg @ref LL_DMAMUX_REQ_I2C1_RX
* @arg @ref LL_DMAMUX_REQ_I2C1_TX
* @arg @ref LL_DMAMUX_REQ_I2C2_RX
* @arg @ref LL_DMAMUX_REQ_I2C2_TX
* @arg @ref LL_DMAMUX_REQ_I2C3_RX
* @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
* @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
* @arg @ref LL_DMAMUX_REQ_I2C4_TX
* @arg @ref LL_DMAMUX_REQ_USART1_RX
* @arg @ref LL_DMAMUX_REQ_USART1_TX
* @arg @ref LL_DMAMUX_REQ_USART2_RX
* @arg @ref LL_DMAMUX_REQ_USART2_TX
* @arg @ref LL_DMAMUX_REQ_USART3_RX
* @arg @ref LL_DMAMUX_REQ_USART3_TX
* @arg @ref LL_DMAMUX_REQ_UART4_RX
* @arg @ref LL_DMAMUX_REQ_UART4_TX
* @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
* @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
* @arg @ref LL_DMAMUX_REQ_LPUART1_RX
* @arg @ref LL_DMAMUX_REQ_LPUART1_TX
* @arg @ref LL_DMAMUX_REQ_ADC2
* @arg @ref LL_DMAMUX_REQ_ADC3 (*)
* @arg @ref LL_DMAMUX_REQ_ADC4 (*)
* @arg @ref LL_DMAMUX_REQ_ADC5 (*)
* @arg @ref LL_DMAMUX_REQ_QSPI (*)
* @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM1_CH1
* @arg @ref LL_DMAMUX_REQ_TIM1_CH2
* @arg @ref LL_DMAMUX_REQ_TIM1_CH3
* @arg @ref LL_DMAMUX_REQ_TIM1_CH4
* @arg @ref LL_DMAMUX_REQ_TIM1_UP
* @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM1_COM
* @arg @ref LL_DMAMUX_REQ_TIM8_CH1
* @arg @ref LL_DMAMUX_REQ_TIM8_CH2
* @arg @ref LL_DMAMUX_REQ_TIM8_CH3
* @arg @ref LL_DMAMUX_REQ_TIM8_CH4
* @arg @ref LL_DMAMUX_REQ_TIM8_UP
* @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM8_COM
* @arg @ref LL_DMAMUX_REQ_TIM2_CH1
* @arg @ref LL_DMAMUX_REQ_TIM2_CH2
* @arg @ref LL_DMAMUX_REQ_TIM2_CH3
* @arg @ref LL_DMAMUX_REQ_TIM2_CH4
* @arg @ref LL_DMAMUX_REQ_TIM2_UP
* @arg @ref LL_DMAMUX_REQ_TIM3_CH1
* @arg @ref LL_DMAMUX_REQ_TIM3_CH2
* @arg @ref LL_DMAMUX_REQ_TIM3_CH3
* @arg @ref LL_DMAMUX_REQ_TIM3_CH4
* @arg @ref LL_DMAMUX_REQ_TIM3_UP
* @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM4_CH1
* @arg @ref LL_DMAMUX_REQ_TIM4_CH2
* @arg @ref LL_DMAMUX_REQ_TIM4_CH3
* @arg @ref LL_DMAMUX_REQ_TIM4_CH4
* @arg @ref LL_DMAMUX_REQ_TIM4_UP
* @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
* @arg @ref LL_DMAMUX_REQ_TIM15_CH1
* @arg @ref LL_DMAMUX_REQ_TIM15_UP
* @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM15_COM
* @arg @ref LL_DMAMUX_REQ_TIM16_CH1
* @arg @ref LL_DMAMUX_REQ_TIM16_UP
* @arg @ref LL_DMAMUX_REQ_TIM17_CH1
* @arg @ref LL_DMAMUX_REQ_TIM17_UP
* @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
* @arg @ref LL_DMAMUX_REQ_AES_IN
* @arg @ref LL_DMAMUX_REQ_AES_OUT
* @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
* @arg @ref LL_DMAMUX_REQ_DAC3_CH1
* @arg @ref LL_DMAMUX_REQ_DAC3_CH2
* @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
* @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
* @arg @ref LL_DMAMUX_REQ_SAI1_A
* @arg @ref LL_DMAMUX_REQ_SAI1_B
* @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
* @arg @ref LL_DMAMUX_REQ_FMAC_READ
* @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
* @arg @ref LL_DMAMUX_REQ_CORDIC_READ
* @arg @ref LL_DMAMUX_REQ_UCPD1_RX
* @arg @ref LL_DMAMUX_REQ_UCPD1_TX
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
{
uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
}
/**
* @brief Get DMA request for DMA instance on Channel x.
* @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
* CSELR C2S LL_DMA_GetPeriphRequest\n
* CSELR C3S LL_DMA_GetPeriphRequest\n
* CSELR C4S LL_DMA_GetPeriphRequest\n
* CSELR C5S LL_DMA_GetPeriphRequest\n
* CSELR C6S LL_DMA_GetPeriphRequest\n
* CSELR C7S LL_DMA_GetPeriphRequest
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_MEM2MEM
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR1
* @arg @ref LL_DMAMUX_REQ_GENERATOR2
* @arg @ref LL_DMAMUX_REQ_GENERATOR3
* @arg @ref LL_DMAMUX_REQ_ADC1
* @arg @ref LL_DMAMUX_REQ_DAC1_CH1
* @arg @ref LL_DMAMUX_REQ_DAC1_CH2
* @arg @ref LL_DMAMUX_REQ_TIM6_UP
* @arg @ref LL_DMAMUX_REQ_TIM7_UP
* @arg @ref LL_DMAMUX_REQ_SPI1_RX
* @arg @ref LL_DMAMUX_REQ_SPI1_TX
* @arg @ref LL_DMAMUX_REQ_SPI2_RX
* @arg @ref LL_DMAMUX_REQ_SPI2_TX
* @arg @ref LL_DMAMUX_REQ_SPI3_RX
* @arg @ref LL_DMAMUX_REQ_SPI3_TX
* @arg @ref LL_DMAMUX_REQ_I2C1_RX
* @arg @ref LL_DMAMUX_REQ_I2C1_TX
* @arg @ref LL_DMAMUX_REQ_I2C2_RX
* @arg @ref LL_DMAMUX_REQ_I2C2_TX
* @arg @ref LL_DMAMUX_REQ_I2C3_RX
* @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
* @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
* @arg @ref LL_DMAMUX_REQ_I2C4_TX
* @arg @ref LL_DMAMUX_REQ_USART1_RX
* @arg @ref LL_DMAMUX_REQ_USART1_TX
* @arg @ref LL_DMAMUX_REQ_USART2_RX
* @arg @ref LL_DMAMUX_REQ_USART2_TX
* @arg @ref LL_DMAMUX_REQ_USART3_RX
* @arg @ref LL_DMAMUX_REQ_USART3_TX
* @arg @ref LL_DMAMUX_REQ_UART4_RX
* @arg @ref LL_DMAMUX_REQ_UART4_TX
* @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
* @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
* @arg @ref LL_DMAMUX_REQ_LPUART1_RX
* @arg @ref LL_DMAMUX_REQ_LPUART1_TX
* @arg @ref LL_DMAMUX_REQ_ADC2
* @arg @ref LL_DMAMUX_REQ_ADC3 (*)
* @arg @ref LL_DMAMUX_REQ_ADC4 (*)
* @arg @ref LL_DMAMUX_REQ_ADC5 (*)
* @arg @ref LL_DMAMUX_REQ_QSPI (*)
* @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM1_CH1
* @arg @ref LL_DMAMUX_REQ_TIM1_CH2
* @arg @ref LL_DMAMUX_REQ_TIM1_CH3
* @arg @ref LL_DMAMUX_REQ_TIM1_CH4
* @arg @ref LL_DMAMUX_REQ_TIM1_UP
* @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM1_COM
* @arg @ref LL_DMAMUX_REQ_TIM8_CH1
* @arg @ref LL_DMAMUX_REQ_TIM8_CH2
* @arg @ref LL_DMAMUX_REQ_TIM8_CH3
* @arg @ref LL_DMAMUX_REQ_TIM8_CH4
* @arg @ref LL_DMAMUX_REQ_TIM8_UP
* @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM8_COM
* @arg @ref LL_DMAMUX_REQ_TIM2_CH1
* @arg @ref LL_DMAMUX_REQ_TIM2_CH2
* @arg @ref LL_DMAMUX_REQ_TIM2_CH3
* @arg @ref LL_DMAMUX_REQ_TIM2_CH4
* @arg @ref LL_DMAMUX_REQ_TIM2_UP
* @arg @ref LL_DMAMUX_REQ_TIM3_CH1
* @arg @ref LL_DMAMUX_REQ_TIM3_CH2
* @arg @ref LL_DMAMUX_REQ_TIM3_CH3
* @arg @ref LL_DMAMUX_REQ_TIM3_CH4
* @arg @ref LL_DMAMUX_REQ_TIM3_UP
* @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM4_CH1
* @arg @ref LL_DMAMUX_REQ_TIM4_CH2
* @arg @ref LL_DMAMUX_REQ_TIM4_CH3
* @arg @ref LL_DMAMUX_REQ_TIM4_CH4
* @arg @ref LL_DMAMUX_REQ_TIM4_UP
* @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
* @arg @ref LL_DMAMUX_REQ_TIM15_CH1
* @arg @ref LL_DMAMUX_REQ_TIM15_UP
* @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM15_COM
* @arg @ref LL_DMAMUX_REQ_TIM16_CH1
* @arg @ref LL_DMAMUX_REQ_TIM16_UP
* @arg @ref LL_DMAMUX_REQ_TIM17_CH1
* @arg @ref LL_DMAMUX_REQ_TIM17_UP
* @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
* @arg @ref LL_DMAMUX_REQ_AES_IN
* @arg @ref LL_DMAMUX_REQ_AES_OUT
* @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
* @arg @ref LL_DMAMUX_REQ_DAC3_CH1
* @arg @ref LL_DMAMUX_REQ_DAC3_CH2
* @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
* @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
* @arg @ref LL_DMAMUX_REQ_SAI1_A
* @arg @ref LL_DMAMUX_REQ_SAI1_B
* @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
* @arg @ref LL_DMAMUX_REQ_FMAC_READ
* @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
* @arg @ref LL_DMAMUX_REQ_CORDIC_READ
* @arg @ref LL_DMAMUX_REQ_UCPD1_RX
* @arg @ref LL_DMAMUX_REQ_UCPD1_TX
* (*) Not on all G4 devices
*/
__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
}
/**
* @}
*/
/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Channel 1 global interrupt flag.
* @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 2 global interrupt flag.
* @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 3 global interrupt flag.
* @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 4 global interrupt flag.
* @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 5 global interrupt flag.
* @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 6 global interrupt flag.
* @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
}
#if defined (DMA1_Channel7)
/**
* @brief Get Channel 7 global interrupt flag.
* @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
}
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
/**
* @brief Get Channel 8 global interrupt flag.
* @rmtoll ISR GIF8 LL_DMA_IsActiveFlag_GI8
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL);
}
#endif /* DMA1_Channel8 */
/**
* @brief Get Channel 1 transfer complete flag.
* @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 2 transfer complete flag.
* @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 3 transfer complete flag.
* @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 4 transfer complete flag.
* @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 5 transfer complete flag.
* @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 6 transfer complete flag.
* @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
}
#if defined (DMA1_Channel7)
/**
* @brief Get Channel 7 transfer complete flag.
* @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
}
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
/**
* @brief Get Channel 8 transfer complete flag.
* @rmtoll ISR TCIF8 LL_DMA_IsActiveFlag_TC8
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
}
#endif /* DMA1_Channel8 */
/**
* @brief Get Channel 1 half transfer flag.
* @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 2 half transfer flag.
* @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 3 half transfer flag.
* @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 4 half transfer flag.
* @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 5 half transfer flag.
* @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 6 half transfer flag.
* @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
}
#if defined (DMA1_Channel8)
/**
* @brief Get Channel 7 half transfer flag.
* @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
}
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
/**
* @brief Get Channel 8 half transfer flag.
* @rmtoll ISR HTIF8 LL_DMA_IsActiveFlag_HT8
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
}
#endif /* DMA1_Channel8 */
/**
* @brief Get Channel 1 transfer error flag.
* @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 2 transfer error flag.
* @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 3 transfer error flag.
* @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 4 transfer error flag.
* @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 5 transfer error flag.
* @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
}
/**
* @brief Get Channel 6 transfer error flag.
* @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
}
#if defined (DMA1_Channel7)
/**
* @brief Get Channel 7 transfer error flag.
* @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
}
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
/**
* @brief Get Channel 8 transfer error flag.
* @rmtoll ISR TEIF8 LL_DMA_IsActiveFlag_TE8
* @param DMAx DMAx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx)
{
return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
}
#endif /* DMA1_Channel8 */
/**
* @brief Clear Channel 1 global interrupt flag.
* @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
Instead clear specific flags transfer complete, half transfer & transfer
error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
}
/**
* @brief Clear Channel 2 global interrupt flag.
* @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
Instead clear specific flags transfer complete, half transfer & transfer
error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
}
/**
* @brief Clear Channel 3 global interrupt flag.
* @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
Instead clear specific flags transfer complete, half transfer & transfer
error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
}
/**
* @brief Clear Channel 4 global interrupt flag.
* @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
Instead clear specific flags transfer complete, half transfer & transfer
error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
}
/**
* @brief Clear Channel 5 global interrupt flag.
* @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
Instead clear specific flags transfer complete, half transfer & transfer
error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
}
/**
* @brief Clear Channel 6 global interrupt flag.
* @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
Instead clear specific flags transfer complete, half transfer & transfer
error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
}
#if defined (DMA1_Channel7)
/**
* @brief Clear Channel 7 global interrupt flag.
* @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
Instead clear specific flags transfer complete, half transfer & transfer
error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
}
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
/**
* @brief Clear Channel 8 global interrupt flag.
* @note Do not Clear Channel 8 global interrupt flag when the channel in ON.
Instead clear specific flags transfer complete, half transfer & transfer
error flag with LL_DMA_ClearFlag_TC8, LL_DMA_ClearFlag_HT8,
LL_DMA_ClearFlag_TE8. bug id 2.3.1 in Product Errata Sheet.
* @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
}
#endif /* DMA1_Channel8 */
/**
* @brief Clear Channel 1 transfer complete flag.
* @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
}
/**
* @brief Clear Channel 2 transfer complete flag.
* @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
}
/**
* @brief Clear Channel 3 transfer complete flag.
* @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
}
/**
* @brief Clear Channel 4 transfer complete flag.
* @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
}
/**
* @brief Clear Channel 5 transfer complete flag.
* @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
}
/**
* @brief Clear Channel 6 transfer complete flag.
* @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
}
#if defined (DMA1_Channel7)
/**
* @brief Clear Channel 7 transfer complete flag.
* @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
}
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
/**
* @brief Clear Channel 8 transfer complete flag.
* @rmtoll IFCR CTCIF8 LL_DMA_ClearFlag_TC8
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
}
#endif /* DMA1_Channel8 */
/**
* @brief Clear Channel 1 half transfer flag.
* @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
}
/**
* @brief Clear Channel 2 half transfer flag.
* @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
}
/**
* @brief Clear Channel 3 half transfer flag.
* @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
}
/**
* @brief Clear Channel 4 half transfer flag.
* @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
}
/**
* @brief Clear Channel 5 half transfer flag.
* @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
}
/**
* @brief Clear Channel 6 half transfer flag.
* @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
}
#if defined (DMA1_Channel7)
/**
* @brief Clear Channel 7 half transfer flag.
* @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
}
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
/**
* @brief Clear Channel 8 half transfer flag.
* @rmtoll IFCR CHTIF8 LL_DMA_ClearFlag_HT8
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
}
#endif /* DMA1_Channel8 */
/**
* @brief Clear Channel 1 transfer error flag.
* @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
}
/**
* @brief Clear Channel 2 transfer error flag.
* @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
}
/**
* @brief Clear Channel 3 transfer error flag.
* @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
}
/**
* @brief Clear Channel 4 transfer error flag.
* @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
}
/**
* @brief Clear Channel 5 transfer error flag.
* @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
}
/**
* @brief Clear Channel 6 transfer error flag.
* @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
}
#if defined (DMA1_Channel7)
/**
* @brief Clear Channel 7 transfer error flag.
* @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
}
#endif /* DMA1_Channel7 */
#if defined (DMA1_Channel8)
/**
* @brief Clear Channel 8 transfer error flag.
* @rmtoll IFCR CTEIF8 LL_DMA_ClearFlag_TE8
* @param DMAx DMAx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
{
WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
}
#endif /* DMA1_Channel8 */
/**
* @}
*/
/** @defgroup DMA_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable Transfer complete interrupt.
* @rmtoll CCR TCIE LL_DMA_EnableIT_TC
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
}
/**
* @brief Enable Half transfer interrupt.
* @rmtoll CCR HTIE LL_DMA_EnableIT_HT
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
}
/**
* @brief Enable Transfer error interrupt.
* @rmtoll CCR TEIE LL_DMA_EnableIT_TE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
}
/**
* @brief Disable Transfer complete interrupt.
* @rmtoll CCR TCIE LL_DMA_DisableIT_TC
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TCIE);
}
/**
* @brief Disable Half transfer interrupt.
* @rmtoll CCR HTIE LL_DMA_DisableIT_HT
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_HTIE);
}
/**
* @brief Disable Transfer error interrupt.
* @rmtoll CCR TEIE LL_DMA_DisableIT_TE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR, DMA_CCR_TEIE);
}
/**
* @brief Check if Transfer complete Interrupt is enabled.
* @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Half transfer Interrupt is enabled.
* @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
}
/**
* @brief Check if Transfer error Interrupt is enabled.
* @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
* @param DMAx DMAx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMA_CHANNEL_1
* @arg @ref LL_DMA_CHANNEL_2
* @arg @ref LL_DMA_CHANNEL_3
* @arg @ref LL_DMA_CHANNEL_4
* @arg @ref LL_DMA_CHANNEL_5
* @arg @ref LL_DMA_CHANNEL_6
* @arg @ref LL_DMA_CHANNEL_7 (*)
* @arg @ref LL_DMA_CHANNEL_8 (*)
* (*) Not on all G4 devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
{
uint32_t dma_base_addr = (uint32_t)DMAx;
return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel])))->CCR,
DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
* @{
*/
uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* DMA1 || DMA2 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_DMA_H */
| 104,723 | C | 39.606437 | 146 | 0.585497 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_usart_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_usart_ex.h
* @author MCD Application Team
* @brief Header file of USART HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_USART_EX_H
#define STM32G4xx_HAL_USART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup USARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants
* @{
*/
/** @defgroup USARTEx_Word_Length USARTEx Word Length
* @{
*/
#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */
#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */
#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */
/**
* @}
*/
/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management
* @{
*/
#define USART_NSS_HARD 0x00000000U /*!< SPI slave selection depends on NSS input pin */
#define USART_NSS_SOFT USART_CR2_DIS_NSS /*!< SPI slave is always selected and NSS input pin is ignored */
/**
* @}
*/
/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable
* @brief USART SLAVE mode
* @{
*/
#define USART_SLAVEMODE_DISABLE 0x00000000U /*!< USART SPI Slave Mode Enable */
#define USART_SLAVEMODE_ENABLE USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */
/**
* @}
*/
/** @defgroup USARTEx_FIFO_mode USARTEx FIFO mode
* @brief USART FIFO mode
* @{
*/
#define USART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define USART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level
* @brief USART TXFIFO level
* @{
*/
#define USART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */
#define USART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */
#define USART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */
#define USART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */
#define USART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */
#define USART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */
/**
* @}
*/
/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level
* @brief USART RXFIFO level
* @{
*/
#define USART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */
#define USART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */
#define USART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */
#define USART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */
#define USART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */
#define USART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup USARTEx_Private_Macros USARTEx Private Macros
* @{
*/
/** @brief Compute the USART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the USART Handle.
* @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define USART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that USART frame length is valid.
* @param __LENGTH__ USART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \
((__LENGTH__) == USART_WORDLENGTH_8B) || \
((__LENGTH__) == USART_WORDLENGTH_9B))
/**
* @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.
* @param __NSS__ USART Negative Slave Select pin management.
* @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)
*/
#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \
((__NSS__) == USART_NSS_SOFT))
/**
* @brief Ensure that USART Slave Mode is valid.
* @param __STATE__ USART Slave Mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_USART_SLAVEMODE(__STATE__) (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \
((__STATE__) == USART_SLAVEMODE_ENABLE))
/**
* @brief Ensure that USART FIFO mode is valid.
* @param __STATE__ USART FIFO mode.
* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
*/
#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \
((__STATE__) == USART_FIFOMODE_ENABLE))
/**
* @brief Ensure that USART TXFIFO threshold level is valid.
* @param __THRESHOLD__ USART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that USART RXFIFO threshold level is valid.
* @param __THRESHOLD__ USART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup USARTEx_Exported_Functions
* @{
*/
/** @addtogroup USARTEx_Exported_Functions_Group1
* @{
*/
/* IO operation functions *****************************************************/
void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);
void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);
/**
* @}
*/
/** @addtogroup USARTEx_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);
HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);
HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_USART_EX_H */
| 12,334 | C | 42.586572 | 132 | 0.446733 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rcc.h | /**
******************************************************************************
* @file stm32g4xx_hal_rcc.h
* @author MCD Application Team
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_RCC_H
#define STM32G4xx_HAL_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup RCC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RCC_Exported_Types RCC Exported Types
* @{
*/
/**
* @brief RCC PLL configuration structure definition
*/
typedef struct
{
uint32_t PLLState; /*!< The new state of the PLL.
This parameter can be a value of @ref RCC_PLL_Config */
uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
This parameter must be a value of @ref RCC_PLL_Clock_Source */
uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
This parameter must be a value of @ref RCC_PLLM_Clock_Divider */
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 8 and Max_Data = 127 */
uint32_t PLLP; /*!< PLLP: Division factor for ADC clock.
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
uint32_t PLLQ; /*!< PLLQ: Division factor for SAI, I2S, USB, FDCAN and QUADSPI clocks.
This parameter must be a value of @ref RCC_PLLQ_Clock_Divider */
uint32_t PLLR; /*!< PLLR: Division for the main system clock.
User have to set the PLLR parameter correctly to not exceed max frequency 170MHZ.
This parameter must be a value of @ref RCC_PLLR_Clock_Divider */
}RCC_PLLInitTypeDef;
/**
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
typedef struct
{
uint32_t OscillatorType; /*!< The oscillators to be configured.
This parameter can be a value of @ref RCC_Oscillator_Type */
uint32_t HSEState; /*!< The new state of the HSE.
This parameter can be a value of @ref RCC_HSE_Config */
uint32_t LSEState; /*!< The new state of the LSE.
This parameter can be a value of @ref RCC_LSE_Config */
uint32_t HSIState; /*!< The new state of the HSI.
This parameter can be a value of @ref RCC_HSI_Config */
uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
uint32_t LSIState; /*!< The new state of the LSI.
This parameter can be a value of @ref RCC_LSI_Config */
uint32_t HSI48State; /*!< The new state of the HSI48.
This parameter can be a value of @ref RCC_HSI48_Config */
RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */
}RCC_OscInitTypeDef;
/**
* @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
uint32_t ClockType; /*!< The clock to be configured.
This parameter can be a value of @ref RCC_System_Clock_Type */
uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK).
This parameter can be a value of @ref RCC_System_Clock_Source */
uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
This parameter can be a value of @ref RCC_AHB_Clock_Source */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
}RCC_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_Exported_Constants RCC Exported Constants
* @{
*/
/** @defgroup RCC_Timeout_Value Timeout Values
* @{
*/
#define RCC_DBP_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
/**
* @}
*/
/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE 0x00000000U /*!< Oscillator configuration unchanged */
#define RCC_OSCILLATORTYPE_HSE 0x00000001U /*!< HSE to configure */
#define RCC_OSCILLATORTYPE_HSI 0x00000002U /*!< HSI to configure */
#define RCC_OSCILLATORTYPE_LSE 0x00000004U /*!< LSE to configure */
#define RCC_OSCILLATORTYPE_LSI 0x00000008U /*!< LSI to configure */
#define RCC_OSCILLATORTYPE_HSI48 0x00000020U /*!< HSI48 to configure */
/**
* @}
*/
/** @defgroup RCC_HSE_Config HSE Config
* @{
*/
#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */
/**
* @}
*/
/** @defgroup RCC_LSE_Config LSE Config
* @{
*/
#define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
#define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */
/**
* @}
*/
/** @defgroup RCC_HSI_Config HSI Config
* @{
*/
#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
#define RCC_HSICALIBRATION_DEFAULT 0x40U /* Default HSI calibration trimming value */
/**
* @}
*/
/** @defgroup RCC_LSI_Config LSI Config
* @{
*/
#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
#define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
/**
* @}
*/
/** @defgroup RCC_HSI48_Config HSI48 Config
* @{
*/
#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */
#define RCC_HSI48_ON RCC_CRRCR_HSI48ON /*!< HSI48 clock activation */
/**
* @}
*/
/** @defgroup RCC_PLL_Config PLL Config
* @{
*/
#define RCC_PLL_NONE 0x00000000U /*!< PLL configuration unchanged */
#define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
#define RCC_PLL_ON 0x00000002U /*!< PLL activation */
/**
* @}
*/
/** @defgroup RCC_PLLM_Clock_Divider PLLM Clock Divider
* @{
*/
#define RCC_PLLM_DIV1 0x00000001U /*!< PLLM division factor = 1 */
#define RCC_PLLM_DIV2 0x00000002U /*!< PLLM division factor = 2 */
#define RCC_PLLM_DIV3 0x00000003U /*!< PLLM division factor = 3 */
#define RCC_PLLM_DIV4 0x00000004U /*!< PLLM division factor = 4 */
#define RCC_PLLM_DIV5 0x00000005U /*!< PLLM division factor = 5 */
#define RCC_PLLM_DIV6 0x00000006U /*!< PLLM division factor = 6 */
#define RCC_PLLM_DIV7 0x00000007U /*!< PLLM division factor = 7 */
#define RCC_PLLM_DIV8 0x00000008U /*!< PLLM division factor = 8 */
#define RCC_PLLM_DIV9 0x00000009U /*!< PLLM division factor = 9 */
#define RCC_PLLM_DIV10 0x0000000AU /*!< PLLM division factor = 10 */
#define RCC_PLLM_DIV11 0x0000000BU /*!< PLLM division factor = 11 */
#define RCC_PLLM_DIV12 0x0000000CU /*!< PLLM division factor = 12 */
#define RCC_PLLM_DIV13 0x0000000DU /*!< PLLM division factor = 13 */
#define RCC_PLLM_DIV14 0x0000000EU /*!< PLLM division factor = 14 */
#define RCC_PLLM_DIV15 0x0000000FU /*!< PLLM division factor = 15 */
#define RCC_PLLM_DIV16 0x00000010U /*!< PLLM division factor = 16 */
/**
* @}
*/
/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
* @{
*/
#define RCC_PLLP_DIV2 0x00000002U /*!< PLLP division factor = 2 */
#define RCC_PLLP_DIV3 0x00000003U /*!< PLLP division factor = 3 */
#define RCC_PLLP_DIV4 0x00000004U /*!< PLLP division factor = 4 */
#define RCC_PLLP_DIV5 0x00000005U /*!< PLLP division factor = 5 */
#define RCC_PLLP_DIV6 0x00000006U /*!< PLLP division factor = 6 */
#define RCC_PLLP_DIV7 0x00000007U /*!< PLLP division factor = 7 */
#define RCC_PLLP_DIV8 0x00000008U /*!< PLLP division factor = 8 */
#define RCC_PLLP_DIV9 0x00000009U /*!< PLLP division factor = 9 */
#define RCC_PLLP_DIV10 0x0000000AU /*!< PLLP division factor = 10 */
#define RCC_PLLP_DIV11 0x0000000BU /*!< PLLP division factor = 11 */
#define RCC_PLLP_DIV12 0x0000000CU /*!< PLLP division factor = 12 */
#define RCC_PLLP_DIV13 0x0000000DU /*!< PLLP division factor = 13 */
#define RCC_PLLP_DIV14 0x0000000EU /*!< PLLP division factor = 14 */
#define RCC_PLLP_DIV15 0x0000000FU /*!< PLLP division factor = 15 */
#define RCC_PLLP_DIV16 0x00000010U /*!< PLLP division factor = 16 */
#define RCC_PLLP_DIV17 0x00000011U /*!< PLLP division factor = 17 */
#define RCC_PLLP_DIV18 0x00000012U /*!< PLLP division factor = 18 */
#define RCC_PLLP_DIV19 0x00000013U /*!< PLLP division factor = 19 */
#define RCC_PLLP_DIV20 0x00000014U /*!< PLLP division factor = 20 */
#define RCC_PLLP_DIV21 0x00000015U /*!< PLLP division factor = 21 */
#define RCC_PLLP_DIV22 0x00000016U /*!< PLLP division factor = 22 */
#define RCC_PLLP_DIV23 0x00000017U /*!< PLLP division factor = 23 */
#define RCC_PLLP_DIV24 0x00000018U /*!< PLLP division factor = 24 */
#define RCC_PLLP_DIV25 0x00000019U /*!< PLLP division factor = 25 */
#define RCC_PLLP_DIV26 0x0000001AU /*!< PLLP division factor = 26 */
#define RCC_PLLP_DIV27 0x0000001BU /*!< PLLP division factor = 27 */
#define RCC_PLLP_DIV28 0x0000001CU /*!< PLLP division factor = 28 */
#define RCC_PLLP_DIV29 0x0000001DU /*!< PLLP division factor = 29 */
#define RCC_PLLP_DIV30 0x0000001EU /*!< PLLP division factor = 30 */
#define RCC_PLLP_DIV31 0x0000001FU /*!< PLLP division factor = 31 */
/**
* @}
*/
/** @defgroup RCC_PLLQ_Clock_Divider PLLQ Clock Divider
* @{
*/
#define RCC_PLLQ_DIV2 0x00000002U /*!< PLLQ division factor = 2 */
#define RCC_PLLQ_DIV4 0x00000004U /*!< PLLQ division factor = 4 */
#define RCC_PLLQ_DIV6 0x00000006U /*!< PLLQ division factor = 6 */
#define RCC_PLLQ_DIV8 0x00000008U /*!< PLLQ division factor = 8 */
/**
* @}
*/
/** @defgroup RCC_PLLR_Clock_Divider PLLR Clock Divider
* @{
*/
#define RCC_PLLR_DIV2 0x00000002U /*!< PLLR division factor = 2 */
#define RCC_PLLR_DIV4 0x00000004U /*!< PLLR division factor = 4 */
#define RCC_PLLR_DIV6 0x00000006U /*!< PLLR division factor = 6 */
#define RCC_PLLR_DIV8 0x00000008U /*!< PLLR division factor = 8 */
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Source PLL Clock Source
* @{
*/
#define RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock selected as PLL entry clock source */
#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */
#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
/**
* @}
*/
/** @defgroup RCC_PLL_Clock_Output PLL Clock Output
* @{
*/
#define RCC_PLL_ADCCLK RCC_PLLCFGR_PLLPEN /*!< PLLADCCLK selection from main PLL */
#define RCC_PLL_48M1CLK RCC_PLLCFGR_PLLQEN /*!< PLL48M1CLK selection from main PLL */
#define RCC_PLL_SYSCLK RCC_PLLCFGR_PLLREN /*!< PLLCLK selection from main PLL */
/**
* @}
*/
/** @defgroup RCC_System_Clock_Type System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source System Clock Source
* @{
*/
#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
/**
* @}
*/
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
* @{
*/
#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
/**
* @}
*/
/** @defgroup RCC_AHB_Clock_Source AHB Clock Source
* @{
*/
#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
/**
* @}
*/
/** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
* @{
*/
#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
/**
* @}
*/
/** @defgroup RCC_MCO_Index MCO Index
* @{
*/
/* 32 28 20 16 0
--------------------------------
| MCO | GPIO | GPIO | GPIO |
| Index | AF | Port | Pin |
-------------------------------*/
#define RCC_MCO_GPIOPORT_POS 16U
#define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS)
#define RCC_MCO_GPIOAF_POS 20U
#define RCC_MCO_GPIOAF_MASK (0xFFUL << RCC_MCO_GPIOAF_POS)
#define RCC_MCO_INDEX_POS 28U
#define RCC_MCO_INDEX_MASK (0x1UL << RCC_MCO_INDEX_POS)
#define RCC_MCO1_INDEX (0x0UL << RCC_MCO_INDEX_POS) /*!< MCO1 index */
#define RCC_MCO_PA8 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOA) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_8)
#define RCC_MCO_PG10 (RCC_MCO1_INDEX | (GPIO_AF0_MCO << RCC_MCO_GPIOAF_POS) | (GPIO_GET_INDEX(GPIOG) << RCC_MCO_GPIOPORT_POS) | GPIO_PIN_10)
/* Legacy Defines*/
#define RCC_MCO1 RCC_MCO_PA8
#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
/**
* @}
*/
/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
* @{
*/
#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */
#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
#define RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
#define RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< PLLCLK selection as MCO1 source */
#define RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
#define RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
/**
* @}
*/
/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler
* @{
*/
#define RCC_MCODIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
#define RCC_MCODIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
#define RCC_MCODIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
#define RCC_MCODIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
#define RCC_MCODIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
/**
* @}
*/
/** @defgroup RCC_Interrupt Interrupts
* @{
*/
#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */
#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
#define RCC_IT_LSECSS RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
/**
* @}
*/
/** @defgroup RCC_Flag Flags
* Elements values convention: XXXYYYYYb
* - YYYYY : Flag position in the register
* - XXX : Register index
* - 001: CR register
* - 010: BDCR register
* - 011: CSR register
* - 100: CRRCR register
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos) /*!< HSI Ready flag */
#define RCC_FLAG_HSERDY ((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos) /*!< HSE Ready flag */
#define RCC_FLAG_PLLRDY ((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos) /*!< PLL Ready flag */
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos) /*!< LSE Ready flag */
#define RCC_FLAG_LSECSSD ((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos) /*!< LSE Clock Security System Interrupt flag */
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos) /*!< LSI Ready flag */
#define RCC_FLAG_OBLRST ((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos) /*!< Option Byte Loader reset flag */
#define RCC_FLAG_PINRST ((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos) /*!< PIN reset flag */
#define RCC_FLAG_BORRST ((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos) /*!< BOR reset flag */
#define RCC_FLAG_SFTRST ((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos) /*!< Software Reset flag */
#define RCC_FLAG_IWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos) /*!< Independent Watchdog reset flag */
#define RCC_FLAG_WWDGRST ((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos) /*!< Window watchdog reset flag */
#define RCC_FLAG_LPWRRST ((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos) /*!< Low-Power reset flag */
/* Flags in the CRRCR register */
#define RCC_FLAG_HSI48RDY ((CRRCR_REG_INDEX << 5U) | RCC_CRRCR_HSI48RDY_Pos) /*!< HSI48 Ready flag */
/**
* @}
*/
/** @defgroup RCC_LSEDrive_Config LSE Drive Config
* @{
*/
#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */
#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */
#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RCC_Exported_Macros RCC Exported Macros
* @{
*/
/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
* @brief Enable or disable the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_DMAMUX1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_FMAC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_FLASH_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_DMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN)
#define __HAL_RCC_DMA2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN)
#define __HAL_RCC_DMAMUX1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN)
#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN)
#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN)
#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN)
#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN)
/**
* @}
*/
/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
* @brief Enable or disable the AHB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_ADC12_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(DAC2)
#define __HAL_RCC_DAC2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(DAC4)
#define __HAL_RCC_DAC4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN); \
UNUSED(tmpreg); \
} while(0)
#endif /* AES */
#define __HAL_RCC_RNG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN)
#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN)
#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN)
#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN)
#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN)
#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN)
#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN)
#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN)
#if defined(DAC2)
#define __HAL_RCC_DAC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN)
#if defined(DAC4)
#define __HAL_RCC_DAC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN);
#endif /* AES */
#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN)
/**
* @}
*/
/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3 Peripheral Clock Enable Disable
* @brief Enable or disable the AHB3 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); \
UNUSED(tmpreg); \
} while(0)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN); \
UNUSED(tmpreg); \
} while(0)
#endif /* QUADSPI */
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN)
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
* @brief Enable or disable the APB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(TIM5)
#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_CRS_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_USART2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_USART3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(UART4)
#define __HAL_RCC_UART4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* UART5 */
#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_USB_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN); \
UNUSED(tmpreg); \
} while(0)
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN); \
UNUSED(tmpreg); \
} while(0)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(I2C4)
#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
#if defined(TIM5)
#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN);
#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN);
#define __HAL_RCC_WWDG_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDG2EN)
#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
#if defined(UART4)
#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
#endif /* UART5 */
#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN)
#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN)
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)
#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN)
#if defined(I2C4)
#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN)
/**
* @}
*/
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
* @brief Enable or disable the APB2 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_USART1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(SPI4)
#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \
UNUSED(tmpreg); \
} while(0)
#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(TIM20)
#define __HAL_RCC_TIM20_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \
UNUSED(tmpreg); \
} while(0)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_CLK_ENABLE() do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN); \
UNUSED(tmpreg); \
} while(0)
#endif /* HRTIM1 */
#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN)
#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN)
#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN)
#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN)
#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN)
#if defined(SPI4)
#define __HAL_RCC_SPI4_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN)
#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN)
#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN)
#if defined(TIM20)
#define __HAL_RCC_TIM20_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN)
#endif /* HRTIM1 */
/**
* @}
*/
/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status
* @brief Check whether the AHB1 peripheral clock is enabled or not.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_DMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) != 0U)
#define __HAL_RCC_DMA2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) != 0U)
#define __HAL_RCC_DMAMUX1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) != 0U)
#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U)
#define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U)
#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U)
#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U)
#define __HAL_RCC_DMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN) == 0U)
#define __HAL_RCC_DMA2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN) == 0U)
#define __HAL_RCC_DMAMUX1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN) == 0U)
#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U)
#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U)
#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U)
#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U)
/**
* @}
*/
/** @defgroup RCC_AHB2_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status
* @brief Check whether the AHB2 peripheral clock is enabled or not.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) != 0U)
#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) != 0U)
#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) != 0U)
#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) != 0U)
#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) != 0U)
#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) != 0U)
#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) != 0U)
#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) != 0U)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) != 0U)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) != 0U)
#if defined(DAC2)
#define __HAL_RCC_DAC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) != 0U)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) != 0U)
#if defined(DAC4)
#define __HAL_RCC_DAC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) != 0U)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) != 0U)
#endif /* AES */
#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) != 0U)
#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN) == 0U)
#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN) == 0U)
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN) == 0U)
#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIODEN) == 0U)
#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOEEN) == 0U)
#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOFEN) == 0U)
#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOGEN) == 0U)
#define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC12EN) == 0U)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_ADC345EN) == 0U)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC1EN) == 0U)
#if defined(DAC2)
#define __HAL_RCC_DAC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC2EN) == 0U)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC3EN) == 0U)
#if defined(DAC4)
#define __HAL_RCC_DAC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DAC4EN) == 0U)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AESEN) == 0U)
#endif /* AES */
#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN) == 0U)
/**
* @}
*/
/** @defgroup RCC_AHB3_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status
* @brief Check whether the AHB3 peripheral clock is enabled or not.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) != 0U)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) != 0U)
#endif /* QUADSPI */
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN) == 0U)
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup RCC_APB1_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status
* @brief Check whether the APB1 peripheral clock is enabled or not.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
#if defined(TIM5)
#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U)
#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) != 0U)
#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
#if defined(UART4)
#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
#endif /* UART5 */
#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U)
#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) != 0U)
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) != 0U)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) != 0U)
#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) != 0U)
#if defined(I2C4)
#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U)
#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U)
#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U)
#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U)
#if defined(TIM5)
#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U)
#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U)
#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U)
#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_RTCAPBEN) == 0U)
#define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) == 0U)
#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U)
#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) == 0U)
#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U)
#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U)
#if defined(UART4)
#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U)
#endif /* UART5 */
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U)
#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U)
#if defined(USB)
#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USBEN) == 0U)
#endif /* USB */
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_FDCANEN) == 0U)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_PWREN) == 0U)
#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) == 0U)
#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) == 0U)
#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPUART1EN) == 0U)
#if defined(I2C4)
#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U)
/**
* @}
*/
/** @defgroup RCC_APB2_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status
* @brief Check whether the APB2 peripheral clock is enabled or not.
* @note After reset, the peripheral clock (used for registers read/write access)
* is disabled and the application software has to enable this clock before
* using it.
* @{
*/
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) != 0U)
#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U)
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U)
#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U)
#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U)
#if defined(SPI4)
#define __HAL_RCC_SPI4_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) != 0U)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U)
#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U)
#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U)
#if defined(TIM20)
#define __HAL_RCC_TIM20_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) != 0U)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) != 0U)
#endif /* HRTIM1 */
#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN) == 0U)
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U)
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U)
#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U)
#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U)
#if defined(SPI4)
#define __HAL_RCC_SPI4_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN) == 0U)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U)
#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U)
#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U)
#if defined(TIM20)
#define __HAL_RCC_TIM20_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM20EN) == 0U)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIM1EN) == 0U)
#endif /* HRTIM1 */
/**
* @}
*/
/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset
* @brief Force or release AHB1 peripheral reset.
* @{
*/
#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0xFFFFFFFFU)
#define __HAL_RCC_DMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define __HAL_RCC_DMA2_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define __HAL_RCC_DMAMUX1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
#define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
#define __HAL_RCC_FLASH_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U)
#define __HAL_RCC_DMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA1RST)
#define __HAL_RCC_DMA2_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2RST)
#define __HAL_RCC_DMAMUX1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMAMUX1RST)
#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST)
#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST)
#define __HAL_RCC_FLASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FLASHRST)
#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST)
/**
* @}
*/
/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset
* @brief Force or release AHB2 peripheral reset.
* @{
*/
#define __HAL_RCC_AHB2_FORCE_RESET() WRITE_REG(RCC->AHB2RSTR, 0xFFFFFFFFU)
#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
#if defined(DAC2)
#define __HAL_RCC_DAC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
#if defined(DAC4)
#define __HAL_RCC_DAC4_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
#endif /* AES */
#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
#define __HAL_RCC_AHB2_RELEASE_RESET() WRITE_REG(RCC->AHB2RSTR, 0x00000000U)
#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOARST)
#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOBRST)
#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOCRST)
#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIODRST)
#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOERST)
#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOFRST)
#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_GPIOGRST)
#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC12RST)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_ADC345RST)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC1RST)
#if defined(DAC2)
#define __HAL_RCC_DAC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC2RST)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC3RST)
#if defined(DAC4)
#define __HAL_RCC_DAC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_DAC4RST)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_AESRST)
#endif /* AES */
#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR, RCC_AHB2RSTR_RNGRST)
/**
* @}
*/
/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset
* @brief Force or release AHB3 peripheral reset.
* @{
*/
#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0xFFFFFFFFU)
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
#endif /* QUADSPI */
#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U)
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_FMCRST)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_QSPIRST)
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset
* @brief Force or release APB1 peripheral reset.
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() WRITE_REG(RCC->APB1RSTR1, 0xFFFFFFFFU)
#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#if defined(TIM5)
#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#if defined(UART4)
#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
#endif /* UART5 */
#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#if defined(I2C4)
#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
#define __HAL_RCC_APB1_RELEASE_RESET() WRITE_REG(RCC->APB1RSTR1, 0x00000000U)
#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST)
#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST)
#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST)
#if defined(TIM5)
#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST)
#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST)
#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST)
#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST)
#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI3RST)
#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST)
#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST)
#if defined(UART4)
#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST)
#endif /* UART5 */
#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST)
#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST)
#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USBRST)
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_FDCANRST)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_PWRRST)
#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C3RST)
#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST)
#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPUART1RST)
#if defined(I2C4)
#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST)
/**
* @}
*/
/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset
* @brief Force or release APB2 peripheral reset.
* @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0xFFFFFFFFU)
#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#if defined(SPI4)
#define __HAL_RCC_SPI4_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#if defined(TIM20)
#define __HAL_RCC_TIM20_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
#endif /* HRTIM1 */
#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U)
#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SYSCFGRST)
#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST)
#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST)
#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST)
#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST)
#if defined(SPI4)
#define __HAL_RCC_SPI4_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI4RST)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST)
#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST)
#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST)
#if defined(TIM20)
#define __HAL_RCC_TIM20_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM20RST)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_HRTIM1RST)
#endif /* HRTIM1 */
/**
* @}
*/
/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable
* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define __HAL_RCC_DMAMUX1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN)
#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN)
#define __HAL_RCC_DMAMUX1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN)
#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN)
#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN)
#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN)
#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN)
#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN)
/**
* @}
*/
/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable
* @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define __HAL_RCC_CCM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
#if defined(DAC2)
#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
#if defined(DAC4)
#define __HAL_RCC_DAC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
#endif /* AES */
#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN)
#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN)
#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN)
#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN)
#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN)
#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN)
#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN)
#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN)
#define __HAL_RCC_CCM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN)
#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN)
#if defined(DAC2)
#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN)
#if defined(DAC4)
#define __HAL_RCC_DAC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN)
#endif /* AES */
#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN)
/**
* @}
*/
/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3 Peripheral Clock Sleep Enable Disable
* @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
#endif /* QUADSPI */
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN)
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable
* @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#if defined(TIM5)
#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#if defined(UART4)
#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
#endif /* UART5 */
#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#if defined(USB)
#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
#endif /* USB */
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#if defined(I2C4)
#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN)
#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN)
#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN)
#if defined(TIM5)
#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN)
#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN)
#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN)
#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN)
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN)
#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN)
#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN)
#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN)
#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN)
#if defined(UART4)
#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN)
#endif /* UART5 */
#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN)
#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN)
#if defined(USB)
#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN)
#endif /* USB */
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN)
#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN)
#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN)
#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN)
#if defined(I2C4)
#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN)
/**
* @}
*/
/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable
* @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#if defined(SPI4)
#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#if defined(TIM20)
#define __HAL_RCC_TIM20_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
#endif /* HRTIM1 */
#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN)
#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN)
#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN)
#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN)
#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN)
#if defined(SPI4)
#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN)
#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN)
#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN)
#if defined(TIM20)
#define __HAL_RCC_TIM20_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN)
#endif /* HRTIM1 */
/**
* @}
*/
/** @defgroup RCC_AHB1_Clock_Sleep_Enable_Disable_Status AHB1 Peripheral Clock Sleep Enabled or Disabled Status
* @brief Check whether the AHB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) != 0U)
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) != 0U)
#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) != 0U)
#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) != 0U)
#define __HAL_RCC_FMAC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) != 0U)
#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) != 0U)
#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) != 0U)
#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) != 0U)
#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA1SMEN) == 0U)
#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2SMEN) == 0U)
#define __HAL_RCC_DMAMUX1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMAMUX1SMEN) == 0U)
#define __HAL_RCC_CORDIC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) == 0U)
#define __HAL_RCC_FMAC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) == 0U)
#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) == 0U)
#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) == 0U)
#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) == 0U)
/**
* @}
*/
/** @defgroup RCC_AHB2_Clock_Sleep_Enable_Disable_Status AHB2 Peripheral Clock Sleep Enabled or Disabled Status
* @brief Check whether the AHB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) != 0U)
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) != 0U)
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) != 0U)
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) != 0U)
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) != 0U)
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) != 0U)
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) != 0U)
#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) != 0U)
#define __HAL_RCC_CCM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) != 0U)
#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) != 0U)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) != 0U)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) != 0U)
#if defined(DAC2)
#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) != 0U)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) != 0U)
#if defined(DAC4)
#define __HAL_RCC_DAC4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) != 0U)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) != 0U)
#endif /* AES */
#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) != 0U)
#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOASMEN) == 0U)
#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOBSMEN) == 0U)
#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOCSMEN) == 0U)
#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIODSMEN) == 0U)
#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOESMEN) == 0U)
#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOFSMEN) == 0U)
#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_GPIOGSMEN) == 0U)
#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_SRAM2SMEN) == 0U)
#define __HAL_RCC_CCM_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_CCMSRAMSMEN) == 0U)
#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC12SMEN) == 0U)
#if defined(ADC345_COMMON)
#define __HAL_RCC_ADC345_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_ADC345SMEN) == 0U)
#endif /* ADC345_COMMON */
#define __HAL_RCC_DAC1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC1SMEN) == 0U)
#if defined(DAC2)
#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC2SMEN) == 0U)
#endif /* DAC2 */
#define __HAL_RCC_DAC3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC3SMEN) == 0U)
#if defined(DAC4)
#define __HAL_RCC_DAC4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_DAC4SMEN) == 0U)
#endif /* DAC4 */
#if defined(AES)
#define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_AESSMEN) == 0U)
#endif /* AES */
#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB2SMENR, RCC_AHB2SMENR_RNGSMEN) == 0U)
/**
* @}
*/
/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable_Status AHB3 Peripheral Clock Sleep Enabled or Disabled Status
* @brief Check whether the AHB3 peripheral clock during Low Power (Sleep) mode is enabled or not.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) != 0U)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) != 0U)
#endif /* QUADSPI */
#if defined(FMC_BANK1)
#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_FMCSMEN) == 0U)
#endif /* FMC_BANK1 */
#if defined(QUADSPI)
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_QSPISMEN) == 0U)
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable_Status APB1 Peripheral Clock Sleep Enabled or Disabled Status
* @brief Check whether the APB1 peripheral clock during Low Power (Sleep) mode is enabled or not.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) != 0U)
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) != 0U)
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) != 0U)
#if defined(TIM5)
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) != 0U)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) != 0U)
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) != 0U)
#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) != 0U)
#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) != 0U)
#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) != 0U)
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) != 0U)
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) != 0U)
#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) != 0U)
#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) != 0U)
#if defined(UART4)
#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) != 0U)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) != 0U)
#endif /* UART5 */
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) != 0U)
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) != 0U)
#define __HAL_RCC_USB_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) != 0U)
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) != 0U)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) != 0U)
#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) != 0U)
#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) != 0U)
#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) != 0U)
#if defined(I2C4)
#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) != 0U)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) != 0U)
#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) == 0U)
#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) == 0U)
#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) == 0U)
#if defined(TIM5)
#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) == 0U)
#endif /* TIM5 */
#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) == 0U)
#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) == 0U)
#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) == 0U)
#define __HAL_RCC_RTCAPB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_RTCAPBSMEN) == 0U)
#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) == 0U)
#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) == 0U)
#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI3SMEN) == 0U)
#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) == 0U)
#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) == 0U)
#if defined(UART4)
#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) == 0U)
#endif /* UART4 */
#if defined(UART5)
#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) == 0U)
#endif /* UART5 */
#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) == 0U)
#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) == 0U)
#define __HAL_RCC_USB_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USBSMEN) == 0U)
#if defined(FDCAN1)
#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_FDCANSMEN) == 0U)
#endif /* FDCAN1 */
#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_PWRSMEN) == 0U)
#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C3SMEN) == 0U)
#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_LPTIM1SMEN) == 0U)
#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPUART1SMEN) == 0U)
#if defined(I2C4)
#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) == 0U)
#endif /* I2C4 */
#define __HAL_RCC_UCPD1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) == 0U)
/**
* @}
*/
/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable_Status APB2 Peripheral Clock Sleep Enabled or Disabled Status
* @brief Check whether the APB2 peripheral clock during Low Power (Sleep) mode is enabled or not.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
* @note By default, all peripheral clocks are enabled during SLEEP mode.
* @{
*/
#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) != 0U)
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) != 0U)
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) != 0U)
#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) != 0U)
#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) != 0U)
#if defined(SPI4)
#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) != 0U)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) != 0U)
#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) != 0U)
#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) != 0U)
#if defined(TIM20)
#define __HAL_RCC_TIM20_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) != 0U)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) != 0U)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) != 0U)
#endif /* HRTIM1 */
#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SYSCFGSMEN) == 0U)
#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) == 0U)
#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) == 0U)
#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) == 0U)
#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) == 0U)
#if defined(SPI4)
#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI4SMEN) == 0U)
#endif /* SPI4 */
#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) == 0U)
#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) == 0U)
#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) == 0U)
#if defined(TIM20)
#define __HAL_RCC_TIM20_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM20SMEN) == 0U)
#endif /* TIM20 */
#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) == 0U)
#if defined(HRTIM1)
#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED() (READ_BIT(RCC->APB2SMENR, RCC_APB2SMENR_HRTIM1SMEN) == 0U)
#endif /* HRTIM1 */
/**
* @}
*/
/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset
* @{
*/
/** @brief Macros to force or release the Backup domain reset.
* @note This function resets the RTC peripheral (including the backup registers)
* and the RTC clock source selection in RCC_CSR register.
* @note The BKPSRAM is not affected by this reset.
* @retval None
*/
#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
/**
* @}
*/
/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
* @{
*/
/** @brief Macros to enable or disable the RTC clock.
* @note As the RTC is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the RTC
* (to be done once after reset).
* @note These macros must be used after the RTC clock source was selected.
* @retval None
*/
#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
/**
* @}
*/
/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI).
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
* It is used (enabled by hardware) as system clock source after startup
* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
* of the HSE used directly or indirectly as system clock (if the Clock
* Security System CSS is enabled).
* @note HSI can not be stopped if it is used as system clock source. In this case,
* you have to select another source of the system clock then stop the HSI.
* @note After enabling the HSI, the application software should wait on HSIRDY
* flag to be set indicating that HSI clock is stable and can be used as
* system clock source.
* This parameter can be: ENABLE or DISABLE.
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
* clock cycles.
* @retval None
*/
#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC.
* @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value
* (default is RCC_HSICALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 0x7F.
* @retval None
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (__HSICALIBRATIONVALUE__) << RCC_ICSCR_HSITRIM_Pos)
/**
* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
* in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.
* @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication
* speed because of the HSI startup time.
* @note The enable of this function has not effect on the HSION bit.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
* @note After enabling the LSI, the application software should wait on
* LSIRDY flag to be set indicating that LSI clock is stable and can
* be used to clock the IWDG and/or the RTC.
* @note LSI can not be disabled if the IWDG is running.
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
* clock cycles.
* @retval None
*/
#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
* @note HSE state can not be changed if it is used directly or through the
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
* function.
* @param __STATE__ specifies the new state of the HSE.
* This parameter can be one of the following values:
* @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after
* 6 HSE oscillator clock cycles.
* @arg @ref RCC_HSE_ON Turn ON the HSE oscillator.
* @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock.
* @retval None
*/
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \
if((__STATE__) == RCC_HSE_ON) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else if((__STATE__) == RCC_HSE_BYPASS) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
} while(0)
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
* supported by this macro. User should request a transition to LSE Off
* first and then LSE On or LSE Bypass.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
* (to be done once after reset).
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC.
* @param __STATE__ specifies the new state of the LSE.
* This parameter can be one of the following values:
* @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
* @arg @ref RCC_LSE_ON Turn ON the LSE oscillator.
* @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
* @retval None
*/
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
do { \
if((__STATE__) == RCC_LSE_ON) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0)
/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48).
* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
* @note After enabling the HSI48, the application software should wait on HSI48RDY
* flag to be set indicating that HSI48 clock is stable.
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON)
/** @brief Macros to configure the RTC clock (RTCCLK).
* @note As the RTC clock configuration bits are in the Backup domain and write
* access is denied to this domain after reset, you have to enable write
* access using the Power Backup Access macro before to configure
* the RTC clock source (to be done once after reset).
* @note Once the RTC clock is configured it cannot be changed unless the
* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
* a Power On Reset (POR).
*
* @param __RTC_CLKSOURCE__ specifies the RTC clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
*
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wakeup source.
* However, when the HSE clock is used as RTC clock source, the RTC
* cannot be used in STOP and STANDBY modes.
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
* RTC clock source).
* @retval None
*/
#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \
MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
/** @brief Macro to get the RTC clock source.
* @retval The returned value can be one of the following:
* @arg @ref RCC_RTCCLKSOURCE_NONE No clock selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock.
* @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected
*/
#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
/** @brief Macros to enable or disable the main PLL.
* @note After enabling the main PLL, the application software should wait on
* PLLRDY flag to be set indicating that PLL clock is stable and can
* be used as system clock source.
* @note The main PLL can not be disabled if it is used as system clock source
* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
* @retval None
*/
#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
/** @brief Macro to configure the PLL clock source.
* @note This function must be used only when the main PLL is disabled.
* @param __PLLSOURCE__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
* @retval None
*
*/
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) \
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
/** @brief Macro to configure the PLL source division factor M.
* @note This function must be used only when the main PLL is disabled.
* @param __PLLM__ specifies the division factor for PLL VCO input clock
* This parameter must be a value of @ref RCC_PLLM_Clock_Divider.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
* of 8 MHz to limit PLL jitter.
* @retval None
*
*/
#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) \
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, ((__PLLM__) - 1) << RCC_PLLCFGR_PLLM_Pos)
/**
* @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This macro must be used only when the main PLL is disabled.
* @note This macro preserves the PLL's output clocks enable state.
*
* @param __PLLSOURCE__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL clock entry
* @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL clock entry
* @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
*
* @param __PLLM__ specifies the division factor for PLL VCO input clock.
* This parameter must be a value of @ref RCC_PLLM_Clock_Divider
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 2.66 to 8 MHz. It is recommended to select a frequency
* of 8 MHz to limit PLL jitter.
*
* @param __PLLN__ specifies the multiplication factor for PLL VCO output clock.
* This parameter must be a number between 8 and 127.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 64 and 344 MHz.
*
* @param __PLLP__ specifies the division factor for SAI clock.
* This parameter must be a number in the range (2 to 31).
*
* @param __PLLQ__ specifies the division factor for OTG FS, SDMMC1 and RNG clocks.
* This parameter must be in the range (2, 4, 6 or 8).
* @note If the USB OTG FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
* the SDMMC1 and RNG need a frequency lower than or equal to 48 MHz to work
* correctly.
* @param __PLLR__ specifies the division factor for the main system clock.
* @note You have to set the PLLR parameter correctly to not exceed 170MHZ.
* This parameter must be in the range (2, 4, 6 or 8).
* @retval None
*/
#define __HAL_RCC_PLL_CONFIG(__PLLSOURCE__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__ ) \
MODIFY_REG(RCC->PLLCFGR, \
(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | \
RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLPDIV), \
((__PLLSOURCE__) | \
(((__PLLM__) - 1U) << RCC_PLLCFGR_PLLM_Pos) | \
((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
((((__PLLQ__) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos) | \
((((__PLLR__) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos) | \
((__PLLP__) << RCC_PLLCFGR_PLLPDIV_Pos)))
/** @brief Macro to get the oscillator used as PLL clock source.
* @retval The oscillator used as PLL clock source. The returned value can be one
* of the following:
* - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.
* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
*/
#define __HAL_RCC_GET_PLL_OSCSOURCE() (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC))
/**
* @brief Enable or disable each clock output (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_ADCCLK)
* @note Enabling/disabling clock outputs RCC_PLL_ADCCLK and RCC_PLL_48M1CLK can be done at anytime
* without the need to stop the PLL in order to save power. But RCC_PLL_SYSCLK cannot
* be stopped if used as System Clock.
* @param __PLLCLOCKOUT__ specifies the PLL clock to be output.
* This parameter can be one or a combination of the following values:
* @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC.
* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz),
* FDCAN (<=48 MHz) and QSPI (<=48 MHz).
* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz)
* @retval None
*/
#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLLCLOCKOUT__) SET_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLLCLOCKOUT__) CLEAR_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
/**
* @brief Get clock output enable status (RCC_PLL_SYSCLK, RCC_PLL_48M1CLK, RCC_PLL_SAI3CLK)
* @param __PLLCLOCKOUT__ specifies the output PLL clock to be checked.
* This parameter can be one of the following values:
* @arg @ref RCC_PLL_ADCCLK This clock is used to generate a clock on ADC.
* @arg @ref RCC_PLL_48M1CLK This Clock is used to generate the clock for the USB (48 MHz),
* FDCAN (<=48 MHz) and QSPI (<=48 MHz).
* @arg @ref RCC_PLL_SYSCLK This Clock is used to generate the high speed system clock (up to 170MHz)
* @retval SET / RESET
*/
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLLCLOCKOUT__) READ_BIT(RCC->PLLCFGR, (__PLLCLOCKOUT__))
/**
* @brief Macro to configure the system clock source.
* @param __SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values:
* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
* @retval None
*/
#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
/** @brief Macro to get the clock source used as system clock.
* @retval The clock source used as system clock. The returned value can be one
* of the following:
* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
*/
#define __HAL_RCC_GET_SYSCLK_SOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_SWS))
/**
* @brief Macro to configure the External Low Speed oscillator (LSE) drive capability.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
* (to be done once after reset).
* @param __LSEDRIVE__ specifies the new state of the LSE drive capability.
* This parameter can be one of the following values:
* @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability.
* @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability.
* @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability.
* @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability.
* @retval None
*/
#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (__LSEDRIVE__))
/** @brief Macro to configure the MCO clock.
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
* This parameter can be one of the following values:
* @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled
* @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee
* @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source
* @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48
* @param __MCODIV__ specifies the MCO clock prescaler.
* This parameter can be one of the following values:
* @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1
* @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2
* @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4
* @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8
* @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16
*/
#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
*/
/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
* the selected interrupts).
* @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
* @retval None
*/
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
* the selected interrupts).
* @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
* @retval None
*/
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
* bits to clear the selected interrupt pending bits.
* @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
* @retval None
*/
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
/** @brief Check whether the RCC interrupt has occurred or not.
* @param __INTERRUPT__ specifies the RCC interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref RCC_IT_LSIRDY LSI ready interrupt
* @arg @ref RCC_IT_LSERDY LSE ready interrupt
* @arg @ref RCC_IT_HSIRDY HSI ready interrupt
* @arg @ref RCC_IT_HSERDY HSE ready interrupt
* @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt
* @arg @ref RCC_IT_CSS HSE Clock security system interrupt
* @arg @ref RCC_IT_LSECSS LSE Clock security system interrupt
* @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt for devices with HSI48
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Set RMVF bit to clear the reset flags.
* The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST,
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
* @retval None
*/
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
/** @brief Check whether the selected RCC flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready
* @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready
* @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready
* @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready for devices with HSI48
* @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready
* @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection
* @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready
* @arg @ref RCC_FLAG_BORRST BOR reset
* @arg @ref RCC_FLAG_OBLRST OBLRST reset
* @arg @ref RCC_FLAG_PINRST Pin reset
* @arg @ref RCC_FLAG_SFTRST Software reset
* @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset
* @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset
* @arg @ref RCC_FLAG_LPWRRST Low Power reset
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \
((((__FLAG__) >> 5U) == 4U) ? RCC->CRRCR : \
((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \
((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \
((uint32_t)1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) \
? 1U : 0U)
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup RCC_Private_Constants
* @{
*/
/* Defines used for Flags */
#define CR_REG_INDEX 1U
#define BDCR_REG_INDEX 2U
#define CSR_REG_INDEX 3U
#define CRRCR_REG_INDEX 4U
#define RCC_FLAG_MASK 0x1FU
/* Define used for IS_RCC_CLOCKTYPE() */
#define RCC_CLOCKTYPE_ALL (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2) /*!< All clcoktype to configure */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @addtogroup RCC_Private_Macros
* @{
*/
#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
((__HSE__) == RCC_HSE_BYPASS))
#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
((__LSE__) == RCC_LSE_BYPASS))
#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (RCC_ICSCR_HSITRIM >> RCC_ICSCR_HSITRIM_Pos))
#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON))
#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || \
((__PLL__) == RCC_PLL_ON))
#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_NONE) || \
((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
((__SOURCE__) == RCC_PLLSOURCE_HSE))
#define IS_RCC_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U))
#define IS_RCC_PLLN_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define IS_RCC_PLLP_VALUE(__VALUE__) (((__VALUE__) >= 2U) && ((__VALUE__) <= 31U))
#define IS_RCC_PLLQ_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
((__VALUE__) == 6U) || ((__VALUE__) == 8U))
#define IS_RCC_PLLR_VALUE(__VALUE__) (((__VALUE__) == 2U) || ((__VALUE__) == 4U) || \
((__VALUE__) == 6U) || ((__VALUE__) == 8U))
#define IS_RCC_CLOCKTYPE(__CLK__) ((((__CLK__) & RCC_CLOCKTYPE_ALL) != 0x00UL) && (((__CLK__) & ~RCC_CLOCKTYPE_ALL) == 0x00UL))
#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
((__HCLK__) == RCC_SYSCLK_DIV512))
#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
((__PCLK__) == RCC_HCLK_DIV16))
#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32))
#define IS_RCC_MCO(__MCOX__) (((__MCOX__) == RCC_MCO_PA8) || \
((__MCOX__) == RCC_MCO_PG10))
#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \
((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \
((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \
((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \
((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
((__DIV__) == RCC_MCODIV_16))
#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \
((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \
((__DRIVE__) == RCC_LSEDRIVE_HIGH))
/**
* @}
*/
/* Include RCC HAL Extended module */
#include "stm32g4xx_hal_rcc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup RCC_Exported_Functions
* @{
*/
/** @addtogroup RCC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
/**
* @}
*/
/** @addtogroup RCC_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
void HAL_RCC_EnableCSS(void);
void HAL_RCC_EnableLSECSS(void);
void HAL_RCC_DisableLSECSS(void);
uint32_t HAL_RCC_GetSysClockFreq(void);
uint32_t HAL_RCC_GetHCLKFreq(void);
uint32_t HAL_RCC_GetPCLK1Freq(void);
uint32_t HAL_RCC_GetPCLK2Freq(void);
void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
/* CSS NMI IRQ handler */
void HAL_RCC_NMI_IRQHandler(void);
/* User Callbacks in non blocking mode (IT mode) */
void HAL_RCC_CSSCallback(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_RCC_H */
| 166,552 | C | 47.88553 | 162 | 0.555952 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_exti.h | /**
******************************************************************************
* @file stm32g4xx_ll_exti.h
* @author MCD Application Team
* @brief Header file of EXTI LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_EXTI_H
#define __STM32G4xx_LL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (EXTI)
/** @defgroup EXTI_LL EXTI
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private Macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure
* @{
*/
typedef struct
{
uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
uint32_t Line_32_63; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63
This parameter can be any combination of @ref EXTI_LL_EC_LINE */
FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
uint8_t Mode; /*!< Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_MODE. */
uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */
} LL_EXTI_InitTypeDef;
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_LL_EC_LINE LINE
* @{
*/
#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */
#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */
#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */
#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */
#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */
#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */
#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */
#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */
#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */
#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */
#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */
#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */
#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */
#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */
#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */
#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */
#if defined(EXTI_IMR1_IM16)
#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */
#endif /* EXTI_IMR1_IM16 */
#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */
#if defined(EXTI_IMR1_IM18)
#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */
#endif /* EXTI_IMR1_IM18 */
#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */
#if defined(EXTI_IMR1_IM20)
#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */
#endif /* EXTI_IMR1_IM20 */
#if defined(EXTI_IMR1_IM21)
#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */
#endif /* EXTI_IMR1_IM21 */
#if defined(EXTI_IMR1_IM22)
#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */
#endif /* EXTI_IMR1_IM22 */
#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */
#if defined(EXTI_IMR1_IM24)
#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */
#endif /* EXTI_IMR1_IM24 */
#if defined(EXTI_IMR1_IM25)
#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */
#endif /* EXTI_IMR1_IM25 */
#if defined(EXTI_IMR1_IM26)
#define LL_EXTI_LINE_26 EXTI_IMR1_IM26 /*!< Extended line 26 */
#endif /* EXTI_IMR1_IM26 */
#if defined(EXTI_IMR1_IM27)
#define LL_EXTI_LINE_27 EXTI_IMR1_IM27 /*!< Extended line 27 */
#endif /* EXTI_IMR1_IM27 */
#if defined(EXTI_IMR1_IM28)
#define LL_EXTI_LINE_28 EXTI_IMR1_IM28 /*!< Extended line 28 */
#endif /* EXTI_IMR1_IM28 */
#if defined(EXTI_IMR1_IM29)
#define LL_EXTI_LINE_29 EXTI_IMR1_IM29 /*!< Extended line 29 */
#endif /* EXTI_IMR1_IM29 */
#if defined(EXTI_IMR1_IM30)
#define LL_EXTI_LINE_30 EXTI_IMR1_IM30 /*!< Extended line 30 */
#endif /* EXTI_IMR1_IM30 */
#if defined(EXTI_IMR1_IM31)
#define LL_EXTI_LINE_31 EXTI_IMR1_IM31 /*!< Extended line 31 */
#endif /* EXTI_IMR1_IM31 */
#define LL_EXTI_LINE_ALL_0_31 EXTI_IMR1_IM /*!< All Extended line not reserved*/
#if defined(EXTI_IMR2_IM32)
#define LL_EXTI_LINE_32 EXTI_IMR2_IM32 /*!< Extended line 32 */
#endif /* EXTI_IMR2_IM32 */
#if defined(EXTI_IMR2_IM33)
#define LL_EXTI_LINE_33 EXTI_IMR2_IM33 /*!< Extended line 33 */
#endif /* EXTI_IMR2_IM33 */
#if defined(EXTI_IMR2_IM34)
#define LL_EXTI_LINE_34 EXTI_IMR2_IM34 /*!< Extended line 34 */
#endif /* EXTI_IMR2_IM34 */
#if defined(EXTI_IMR2_IM35)
#define LL_EXTI_LINE_35 EXTI_IMR2_IM35 /*!< Extended line 35 */
#endif /* EXTI_IMR2_IM35 */
#if defined(EXTI_IMR2_IM36)
#define LL_EXTI_LINE_36 EXTI_IMR2_IM36 /*!< Extended line 36 */
#endif /* EXTI_IMR2_IM36 */
#if defined(EXTI_IMR2_IM37)
#define LL_EXTI_LINE_37 EXTI_IMR2_IM37 /*!< Extended line 37 */
#endif /* EXTI_IMR2_IM37 */
#if defined(EXTI_IMR2_IM38)
#define LL_EXTI_LINE_38 EXTI_IMR2_IM38 /*!< Extended line 38 */
#endif /* EXTI_IMR2_IM38 */
#if defined(EXTI_IMR2_IM39)
#define LL_EXTI_LINE_39 EXTI_IMR2_IM39 /*!< Extended line 39 */
#endif /* EXTI_IMR2_IM39 */
#if defined(EXTI_IMR2_IM40)
#define LL_EXTI_LINE_40 EXTI_IMR2_IM40 /*!< Extended line 40 */
#endif /* EXTI_IMR2_IM40 */
#if defined(EXTI_IMR2_IM41)
#define LL_EXTI_LINE_41 EXTI_IMR2_IM41 /*!< Extended line 41 */
#endif /* EXTI_IMR2_IM41 */
#if defined(EXTI_IMR2_IM42)
#define LL_EXTI_LINE_42 EXTI_IMR2_IM42 /*!< Extended line 42 */
#endif /* EXTI_IMR2_IM42 */
#define LL_EXTI_LINE_ALL_32_63 EXTI_IMR2_IM /*!< All Extended line not reserved*/
#define LL_EXTI_LINE_ALL (0xFFFFFFFFU) /*!< All Extended line */
#if defined(USE_FULL_LL_DRIVER)
#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EC_MODE Mode
* @{
*/
#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */
#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */
#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */
/**
* @}
*/
/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger
* @{
*/
#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */
#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */
#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */
#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros
* @{
*/
/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in EXTI register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))
/**
* @brief Read a value in EXTI register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->IMR1, ExtiLine);
}
/**
* @brief Enable ExtiLine Interrupt request for Lines in range 32 to 63
* @note The reset value for the direct lines (lines from 32 to 34, line
* 39) is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR2 IMx LL_EXTI_EnableIT_32_63
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35 (*)
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42(*)
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
{
SET_BIT(EXTI->IMR2, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->IMR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Interrupt request for Lines in range 32 to 63
* @note The reset value for the direct lines (lines from 32 to 34, line
* 39) is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR2 IMx LL_EXTI_DisableIT_32_63
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35 (*)
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42(*)
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->IMR2, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31
* @note The reset value for the direct or internal lines (see RM)
* is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63
* @note The reset value for the direct lines (lines from 32 to 34, line
* 39) is set to 1 in order to enable the interrupt by default.
* Bits are set automatically at Power on.
* @rmtoll IMR2 IMx LL_EXTI_IsEnabledIT_32_63
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35 (*)
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42(*)
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Event_Management Event_Management
* @{
*/
/**
* @brief Enable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->EMR1, ExtiLine);
}
/**
* @brief Enable ExtiLine Event request for Lines in range 32 to 63
* @rmtoll EMR2 EMx LL_EXTI_EnableEvent_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35 (*)
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42(*)
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
{
SET_BIT(EXTI->EMR2, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @arg @ref LL_EXTI_LINE_ALL_0_31
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->EMR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Event request for Lines in range 32 to 63
* @rmtoll EMR2 EMx LL_EXTI_DisableEvent_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35 (*)
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42(*)
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->EMR2, ExtiLine);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31
* @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31
* @param ExtiLine This parameter can be one of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_17
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_23
* @arg @ref LL_EXTI_LINE_24
* @arg @ref LL_EXTI_LINE_25
* @arg @ref LL_EXTI_LINE_26
* @arg @ref LL_EXTI_LINE_27
* @arg @ref LL_EXTI_LINE_28
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31
* @arg @ref LL_EXTI_LINE_ALL_0_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @brief Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63
* @rmtoll EMR2 EMx LL_EXTI_IsEnabledEvent_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_34
* @arg @ref LL_EXTI_LINE_35 (*)
* @arg @ref LL_EXTI_LINE_36
* @arg @ref LL_EXTI_LINE_37
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @arg @ref LL_EXTI_LINE_42(*)
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->RTSR1, ExtiLine);
}
/**
* @brief Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR2 RTx LL_EXTI_EnableRisingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
{
SET_BIT(EXTI->RTSR2, ExtiLine);
}
/**
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->RTSR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a rising edge on a configurable interrupt
* line occurs during a write operation in the EXTI_RTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll RTSR2 RTx LL_EXTI_DisableRisingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->RTSR2, ExtiLine);
}
/**
* @brief Check if rising edge trigger is enabled for Lines in range 0 to 31
* @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @brief Check if rising edge trigger is enabled for Lines in range 32 to 63
* @rmtoll RTSR2 RTx LL_EXTI_IsEnabledRisingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management
* @{
*/
/**
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->FTSR1, ExtiLine);
}
/**
* @brief Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a Falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for
* the same interrupt line. In this case, both generate a trigger
* condition.
* @rmtoll FTSR2 FTx LL_EXTI_EnableFallingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
{
SET_BIT(EXTI->FTSR2, ExtiLine);
}
/**
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a Falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for the same interrupt line.
* In this case, both generate a trigger condition.
* @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->FTSR1, ExtiLine);
}
/**
* @brief Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63
* @note The configurable wakeup lines are edge-triggered. No glitch must be
* generated on these lines. If a Falling edge on a configurable interrupt
* line occurs during a write operation in the EXTI_FTSR register, the
* pending bit is not set.
* Rising and falling edge triggers can be set for the same interrupt line.
* In this case, both generate a trigger condition.
* @rmtoll FTSR2 FTx LL_EXTI_DisableFallingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
{
CLEAR_BIT(EXTI->FTSR2, ExtiLine);
}
/**
* @brief Check if falling edge trigger is enabled for Lines in range 0 to 31
* @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @brief Check if falling edge trigger is enabled for Lines in range 32 to 63
* @rmtoll FTSR2 FTx LL_EXTI_IsEnabledFallingTrig_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management
* @{
*/
/**
* @brief Generate a software Interrupt Event for Lines in range 0 to 31
* @note If the interrupt is enabled on this line in the EXTI_IMR1, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR1
* register (by writing a 1 into the bit)
* @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)
{
SET_BIT(EXTI->SWIER1, ExtiLine);
}
/**
* @brief Generate a software Interrupt Event for Lines in range 32 to 63
* @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to
* this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2
* resulting in an interrupt request generation.
* This bit is cleared by clearing the corresponding bit in the EXTI_PR2
* register (by writing a 1 into the bit)
* @rmtoll SWIER2 SWIx LL_EXTI_GenerateSWI_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)
{
SET_BIT(EXTI->SWIER2, ExtiLine);
}
/**
* @}
*/
/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management
* @{
*/
/**
* @brief Check if the ExtLine Flag is set or not for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR1 PIFx LL_EXTI_IsActiveFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @brief Check if the ExtLine Flag is set or not for Lines in range 32 to 63
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR2 PIFx LL_EXTI_IsActiveFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
{
return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
}
/**
* @brief Read ExtLine Combination Flag for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR1 PIFx LL_EXTI_ReadFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));
}
/**
* @brief Read ExtLine Combination Flag for Lines in range 32 to 63
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR2 PIFx LL_EXTI_ReadFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval @note This bit is set when the selected edge event arrives on the interrupt
*/
__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)
{
return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));
}
/**
* @brief Clear ExtLine Flags for Lines in range 0 to 31
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR1 PIFx LL_EXTI_ClearFlag_0_31
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_0
* @arg @ref LL_EXTI_LINE_1
* @arg @ref LL_EXTI_LINE_2
* @arg @ref LL_EXTI_LINE_3
* @arg @ref LL_EXTI_LINE_4
* @arg @ref LL_EXTI_LINE_5
* @arg @ref LL_EXTI_LINE_6
* @arg @ref LL_EXTI_LINE_7
* @arg @ref LL_EXTI_LINE_8
* @arg @ref LL_EXTI_LINE_9
* @arg @ref LL_EXTI_LINE_10
* @arg @ref LL_EXTI_LINE_11
* @arg @ref LL_EXTI_LINE_12
* @arg @ref LL_EXTI_LINE_13
* @arg @ref LL_EXTI_LINE_14
* @arg @ref LL_EXTI_LINE_15
* @arg @ref LL_EXTI_LINE_16
* @arg @ref LL_EXTI_LINE_18
* @arg @ref LL_EXTI_LINE_19
* @arg @ref LL_EXTI_LINE_20
* @arg @ref LL_EXTI_LINE_21
* @arg @ref LL_EXTI_LINE_22
* @arg @ref LL_EXTI_LINE_29
* @arg @ref LL_EXTI_LINE_30
* @arg @ref LL_EXTI_LINE_31 (*)
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
{
WRITE_REG(EXTI->PR1, ExtiLine);
}
/**
* @brief Clear ExtLine Flags for Lines in range 32 to 63
* @note This bit is set when the selected edge event arrives on the interrupt
* line. This bit is cleared by writing a 1 to the bit.
* @rmtoll PR2 PIFx LL_EXTI_ClearFlag_32_63
* @param ExtiLine This parameter can be a combination of the following values:
* @arg @ref LL_EXTI_LINE_32 (*)
* @arg @ref LL_EXTI_LINE_33 (*)
* @arg @ref LL_EXTI_LINE_38
* @arg @ref LL_EXTI_LINE_39
* @arg @ref LL_EXTI_LINE_40
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
{
WRITE_REG(EXTI->PR2, ExtiLine);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions
* @{
*/
uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);
uint32_t LL_EXTI_DeInit(void);
void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* EXTI */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_EXTI_H */
| 54,310 | C | 37.16655 | 115 | 0.559363 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_tim_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_tim_ex.h
* @author MCD Application Team
* @brief Header file of TIM HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_TIM_EX_H
#define STM32G4xx_HAL_TIM_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup TIMEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
* @{
*/
/**
* @brief TIM Hall sensor Configuration Structure definition
*/
typedef struct
{
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint32_t IC1Filter; /*!< Specifies the input capture filter.
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
} TIM_HallSensor_InitTypeDef;
/**
* @brief TIM Break/Break2 input configuration
*/
typedef struct
{
uint32_t Source; /*!< Specifies the source of the timer break input.
This parameter can be a value of @ref TIMEx_Break_Input_Source */
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
uint32_t Polarity; /*!< Specifies the break input source polarity.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
} TIMEx_BreakInputConfigTypeDef;
/**
* @brief TIM Encoder index configuration
*/
typedef struct
{
uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */
uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */
uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */
uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */
uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */
} TIMEx_EncoderIndexConfigTypeDef;
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
* @{
*/
/** @defgroup TIMEx_Remap TIM Extended Remapping
* @{
*/
#define TIM_TIM1_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
#define TIM_TIM1_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
#define TIM_TIM1_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM1_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM1_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM1_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC1 analog watchdog 1 */
#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC1 analog watchdog 2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC1 analog watchdog 3 */
#if defined (ADC4)
#define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 1 */
#define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC4 analog watchdog 2 */
#define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC4 analog watchdog 3 */
#endif /* ADC4 */
#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
#define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
#define TIM_TIM2_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
#define TIM_TIM2_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM2_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM2_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM2_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)/* !< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM3 ETR */
#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM4 ETR */
#if defined (TIM5)
#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to TIM5 ETR */
#endif /* TIM5 */
#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to LSE */
#define TIM_TIM3_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
#define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
#define TIM_TIM3_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
#define TIM_TIM3_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM3_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM3_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM3_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM2 ETR */
#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM4 ETR */
#define TIM_TIM3_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 1 */
#define TIM_TIM3_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC2 analog watchdog 2 */
#define TIM_TIM3_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 3 */
#define TIM_TIM4_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
#define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
#define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
#define TIM_TIM4_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
#define TIM_TIM4_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM4_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM4_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM4_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM3 ETR */
#if defined (TIM5)
#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM5 ETR */
#endif /* TIM5 */
#if defined (TIM5)
#define TIM_TIM5_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
#define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
#define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
#define TIM_TIM5_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
#define TIM_TIM5_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM5_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM5_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM5_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /* !< ETR input is connected to TIM2 ETR */
#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to TIM3 ETR */
#endif /* TIM5 */
#define TIM_TIM8_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
#define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
#define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
#define TIM_TIM8_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
#define TIM_TIM8_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM8_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM8_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM8_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM8_ETR_ADC2_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC2 analog watchdog 1 */
#define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC2 analog watchdog 2 */
#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC2 analog watchdog 3 */
#if defined (ADC3)
#define TIM_TIM8_ETR_ADC3_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 1 */
#define TIM_TIM8_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC3 analog watchdog 2 */
#define TIM_TIM8_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 3 */
#endif /* ADC3 */
#if defined (TIM20)
#define TIM_TIM20_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */
#define TIM_TIM20_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */
#define TIM_TIM20_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */
#define TIM_TIM20_ETR_COMP3 (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */
#define TIM_TIM20_ETR_COMP4 TIM1_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM20_ETR_COMP5 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM20_ETR_COMP6 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM20_ETR_COMP7 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ETR input is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM20_ETR_ADC3_AWD1 TIM1_AF1_ETRSEL_3 /* !< ADC3 analog watchdog 1 */
#define TIM_TIM20_ETR_ADC3_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /* !< ADC3 analog watchdog 2 */
#define TIM_TIM20_ETR_ADC3_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /* !< ADC3 analog watchdog 3 */
#if defined (ADC5)
#define TIM_TIM20_ETR_ADC5_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 1 */
#define TIM_TIM20_ETR_ADC5_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /* !< ADC5 analog watchdog 2 */
#define TIM_TIM20_ETR_ADC5_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /* !< ADC5 analog watchdog 3 */
#endif /* ADC5 */
#endif /* TIM20 */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input TIM Extended Break input
* @{
*/
#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */
#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source
* @{
*/
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP3 0x00000008U /* !< The COMP3 output is connected to the break input */
#define TIM_BREAKINPUTSOURCE_COMP4 0x00000010U /* !< The COMP4 output is connected to the break input */
#if defined(COMP5)
#define TIM_BREAKINPUTSOURCE_COMP5 0x00000020U /* !< The COMP5 output is connected to the break input */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_BREAKINPUTSOURCE_COMP6 0x00000040U /* !< The COMP6 output is connected to the break input */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_BREAKINPUTSOURCE_COMP7 0x00000080U /* !< The COMP7 output is connected to the break input */
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
* @{
*/
#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */
#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */
/**
* @}
*/
/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
* @{
*/
#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */
#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */
/**
* @}
*/
/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection
* @{
*/
#define TIM_TIM1_TI1_GPIO 0x00000000U /*!< TIM1 input 1 is connected to GPIO */
#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1 input 1 is connected to COMP1_OUT */
#define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1 input 1 is connected to COMP2_OUT */
#define TIM_TIM1_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM1 input 1 is connected to COMP3_OUT */
#define TIM_TIM1_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM1 input 1 is connected to COMP4_OUT */
#define TIM_TIM2_TI1_GPIO 0x00000000U /*!< TIM2 input 1 is connected to GPIO */
#define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2 input 1 is connected to COMP1_OUT */
#define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2 input 1 is connected to COMP2_OUT */
#define TIM_TIM2_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP3_OUT */
#define TIM_TIM2_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM2 input 1 is connected to COMP4_OUT */
#if defined (COMP5)
#define TIM_TIM2_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM2 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#define TIM_TIM2_TI2_GPIO 0x00000000U /*!< TIM2 input 2 is connected to GPIO */
#define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2 input 2 is connected to COMP1_OUT */
#define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2 input 2 is connected to COMP2_OUT */
#define TIM_TIM2_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP3_OUT */
#define TIM_TIM2_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM2 input 2 is connected to COMP4_OUT */
#if defined (COMP6)
#define TIM_TIM2_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM2 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#define TIM_TIM2_TI3_GPIO 0x00000000U /*!< TIM2 input 3 is connected to GPIO */
#define TIM_TIM2_TI3_COMP4 TIM_TISEL_TI3SEL_0 /*!< TIM2 input 3 is connected to COMP4_OUT */
#define TIM_TIM2_TI4_GPIO 0x00000000U /*!< TIM2 input 4 is connected to GPIO */
#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2 input 4 is connected to COMP1_OUT */
#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2 input 4 is connected to COMP2_OUT */
#define TIM_TIM3_TI1_GPIO 0x00000000U /*!< TIM3 input 1 is connected to GPIO */
#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3 input 1 is connected to COMP1_OUT */
#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3 input 1 is connected to COMP2_OUT */
#define TIM_TIM3_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP3_OUT */
#define TIM_TIM3_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM3 input 1 is connected to COMP4_OUT */
#if defined (COMP5)
#define TIM_TIM3_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined (COMP6)
#define TIM_TIM3_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM3 input 1 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined (COMP7)
#define TIM_TIM3_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM3 input 1 is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM3_TI2_GPIO 0x00000000U /*!< TIM3 input 2 is connected to GPIO */
#define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3 input 2 is connected to COMP1_OUT */
#define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3 input 2 is connected to COMP2_OUT */
#define TIM_TIM3_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP3_OUT */
#define TIM_TIM3_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM3 input 2 is connected to COMP4_OUT */
#if defined (COMP5)
#define TIM_TIM3_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined (COMP6)
#define TIM_TIM3_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM3 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined (COMP7)
#define TIM_TIM3_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM3 input 2 is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM3_TI3_GPIO 0x00000000U /*!< TIM3 input 3 is connected to GPIO */
#define TIM_TIM3_TI3_COMP3 TIM_TISEL_TI3SEL_0 /*!< TIM3 input 3 is connected to COMP3_OUT */
#define TIM_TIM4_TI1_GPIO 0x00000000U /*!< TIM4 input 1 is connected to GPIO */
#define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4 input 1 is connected to COMP1_OUT */
#define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4 input 1 is connected to COMP2_OUT */
#define TIM_TIM4_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP3_OUT */
#define TIM_TIM4_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM4 input 1 is connected to COMP4_OUT */
#if defined (COMP5)
#define TIM_TIM4_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined (COMP6)
#define TIM_TIM4_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM4 input 1 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined (COMP7)
#define TIM_TIM4_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM4 input 1 is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM4_TI2_GPIO 0x00000000U /*!< TIM4 input 2 is connected to GPIO */
#define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4 input 2 is connected to COMP1_OUT */
#define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4 input 2 is connected to COMP2_OUT */
#define TIM_TIM4_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP3_OUT */
#define TIM_TIM4_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM4 input 2 is connected to COMP4_OUT */
#if defined (COMP5)
#define TIM_TIM4_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined (COMP6)
#define TIM_TIM4_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM4 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined (COMP7)
#define TIM_TIM4_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM4 input 2 is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM4_TI3_GPIO 0x00000000U /*!< TIM4 input 3 is connected to GPIO */
#if defined (COMP5)
#define TIM_TIM4_TI3_COMP5 TIM_TISEL_TI3SEL_0 /*!< TIM4 input 3 is connected to COMP5_OUT */
#endif /* COMP5 */
#define TIM_TIM4_TI4_GPIO 0x00000000U /*!< TIM4 input 4 is connected to GPIO */
#if defined (COMP6)
#define TIM_TIM4_TI4_COMP6 TIM_TISEL_TI4SEL_0 /*!< TIM4 input 4 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(TIM5)
#define TIM_TIM5_TI1_GPIO 0x00000000U /*!< TIM5 input 1 is connected to GPIO */
#define TIM_TIM5_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5 input 1 is connected to LSI */
#define TIM_TIM5_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5 input 1 is connected to LSE */
#define TIM_TIM5_TI1_RTC_WK (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to RTC_WAKEUP */
#define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5 input 1 is connected to COMP1_OUT */
#define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP2_OUT */
#define TIM_TIM5_TI1_COMP3 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP3_OUT */
#define TIM_TIM5_TI1_COMP4 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM5_TI1_COMP5 TIM_TISEL_TI1SEL_3 /*!< TIM5 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM5_TI1_COMP6 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM5 input 1 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM5_TI1_COMP7 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /*!< TIM5 input 1 is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM5_TI2_GPIO 0x00000000U /*!< TIM5 input 2 is connected to GPIO */
#define TIM_TIM5_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5 input 2 is connected to COMP1_OUT */
#define TIM_TIM5_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5 input 2 is connected to COMP2_OUT */
#define TIM_TIM5_TI2_COMP3 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP3_OUT */
#define TIM_TIM5_TI2_COMP4 TIM_TISEL_TI2SEL_2 /*!< TIM5 input 2 is connected to COMP4_OUT */
#if defined(COMP5)
#define TIM_TIM5_TI2_COMP5 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP6)
#define TIM_TIM5_TI2_COMP6 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1) /*!< TIM5 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM5_TI2_COMP7 (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM5 input 2 is connected to COMP7_OUT */
#endif /* COMP7 */
#endif /* TIM5 */
#define TIM_TIM8_TI1_GPIO 0x00000000U /*!< TIM8 input 1 is connected to GPIO */
#define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8 input 1 is connected to COMP1_OUT */
#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8 input 1 is connected to COMP2_OUT */
#define TIM_TIM8_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM8 input 1 is connected to COMP3_OUT */
#define TIM_TIM8_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM8 input 1 is connected to COMP4_OUT */
#define TIM_TIM15_TI1_GPIO 0x00000000U /*!< TIM15 input 1 is connected to GPIO */
#define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15 input 1 is connected to LSE */
#define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15 input 1 is connected to COMP1_OUT */
#define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP2_OUT */
#if defined (COMP5)
#define TIM_TIM15_TI1_COMP5 TIM_TISEL_TI1SEL_2 /*!< TIM15 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#if defined(COMP7)
#define TIM_TIM15_TI1_COMP7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM15 input 1 is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM15_TI2_GPIO 0x00000000U /*!< TIM15 input 2 is connected to GPIO */
#define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15 input 2 is connected to COMP2_OUT */
#define TIM_TIM15_TI2_COMP3 TIM_TISEL_TI2SEL_1 /*!< TIM15 input 2 is connected to COMP3_OUT */
#if defined (COMP6)
#define TIM_TIM15_TI2_COMP6 (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0) /*!< TIM15 input 2 is connected to COMP6_OUT */
#endif /* COMP6 */
#if defined(COMP7)
#define TIM_TIM15_TI2_COMP7 TIM_TISEL_TI2SEL_2 /*!< TIM15 input 2 is connected to COMP7_OUT */
#endif /* COMP7 */
#define TIM_TIM16_TI1_GPIO 0x00000000U /*!< TIM16 input 1 is connected to GPIO */
#if defined (COMP6)
#define TIM_TIM16_TI1_COMP6 TIM_TISEL_TI1SEL_0 /*!< TIM16 input 1 is connected to COMP6_OUT */
#endif /* COMP6 */
#define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16 input 1 is connected to MCO */
#define TIM_TIM16_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to HSE/32 */
#define TIM_TIM16_TI1_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM16 input 1 is connected to RTC_WAKEUP */
#define TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16 input 1 is connected to LSE */
#define TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16 input 1 is connected to LSI */
#define TIM_TIM17_TI1_GPIO 0x00000000U /*!< TIM17 input 1 is connected to GPIO */
#if defined (COMP5)
#define TIM_TIM17_TI1_COMP5 TIM_TISEL_TI1SEL_0 /*!< TIM17 input 1 is connected to COMP5_OUT */
#endif /* COMP5 */
#define TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17 input 1 is connected to MCO */
#define TIM_TIM17_TI1_HSE_32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to HSE/32 */
#define TIM_TIM17_TI1_RTC_WK TIM_TISEL_TI1SEL_2 /*!< TIM17 input 1 is connected to RTC_WAKEUP */
#define TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17 input 1 is connected to LSE */
#define TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17 input 1 is connected to LSI */
#if defined (TIM20)
#define TIM_TIM20_TI1_GPIO 0x00000000U /*!< TIM20 input 1 is connected to GPIO */
#define TIM_TIM20_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM20 input 1 is connected to COMP1_OUT */
#define TIM_TIM20_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM20 input 1 is connected to COMP2_OUT */
#define TIM_TIM20_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM20 input 1 is connected to COMP3_OUT */
#define TIM_TIM20_TI1_COMP4 TIM_TISEL_TI1SEL_2 /*!< TIM20 input 1 is connected to COMP4_OUT */
#endif /* TIM20 */
/**
* @}
*/
/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling
* @{
*/
#define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U /*!< Prelaod of SMS bitfield is disabled */
#define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */
/**
* @}
*/
/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position
* @{
*/
#define TIM_ENCODERINDEX_POSITION_00 0x00000000U /*!< Encoder index position is AB=00 */
#define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */
#define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */
#define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */
#define TIM_ENCODERINDEX_POSITION_0 0x00000000U /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */
#define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */
/**
* @}
*/
/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction
* @{
*/
#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */
#define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */
#define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */
/**
* @}
*/
/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity
* @{
*/
#define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
#define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
/**
* @}
*/
/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler
* @{
*/
#define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
#define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
#define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
#define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
* @{
*/
/**
* @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
* @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __CNTCLK__ counter clock frequency (in Hz)
* @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
*/
#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
* @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __FREQ__ output signal frequency (in Hz)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \
(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
/**
* @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
* output signal frequency.
* @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000);
* @note This macro should be used only if dithering is already enabled
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __FREQ__ output signal frequency (in Hz)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65519)
*/
#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
(((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
(uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U
/**
* @brief HELPER macro calculating the compare value required to achieve the required timer output compare
* active/inactive delay.
* @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @retval Compare value (between Min_Data=0 and Max_Data=65535)
*/
#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
* output compare active/inactive delay.
* @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10);
* @note This macro should be used only if dithering is already enabled
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @retval Compare value (between Min_Data=0 and Max_Data=65519)
*/
#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \
((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
/ ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
/**
* @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration
* (when the timer operates in one pulse mode).
* @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20);
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @param __PULSE__ pulse duration (in us)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
*/
#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
* pulse duration (when the timer operates in one pulse mode).
* @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20);
* @note This macro should be used only if dithering is already enabled
* @param __TIMCLK__ timer input clock frequency (in Hz)
* @param __PSC__ prescaler
* @param __DELAY__ timer output compare active/inactive delay (in us)
* @param __PULSE__ pulse duration (in us)
* @retval Auto-reload value (between Min_Data=0 and Max_Data=65519)
*/
#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+ __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
/**
* @}
*/
/* End of exported macro -----------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
* @{
*/
#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U))
#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#if defined (COMP5) && defined (COMP6) && defined (COMP7)
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP5) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP6) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP7))
#else
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP3) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP4))
#endif /* COMP5 && COMP6 && COMP7 */
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U))
#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \
(IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5))
#if defined(TIM5) && defined(TIM20)
#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
((((INSTANCE) == TIM1) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \
|| \
(((INSTANCE) == TIM2) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \
|| \
(((INSTANCE) == TIM3) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \
|| \
(((INSTANCE) == TIM4) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \
|| \
(((INSTANCE) == TIM5) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \
|| \
(((INSTANCE) == TIM8) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \
|| \
(((INSTANCE) == TIM15) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))) \
|| \
(((INSTANCE) == TIM20) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR10))))
#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
((((INSTANCE) == TIM1) && \
(((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10))) \
|| \
(((INSTANCE) == TIM2) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10) || \
((__SELECTION__) == TIM_TS_ITR11))) \
|| \
(((INSTANCE) == TIM3) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10))) \
|| \
(((INSTANCE) == TIM4) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10))) \
|| \
(((INSTANCE) == TIM5) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10))) \
|| \
(((INSTANCE) == TIM8) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10))) \
|| \
(((INSTANCE) == TIM15) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10))) \
|| \
(((INSTANCE) == TIM20) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR10))))
#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
((((INSTANCE) == TIM1) && \
(((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM2) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM3) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM4) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM5) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM8) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM15) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM20) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR10)|| \
((__SELECTION__) == TIM_TS_NONE))))
#elif defined(TIM5)
#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
((((INSTANCE) == TIM1) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM2) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \
|| \
(((INSTANCE) == TIM3) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM4) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM5) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM8) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM15) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
((((INSTANCE) == TIM1) && \
(((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM2) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR11))) \
|| \
(((INSTANCE) == TIM3) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM4) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM5) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM8) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM15) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))))
#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
((((INSTANCE) == TIM1) && \
(((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM2) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM3) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM4) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM5) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM8) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM15) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))))
#elif defined(TIM20)
#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
((((INSTANCE) == TIM1) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \
|| \
(((INSTANCE) == TIM2) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \
|| \
(((INSTANCE) == TIM3) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \
|| \
(((INSTANCE) == TIM4) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \
|| \
(((INSTANCE) == TIM8) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \
|| \
(((INSTANCE) == TIM15) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR9))) \
|| \
(((INSTANCE) == TIM20) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
((((INSTANCE) == TIM1) && \
(((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9))) \
|| \
(((INSTANCE) == TIM2) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR11))) \
|| \
(((INSTANCE) == TIM3) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9))) \
|| \
(((INSTANCE) == TIM4) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9))) \
|| \
(((INSTANCE) == TIM8) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9))) \
|| \
(((INSTANCE) == TIM15) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9))) \
|| \
(((INSTANCE) == TIM20) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))))
#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
((((INSTANCE) == TIM1) && \
(((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM2) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM3) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM4) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM8) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM15) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR9) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM20) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))))
#else
#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \
((((INSTANCE) == TIM1) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM2) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \
|| \
(((INSTANCE) == TIM3) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM4) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM8) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \
|| \
(((INSTANCE) == TIM15) && \
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))))
#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \
((((INSTANCE) == TIM1) && \
(((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM2) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR11))) \
|| \
(((INSTANCE) == TIM3) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM4) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM8) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))) \
|| \
(((INSTANCE) == TIM15) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8))))
#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \
((((INSTANCE) == TIM1) && \
(((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM2) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR11)|| \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM3) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM4) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM8) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))) \
|| \
(((INSTANCE) == TIM15) && \
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_NONE))))
#endif /* TIM5 && TIM20 */
#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \
(IS_TIM_OC_MODE(__MODE__) \
&& ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \
? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1)))
#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_3) || \
((__CHANNEL__) == TIM_CHANNEL_4))
#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE)
#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU)
#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U)
#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \
|| ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX))
#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \
((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED))
#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \
((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \
((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \
((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8))
#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL)
#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \
((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \
((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \
((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \
((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \
((__POSITION__) == TIM_ENCODERINDEX_POSITION_1))
#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \
((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \
((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN))
/**
* @}
*/
/* End of private macro ------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
* @{
*/
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions
* @{
*/
/* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions
* @{
*/
/* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions
* @{
*/
/* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions
* @{
*/
/* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions
* @{
*/
/* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);
HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler,
uint32_t PulseWidth);
HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source);
HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime);
HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime);
HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim,
TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig);
HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions
* @brief Extended Callbacks functions
* @{
*/
/* Extended Callback **********************************************************/
void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim);
void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim);
/**
* @}
*/
/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
* @brief Extended Peripheral State functions
* @{
*/
/* Extended Peripheral State functions ***************************************/
HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions
* @{
*/
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/* End of private functions --------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_TIM_EX_H */
| 122,196 | C | 56.128097 | 189 | 0.45292 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dmamux.h | /**
******************************************************************************
* @file stm32g4xx_ll_dmamux.h
* @author MCD Application Team
* @brief Header file of DMAMUX LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_DMAMUX_H
#define __STM32G4xx_LL_DMAMUX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (DMAMUX1)
/** @defgroup DMAMUX_LL DMAMUX
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
* @{
*/
/* Define used to get DMAMUX CCR register size */
#define DMAMUX_CCR_SIZE 0x00000004U
/* Define used to get DMAMUX RGCR register size */
#define DMAMUX_RGCR_SIZE 0x00000004U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMAMUX_LL_Private_Macros DMAMUX Private Macros
* @{
*/
#define UNUSED(X) (void)X
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
* @{
*/
/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
* @{
*/
#define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
#define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
#define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
#define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
#define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
#define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
#define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
#define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
#define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
#define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
#define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
#define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
#define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
#define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
#define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
#define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
#define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
#define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
#define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
#define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
* @{
*/
#define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
#define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
#define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
#define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
#define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
#define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
#define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
#define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
#define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
#define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
#define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
#define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
#define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
#define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
#define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
#define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
#define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
#define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
#define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
#define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
* @{
*/
#define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
#define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_REQUEST Transfer request
* @{
*/
#define LL_DMAMUX_REQ_MEM2MEM 0x00000000U /*!< Memory to memory transfer */
#define LL_DMAMUX_REQ_GENERATOR0 0x00000001U /*!< DMAMUX request generator 0 */
#define LL_DMAMUX_REQ_GENERATOR1 0x00000002U /*!< DMAMUX request generator 1 */
#define LL_DMAMUX_REQ_GENERATOR2 0x00000003U /*!< DMAMUX request generator 2 */
#define LL_DMAMUX_REQ_GENERATOR3 0x00000004U /*!< DMAMUX request generator 3 */
#define LL_DMAMUX_REQ_ADC1 0x00000005U /*!< DMAMUX ADC1 request */
#define LL_DMAMUX_REQ_DAC1_CH1 0x00000006U /*!< DMAMUX DAC1 CH1 request */
#define LL_DMAMUX_REQ_DAC1_CH2 0x00000007U /*!< DMAMUX DAC1 CH2 request */
#define LL_DMAMUX_REQ_TIM6_UP 0x00000008U /*!< DMAMUX TIM6 UP request */
#define LL_DMAMUX_REQ_TIM7_UP 0x00000009U /*!< DMAMUX TIM7 UP request */
#define LL_DMAMUX_REQ_SPI1_RX 0x0000000AU /*!< DMAMUX SPI1 RX request */
#define LL_DMAMUX_REQ_SPI1_TX 0x0000000BU /*!< DMAMUX SPI1 TX request */
#define LL_DMAMUX_REQ_SPI2_RX 0x0000000CU /*!< DMAMUX SPI2 RX request */
#define LL_DMAMUX_REQ_SPI2_TX 0x0000000DU /*!< DMAMUX SPI2 TX request */
#define LL_DMAMUX_REQ_SPI3_RX 0x0000000EU /*!< DMAMUX SPI3 RX request */
#define LL_DMAMUX_REQ_SPI3_TX 0x0000000FU /*!< DMAMUX SPI3 TX request */
#define LL_DMAMUX_REQ_I2C1_RX 0x00000010U /*!< DMAMUX I2C1 RX request */
#define LL_DMAMUX_REQ_I2C1_TX 0x00000011U /*!< DMAMUX I2C1 TX request */
#define LL_DMAMUX_REQ_I2C2_RX 0x00000012U /*!< DMAMUX I2C2 RX request */
#define LL_DMAMUX_REQ_I2C2_TX 0x00000013U /*!< DMAMUX I2C2 TX request */
#define LL_DMAMUX_REQ_I2C3_RX 0x00000014U /*!< DMAMUX I2C3 RX request */
#define LL_DMAMUX_REQ_I2C3_TX 0x00000015U /*!< DMAMUX I2C3 TX request */
#define LL_DMAMUX_REQ_I2C4_RX 0x00000016U /*!< DMAMUX I2C4 RX request */
#define LL_DMAMUX_REQ_I2C4_TX 0x00000017U /*!< DMAMUX I2C4 TX request */
#define LL_DMAMUX_REQ_USART1_RX 0x00000018U /*!< DMAMUX USART1 RX request */
#define LL_DMAMUX_REQ_USART1_TX 0x00000019U /*!< DMAMUX USART1 TX request */
#define LL_DMAMUX_REQ_USART2_RX 0x0000001AU /*!< DMAMUX USART2 RX request */
#define LL_DMAMUX_REQ_USART2_TX 0x0000001BU /*!< DMAMUX USART2 TX request */
#define LL_DMAMUX_REQ_USART3_RX 0x0000001CU /*!< DMAMUX USART3 RX request */
#define LL_DMAMUX_REQ_USART3_TX 0x0000001DU /*!< DMAMUX USART3 TX request */
#define LL_DMAMUX_REQ_UART4_RX 0x0000001EU /*!< DMAMUX UART4 RX request */
#define LL_DMAMUX_REQ_UART4_TX 0x0000001FU /*!< DMAMUX UART4 TX request */
#define LL_DMAMUX_REQ_UART5_RX 0x00000020U /*!< DMAMUX UART5 RX request */
#define LL_DMAMUX_REQ_UART5_TX 0x00000021U /*!< DMAMUX UART5 TX request */
#define LL_DMAMUX_REQ_LPUART1_RX 0x00000022U /*!< DMAMUX LPUART1 RX request */
#define LL_DMAMUX_REQ_LPUART1_TX 0x00000023U /*!< DMAMUX LPUART1 TX request */
#define LL_DMAMUX_REQ_ADC2 0x00000024U /*!< DMAMUX ADC2 request */
#define LL_DMAMUX_REQ_ADC3 0x00000025U /*!< DMAMUX ADC3 request */
#define LL_DMAMUX_REQ_ADC4 0x00000026U /*!< DMAMUX ADC4 request */
#define LL_DMAMUX_REQ_ADC5 0x00000027U /*!< DMAMUX ADC5 request */
#define LL_DMAMUX_REQ_QSPI 0x00000028U /*!< DMAMUX QSPI request */
#define LL_DMAMUX_REQ_DAC2_CH1 0x00000029U /*!< DMAMUX DAC2 CH1 request */
#define LL_DMAMUX_REQ_TIM1_CH1 0x0000002AU /*!< DMAMUX TIM1 CH1 request */
#define LL_DMAMUX_REQ_TIM1_CH2 0x0000002BU /*!< DMAMUX TIM1 CH2 request */
#define LL_DMAMUX_REQ_TIM1_CH3 0x0000002CU /*!< DMAMUX TIM1 CH3 request */
#define LL_DMAMUX_REQ_TIM1_CH4 0x0000002DU /*!< DMAMUX TIM1 CH4 request */
#define LL_DMAMUX_REQ_TIM1_UP 0x0000002EU /*!< DMAMUX TIM1 UP request */
#define LL_DMAMUX_REQ_TIM1_TRIG 0x0000002FU /*!< DMAMUX TIM1 TRIG request */
#define LL_DMAMUX_REQ_TIM1_COM 0x00000030U /*!< DMAMUX TIM1 COM request */
#define LL_DMAMUX_REQ_TIM8_CH1 0x00000031U /*!< DMAMUX TIM8 CH1 request */
#define LL_DMAMUX_REQ_TIM8_CH2 0x00000032U /*!< DMAMUX TIM8 CH2 request */
#define LL_DMAMUX_REQ_TIM8_CH3 0x00000033U /*!< DMAMUX TIM8 CH3 request */
#define LL_DMAMUX_REQ_TIM8_CH4 0x00000034U /*!< DMAMUX TIM8 CH4 request */
#define LL_DMAMUX_REQ_TIM8_UP 0x00000035U /*!< DMAMUX TIM8 UP request */
#define LL_DMAMUX_REQ_TIM8_TRIG 0x00000036U /*!< DMAMUX TIM8 TRIG request */
#define LL_DMAMUX_REQ_TIM8_COM 0x00000037U /*!< DMAMUX TIM8 COM request */
#define LL_DMAMUX_REQ_TIM2_CH1 0x00000038U /*!< DMAMUX TIM2 CH1 request */
#define LL_DMAMUX_REQ_TIM2_CH2 0x00000039U /*!< DMAMUX TIM2 CH2 request */
#define LL_DMAMUX_REQ_TIM2_CH3 0x0000003AU /*!< DMAMUX TIM2 CH3 request */
#define LL_DMAMUX_REQ_TIM2_CH4 0x0000003BU /*!< DMAMUX TIM2 CH4 request */
#define LL_DMAMUX_REQ_TIM2_UP 0x0000003CU /*!< DMAMUX TIM2 UP request */
#define LL_DMAMUX_REQ_TIM3_CH1 0x0000003DU /*!< DMAMUX TIM3 CH1 request */
#define LL_DMAMUX_REQ_TIM3_CH2 0x0000003EU /*!< DMAMUX TIM3 CH2 request */
#define LL_DMAMUX_REQ_TIM3_CH3 0x0000003FU /*!< DMAMUX TIM3 CH3 request */
#define LL_DMAMUX_REQ_TIM3_CH4 0x00000040U /*!< DMAMUX TIM3 CH4 request */
#define LL_DMAMUX_REQ_TIM3_UP 0x00000041U /*!< DMAMUX TIM3 UP request */
#define LL_DMAMUX_REQ_TIM3_TRIG 0x00000042U /*!< DMAMUX TIM3 TRIG request */
#define LL_DMAMUX_REQ_TIM4_CH1 0x00000043U /*!< DMAMUX TIM4 CH1 request */
#define LL_DMAMUX_REQ_TIM4_CH2 0x00000044U /*!< DMAMUX TIM4 CH2 request */
#define LL_DMAMUX_REQ_TIM4_CH3 0x00000045U /*!< DMAMUX TIM4 CH3 request */
#define LL_DMAMUX_REQ_TIM4_CH4 0x00000046U /*!< DMAMUX TIM4 CH4 request */
#define LL_DMAMUX_REQ_TIM4_UP 0x00000047U /*!< DMAMUX TIM4 UP request */
#define LL_DMAMUX_REQ_TIM5_CH1 0x00000048U /*!< DMAMUX TIM5 CH1 request */
#define LL_DMAMUX_REQ_TIM5_CH2 0x00000049U /*!< DMAMUX TIM5 CH2 request */
#define LL_DMAMUX_REQ_TIM5_CH3 0x0000004AU /*!< DMAMUX TIM5 CH3 request */
#define LL_DMAMUX_REQ_TIM5_CH4 0x0000004BU /*!< DMAMUX TIM5 CH4 request */
#define LL_DMAMUX_REQ_TIM5_UP 0x0000004CU /*!< DMAMUX TIM5 UP request */
#define LL_DMAMUX_REQ_TIM5_TRIG 0x0000004DU /*!< DMAMUX TIM5 TRIG request */
#define LL_DMAMUX_REQ_TIM15_CH1 0x0000004EU /*!< DMAMUX TIM15 CH1 request */
#define LL_DMAMUX_REQ_TIM15_UP 0x0000004FU /*!< DMAMUX TIM15 UP request */
#define LL_DMAMUX_REQ_TIM15_TRIG 0x00000050U /*!< DMAMUX TIM15 TRIG request */
#define LL_DMAMUX_REQ_TIM15_COM 0x00000051U /*!< DMAMUX TIM15 COM request */
#define LL_DMAMUX_REQ_TIM16_CH1 0x00000052U /*!< DMAMUX TIM16 CH1 request */
#define LL_DMAMUX_REQ_TIM16_UP 0x00000053U /*!< DMAMUX TIM16 UP request */
#define LL_DMAMUX_REQ_TIM17_CH1 0x00000054U /*!< DMAMUX TIM17 CH1 request */
#define LL_DMAMUX_REQ_TIM17_UP 0x00000055U /*!< DMAMUX TIM17 UP request */
#define LL_DMAMUX_REQ_TIM20_CH1 0x00000056U /*!< DMAMUX TIM20 CH1 request */
#define LL_DMAMUX_REQ_TIM20_CH2 0x00000057U /*!< DMAMUX TIM20 CH2 request */
#define LL_DMAMUX_REQ_TIM20_CH3 0x00000058U /*!< DMAMUX TIM20 CH3 request */
#define LL_DMAMUX_REQ_TIM20_CH4 0x00000059U /*!< DMAMUX TIM20 CH4 request */
#define LL_DMAMUX_REQ_TIM20_UP 0x0000005AU /*!< DMAMUX TIM20 UP request */
#define LL_DMAMUX_REQ_AES_IN 0x0000005BU /*!< DMAMUX AES_IN request */
#define LL_DMAMUX_REQ_AES_OUT 0x0000005CU /*!< DMAMUX AES_OUT request */
#define LL_DMAMUX_REQ_TIM20_TRIG 0x0000005DU /*!< DMAMUX TIM20 TRIG request */
#define LL_DMAMUX_REQ_TIM20_COM 0x0000005EU /*!< DMAMUX TIM20 COM request */
#define LL_DMAMUX_REQ_HRTIM1_M 0x0000005FU /*!< DMAMUX HRTIM M request */
#define LL_DMAMUX_REQ_HRTIM1_A 0x00000060U /*!< DMAMUX HRTIM A request */
#define LL_DMAMUX_REQ_HRTIM1_B 0x00000061U /*!< DMAMUX HRTIM B request */
#define LL_DMAMUX_REQ_HRTIM1_C 0x00000062U /*!< DMAMUX HRTIM C request */
#define LL_DMAMUX_REQ_HRTIM1_D 0x00000063U /*!< DMAMUX HRTIM D request */
#define LL_DMAMUX_REQ_HRTIM1_E 0x00000064U /*!< DMAMUX HRTIM E request */
#define LL_DMAMUX_REQ_HRTIM1_F 0x00000065U /*!< DMAMUX HRTIM F request */
#define LL_DMAMUX_REQ_DAC3_CH1 0x00000066U /*!< DMAMUX DAC3 CH1 request */
#define LL_DMAMUX_REQ_DAC3_CH2 0x00000067U /*!< DMAMUX DAC3 CH2 request */
#define LL_DMAMUX_REQ_DAC4_CH1 0x00000068U /*!< DMAMUX DAC4 CH1 request */
#define LL_DMAMUX_REQ_DAC4_CH2 0x00000069U /*!< DMAMUX DAC4 CH2 request */
#define LL_DMAMUX_REQ_SPI4_RX 0x0000006AU /*!< DMAMUX SPI4 RX request */
#define LL_DMAMUX_REQ_SPI4_TX 0x0000006BU /*!< DMAMUX SPI4 TX request */
#define LL_DMAMUX_REQ_SAI1_A 0x0000006CU /*!< DMAMUX SAI1 A request */
#define LL_DMAMUX_REQ_SAI1_B 0x0000006DU /*!< DMAMUX SAI1 B request */
#define LL_DMAMUX_REQ_FMAC_READ 0x0000006EU /*!< DMAMUX FMAC READ request */
#define LL_DMAMUX_REQ_FMAC_WRITE 0x0000006FU /*!< DMAMUX FMAC WRITE request */
#define LL_DMAMUX_REQ_CORDIC_READ 0x00000070U /*!< DMAMUX CORDIC READ request */
#define LL_DMAMUX_REQ_CORDIC_WRITE 0x00000071U /*!< DMAMUX CORDIC WRITE request*/
#define LL_DMAMUX_REQ_UCPD1_RX 0x00000072U /*!< DMAMUX USBPD1_RX request */
#define LL_DMAMUX_REQ_UCPD1_TX 0x00000073U /*!< DMAMUX USBPD1_TX request */
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
* @{
*/
#define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX Channel 0 connected to DMA1 Channel 1 */
#define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX Channel 1 connected to DMA1 Channel 2 */
#define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX Channel 2 connected to DMA1 Channel 3 */
#define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX Channel 3 connected to DMA1 Channel 4 */
#define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX Channel 4 connected to DMA1 Channel 5 */
#define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX Channel 5 connected to DMA1 Channel 6 */
#define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX Channel 6 connected to DMA1 Channel 7 */
#define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX Channel 7 connected to DMA1 Channel 8 */
#define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX Channel 8 connected to DMA2 Channel 1 */
#define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX Channel 9 connected to DMA2 Channel 2 */
#define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX Channel 10 connected to DMA2 Channel 3 */
#define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX Channel 11 connected to DMA2 Channel 4 */
#define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX Channel 12 connected to DMA2 Channel 5 */
#define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX Channel 13 connected to DMA2 Channel 6 */
#define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX Channel 14 connected to DMA2 Channel 7 */
#define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX Channel 15 connected to DMA2 Channel 8 */
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
* @{
*/
#define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
#define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
#define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
#define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
* @{
*/
#define LL_DMAMUX_SYNC_EXTI_LINE0 0x00000000U /*!< Synchronization signal from EXTI Line0 */
#define LL_DMAMUX_SYNC_EXTI_LINE1 DMAMUX_CxCR_SYNC_ID_0 /*!< Synchronization signal from EXTI Line1 */
#define LL_DMAMUX_SYNC_EXTI_LINE2 DMAMUX_CxCR_SYNC_ID_1 /*!< Synchronization signal from EXTI Line2 */
#define LL_DMAMUX_SYNC_EXTI_LINE3 (DMAMUX_CxCR_SYNC_ID_1 |DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line3 */
#define LL_DMAMUX_SYNC_EXTI_LINE4 DMAMUX_CxCR_SYNC_ID_2 /*!< Synchronization signal from EXTI Line4 */
#define LL_DMAMUX_SYNC_EXTI_LINE5 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line5 */
#define LL_DMAMUX_SYNC_EXTI_LINE6 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line6 */
#define LL_DMAMUX_SYNC_EXTI_LINE7 (DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line7 */
#define LL_DMAMUX_SYNC_EXTI_LINE8 DMAMUX_CxCR_SYNC_ID_3 /*!< Synchronization signal from EXTI Line8 */
#define LL_DMAMUX_SYNC_EXTI_LINE9 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line9 */
#define LL_DMAMUX_SYNC_EXTI_LINE10 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line10 */
#define LL_DMAMUX_SYNC_EXTI_LINE11 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line11 */
#define LL_DMAMUX_SYNC_EXTI_LINE12 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from EXTI Line12 */
#define LL_DMAMUX_SYNC_EXTI_LINE13 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line13 */
#define LL_DMAMUX_SYNC_EXTI_LINE14 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from EXTI Line14 */
#define LL_DMAMUX_SYNC_EXTI_LINE15 (DMAMUX_CxCR_SYNC_ID_3 | DMAMUX_CxCR_SYNC_ID_2 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from EXTI Line15 */
#define LL_DMAMUX_SYNC_DMAMUX_CH0 DMAMUX_CxCR_SYNC_ID_4 /*!< Synchronization signal from DMAMUX channel0 Event */
#define LL_DMAMUX_SYNC_DMAMUX_CH1 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel1 Event */
#define LL_DMAMUX_SYNC_DMAMUX_CH2 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1) /*!< Synchronization signal from DMAMUX channel2 Event */
#define LL_DMAMUX_SYNC_DMAMUX_CH3 (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_1 | DMAMUX_CxCR_SYNC_ID_0) /*!< Synchronization signal from DMAMUX channel3 Event */
#define LL_DMAMUX_SYNC_LPTIM1_OUT (DMAMUX_CxCR_SYNC_ID_4 | DMAMUX_CxCR_SYNC_ID_2) /*!< Synchronization signal from LPTIM1 Output */
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
* @{
*/
#define LL_DMAMUX_REQ_GEN_0 0x00000000U
#define LL_DMAMUX_REQ_GEN_1 0x00000001U
#define LL_DMAMUX_REQ_GEN_2 0x00000002U
#define LL_DMAMUX_REQ_GEN_3 0x00000003U
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
* @{
*/
#define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
#define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
#define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
/**
* @}
*/
/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
* @{
*/
#define LL_DMAMUX_REQ_GEN_EXTI_LINE0 0x00000000U /*!< Request signal generation from EXTI Line0 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE1 DMAMUX_RGxCR_SIG_ID_0 /*!< Request signal generation from EXTI Line1 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE2 DMAMUX_RGxCR_SIG_ID_1 /*!< Request signal generation from EXTI Line2 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE3 (DMAMUX_RGxCR_SIG_ID_1 |DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line3 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE4 DMAMUX_RGxCR_SIG_ID_2 /*!< Request signal generation from EXTI Line4 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE5 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line5 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE6 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line6 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE7 (DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line7 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE8 DMAMUX_RGxCR_SIG_ID_3 /*!< Request signal generation from EXTI Line8 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE9 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line9 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE10 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line10 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE11 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line11 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE12 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from EXTI Line12 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE13 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line13 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE14 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from EXTI Line14 */
#define LL_DMAMUX_REQ_GEN_EXTI_LINE15 (DMAMUX_RGxCR_SIG_ID_3 | DMAMUX_RGxCR_SIG_ID_2 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from EXTI Line15 */
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH0 DMAMUX_RGxCR_SIG_ID_4 /*!< Request signal generation from DMAMUX channel0 Event */
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH1 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel1 Event */
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH2 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1) /*!< Request signal generation from DMAMUX channel2 Event */
#define LL_DMAMUX_REQ_GEN_DMAMUX_CH3 (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_1 | DMAMUX_RGxCR_SIG_ID_0) /*!< Request signal generation from DMAMUX channel3 Event */
#define LL_DMAMUX_REQ_GEN_LPTIM1_OUT (DMAMUX_RGxCR_SIG_ID_4 | DMAMUX_RGxCR_SIG_ID_2) /*!< Request signal generation from LPTIM1 Output */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
* @{
*/
/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
* @{
*/
/**
* @brief Write a value in DMAMUX register
* @param __INSTANCE__ DMAMUX Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in DMAMUX register
* @param __INSTANCE__ DMAMUX Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
* @{
*/
/** @defgroup DMAMUX_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Set DMAMUX request ID for DMAMUX Channel x.
* @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
* DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
* @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @param Request This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_MEM2MEM
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR1
* @arg @ref LL_DMAMUX_REQ_GENERATOR2
* @arg @ref LL_DMAMUX_REQ_GENERATOR3
* @arg @ref LL_DMAMUX_REQ_ADC1
* @arg @ref LL_DMAMUX_REQ_DAC1_CH1
* @arg @ref LL_DMAMUX_REQ_DAC1_CH2
* @arg @ref LL_DMAMUX_REQ_TIM6_UP
* @arg @ref LL_DMAMUX_REQ_TIM7_UP
* @arg @ref LL_DMAMUX_REQ_SPI1_RX
* @arg @ref LL_DMAMUX_REQ_SPI1_TX
* @arg @ref LL_DMAMUX_REQ_SPI2_RX
* @arg @ref LL_DMAMUX_REQ_SPI2_TX
* @arg @ref LL_DMAMUX_REQ_SPI3_RX
* @arg @ref LL_DMAMUX_REQ_SPI3_TX
* @arg @ref LL_DMAMUX_REQ_I2C1_RX
* @arg @ref LL_DMAMUX_REQ_I2C1_TX
* @arg @ref LL_DMAMUX_REQ_I2C2_RX
* @arg @ref LL_DMAMUX_REQ_I2C2_TX
* @arg @ref LL_DMAMUX_REQ_I2C3_RX
* @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
* @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
* @arg @ref LL_DMAMUX_REQ_I2C4_TX
* @arg @ref LL_DMAMUX_REQ_USART1_RX
* @arg @ref LL_DMAMUX_REQ_USART1_TX
* @arg @ref LL_DMAMUX_REQ_USART2_RX
* @arg @ref LL_DMAMUX_REQ_USART2_TX
* @arg @ref LL_DMAMUX_REQ_USART3_RX
* @arg @ref LL_DMAMUX_REQ_USART3_TX
* @arg @ref LL_DMAMUX_REQ_UART4_RX
* @arg @ref LL_DMAMUX_REQ_UART4_TX
* @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
* @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
* @arg @ref LL_DMAMUX_REQ_LPUART1_RX
* @arg @ref LL_DMAMUX_REQ_LPUART1_TX
* @arg @ref LL_DMAMUX_REQ_ADC2
* @arg @ref LL_DMAMUX_REQ_ADC3 (*)
* @arg @ref LL_DMAMUX_REQ_ADC4 (*)
* @arg @ref LL_DMAMUX_REQ_ADC5 (*)
* @arg @ref LL_DMAMUX_REQ_QSPI (*)
* @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM1_CH1
* @arg @ref LL_DMAMUX_REQ_TIM1_CH2
* @arg @ref LL_DMAMUX_REQ_TIM1_CH3
* @arg @ref LL_DMAMUX_REQ_TIM1_CH4
* @arg @ref LL_DMAMUX_REQ_TIM1_UP
* @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM1_COM
* @arg @ref LL_DMAMUX_REQ_TIM8_CH1
* @arg @ref LL_DMAMUX_REQ_TIM8_CH2
* @arg @ref LL_DMAMUX_REQ_TIM8_CH3
* @arg @ref LL_DMAMUX_REQ_TIM8_CH4
* @arg @ref LL_DMAMUX_REQ_TIM8_UP
* @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM8_COM
* @arg @ref LL_DMAMUX_REQ_TIM2_CH1
* @arg @ref LL_DMAMUX_REQ_TIM2_CH2
* @arg @ref LL_DMAMUX_REQ_TIM2_CH3
* @arg @ref LL_DMAMUX_REQ_TIM2_CH4
* @arg @ref LL_DMAMUX_REQ_TIM2_UP
* @arg @ref LL_DMAMUX_REQ_TIM3_CH1
* @arg @ref LL_DMAMUX_REQ_TIM3_CH2
* @arg @ref LL_DMAMUX_REQ_TIM3_CH3
* @arg @ref LL_DMAMUX_REQ_TIM3_CH4
* @arg @ref LL_DMAMUX_REQ_TIM3_UP
* @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM4_CH1
* @arg @ref LL_DMAMUX_REQ_TIM4_CH2
* @arg @ref LL_DMAMUX_REQ_TIM4_CH3
* @arg @ref LL_DMAMUX_REQ_TIM4_CH4
* @arg @ref LL_DMAMUX_REQ_TIM4_UP
* @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
* @arg @ref LL_DMAMUX_REQ_TIM15_CH1
* @arg @ref LL_DMAMUX_REQ_TIM15_UP
* @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM15_COM
* @arg @ref LL_DMAMUX_REQ_TIM16_CH1
* @arg @ref LL_DMAMUX_REQ_TIM16_UP
* @arg @ref LL_DMAMUX_REQ_TIM17_CH1
* @arg @ref LL_DMAMUX_REQ_TIM17_UP
* @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
* @arg @ref LL_DMAMUX_REQ_AES_IN
* @arg @ref LL_DMAMUX_REQ_AES_OUT
* @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
* @arg @ref LL_DMAMUX_REQ_DAC3_CH1
* @arg @ref LL_DMAMUX_REQ_DAC3_CH2
* @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
* @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
* @arg @ref LL_DMAMUX_REQ_SAI1_A
* @arg @ref LL_DMAMUX_REQ_SAI1_B
* @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
* @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
* @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
* @arg @ref LL_DMAMUX_REQ_CORDIC_READ
* @arg @ref LL_DMAMUX_REQ_UCPD1_RX
* @arg @ref LL_DMAMUX_REQ_UCPD1_TX
* (*) Not on all G4 devices
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
{
(void)(DMAMUXx);
MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
}
/**
* @brief Get DMAMUX request ID for DMAMUX Channel x.
* @note DMAMUX channel 0 to 7 are mapped to DMA1 channel 1 to 8.
* DMAMUX channel 8 to 15 are mapped to DMA2 channel 1 to 8.
* @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* (*) Not on all G4 devices
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_MEM2MEM
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR0
* @arg @ref LL_DMAMUX_REQ_GENERATOR1
* @arg @ref LL_DMAMUX_REQ_GENERATOR2
* @arg @ref LL_DMAMUX_REQ_GENERATOR3
* @arg @ref LL_DMAMUX_REQ_ADC1
* @arg @ref LL_DMAMUX_REQ_DAC1_CH1
* @arg @ref LL_DMAMUX_REQ_DAC1_CH2
* @arg @ref LL_DMAMUX_REQ_TIM6_UP
* @arg @ref LL_DMAMUX_REQ_TIM7_UP
* @arg @ref LL_DMAMUX_REQ_SPI1_RX
* @arg @ref LL_DMAMUX_REQ_SPI1_TX
* @arg @ref LL_DMAMUX_REQ_SPI2_RX
* @arg @ref LL_DMAMUX_REQ_SPI2_TX
* @arg @ref LL_DMAMUX_REQ_SPI3_RX
* @arg @ref LL_DMAMUX_REQ_SPI3_TX
* @arg @ref LL_DMAMUX_REQ_I2C1_RX
* @arg @ref LL_DMAMUX_REQ_I2C1_TX
* @arg @ref LL_DMAMUX_REQ_I2C2_RX
* @arg @ref LL_DMAMUX_REQ_I2C2_TX
* @arg @ref LL_DMAMUX_REQ_I2C3_RX
* @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
* @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
* @arg @ref LL_DMAMUX_REQ_I2C4_TX
* @arg @ref LL_DMAMUX_REQ_USART1_RX
* @arg @ref LL_DMAMUX_REQ_USART1_TX
* @arg @ref LL_DMAMUX_REQ_USART2_RX
* @arg @ref LL_DMAMUX_REQ_USART2_TX
* @arg @ref LL_DMAMUX_REQ_USART3_RX
* @arg @ref LL_DMAMUX_REQ_USART3_TX
* @arg @ref LL_DMAMUX_REQ_UART4_RX
* @arg @ref LL_DMAMUX_REQ_UART4_TX
* @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
* @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
* @arg @ref LL_DMAMUX_REQ_LPUART1_RX
* @arg @ref LL_DMAMUX_REQ_LPUART1_TX
* @arg @ref LL_DMAMUX_REQ_ADC2
* @arg @ref LL_DMAMUX_REQ_ADC3 (*)
* @arg @ref LL_DMAMUX_REQ_ADC4 (*)
* @arg @ref LL_DMAMUX_REQ_ADC5 (*)
* @arg @ref LL_DMAMUX_REQ_QSPI (*)
* @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM1_CH1
* @arg @ref LL_DMAMUX_REQ_TIM1_CH2
* @arg @ref LL_DMAMUX_REQ_TIM1_CH3
* @arg @ref LL_DMAMUX_REQ_TIM1_CH4
* @arg @ref LL_DMAMUX_REQ_TIM1_UP
* @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM1_COM
* @arg @ref LL_DMAMUX_REQ_TIM8_CH1
* @arg @ref LL_DMAMUX_REQ_TIM8_CH2
* @arg @ref LL_DMAMUX_REQ_TIM8_CH3
* @arg @ref LL_DMAMUX_REQ_TIM8_CH4
* @arg @ref LL_DMAMUX_REQ_TIM8_UP
* @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM8_COM
* @arg @ref LL_DMAMUX_REQ_TIM2_CH1
* @arg @ref LL_DMAMUX_REQ_TIM2_CH2
* @arg @ref LL_DMAMUX_REQ_TIM2_CH3
* @arg @ref LL_DMAMUX_REQ_TIM2_CH4
* @arg @ref LL_DMAMUX_REQ_TIM2_UP
* @arg @ref LL_DMAMUX_REQ_TIM3_CH1
* @arg @ref LL_DMAMUX_REQ_TIM3_CH2
* @arg @ref LL_DMAMUX_REQ_TIM3_CH3
* @arg @ref LL_DMAMUX_REQ_TIM3_CH4
* @arg @ref LL_DMAMUX_REQ_TIM3_UP
* @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM4_CH1
* @arg @ref LL_DMAMUX_REQ_TIM4_CH2
* @arg @ref LL_DMAMUX_REQ_TIM4_CH3
* @arg @ref LL_DMAMUX_REQ_TIM4_CH4
* @arg @ref LL_DMAMUX_REQ_TIM4_UP
* @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
* @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
* @arg @ref LL_DMAMUX_REQ_TIM15_CH1
* @arg @ref LL_DMAMUX_REQ_TIM15_UP
* @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
* @arg @ref LL_DMAMUX_REQ_TIM15_COM
* @arg @ref LL_DMAMUX_REQ_TIM16_CH1
* @arg @ref LL_DMAMUX_REQ_TIM16_UP
* @arg @ref LL_DMAMUX_REQ_TIM17_CH1
* @arg @ref LL_DMAMUX_REQ_TIM17_UP
* @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
* @arg @ref LL_DMAMUX_REQ_AES_IN
* @arg @ref LL_DMAMUX_REQ_AES_OUT
* @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
* @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
* @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
* @arg @ref LL_DMAMUX_REQ_DAC3_CH1
* @arg @ref LL_DMAMUX_REQ_DAC3_CH2
* @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
* @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
* @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
* @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
* @arg @ref LL_DMAMUX_REQ_SAI1_A
* @arg @ref LL_DMAMUX_REQ_SAI1_B
* @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
* @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
* @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
* @arg @ref LL_DMAMUX_REQ_CORDIC_READ
* @arg @ref LL_DMAMUX_REQ_UCPD1_RX
* @arg @ref LL_DMAMUX_REQ_UCPD1_TX
* (*) Not on all G4 devices
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID));
}
/**
* @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
* @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
{
(void)(DMAMUXx);
MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos));
}
/**
* @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
* @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval Between Min_Data = 1 and Max_Data = 32
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
}
/**
* @brief Set the polarity of the signal on which the DMA request is synchronized.
* @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_SYNC_NO_EVENT
* @arg @ref LL_DMAMUX_SYNC_POL_RISING
* @arg @ref LL_DMAMUX_SYNC_POL_FALLING
* @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
{
(void)(DMAMUXx);
MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity);
}
/**
* @brief Get the polarity of the signal on which the DMA request is synchronized.
* @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMAMUX_SYNC_NO_EVENT
* @arg @ref LL_DMAMUX_SYNC_POL_RISING
* @arg @ref LL_DMAMUX_SYNC_POL_FALLING
* @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL));
}
/**
* @brief Enable the Event Generation on DMAMUX channel x.
* @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
}
/**
* @brief Disable the Event Generation on DMAMUX channel x.
* @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE);
}
/**
* @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
* @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL);
}
/**
* @brief Enable the synchronization mode.
* @rmtoll CxCR SE LL_DMAMUX_EnableSync
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
}
/**
* @brief Disable the synchronization mode.
* @rmtoll CxCR SE LL_DMAMUX_DisableSync
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE);
}
/**
* @brief Check if the synchronization mode is enabled or disabled.
* @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL);
}
/**
* @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
* @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @param SyncID This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
* @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
* @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
* @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
* @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
* @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
{
(void)(DMAMUXx);
MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
}
/**
* @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
* @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE0
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE1
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE2
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE3
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE4
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE5
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE6
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE7
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE8
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE9
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE10
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE11
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE12
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE13
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE14
* @arg @ref LL_DMAMUX_SYNC_EXTI_LINE15
* @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH0
* @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH1
* @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH2
* @arg @ref LL_DMAMUX_SYNC_DMAMUX_CH3
* @arg @ref LL_DMAMUX_SYNC_LPTIM1_OUT
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID));
}
/**
* @brief Enable the Request Generator.
* @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
(void)(DMAMUXx);
SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
}
/**
* @brief Disable the Request Generator.
* @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
(void)(DMAMUXx);
CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE);
}
/**
* @brief Check if the Request Generator is enabled or disabled.
* @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
(void)(DMAMUXx);
return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL);
}
/**
* @brief Set the polarity of the signal on which the DMA request is generated.
* @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
* @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
* @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
* @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
uint32_t Polarity)
{
UNUSED(DMAMUXx);
MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
}
/**
* @brief Get the polarity of the signal on which the DMA request is generated.
* @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
* @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
* @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
* @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
UNUSED(DMAMUXx);
return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL));
}
/**
* @brief Set the number of DMA request that will be autorized after a generation event.
* @note This field can only be written when Generator is disabled.
* @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
uint32_t RequestNb)
{
UNUSED(DMAMUXx);
MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
}
/**
* @brief Get the number of DMA request that will be autorized after a generation event.
* @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval Between Min_Data = 1 and Max_Data = 32
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
UNUSED(DMAMUXx);
return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
}
/**
* @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
* @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @param RequestSignalID This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
* @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
* @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
* @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
* @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
* @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel,
uint32_t RequestSignalID)
{
UNUSED(DMAMUXx);
MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
}
/**
* @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
* @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE0
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE1
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE2
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE3
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE4
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE5
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE6
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE7
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE8
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE9
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE10
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE11
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE12
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE13
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE14
* @arg @ref LL_DMAMUX_REQ_GEN_EXTI_LINE15
* @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH0
* @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH1
* @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH2
* @arg @ref LL_DMAMUX_REQ_GEN_DMAMUX_CH3
* @arg @ref LL_DMAMUX_REQ_GEN_LPTIM1_OUT
*/
__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
UNUSED(DMAMUXx);
return (READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID));
}
/**
* @}
*/
/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Synchronization Event Overrun Flag Channel 0.
* @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 1.
* @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 2.
* @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 3.
* @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 4.
* @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 5.
* @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 6.
* @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 7.
* @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 8.
* @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 9.
* @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 10.
* @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
}
/**
* @brief Get Synchronization Event Overrun Flag Channel 11.
* @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
}
#if defined (DMAMUX_CSR_SOF12)
/**
* @brief Get Synchronization Event Overrun Flag Channel 12.
* @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
}
#endif /* DMAMUX_CSR_SOF12 */
#if defined (DMAMUX_CSR_SOF13)
/**
* @brief Get Synchronization Event Overrun Flag Channel 13.
* @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
}
#endif /* DMAMUX_CSR_SOF13 */
#if defined (DMAMUX_CSR_SOF14)
/**
* @brief Get Synchronization Event Overrun Flag Channel 14.
* @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO14
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
}
#endif /* DMAMUX_CSR_SOF14 */
#if defined (DMAMUX_CSR_SOF15)
/**
* @brief Get Synchronization Event Overrun Flag Channel 15.
* @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO15
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
}
#endif /* DMAMUX_CSR_SOF15 */
/**
* @brief Get Request Generator 0 Trigger Event Overrun Flag.
* @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
}
/**
* @brief Get Request Generator 1 Trigger Event Overrun Flag.
* @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
}
/**
* @brief Get Request Generator 2 Trigger Event Overrun Flag.
* @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
}
/**
* @brief Get Request Generator 3 Trigger Event Overrun Flag.
* @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 0.
* @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 1.
* @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 2.
* @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 3.
* @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 4.
* @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 5.
* @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 6.
* @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 7.
* @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 8.
* @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 9.
* @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 10.
* @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10);
}
/**
* @brief Clear Synchronization Event Overrun Flag Channel 11.
* @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11);
}
#if defined (DMAMUX_CFR_CSOF12)
/**
* @brief Clear Synchronization Event Overrun Flag Channel 12.
* @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12);
}
#endif /* DMAMUX_CFR_CSOF12 */
#if defined (DMAMUX_CFR_CSOF13)
/**
* @brief Clear Synchronization Event Overrun Flag Channel 13.
* @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13);
}
#endif /* DMAMUX_CFR_CSOF13 */
#if defined (DMAMUX_CFR_CSOF14)
/**
* @brief Clear Synchronization Event Overrun Flag Channel 14.
* @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF14);
}
#endif /* DMAMUX_CFR_CSOF14 */
#if defined (DMAMUX_CFR_CSOF15)
/**
* @brief Clear Synchronization Event Overrun Flag Channel 15.
* @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF15);
}
#endif /* DMAMUX_CFR_CSOF15 */
/**
* @brief Clear Request Generator 0 Trigger Event Overrun Flag.
* @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0);
}
/**
* @brief Clear Request Generator 1 Trigger Event Overrun Flag.
* @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1);
}
/**
* @brief Clear Request Generator 2 Trigger Event Overrun Flag.
* @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2);
}
/**
* @brief Clear Request Generator 3 Trigger Event Overrun Flag.
* @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
* @param DMAMUXx DMAMUXx DMAMUXx Instance
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
{
UNUSED(DMAMUXx);
SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3);
}
/**
* @}
*/
/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
* @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
}
/**
* @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
* @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE);
}
/**
* @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
* @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
* @param DMAMUXx DMAMUXx Instance
* @param Channel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_CHANNEL_0
* @arg @ref LL_DMAMUX_CHANNEL_1
* @arg @ref LL_DMAMUX_CHANNEL_2
* @arg @ref LL_DMAMUX_CHANNEL_3
* @arg @ref LL_DMAMUX_CHANNEL_4
* @arg @ref LL_DMAMUX_CHANNEL_5
* @arg @ref LL_DMAMUX_CHANNEL_6
* @arg @ref LL_DMAMUX_CHANNEL_7
* @arg @ref LL_DMAMUX_CHANNEL_8
* @arg @ref LL_DMAMUX_CHANNEL_9
* @arg @ref LL_DMAMUX_CHANNEL_10
* @arg @ref LL_DMAMUX_CHANNEL_11
* @arg @ref LL_DMAMUX_CHANNEL_12
* @arg @ref LL_DMAMUX_CHANNEL_13
* @arg @ref LL_DMAMUX_CHANNEL_14
* @arg @ref LL_DMAMUX_CHANNEL_15
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
{
(void)(DMAMUXx);
return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL);
}
/**
* @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
* @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
UNUSED(DMAMUXx);
SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE);
}
/**
* @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
* @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval None
*/
__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
UNUSED(DMAMUXx);
CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE);
}
/**
* @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
* @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
* @param DMAMUXx DMAMUXx Instance
* @param RequestGenChannel This parameter can be one of the following values:
* @arg @ref LL_DMAMUX_REQ_GEN_0
* @arg @ref LL_DMAMUX_REQ_GEN_1
* @arg @ref LL_DMAMUX_REQ_GEN_2
* @arg @ref LL_DMAMUX_REQ_GEN_3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
{
UNUSED(DMAMUXx);
return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE *
(RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* DMAMUX1 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_DMAMUX_H */
| 94,191 | C | 45.931739 | 202 | 0.602499 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_cordic.h | /**
******************************************************************************
* @file stm32g4xx_hal_cordic.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the CORDIC firmware
* library.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_CORDIC_H
#define STM32G4xx_HAL_CORDIC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(CORDIC)
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup CORDIC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORDIC_Exported_Types CORDIC Exported Types
* @{
*/
/**
* @brief CORDIC HAL State Structure definition
*/
typedef enum
{
HAL_CORDIC_STATE_RESET = 0x00U, /*!< CORDIC not yet initialized or disabled */
HAL_CORDIC_STATE_READY = 0x01U, /*!< CORDIC initialized and ready for use */
HAL_CORDIC_STATE_BUSY = 0x02U, /*!< CORDIC internal process is ongoing */
HAL_CORDIC_STATE_ERROR = 0x03U /*!< CORDIC error state */
} HAL_CORDIC_StateTypeDef;
/**
* @brief CORDIC Handle Structure definition
*/
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
typedef struct __CORDIC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
{
CORDIC_TypeDef *Instance; /*!< Register base address */
int32_t *pInBuff; /*!< Pointer to CORDIC input data buffer */
int32_t *pOutBuff; /*!< Pointer to CORDIC output data buffer */
uint32_t NbCalcToOrder; /*!< Remaining number of calculation to order */
uint32_t NbCalcToGet; /*!< Remaining number of calculation result to get */
uint32_t DMADirection; /*!< Direction of CORDIC DMA transfers */
DMA_HandleTypeDef *hdmaIn; /*!< CORDIC peripheral input data DMA handle parameters */
DMA_HandleTypeDef *hdmaOut; /*!< CORDIC peripheral output data DMA handle parameters */
HAL_LockTypeDef Lock; /*!< CORDIC locking object */
__IO HAL_CORDIC_StateTypeDef State; /*!< CORDIC state */
__IO uint32_t ErrorCode; /*!< CORDIC peripheral error code
This parameter can be a value of @ref CORDIC_Error_Code */
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
void (* ErrorCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC error callback */
void (* CalculateCpltCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC calculate complete callback */
void (* MspInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp Init callback */
void (* MspDeInitCallback)(struct __CORDIC_HandleTypeDef *hcordic); /*!< CORDIC Msp DeInit callback */
#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
} CORDIC_HandleTypeDef;
/**
* @brief CORDIC Config Structure definition
*/
typedef struct
{
uint32_t Function; /*!< Function
This parameter can be a value of @ref CORDIC_Function */
uint32_t Scale; /*!< Scaling factor
This parameter can be a value of @ref CORDIC_Scale */
uint32_t InSize; /*!< Width of input data
This parameter can be a value of @ref CORDIC_In_Size */
uint32_t OutSize; /*!< Width of output data
This parameter can be a value of @ref CORDIC_Out_Size */
uint32_t NbWrite; /*!< Number of 32-bit write expected for one calculation
This parameter can be a value of @ref CORDIC_Nb_Write */
uint32_t NbRead; /*!< Number of 32-bit read expected after one calculation
This parameter can be a value of @ref CORDIC_Nb_Read */
uint32_t Precision; /*!< Number of cycles for calculation
This parameter can be a value of @ref CORDIC_Precision_In_Cycles_Number */
} CORDIC_ConfigTypeDef;
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/**
* @brief HAL CORDIC Callback ID enumeration definition
*/
typedef enum
{
HAL_CORDIC_ERROR_CB_ID = 0x00U, /*!< CORDIC error callback ID */
HAL_CORDIC_CALCULATE_CPLT_CB_ID = 0x01U, /*!< CORDIC calculate complete callback ID */
HAL_CORDIC_MSPINIT_CB_ID = 0x02U, /*!< CORDIC MspInit callback ID */
HAL_CORDIC_MSPDEINIT_CB_ID = 0x03U, /*!< CORDIC MspDeInit callback ID */
} HAL_CORDIC_CallbackIDTypeDef;
/**
* @brief HAL CORDIC Callback pointer definition
*/
typedef void (*pCORDIC_CallbackTypeDef)(CORDIC_HandleTypeDef *hcordic); /*!< pointer to a CORDIC callback function */
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORDIC_Exported_Constants CORDIC Exported Constants
* @{
*/
/** @defgroup CORDIC_Error_Code CORDIC Error code
* @{
*/
#define HAL_CORDIC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_CORDIC_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Wrong parameter error */
#define HAL_CORDIC_ERROR_NOT_READY ((uint32_t)0x00000002U) /*!< Peripheral not ready */
#define HAL_CORDIC_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
#define HAL_CORDIC_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA error */
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
#define HAL_CORDIC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U) /*!< Invalid Callback error */
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup CORDIC_Function CORDIC Function
* @{
*/
#define CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
#define CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
#define CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
#define CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
#define CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
#define CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
#define CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
#define CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
#define CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
#define CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
/**
* @}
*/
/** @defgroup CORDIC_Precision_In_Cycles_Number CORDIC Precision in Cycles Number
* @{
*/
/* Note: 1 cycle corresponds to 4 algorithm iterations */
#define CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
#define CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
#define CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
#define CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
|CORDIC_CSR_PRECISION_0))
/**
* @}
*/
/** @defgroup CORDIC_Scale CORDIC Scaling factor
* @{
*/
/* Scale factor value 'n' implies that the input data have been multiplied
by a factor 2exp(-n), and/or the output data need to be multiplied by 2exp(n). */
#define CORDIC_SCALE_0 (0x00000000U)
#define CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
#define CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
#define CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
#define CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
#define CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
#define CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
/**
* @}
*/
/** @defgroup CORDIC_Interrupts_Enable CORDIC Interrupts Enable bit
* @{
*/
#define CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result ready interrupt enable */
/**
* @}
*/
/** @defgroup CORDIC_DMAR DMA Read Request Enable bit
* @{
*/
#define CORDIC_DMA_REN CORDIC_CSR_DMAREN /*!< DMA Read requests enable */
/**
* @}
*/
/** @defgroup CORDIC_DMAW DMA Write Request Enable bit
* @{
*/
#define CORDIC_DMA_WEN CORDIC_CSR_DMAWEN /*!< DMA Write channel enable */
/**
* @}
*/
/** @defgroup CORDIC_Nb_Write CORDIC Number of 32-bit write required for one calculation
* @{
*/
#define CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
32-bit data input (Q1.31 format), or two 16-bit
data input (Q1.15 format) packed in one 32 bits
Data */
#define CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
(Q1.31 format) */
/**
* @}
*/
/** @defgroup CORDIC_Nb_Read CORDIC Number of 32-bit read required after one calculation
* @{
*/
#define CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
32-bit data output (Q1.31 format), or two 16-bit
data output (Q1.15 format) packed in one 32 bits
Data */
#define CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
(Q1.31 format) */
/**
* @}
*/
/** @defgroup CORDIC_In_Size CORDIC input data size
* @{
*/
#define CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
#define CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
/**
* @}
*/
/** @defgroup CORDIC_Out_Size CORDIC Results Size
* @{
*/
#define CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
#define CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
/**
* @}
*/
/** @defgroup CORDIC_Flags CORDIC status flags
* @{
*/
#define CORDIC_FLAG_RRDY CORDIC_CSR_RRDY /*!< Result Ready Flag */
/**
* @}
*/
/** @defgroup CORDIC_DMA_Direction CORDIC DMA direction
* @{
*/
#define CORDIC_DMA_DIR_NONE ((uint32_t)0x00000000U) /*!< DMA direction : none */
#define CORDIC_DMA_DIR_IN ((uint32_t)0x00000001U) /*!< DMA direction : Input of CORDIC */
#define CORDIC_DMA_DIR_OUT ((uint32_t)0x00000002U) /*!< DMA direction : Output of CORDIC */
#define CORDIC_DMA_DIR_IN_OUT ((uint32_t)0x00000003U) /*!< DMA direction : Input and Output of CORDIC */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CORDIC_Exported_Macros CORDIC Exported Macros
* @{
*/
/** @brief Reset CORDIC handle state.
* @param __HANDLE__ CORDIC handle
* @retval None
*/
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_CORDIC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_CORDIC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CORDIC_STATE_RESET)
#endif /*USE_HAL_CORDIC_REGISTER_CALLBACKS */
/**
* @brief Enable the CORDIC interrupt when result is ready
* @param __HANDLE__ CORDIC handle.
* @param __INTERRUPT__ CORDIC Interrupt.
* This parameter can be one of the following values:
* @arg @ref CORDIC_IT_IEN Enable Interrupt
* @retval None
*/
#define __HAL_CORDIC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CSR) |= (__INTERRUPT__))
/**
* @brief Disable the CORDIC interrupt
* @param __HANDLE__ CORDIC handle.
* @param __INTERRUPT__ CORDIC Interrupt.
* This parameter can be one of the following values:
* @arg @ref CORDIC_IT_IEN Enable Interrupt
* @retval None
*/
#define __HAL_CORDIC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CSR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified CORDIC interrupt occurred or not.
Dummy macro as no interrupt status flag.
* @param __HANDLE__ CORDIC handle.
* @param __INTERRUPT__ CORDIC interrupt to check
* @retval SET (interrupt occurred) or RESET (interrupt did not occurred)
*/
#define __HAL_CORDIC_GET_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
/** @brief Clear specified CORDIC interrupt status. Dummy macro as no
interrupt status flag.
* @param __HANDLE__ CORDIC handle.
* @param __INTERRUPT__ CORDIC interrupt to clear
* @retval None
*/
#define __HAL_CORDIC_CLEAR_IT(__HANDLE__, __INTERRUPT__) /* Dummy macro */
/** @brief Check whether the specified CORDIC status flag is set or not.
* @param __HANDLE__ CORDIC handle.
* @param __FLAG__ CORDIC flag to check
* This parameter can be one of the following values:
* @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
* @retval SET (flag is set) or RESET (flag is reset)
*/
#define __HAL_CORDIC_GET_FLAG(__HANDLE__, __FLAG__) \
((((__HANDLE__)->Instance->CSR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear specified CORDIC status flag. Dummy macro as no
flag can be cleared.
* @param __HANDLE__ CORDIC handle.
* @param __FLAG__ CORDIC flag to clear
* This parameter can be one of the following values:
* @arg @ref CORDIC_FLAG_RRDY Result Ready Flag
* @retval None
*/
#define __HAL_CORDIC_CLEAR_FLAG(__HANDLE__, __FLAG__) /* Dummy macro */
/** @brief Check whether the specified CORDIC interrupt is enabled or not.
* @param __HANDLE__ CORDIC handle.
* @param __INTERRUPT__ CORDIC interrupt to check
* This parameter can be one of the following values:
* @arg @ref CORDIC_IT_IEN Enable Interrupt
* @retval FlagStatus
*/
#define __HAL_CORDIC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->CSR) & (__INTERRUPT__))
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup CORDIC_Private_Macros CORDIC Private Macros
* @{
*/
/**
* @brief Verify the CORDIC function.
* @param __FUNCTION__ Name of the function.
* @retval SET (__FUNCTION__ is a valid value) or RESET (__FUNCTION__ is invalid)
*/
#define IS_CORDIC_FUNCTION(__FUNCTION__) (((__FUNCTION__) == CORDIC_FUNCTION_COSINE) || \
((__FUNCTION__) == CORDIC_FUNCTION_SINE) || \
((__FUNCTION__) == CORDIC_FUNCTION_PHASE) || \
((__FUNCTION__) == CORDIC_FUNCTION_MODULUS) || \
((__FUNCTION__) == CORDIC_FUNCTION_ARCTANGENT) || \
((__FUNCTION__) == CORDIC_FUNCTION_HCOSINE) || \
((__FUNCTION__) == CORDIC_FUNCTION_HSINE) || \
((__FUNCTION__) == CORDIC_FUNCTION_HARCTANGENT) || \
((__FUNCTION__) == CORDIC_FUNCTION_NATURALLOG) || \
((__FUNCTION__) == CORDIC_FUNCTION_SQUAREROOT))
/**
* @brief Verify the CORDIC precision.
* @param __PRECISION__ CORDIC Precision in Cycles Number.
* @retval SET (__PRECISION__ is a valid value) or RESET (__PRECISION__ is invalid)
*/
#define IS_CORDIC_PRECISION(__PRECISION__) (((__PRECISION__) == CORDIC_PRECISION_1CYCLE) || \
((__PRECISION__) == CORDIC_PRECISION_2CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_3CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_4CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_5CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_6CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_7CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_8CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_9CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_10CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_11CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_12CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_13CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_14CYCLES) || \
((__PRECISION__) == CORDIC_PRECISION_15CYCLES))
/**
* @brief Verify the CORDIC scaling factor.
* @param __SCALE__ Number of cycles for calculation, 1 cycle corresponding to 4 algorithm iterations.
* @retval SET (__SCALE__ is a valid value) or RESET (__SCALE__ is invalid)
*/
#define IS_CORDIC_SCALE(__SCALE__) (((__SCALE__) == CORDIC_SCALE_0) || \
((__SCALE__) == CORDIC_SCALE_1) || \
((__SCALE__) == CORDIC_SCALE_2) || \
((__SCALE__) == CORDIC_SCALE_3) || \
((__SCALE__) == CORDIC_SCALE_4) || \
((__SCALE__) == CORDIC_SCALE_5) || \
((__SCALE__) == CORDIC_SCALE_6) || \
((__SCALE__) == CORDIC_SCALE_7))
/**
* @brief Verify the CORDIC number of 32-bits write expected for one calculation.
* @param __NBWRITE__ Number of 32-bits write expected for one calculation.
* @retval SET (__NBWRITE__ is a valid value) or RESET (__NBWRITE__ is invalid)
*/
#define IS_CORDIC_NBWRITE(__NBWRITE__) (((__NBWRITE__) == CORDIC_NBWRITE_1) || \
((__NBWRITE__) == CORDIC_NBWRITE_2))
/**
* @brief Verify the CORDIC number of 32-bits read expected after one calculation.
* @param __NBREAD__ Number of 32-bits read expected after one calculation.
* @retval SET (__NBREAD__ is a valid value) or RESET (__NBREAD__ is invalid)
*/
#define IS_CORDIC_NBREAD(__NBREAD__) (((__NBREAD__) == CORDIC_NBREAD_1) || \
((__NBREAD__) == CORDIC_NBREAD_2))
/**
* @brief Verify the CORDIC input data size for one calculation.
* @param __INSIZE__ input data size for one calculation.
* @retval SET (__INSIZE__ is a valid value) or RESET (__INSIZE__ is invalid)
*/
#define IS_CORDIC_INSIZE(__INSIZE__) (((__INSIZE__) == CORDIC_INSIZE_32BITS) || \
((__INSIZE__) == CORDIC_INSIZE_16BITS))
/**
* @brief Verify the CORDIC output data size for one calculation.
* @param __OUTSIZE__ output data size for one calculation.
* @retval SET (__OUTSIZE__ is a valid value) or RESET (__OUTSIZE__ is invalid)
*/
#define IS_CORDIC_OUTSIZE(__OUTSIZE__) (((__OUTSIZE__) == CORDIC_OUTSIZE_32BITS) || \
((__OUTSIZE__) == CORDIC_OUTSIZE_16BITS))
/**
* @brief Verify the CORDIC DMA transfer Direction.
* @param __DMADIR__ DMA transfer direction.
* @retval SET (__DMADIR__ is a valid value) or RESET (__DMADIR__ is invalid)
*/
#define IS_CORDIC_DMA_DIRECTION(__DMADIR__) (((__DMADIR__) == CORDIC_DMA_DIR_IN) || \
((__DMADIR__) == CORDIC_DMA_DIR_OUT) || \
((__DMADIR__) == CORDIC_DMA_DIR_IN_OUT))
/**
* @}
*/
/** @addtogroup CORDIC_Exported_Functions
* @{
*/
/* Exported functions ------------------------------------------------------- */
/** @addtogroup CORDIC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic);
HAL_StatusTypeDef HAL_CORDIC_DeInit(CORDIC_HandleTypeDef *hcordic);
void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef *hcordic);
void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef *hcordic);
#if USE_HAL_CORDIC_REGISTER_CALLBACKS == 1
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_CORDIC_RegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID,
pCORDIC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_CORDIC_UnRegisterCallback(CORDIC_HandleTypeDef *hcordic, HAL_CORDIC_CallbackIDTypeDef CallbackID);
/**
* @}
*/
/** @addtogroup CORDIC_Exported_Functions_Group2
* @{
*/
#endif /* USE_HAL_CORDIC_REGISTER_CALLBACKS */
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_CORDIC_Configure(CORDIC_HandleTypeDef *hcordic, CORDIC_ConfigTypeDef *sConfig);
HAL_StatusTypeDef HAL_CORDIC_Calculate(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t Timeout);
HAL_StatusTypeDef HAL_CORDIC_CalculateZO(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t Timeout);
HAL_StatusTypeDef HAL_CORDIC_Calculate_IT(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc);
HAL_StatusTypeDef HAL_CORDIC_Calculate_DMA(CORDIC_HandleTypeDef *hcordic, int32_t *pInBuff, int32_t *pOutBuff,
uint32_t NbCalc, uint32_t DMADirection);
/**
* @}
*/
/** @addtogroup CORDIC_Exported_Functions_Group3
* @{
*/
/* Callback functions *********************************************************/
void HAL_CORDIC_ErrorCallback(CORDIC_HandleTypeDef *hcordic);
void HAL_CORDIC_CalculateCpltCallback(CORDIC_HandleTypeDef *hcordic);
/**
* @}
*/
/** @addtogroup CORDIC_Exported_Functions_Group4
* @{
*/
/* IRQ handler management *****************************************************/
void HAL_CORDIC_IRQHandler(CORDIC_HandleTypeDef *hcordic);
/**
* @}
*/
/** @addtogroup CORDIC_Exported_Functions_Group5
* @{
*/
/* Peripheral State functions *************************************************/
HAL_CORDIC_StateTypeDef HAL_CORDIC_GetState(CORDIC_HandleTypeDef *hcordic);
uint32_t HAL_CORDIC_GetError(CORDIC_HandleTypeDef *hcordic);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* CORDIC */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_CORDIC_H */
| 26,472 | C | 42.398361 | 136 | 0.537209 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp.h | /**
******************************************************************************
* @file stm32g4xx_hal_opamp.h
* @author MCD Application Team
* @brief Header file of OPAMP HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_OPAMP_H
#define STM32G4xx_HAL_OPAMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup OPAMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
* @{
*/
/**
* @brief OPAMP Init structure definition
*/
typedef struct
{
uint32_t PowerMode; /*!< Specifies the power mode Normal or High Speed.
This parameter must be a value of @ref OPAMP_PowerMode */
uint32_t Mode; /*!< Specifies the OPAMP mode
This parameter must be a value of @ref OPAMP_Mode
mode is either Standalone, Follower or PGA */
uint32_t InvertingInput; /*!< Specifies the inverting input in Standalone & Pga modes
- In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
This parameter must be a value of @ref OPAMP_InvertingInput
InvertingInput is either VINM0 or VINM1
- In PGA mode: i.e when mode is OPAMP_PGA_MODE
& in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
This parameter is Not Applicable */
uint32_t NonInvertingInput; /*!< Specifies the non inverting input of the opamp:
This parameter must be a value of @ref OPAMP_NonInvertingInput
NonInvertingInput is either VINP0, VINP1, VINP2 or VINP3 */
FunctionalState InternalOutput; /*!< Specifies the configuration of the internal output from OPAMP to ADC.
This parameter can be ENABLE or DISABLE
Note: When this output is enabled, regular output to I/O is disabled */
uint32_t TimerControlledMuxmode; /*!< Specifies if the Timer controlled Mux mode is enabled or disabled
This parameter must be a single value of @ref OPAMP_TimerControlledMuxmode
or a combination of them to build a more complex switch scheme by
using different timers */
uint32_t InvertingInputSecondary; /*!< Specifies the inverting input (secondary) of the opamp when
TimerControlledMuxmode is enabled
i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
- In Standalone mode: i.e when mode is OPAMP_STANDALONE_MODE
This parameter must be a value of @ref OPAMP_InvertingInputSecondary
InvertingInputSecondary is either VINM0 or VINM1
- In PGA mode: i.e when mode is OPAMP_PGA_MODE
& in Follower mode i.e when mode is OPAMP_FOLLOWER_MODE
This parameter must be a value of @ref OPAMP_InvertingInputSecondary
and is used to choose secondary mode (PGA or follower) */
uint32_t NonInvertingInputSecondary; /*!< Specifies the non inverting input (secondary) of the opamp when
TimerControlledMuxmode is enabled
i.e. when TimerControlledMuxmode is OPAMP_TIMERCONTROLLEDMUXMODE_ENABLE
This parameter must be a value of @ref OPAMP_NonInvertingInputSecondary
NonInvertingInput is either VINP0, VINP1, VINP2 or VINP3 */
uint32_t PgaConnect; /*!< Specifies the inverting pin in PGA mode
i.e. when mode is OPAMP_PGA_MODE
This parameter must be a value of @ref OPAMP_PgaConnect
Either: not connected, connected to VINM0
In this last case, VINM0 can then be used to input signal (negative gain case
with or without bias on VINPx) or to input bias (positive gain case with bias) */
uint32_t PgaGain; /*!< Specifies the gain in PGA mode
i.e. when mode is OPAMP_PGA_MODE.
This parameter must be a value of @ref OPAMP_PgaGain
(2, 4, 8, 16, 32 or 64) for positive gain & (-1, -3 ,-7, -15, -31 or -63) for negative gain */
uint32_t UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref OPAMP_UserTrimming
UserTrimming is either factory or user trimming */
uint32_t TrimmingValueP; /*!< Specifies the offset trimming value (PMOS)
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
uint32_t TrimmingValueN; /*!< Specifies the offset trimming value (NMOS)
i.e. when UserTrimming is OPAMP_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
} OPAMP_InitTypeDef;
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_OPAMP_STATE_RESET = 0x00000000UL, /*!< OPAMP is not yet Initialized */
HAL_OPAMP_STATE_READY = 0x00000001UL, /*!< OPAMP is initialized and ready for use */
HAL_OPAMP_STATE_CALIBBUSY = 0x00000002UL, /*!< OPAMP is enabled in auto calibration mode */
HAL_OPAMP_STATE_BUSY = 0x00000004UL, /*!< OPAMP is enabled and running in normal mode */
HAL_OPAMP_STATE_BUSYLOCKED = 0x00000005UL, /*!< OPAMP control register is locked
only system reset allows reconfiguring the opamp. */
} HAL_OPAMP_StateTypeDef;
/**
* @brief OPAMP Handle Structure definition
*/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
typedef struct __OPAMP_HandleTypeDef
#else
typedef struct
#endif
{
OPAMP_TypeDef *Instance; /*!< OPAMP instance's registers base address */
OPAMP_InitTypeDef Init; /*!< OPAMP required parameters */
HAL_StatusTypeDef Status; /*!< OPAMP peripheral status */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_OPAMP_StateTypeDef State; /*!< OPAMP communication state */
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __OPAMP_HandleTypeDef *hopamp);
void (* MspDeInitCallback)(struct __OPAMP_HandleTypeDef *hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
} OPAMP_HandleTypeDef;
/**
* @brief OPAMP_TrimmingValueTypeDef definition
*/
typedef uint32_t OPAMP_TrimmingValueTypeDef;
/**
* @}
*/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL OPAMP Callback ID enumeration definition
*/
typedef enum
{
HAL_OPAMP_MSPINIT_CB_ID = 0x01UL, /*!< OPAMP MspInit Callback ID */
HAL_OPAMP_MSPDEINIT_CB_ID = 0x02UL, /*!< OPAMP MspDeInit Callback ID */
HAL_OPAMP_ALL_CB_ID = 0x03UL /*!< OPAMP All ID */
} HAL_OPAMP_CallbackIDTypeDef;
/**
* @brief HAL OPAMP Callback pointer definition
*/
typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
/* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
* @{
*/
/** @defgroup OPAMP_Mode OPAMP Mode
* @{
*/
#define OPAMP_STANDALONE_MODE (0x00000000UL) /*!< standalone mode */
#define OPAMP_PGA_MODE OPAMP_CSR_VMSEL_1 /*!< PGA mode */
#define OPAMP_FOLLOWER_MODE OPAMP_CSR_VMSEL /*!< follower mode */
/**
* @}
*/
/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input
* @{
*/
#define OPAMP_NONINVERTINGINPUT_IO0 (0x00000000UL) /*!< Non inverting input connected to I/O VINP0
(PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_NONINVERTINGINPUT_IO1 OPAMP_CSR_VPSEL_0 /*!< Non inverting input connected to I/O VINP1
(PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_NONINVERTINGINPUT_IO2 OPAMP_CSR_VPSEL_1 /*!< Non inverting input connected to I/O VINP2
(PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_NONINVERTINGINPUT_IO3 OPAMP_CSR_VPSEL /*!< Non inverting input connected to I/O VINP3
(PD14 for OPAMP2) */
#define OPAMP_NONINVERTINGINPUT_DAC OPAMP_CSR_VPSEL /*!< Non inverting input connected internally to DAC channel
(DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
/**
* @}
*/
/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input
* @{
*/
#define OPAMP_INVERTINGINPUT_IO0 (0x00000000UL) /*!< Inverting input connected to I/O VINM0
(PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_INVERTINGINPUT_IO1 OPAMP_CSR_VMSEL_0 /*!< Inverting input connected to I/0 VINM1
(PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
/**
* @}
*/
/** @defgroup OPAMP_TimerControlledMuxmode OPAMP Timer Controlled Mux mode
* @note The switch can be controlled either by a single timer or a combination of them,
* in this case application has to 'ORed' the values below
* ex OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 | OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6
* @{
*/
#define OPAMP_TIMERCONTROLLEDMUXMODE_DISABLE (0x00000000UL) /*!< Timer controlled Mux mode disabled */
#define OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 OPAMP_TCMR_T1CMEN /*!< Timer controlled Mux mode enabled using TIM1 OC6 */
#define OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 OPAMP_TCMR_T8CMEN /*!< Timer controlled Mux mode enabled using TIM8 OC6 */
#if defined(TIM20)
#define OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6 OPAMP_TCMR_T20CMEN /*!< Timer controlled Mux mode enabled using TIM20 OC6
Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
#endif
/**
* @}
*/
/** @defgroup OPAMP_NonInvertingInputSecondary OPAMP Non Inverting Input Secondary
* @{
*/
#define OPAMP_SEC_NONINVERTINGINPUT_IO0 (0x00000000UL) /*!< Secondary non inverting input connected to I/O VINP0
(PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_SEC_NONINVERTINGINPUT_IO1 OPAMP_TCMR_VPSSEL_0 /*!< Secondary non inverting input connected to I/O VINP1
(PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_SEC_NONINVERTINGINPUT_IO2 OPAMP_TCMR_VPSSEL_1 /*!< Secondary non inverting input connected to I/O VINP2
(PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_SEC_NONINVERTINGINPUT_IO3 OPAMP_TCMR_VPSSEL /*!< Secondary non inverting input connected to I/O VINP3
(PD14 for OPAMP2) */
#define OPAMP_SEC_NONINVERTINGINPUT_DAC OPAMP_TCMR_VPSSEL /*!< Secondary non inverting input connected internally to DAC channel
(DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
/**
* @}
*/
/** @defgroup OPAMP_InvertingInputSecondary OPAMP Inverting Input Secondary
* @{
*/
#define OPAMP_SEC_INVERTINGINPUT_IO0 (0x00000000UL) /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref OPAMP_STANDALONE_MODE
has been configured by call to @ref HAL_OPAMP_Init().
Secondary inverting input connected to I/O VINM0
(PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_SEC_INVERTINGINPUT_IO1 OPAMP_TCMR_VMSSEL /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref OPAMP_STANDALONE_MODE
has been configured by call to @ref HAL_OPAMP_Init().
Secondary inverting input connected to I/0 VINM1
(PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define OPAMP_SEC_INVERTINGINPUT_PGA (0x00000000UL) /*!< OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to @ref HAL_OPAMP_Init()
is @ref OPAMP_PGA_MODE or @ref OPAMP_FOLLOWER_MODE.
OPAMP secondary inverting input is:
- Not connected if configured mode is @ref OPAMP_FOLLOWER_MODE
- Not connected if configured mode is @ref OPAMP_PGA_MODE and PGA connect mode is @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
- Connected to VINM0 and possibly VINM1 if any of the other modes as been configured
(see @ref OPAMP_PgaConnect description for more details on PGA connection modes) */
#define OPAMP_SEC_INVERTINGINPUT_FOLLOWER OPAMP_TCMR_VMSSEL /*!< OPAMP secondary mode is Follower mode - Only applicable if configured mode through call to @ref HAL_OPAMP_Init()
is @ref OPAMP_PGA_MODE or @ref OPAMP_FOLLOWER_MODE.
OPAMP secondary inverting input is not connected. */
/**
* @}
*/
/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect
* @{
*/
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO (0x00000000UL) /*!< In PGA mode, the inverting input is not connected */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 OPAMP_CSR_PGGAIN_4 /*!< In PGA mode, the inverting input is connected to VINM0 for filtering */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS OPAMP_CSR_PGGAIN_3 /*!< In PGA mode, the inverting input is connected to VINM0
- Input signal on VINM0, bias on VINPx: negative gain
- Bias on VINM0, input signal on VINPx: positive gain */
#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3) /*!< In PGA mode, the inverting input is connected to VINM0
- Input signal on VINM0, bias on VINPx: negative gain
- Bias on VINM0, input signal on VINPx: positive gain
And VINM1 is connected too for filtering */
/**
* @}
*/
/** @defgroup OPAMP_PgaGain OPAMP Pga Gain
* @note Gain sign:
* - is positive if the @ref OPAMP_PgaConnect configuration is
* @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_NO or OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
* - may be positive or negative if the @ref OPAMP_PgaConnect configuration is
* @ref OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS or OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS
* see @ref OPAMP_PgaConnect for more details
* @{
*/
#define OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL) /*!< PGA gain could be 2 or -1 */
#define OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0) /*!< PGA gain could be 4 or -3 */
#define OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 ) /*!< PGA gain could be 8 or -7 */
#define OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0) /*!< PGA gain could be 16 or -15 */
#define OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 ) /*!< PGA gain could be 32 or -31 */
#define OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0) /*!< PGA gain could be 64 or -63 */
/**
* @}
*/
/** @defgroup OPAMP_PowerMode OPAMP PowerMode
* @{
*/
#define OPAMP_POWERMODE_NORMALSPEED (0x00000000UL) /*!< Output in normal mode */
#define OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN /*!< Output in highspeed mode */
/**
* @}
*/
/** @defgroup OPAMP_UserTrimming OPAMP User Trimming
* @{
*/
#define OPAMP_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
#define OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< User trimming */
/**
* @}
*/
/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming
* @{
*/
#define OPAMP_FACTORYTRIMMING_DUMMY (0xFFFFFFFFUL) /*!< Dummy trimming value */
#define OPAMP_FACTORYTRIMMING_N (0x00000000UL) /*!< Offset trimming N */
#define OPAMP_FACTORYTRIMMING_P (0x00000001UL) /*!< Offset trimming P */
/**
* @}
*/
/** @defgroup OPAMP_VREF OPAMP VREF
* @{
*/
#define OPAMP_VREF_3VDDA (0x00000000UL) /*!< OPAMP Vref = 3.3% VDDA */
#define OPAMP_VREF_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPAMP Vref = 10% VDDA */
#define OPAMP_VREF_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPAMP Vref = 50% VDDA */
#define OPAMP_VREF_90VDDA OPAMP_CSR_CALSEL /*!< OPAMP Vref = 90% VDDA */
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
* @brief OPAMP Private constants and defines
* @{
*/
/** @defgroup OPAMP_Input OPAMP Input
* @{
*/
#define OPAMP_INPUT_INVERTING ( 24UL) /*!< Inverting input */
#define OPAMP_INPUT_NONINVERTING ( 19UL) /*!< Non inverting input */
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_INPUT_INVERTING) || \
((INPUT) == OPAMP_INPUT_NONINVERTING))
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup OPAMP_Private_Macros OPAMP Private Macros
* @{
*/
#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
((INPUT) == OPAMP_PGA_MODE) || \
((INPUT) == OPAMP_FOLLOWER_MODE))
#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_IO1) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_IO2) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_IO3) || \
((INPUT) == OPAMP_NONINVERTINGINPUT_DAC))
#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_INVERTINGINPUT_IO1))
#if defined(TIM20)
#define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) \
((MUXMODE) <= (OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 | \
OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6 | \
OPAMP_TIMERCONTROLLEDMUXMODE_TIM20_CH6))
#else
#define IS_OPAMP_TIMERCONTROLLED_MUXMODE(MUXMODE) \
((MUXMODE) <= (OPAMP_TIMERCONTROLLEDMUXMODE_TIM1_CH6 | \
OPAMP_TIMERCONTROLLEDMUXMODE_TIM8_CH6))
#endif
#define IS_OPAMP_SEC_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO1) || \
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO2) || \
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_IO3) || \
((INPUT) == OPAMP_SEC_NONINVERTINGINPUT_DAC))
#define IS_OPAMP_SEC_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO0) || \
((INPUT) == OPAMP_SEC_INVERTINGINPUT_IO1) || \
((INPUT) == OPAMP_SEC_INVERTINGINPUT_PGA) || \
((INPUT) == OPAMP_SEC_INVERTINGINPUT_FOLLOWER))
#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO) || \
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \
((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))
#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \
((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \
((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \
((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15) || \
((GAIN) == OPAMP_PGA_GAIN_32_OR_MINUS_31) || \
((GAIN) == OPAMP_PGA_GAIN_64_OR_MINUS_63))
#define IS_OPAMP_POWERMODE(POWERMODE) (((POWERMODE) == OPAMP_POWERMODE_NORMALSPEED) || \
((POWERMODE) == OPAMP_POWERMODE_HIGHSPEED) )
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
((TRIMMING) == OPAMP_TRIMMING_USER))
#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
((TRIMMING) == OPAMP_FACTORYTRIMMING_P))
#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FUL)
#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA) || \
((VREF) == OPAMP_VREF_10VDDA) || \
((VREF) == OPAMP_VREF_50VDDA) || \
((VREF) == OPAMP_VREF_90VDDA))
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros
* @{
*/
/** @brief Reset OPAMP handle state
* @param __HANDLE__ OPAMP handle.
* @retval None
*/
#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
/**
* @}
*/
/* Include OPAMP HAL Extended module */
#include "stm32g4xx_hal_opamp_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
* @{
*/
/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions **********************************/
HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp);
void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* I/O operation functions *****************************************************/
HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)
/* OPAMP callback registering/unregistering */
HAL_StatusTypeDef HAL_OPAMP_RegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId,
pOPAMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback(OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
HAL_StatusTypeDef HAL_OPAMP_LockTimerMux(OPAMP_HandleTypeDef *hopamp);
/**
* @}
*/
/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* Peripheral State functions **************************************************/
HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset(OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_OPAMP_H */
| 31,311 | C | 53.550523 | 199 | 0.512536 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_system.h | /**
******************************************************************************
* @file stm32g4xx_ll_system.h
* @author MCD Application Team
* @brief Header file of SYSTEM LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL SYSTEM driver contains a set of generic APIs that can be
used by user:
(+) Some of the FLASH features need to be handled in the SYSTEM file.
(+) Access to DBGCMU registers
(+) Access to SYSCFG registers
(+) Access to VREFBUF registers
@endverbatim
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_LL_SYSTEM_H
#define __STM32G4xx_LL_SYSTEM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF)
/** @defgroup SYSTEM_LL SYSTEM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
* @{
*/
/* Defines used for position in the register */
#define DBGMCU_REVID_POSITION (uint32_t)POSITION_VAL(DBGMCU_IDCODE_REV_ID)
/**
* @brief Power-down in Run mode Flash key
*/
#define FLASH_PDKEY1 0x04152637U /*!< Flash power down key1 */
#define FLASH_PDKEY2 0xFAFBFCFDU /*!< Flash power down key2: used with FLASH_PDKEY1
to unlock the RUN_PD bit in FLASH_ACR */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
* @{
*/
/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
* @{
*/
#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */
#if defined(FMC_Bank1_R)
#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC bank 1 (NOR/PSRAM 1 and 2) mapped at 0x00000000 */
#endif /* FMC_Bank1_R */
#define LL_SYSCFG_REMAP_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) /*!< QUADSPI memory mapped at 0x00000000 */
/**
* @}
*/
#if defined(SYSCFG_MEMRMP_FB_MODE)
/** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
* @{
*/
#define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank1 mapped at 0x08000000 (and aliased @0x00000000)
and Flash Bank2 mapped at 0x08040000 (and aliased at 0x00080000) */
#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_FB_MODE /*!< Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
and Flash Bank1 mapped at 0x08040000 (and aliased at 0x00080000) */
/**
* @}
*/
#endif /* SYSCFG_MEMRMP_FB_MODE */
/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
* @{
*/
#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(I2C2)
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#endif /* I2C2 */
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(I2C4)
#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#endif /* I2C4 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
* @{
*/
#define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
#define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
#define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
#define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
#define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
#define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
#define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
* @{
*/
#define LL_SYSCFG_EXTI_LINE0 (uint32_t)((0x000FU << 16U) | 0U) /* !< EXTI_POSITION_0 | EXTICR[0] */
#define LL_SYSCFG_EXTI_LINE1 (uint32_t)((0x00F0U << 16U) | 0U) /* !< EXTI_POSITION_4 | EXTICR[0] */
#define LL_SYSCFG_EXTI_LINE2 (uint32_t)((0x0F00U << 16U) | 0U) /* !< EXTI_POSITION_8 | EXTICR[0] */
#define LL_SYSCFG_EXTI_LINE3 (uint32_t)((0xF000U << 16U) | 0U) /* !< EXTI_POSITION_12 | EXTICR[0] */
#define LL_SYSCFG_EXTI_LINE4 (uint32_t)((0x000FU << 16U) | 1U) /* !< EXTI_POSITION_0 | EXTICR[1] */
#define LL_SYSCFG_EXTI_LINE5 (uint32_t)((0x00F0U << 16U) | 1U) /* !< EXTI_POSITION_4 | EXTICR[1] */
#define LL_SYSCFG_EXTI_LINE6 (uint32_t)((0x0F00U << 16U) | 1U) /* !< EXTI_POSITION_8 | EXTICR[1] */
#define LL_SYSCFG_EXTI_LINE7 (uint32_t)((0xF000U << 16U) | 1U) /* !< EXTI_POSITION_12 | EXTICR[1] */
#define LL_SYSCFG_EXTI_LINE8 (uint32_t)((0x000FU << 16U) | 2U) /* !< EXTI_POSITION_0 | EXTICR[2] */
#define LL_SYSCFG_EXTI_LINE9 (uint32_t)((0x00F0U << 16U) | 2U) /* !< EXTI_POSITION_4 | EXTICR[2] */
#define LL_SYSCFG_EXTI_LINE10 (uint32_t)((0x0F00U << 16U) | 2U) /* !< EXTI_POSITION_8 | EXTICR[2] */
#define LL_SYSCFG_EXTI_LINE11 (uint32_t)((0xF000U << 16U) | 2U) /* !< EXTI_POSITION_12 | EXTICR[2] */
#define LL_SYSCFG_EXTI_LINE12 (uint32_t)((0x000FU << 16U) | 3U) /* !< EXTI_POSITION_0 | EXTICR[3] */
#define LL_SYSCFG_EXTI_LINE13 (uint32_t)((0x00F0U << 16U) | 3U) /* !< EXTI_POSITION_4 | EXTICR[3] */
#define LL_SYSCFG_EXTI_LINE14 (uint32_t)((0x0F00U << 16U) | 3U) /* !< EXTI_POSITION_8 | EXTICR[3] */
#define LL_SYSCFG_EXTI_LINE15 (uint32_t)((0xF000U << 16U) | 3U) /* !< EXTI_POSITION_12 | EXTICR[3] */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
* @{
*/
#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal
with Break Input of TIM1/8/15/16/17 */
#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection
with TIM1/8/15/16/17 Break Input
and also the PVDE and PLS bits of the Power Control Interface */
#define LL_SYSCFG_TIMBREAK_SRAM_PARITY SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal
with Break Input of TIM1/8/15/16/17 */
#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4
with Break Input of TIM1/15/16/17 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_CCMSRAMWRP SYSCFG CCMSRAM WRP
* @{
*/
#define LL_SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
#if defined(SYSCFG_SWPR_PAGE10)
#define LL_SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
#define LL_SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
#endif /* SYSCFG_SWPR_PAGE10 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
* @{
*/
#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/
#if defined(TIM3)
#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/
#endif /* TIM3 */
#if defined(TIM4)
#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/
#endif /* TIM4 */
#if defined(TIM5)
#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/
#endif /* TIM5 */
#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/
#if defined(TIM7)
#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/
#endif /* TIM7 */
#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP /*!< The clock of the RTC counter is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/
#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/
#if defined(I2C2)
#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/
#endif /* I2C2 */
#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP /*!< The I2C3 SMBus timeout is frozen*/
#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP
* @{
*/
#if defined(I2C4)
#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/
#endif /* I2C4 */
/**
* @}
*/
/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
* @{
*/
#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/
#if defined(TIM8)
#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/
#endif /* TIM8 */
#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/
#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/
#if defined(TIM17)
#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/
#endif /* TIM17 */
#if defined(TIM20)
#define LL_DBGMCU_APB2_GRP1_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP /*!< The counter clock of TIM20 is stopped when the core is halted*/
#endif /* TIM20 */
#if defined(HRTIM1)
#define LL_DBGMCU_APB2_GRP1_HRTIM1_STOP DBGMCU_APB2FZ_DBG_HRTIM1_STOP /*!< The counter clock of HRTIM1 is stopped when the core is halted*/
#endif /* HRTIM1 */
/**
* @}
*/
#if defined(VREFBUF)
/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE
* @{
*/
#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
* @{
*/
#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
#if defined(FLASH_ACR_LATENCY_5WS)
#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
#endif /* FLASH_ACR_LATENCY_5WS */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
* @{
*/
/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
* @{
*/
/**
* @brief Set memory mapping at address 0x00000000
* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_SetRemapMemory
* @param Memory This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_REMAP_FLASH
* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
* @arg @ref LL_SYSCFG_REMAP_SRAM
* @arg @ref LL_SYSCFG_REMAP_FMC (*)
* @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
{
MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
}
/**
* @brief Get memory mapping at address 0x00000000
* @rmtoll SYSCFG_MEMRMP MEM_MODE LL_SYSCFG_GetRemapMemory
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_REMAP_FLASH
* @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
* @arg @ref LL_SYSCFG_REMAP_SRAM
* @arg @ref LL_SYSCFG_REMAP_FMC (*)
* @arg @ref LL_SYSCFG_REMAP_QUADSPI (*)
*
* (*) value not defined in all devices
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
{
return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
}
#if defined(SYSCFG_MEMRMP_FB_MODE)
/**
* @brief Select Flash bank mode (Bank flashed at 0x08000000)
* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
* @param Bank This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_BANKMODE_BANK1
* @arg @ref LL_SYSCFG_BANKMODE_BANK2
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
{
MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE, Bank);
}
/**
* @brief Get Flash bank mode (Bank flashed at 0x08000000)
* @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_BANKMODE_BANK1
* @arg @ref LL_SYSCFG_BANKMODE_BANK2
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
{
return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE));
}
#endif /* SYSCFG_MEMRMP_FB_MODE */
/**
* @brief Enable I/O analog switch voltage booster.
* @note When voltage booster is enabled, I/O analog switches are supplied
* by a dedicated voltage booster, from VDD power domain. This is
* the recommended configuration with low VDDA voltage operation.
* @note The I/O analog switch voltage booster is relevant for peripherals
* using I/O in analog input: ADC, COMP, OPAMP.
* However, COMP and OPAMP inputs have a high impedance and
* voltage booster do not impact performance significantly.
* Therefore, the voltage booster is mainly intended for
* usage with ADC.
* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Disable I/O analog switch voltage booster.
* @note When voltage booster is enabled, I/O analog switches are supplied
* by a dedicated voltage booster, from VDD power domain. This is
* the recommended configuration with low VDDA voltage operation.
* @note The I/O analog switch voltage booster is relevant for peripherals
* using I/O in analog input: ADC, COMP, OPAMP.
* However, COMP and OPAMP inputs have a high impedance and
* voltage booster do not impact performance significantly.
* Therefore, the voltage booster is mainly intended for
* usage with ADC.
* @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
}
/**
* @brief Enable the I2C fast mode plus driving capability.
* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_EnableFastModePlus
* @param ConfigFastModePlus This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
}
/**
* @brief Disable the I2C fast mode plus driving capability.
* @rmtoll SYSCFG_CFGR1 I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
* SYSCFG_CFGR1 I2Cx_FMP LL_SYSCFG_DisableFastModePlus
* @param ConfigFastModePlus This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
* @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 (*)
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
}
/**
* @brief Enable Floating Point Unit Invalid operation Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
}
/**
* @brief Enable Floating Point Unit Divide-by-zero Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
}
/**
* @brief Enable Floating Point Unit Underflow Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
}
/**
* @brief Enable Floating Point Unit Overflow Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
}
/**
* @brief Enable Floating Point Unit Input denormal Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
}
/**
* @brief Enable Floating Point Unit Inexact Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void)
{
SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
}
/**
* @brief Disable Floating Point Unit Invalid operation Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0);
}
/**
* @brief Disable Floating Point Unit Divide-by-zero Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1);
}
/**
* @brief Disable Floating Point Unit Underflow Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2);
}
/**
* @brief Disable Floating Point Unit Overflow Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3);
}
/**
* @brief Disable Floating Point Unit Input denormal Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4);
}
/**
* @brief Disable Floating Point Unit Inexact Interrupt
* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void)
{
CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5);
}
/**
* @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_CFGR1 FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void)
{
return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_0) == (SYSCFG_CFGR1_FPU_IE_0)) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_CFGR1 FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void)
{
return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_1) == (SYSCFG_CFGR1_FPU_IE_1)) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_CFGR1 FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void)
{
return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_2) == (SYSCFG_CFGR1_FPU_IE_2)) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_CFGR1 FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void)
{
return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_3) == (SYSCFG_CFGR1_FPU_IE_3)) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_CFGR1 FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void)
{
return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_4) == (SYSCFG_CFGR1_FPU_IE_4)) ? 1UL : 0UL);
}
/**
* @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled.
* @rmtoll SYSCFG_CFGR1 FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void)
{
return ((READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_FPU_IE_5) == (SYSCFG_CFGR1_FPU_IE_5)) ? 1UL : 0UL);
}
/**
* @brief Configure source input for the EXTI external interrupt.
* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
* @param Port This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_EXTI_PORTA
* @arg @ref LL_SYSCFG_EXTI_PORTB
* @arg @ref LL_SYSCFG_EXTI_PORTC
* @arg @ref LL_SYSCFG_EXTI_PORTD
* @arg @ref LL_SYSCFG_EXTI_PORTE
* @arg @ref LL_SYSCFG_EXTI_PORTF
* @arg @ref LL_SYSCFG_EXTI_PORTG
*
* (*) value not defined in all devices
* @param Line This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_EXTI_LINE0
* @arg @ref LL_SYSCFG_EXTI_LINE1
* @arg @ref LL_SYSCFG_EXTI_LINE2
* @arg @ref LL_SYSCFG_EXTI_LINE3
* @arg @ref LL_SYSCFG_EXTI_LINE4
* @arg @ref LL_SYSCFG_EXTI_LINE5
* @arg @ref LL_SYSCFG_EXTI_LINE6
* @arg @ref LL_SYSCFG_EXTI_LINE7
* @arg @ref LL_SYSCFG_EXTI_LINE8
* @arg @ref LL_SYSCFG_EXTI_LINE9
* @arg @ref LL_SYSCFG_EXTI_LINE10
* @arg @ref LL_SYSCFG_EXTI_LINE11
* @arg @ref LL_SYSCFG_EXTI_LINE12
* @arg @ref LL_SYSCFG_EXTI_LINE13
* @arg @ref LL_SYSCFG_EXTI_LINE14
* @arg @ref LL_SYSCFG_EXTI_LINE15
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
{
MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << (POSITION_VAL((Line >> 16U)) & 0x1FU) );
}
/**
* @brief Get the configured defined for specific EXTI Line
* @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
* SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
* SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
* SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
* @param Line This parameter can be one of the following values:
* @arg @ref LL_SYSCFG_EXTI_LINE0
* @arg @ref LL_SYSCFG_EXTI_LINE1
* @arg @ref LL_SYSCFG_EXTI_LINE2
* @arg @ref LL_SYSCFG_EXTI_LINE3
* @arg @ref LL_SYSCFG_EXTI_LINE4
* @arg @ref LL_SYSCFG_EXTI_LINE5
* @arg @ref LL_SYSCFG_EXTI_LINE6
* @arg @ref LL_SYSCFG_EXTI_LINE7
* @arg @ref LL_SYSCFG_EXTI_LINE8
* @arg @ref LL_SYSCFG_EXTI_LINE9
* @arg @ref LL_SYSCFG_EXTI_LINE10
* @arg @ref LL_SYSCFG_EXTI_LINE11
* @arg @ref LL_SYSCFG_EXTI_LINE12
* @arg @ref LL_SYSCFG_EXTI_LINE13
* @arg @ref LL_SYSCFG_EXTI_LINE14
* @arg @ref LL_SYSCFG_EXTI_LINE15
* @retval Returned value can be one of the following values:
* @arg @ref LL_SYSCFG_EXTI_PORTA
* @arg @ref LL_SYSCFG_EXTI_PORTB
* @arg @ref LL_SYSCFG_EXTI_PORTC
* @arg @ref LL_SYSCFG_EXTI_PORTD
* @arg @ref LL_SYSCFG_EXTI_PORTE
* @arg @ref LL_SYSCFG_EXTI_PORTF
* @arg @ref LL_SYSCFG_EXTI_PORTG
*
* (*) value not defined in all devices
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
{
return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 0x1FU));
}
/**
* @brief Enable CCMSRAM Erase (starts a hardware CCMSRAM erase operation. This bit is
* automatically cleared at the end of the CCMSRAM erase operation.)
* @note This bit is write-protected: setting this bit is possible only after the
* correct key sequence is written in the SYSCFG_SKR register as described in
* the Reference Manual.
* @rmtoll SYSCFG_SCSR CCMER LL_SYSCFG_EnableCCMSRAMErase
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMErase(void)
{
/* Starts a hardware CCMSRAM erase operation*/
SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER);
}
/**
* @brief Check if CCMSRAM erase operation is on going
* @rmtoll SYSCFG_SCSR CCMBSY LL_SYSCFG_IsCCMSRAMEraseOngoing
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsCCMSRAMEraseOngoing(void)
{
return ((READ_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMBSY) == (SYSCFG_SCSR_CCMBSY)) ? 1UL : 0UL);
}
/**
* @brief Set connections to TIM1/8/15/16/17 Break inputs
* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
* SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n
* SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n
* SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs
* @param Break This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_TIMBREAK_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_PVD
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
{
MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break);
}
/**
* @brief Get connections to TIM1/8/15/16/17 Break inputs
* @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
* SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n
* SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n
* SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs
* @retval Returned value can be can be a combination of the following values:
* @arg @ref LL_SYSCFG_TIMBREAK_ECC
* @arg @ref LL_SYSCFG_TIMBREAK_PVD
* @arg @ref LL_SYSCFG_TIMBREAK_SRAM_PARITY
* @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
*/
__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
{
return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL));
}
/**
* @brief Check if SRAM parity error detected
* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_IsActiveFlag_SP
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SP(void)
{
return ((READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) == (SYSCFG_CFGR2_SPF)) ? 1UL : 0UL);
}
/**
* @brief Clear SRAM parity error flag
* @rmtoll SYSCFG_CFGR2 SPF LL_SYSCFG_ClearFlag_SP
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_ClearFlag_SP(void)
{
SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF);
}
/**
* @brief Enable CCMSRAM page write protection
* @note Write protection is cleared only by a system reset
* @rmtoll SYSCFG_SWPR PAGEx LL_SYSCFG_EnableCCMSRAMPageWRP
* @param CCMSRAMWRP This parameter can be a combination of the following values:
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE0
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE1
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE2
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE3
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE4
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE5
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE6
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE7
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE8
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE9
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE10 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE11 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE12 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE13 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE14 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE15 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE16 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE17 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE18 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE19 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE20 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE21 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE22 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE23 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE24 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE25 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE26 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE27 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE28 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE29 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE30 (*)
* @arg @ref LL_SYSCFG_CCMSRAMWRP_PAGE31 (*)
*
* (*) value not defined in all devices
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_EnableCCMSRAMPageWRP(uint32_t CCMSRAMWRP)
{
SET_BIT(SYSCFG->SWPR, CCMSRAMWRP);
}
/**
* @brief CCMSRAM page write protection lock prior to erase
* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_LockCCMSRAMWRP
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_LockCCMSRAMWRP(void)
{
/* Writing a wrong key reactivates the write protection */
WRITE_REG(SYSCFG->SKR, 0x00);
}
/**
* @brief CCMSRAM page write protection unlock prior to erase
* @rmtoll SYSCFG_SKR KEY LL_SYSCFG_UnlockCCMSRAMWRP
* @retval None
*/
__STATIC_INLINE void LL_SYSCFG_UnlockCCMSRAMWRP(void)
{
/* unlock the write protection of the CCMER bit */
WRITE_REG(SYSCFG->SKR, 0xCA);
WRITE_REG(SYSCFG->SKR, 0x53);
}
/**
* @}
*/
/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
* @{
*/
/**
* @brief Return the device identifier
* @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
* @retval Values between Min_Data=0x00 and Max_Data=0x0FFF (ex: device ID is 0x6415)
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
}
/**
* @brief Return the device revision identifier
* @note This field indicates the revision of the device.
* @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
* @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
{
return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> (DBGMCU_REVID_POSITION & 0x1FU));
}
/**
* @brief Enable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Disable the Debug Module during SLEEP mode
* @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
}
/**
* @brief Enable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Disable the Debug Module during STOP mode
* @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
}
/**
* @brief Enable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
{
SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Disable the Debug Module during STANDBY mode
* @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
{
CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
}
/**
* @brief Set Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
* @param PinAssignment This parameter can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
{
MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
}
/**
* @brief Get Trace pin assignment control
* @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
* DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
* @retval Returned value can be one of the following values:
* @arg @ref LL_DBGMCU_TRACE_NONE
* @arg @ref LL_DBGMCU_TRACE_ASYNCH
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
* @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
*/
__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
{
return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
}
/**
* @brief Freeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB1FZR1, Periphs);
}
/**
* @brief Freeze APB1 peripherals (group2 peripherals)
* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB1FZR2, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group1 peripherals)
* @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP (*)
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
* @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB1FZR1, Periphs);
}
/**
* @brief Unfreeze APB1 peripherals (group2 peripherals)
* @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB1FZR2, Periphs);
}
/**
* @brief Freeze APB2 peripherals
* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
{
SET_BIT(DBGMCU->APB2FZ, Periphs);
}
/**
* @brief Unfreeze APB2 peripherals
* @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
* @arg @ref LL_DBGMCU_APB2_GRP1_TIM20_STOP (*)
* @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM1_STOP (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
{
CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
}
/**
* @}
*/
#if defined(VREFBUF)
/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF
* @{
*/
/**
* @brief Enable Internal voltage reference
* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_Enable(void)
{
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
/**
* @brief Disable Internal voltage reference
* @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_Disable(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
}
/**
* @brief Enable high impedance (VREF+pin is high impedance)
* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void)
{
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
}
/**
* @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output)
* @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void)
{
CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ);
}
/**
* @brief Set the Voltage reference scale
* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling
* @param Scale This parameter can be one of the following values:
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale)
{
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale);
}
/**
* @brief Get the Voltage reference scale
* @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling
* @retval Returned value can be one of the following values:
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE0
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE1
* @arg @ref LL_VREFBUF_VOLTAGE_SCALE2
*/
__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void)
{
return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS));
}
/**
* @brief Check if Voltage reference buffer is ready
* @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void)
{
return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == (VREFBUF_CSR_VRR)) ? 1UL : 0UL);
}
/**
* @brief Get the trimming code for VREFBUF calibration
* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming
* @retval Between 0 and 0x3F
*/
__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void)
{
return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM));
}
/**
* @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage)
* @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming
* @param Value Between 0 and 0x3F
* @retval None
*/
__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value)
{
WRITE_REG(VREFBUF->CCR, Value);
}
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSTEM_LL_EF_FLASH FLASH
* @{
*/
/**
* @brief Set FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
* @param Latency This parameter can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @arg @ref LL_FLASH_LATENCY_3
* @arg @ref LL_FLASH_LATENCY_4
* @arg @ref LL_FLASH_LATENCY_5 (*)
* @arg @ref LL_FLASH_LATENCY_6 (*)
* @arg @ref LL_FLASH_LATENCY_7 (*)
* @arg @ref LL_FLASH_LATENCY_8 (*)
* @arg @ref LL_FLASH_LATENCY_9 (*)
* @arg @ref LL_FLASH_LATENCY_10 (*)
* @arg @ref LL_FLASH_LATENCY_11 (*)
* @arg @ref LL_FLASH_LATENCY_12 (*)
* @arg @ref LL_FLASH_LATENCY_13 (*)
* @arg @ref LL_FLASH_LATENCY_14 (*)
* @arg @ref LL_FLASH_LATENCY_15 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
{
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
}
/**
* @brief Get FLASH Latency
* @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
* @retval Returned value can be one of the following values:
* @arg @ref LL_FLASH_LATENCY_0
* @arg @ref LL_FLASH_LATENCY_1
* @arg @ref LL_FLASH_LATENCY_2
* @arg @ref LL_FLASH_LATENCY_3
* @arg @ref LL_FLASH_LATENCY_4
* @arg @ref LL_FLASH_LATENCY_5 (*)
* @arg @ref LL_FLASH_LATENCY_6 (*)
* @arg @ref LL_FLASH_LATENCY_7 (*)
* @arg @ref LL_FLASH_LATENCY_8 (*)
* @arg @ref LL_FLASH_LATENCY_9 (*)
* @arg @ref LL_FLASH_LATENCY_10 (*)
* @arg @ref LL_FLASH_LATENCY_11 (*)
* @arg @ref LL_FLASH_LATENCY_12 (*)
* @arg @ref LL_FLASH_LATENCY_13 (*)
* @arg @ref LL_FLASH_LATENCY_14 (*)
* @arg @ref LL_FLASH_LATENCY_15 (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
{
return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
}
/**
* @brief Enable Prefetch
* @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
}
/**
* @brief Disable Prefetch
* @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
}
/**
* @brief Check if Prefetch buffer is enabled
* @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
{
return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Instruction cache
* @rmtoll FLASH_ACR ICEN LL_FLASH_EnableInstCache
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
}
/**
* @brief Disable Instruction cache
* @rmtoll FLASH_ACR ICEN LL_FLASH_DisableInstCache
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
}
/**
* @brief Enable Data cache
* @rmtoll FLASH_ACR DCEN LL_FLASH_EnableDataCache
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
}
/**
* @brief Disable Data cache
* @rmtoll FLASH_ACR DCEN LL_FLASH_DisableDataCache
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
}
/**
* @brief Enable Instruction cache reset
* @note bit can be written only when the instruction cache is disabled
* @rmtoll FLASH_ACR ICRST LL_FLASH_EnableInstCacheReset
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
}
/**
* @brief Disable Instruction cache reset
* @rmtoll FLASH_ACR ICRST LL_FLASH_DisableInstCacheReset
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
}
/**
* @brief Enable Data cache reset
* @note bit can be written only when the data cache is disabled
* @rmtoll FLASH_ACR DCRST LL_FLASH_EnableDataCacheReset
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
}
/**
* @brief Disable Data cache reset
* @rmtoll FLASH_ACR DCRST LL_FLASH_DisableDataCacheReset
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
}
/**
* @brief Enable Flash Power-down mode during run mode or Low-power run mode
* @note Flash memory can be put in power-down mode only when the code is executed
* from RAM
* @note Flash must not be accessed when power down is enabled
* @note Flash must not be put in power-down while a program or an erase operation
* is on-going
* @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY1 LL_FLASH_EnableRunPowerDown\n
* FLASH_PDKEYR PDKEY2 LL_FLASH_EnableRunPowerDown
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void)
{
/* Following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR */
WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
}
/**
* @brief Disable Flash Power-down mode during run mode or Low-power run mode
* @rmtoll FLASH_ACR RUN_PD LL_FLASH_DisableRunPowerDown\n
* FLASH_PDKEYR PDKEY1 LL_FLASH_DisableRunPowerDown\n
* FLASH_PDKEYR PDKEY2 LL_FLASH_DisableRunPowerDown
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableRunPowerDown(void)
{
/* Following values must be written consecutively to unlock the RUN_PD bit in
FLASH_ACR */
WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1);
WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2);
CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);
}
/**
* @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode
* @note Flash must not be put in power-down while a program or an erase operation
* is on-going
* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown
* @retval None
*/
__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void)
{
SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
}
/**
* @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode
* @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown
* @retval None
*/
__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void)
{
CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_LL_SYSTEM_H */
| 59,149 | C | 37.99143 | 167 | 0.624136 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_def.h | /**
******************************************************************************
* @file stm32g4xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_HAL_DEF
#define __STM32G4xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h>
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00U,
HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macros -----------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
#define UNUSED(X) (void)X
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1U)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U)
#endif /* USE_RTOS */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __weak
#define __weak __attribute__((weak))
#endif
#ifndef __packed
#define __packed __attribute__((packed))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif
#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4U)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler V5*/
#define __ALIGN_BEGIN __align(4U)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
/* ARM Compiler V4/V5 and V6
--------------------------
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
------------
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif /* __CC_ARM */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ )
/* ARM V4/V5 and V6 & GNU Compiler
-------------------------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* __CC_ARM || __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* ___STM32G4xx_HAL_DEF */
| 6,885 | C | 31.790476 | 124 | 0.533043 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rng.h | /**
******************************************************************************
* @file stm32g4xx_hal_rng.h
* @author MCD Application Team
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_RNG_H
#define STM32G4xx_HAL_RNG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
#if defined (RNG)
/** @defgroup RNG RNG
* @brief RNG HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RNG_Exported_Types RNG Exported Types
* @{
*/
/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition
* @{
*/
typedef struct
{
uint32_t ClockErrorDetection; /*!< CED Clock error detection */
} RNG_InitTypeDef;
/**
* @}
*/
/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition
* @{
*/
typedef enum
{
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
} HAL_RNG_StateTypeDef;
/**
* @}
*/
/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition
* @{
*/
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
typedef struct __RNG_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
{
RNG_TypeDef *Instance; /*!< Register base address */
RNG_InitTypeDef Init; /*!< RNG configuration parameters */
HAL_LockTypeDef Lock; /*!< RNG locking object */
__IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */
__IO uint32_t ErrorCode; /*!< RNG Error code */
uint32_t RandomNumber; /*!< Last Generated RNG Data */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< RNG Data Ready Callback */
void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Error Callback */
void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp Init callback */
void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng); /*!< RNG Msp DeInit callback */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
} RNG_HandleTypeDef;
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
/**
* @brief HAL RNG Callback ID enumeration definition
*/
typedef enum
{
HAL_RNG_ERROR_CB_ID = 0x00U, /*!< RNG Error Callback ID */
HAL_RNG_MSPINIT_CB_ID = 0x01U, /*!< RNG MspInit callback ID */
HAL_RNG_MSPDEINIT_CB_ID = 0x02U /*!< RNG MspDeInit callback ID */
} HAL_RNG_CallbackIDTypeDef;
/**
* @brief HAL RNG Callback pointer definition
*/
typedef void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng); /*!< pointer to a common RNG callback function */
typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit); /*!< pointer to an RNG Data Ready specific callback function */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RNG_Exported_Constants RNG Exported Constants
* @{
*/
/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition
* @{
*/
#define RNG_IT_DRDY RNG_SR_DRDY /*!< Data Ready interrupt */
#define RNG_IT_CEI RNG_SR_CEIS /*!< Clock error interrupt */
#define RNG_IT_SEI RNG_SR_SEIS /*!< Seed error interrupt */
/**
* @}
*/
/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition
* @{
*/
#define RNG_FLAG_DRDY RNG_SR_DRDY /*!< Data ready */
#define RNG_FLAG_CECS RNG_SR_CECS /*!< Clock error current status */
#define RNG_FLAG_SECS RNG_SR_SECS /*!< Seed error current status */
/**
* @}
*/
/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection
* @{
*/
#define RNG_CED_ENABLE 0x00000000U /*!< Clock error detection Enabled */
#define RNG_CED_DISABLE RNG_CR_CED /*!< Clock error detection Disabled */
/**
* @}
*/
/** @defgroup RNG_Error_Definition RNG Error Definition
* @{
*/
#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RNG_Exported_Macros RNG Exported Macros
* @{
*/
/** @brief Reset RNG handle state
* @param __HANDLE__ RNG Handle
* @retval None
*/
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_RNG_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0U)
#else
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @brief Enables the RNG peripheral.
* @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
/**
* @brief Disables the RNG peripheral.
* @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
/**
* @brief Check the selected RNG flag status.
* @param __HANDLE__ RNG Handle
* @param __FLAG__ RNG flag
* This parameter can be one of the following values:
* @arg RNG_FLAG_DRDY: Data ready
* @arg RNG_FLAG_CECS: Clock error current status
* @arg RNG_FLAG_SECS: Seed error current status
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @brief Clears the selected RNG flag status.
* @param __HANDLE__ RNG handle
* @param __FLAG__ RNG flag to clear
* @note WARNING: This is a dummy macro for HAL code alignment,
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
* @retval None
*/
#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */
/**
* @brief Enables the RNG interrupts.
* @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
/**
* @brief Disables the RNG interrupts.
* @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
/**
* @brief Checks whether the specified RNG interrupt has occurred or not.
* @param __HANDLE__ RNG Handle
* @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
* This parameter can be one of the following values:
* @arg RNG_IT_DRDY: Data ready interrupt
* @arg RNG_IT_CEI: Clock error interrupt
* @arg RNG_IT_SEI: Seed error interrupt
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))
/**
* @brief Clear the RNG interrupt status flags.
* @param __HANDLE__ RNG Handle
* @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
* This parameter can be one of the following values:
* @arg RNG_IT_CEI: Clock error interrupt
* @arg RNG_IT_SEI: Seed error interrupt
* @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.
* @retval None
*/
#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RNG_Exported_Functions RNG Exported Functions
* @{
*/
/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions
* @{
*/
HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID,
pRNG_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
* @{
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);
/**
* @}
*/
/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
* @{
*/
HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RNG_Private_Macros RNG Private Macros
* @{
*/
#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \
((IT) == RNG_IT_SEI))
#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \
((FLAG) == RNG_FLAG_CECS) || \
((FLAG) == RNG_FLAG_SECS))
/**
* @brief Verify the RNG Clock Error Detection mode.
* @param __MODE__ RNG Clock Error Detection mode
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_RNG_CED(__MODE__) (((__MODE__) == RNG_CED_ENABLE) || \
((__MODE__) == RNG_CED_DISABLE))
/**
* @}
*/
/**
* @}
*/
#endif /* RNG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_RNG_H */
| 12,374 | C | 31.565789 | 160 | 0.561985 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_nand.h | /**
******************************************************************************
* @file stm32g4xx_hal_nand.h
* @author MCD Application Team
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_NAND_H
#define STM32G4xx_HAL_NAND_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined(FMC_BANK3)
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_ll_fmc.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup NAND
* @{
*/
/* Exported typedef ----------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Types NAND Exported Types
* @{
*/
/**
* @brief HAL NAND State structures definition
*/
typedef enum
{
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
} HAL_NAND_StateTypeDef;
/**
* @brief NAND Memory electronic signature Structure definition
*/
typedef struct
{
/*<! NAND memory electronic signature maker and device IDs */
uint8_t Maker_Id;
uint8_t Device_Id;
uint8_t Third_Id;
uint8_t Fourth_Id;
} NAND_IDTypeDef;
/**
* @brief NAND Memory address Structure definition
*/
typedef struct
{
uint16_t Page; /*!< NAND memory Page address */
uint16_t Plane; /*!< NAND memory Zone address */
uint16_t Block; /*!< NAND memory Block address */
} NAND_AddressTypeDef;
/**
* @brief NAND Memory info Structure definition
*/
typedef struct
{
uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
for 8 bits addressing or words for 16 bits addressing */
uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
for 8 bits addressing or words for 16 bits addressing */
uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
uint32_t BlockNbr; /*!< NAND memory number of total blocks */
uint32_t PlaneNbr; /*!< NAND memory number of planes */
uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
parameter is mandatory for some NAND parts after the read
command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
Example: Toshiba THTH58BYG3S0HBAI6.
This parameter could be ENABLE or DISABLE
Please check the Read Mode sequnece in the NAND device datasheet */
} NAND_DeviceConfigTypeDef;
/**
* @brief NAND handle Structure definition
*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
typedef struct __NAND_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
{
FMC_NAND_TypeDef *Instance; /*!< Register base address */
FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
HAL_LockTypeDef Lock; /*!< NAND locking object */
__IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */
void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */
void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
} NAND_HandleTypeDef;
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/**
* @brief HAL NAND Callback ID enumeration definition
*/
typedef enum
{
HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */
HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */
HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */
} HAL_NAND_CallbackIDTypeDef;
/**
* @brief HAL NAND Callback pointer definition
*/
typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup NAND_Exported_Macros NAND Exported Macros
* @{
*/
/** @brief Reset NAND handle state
* @param __HANDLE__ specifies the NAND handle.
* @retval None
*/
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_NAND_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup NAND_Exported_Functions NAND Exported Functions
* @{
*/
/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing,
FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
* @{
*/
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer,
uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress,
uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)
/* NAND callback registering/unregistering */
HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId,
pNAND_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);
#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* NAND Control functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
/**
* @}
*/
/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
* @{
*/
/* NAND State functions *******************************************************/
HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE 0x80000000UL
#define NAND_WRITE_TIMEOUT 0x01000000UL
#define CMD_AREA (1UL<<16U) /* A16 = CLE high */
#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00)
#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define NAND_CMD_READID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define NAND_CMD_RESET ((uint8_t)0xFF)
/* NAND memory status */
#define NAND_VALID_ADDRESS 0x00000100UL
#define NAND_INVALID_ADDRESS 0x00000200UL
#define NAND_TIMEOUT_ERROR 0x00000400UL
#define NAND_BUSY 0x00000000UL
#define NAND_ERROR 0x00000001UL
#define NAND_READY 0x00000040UL
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup NAND_Private_Macros NAND Private Macros
* @{
*/
/**
* @brief NAND memory address computation.
* @param __ADDRESS__ NAND memory address.
* @param __HANDLE__ NAND handle.
* @retval NAND Raw address value
*/
#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
(((__ADDRESS__)->Block + \
(((__ADDRESS__)->Plane) * \
((__HANDLE__)->Config.PlaneSize))) * \
((__HANDLE__)->Config.BlockSize)))
/**
* @brief NAND memory Column address computation.
* @param __HANDLE__ NAND handle.
* @retval NAND Raw address value
*/
#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
/**
* @brief NAND memory address cycling.
* @param __ADDRESS__ NAND memory address.
* @retval NAND address cycling value.
*/
#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
/**
* @brief NAND memory Columns cycling.
* @param __ADDRESS__ NAND memory address.
* @retval NAND Column address cycling value.
*/
#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */
#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK3 */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_NAND_H */
| 14,485 | C | 37.121053 | 121 | 0.541319 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_conf_template.h | /**
******************************************************************************
* @file stm32g4xx_hal_conf.h
* @author MCD Application Team
* @brief HAL configuration template file.
* This file should be copied to the application folder and renamed
* to stm32g4xx_hal_conf.h.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_CONF_H
#define STM32G4xx_HAL_CONF_H
#ifdef __cplusplus
extern "C" {
#endif
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* ########################## Module Selection ############################## */
/**
* @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
#define HAL_ADC_MODULE_ENABLED
#define HAL_COMP_MODULE_ENABLED
#define HAL_CORDIC_MODULE_ENABLED
#define HAL_CORTEX_MODULE_ENABLED
#define HAL_CRC_MODULE_ENABLED
#define HAL_CRYP_MODULE_ENABLED
#define HAL_DAC_MODULE_ENABLED
#define HAL_DMA_MODULE_ENABLED
#define HAL_EXTI_MODULE_ENABLED
#define HAL_FDCAN_MODULE_ENABLED
#define HAL_FLASH_MODULE_ENABLED
#define HAL_FMAC_MODULE_ENABLED
#define HAL_GPIO_MODULE_ENABLED
#define HAL_HRTIM_MODULE_ENABLED
#define HAL_IRDA_MODULE_ENABLED
#define HAL_IWDG_MODULE_ENABLED
#define HAL_I2C_MODULE_ENABLED
#define HAL_I2S_MODULE_ENABLED
#define HAL_LPTIM_MODULE_ENABLED
#define HAL_NAND_MODULE_ENABLED
#define HAL_NOR_MODULE_ENABLED
#define HAL_OPAMP_MODULE_ENABLED
#define HAL_PCD_MODULE_ENABLED
#define HAL_PWR_MODULE_ENABLED
#define HAL_QSPI_MODULE_ENABLED
#define HAL_RCC_MODULE_ENABLED
#define HAL_RNG_MODULE_ENABLED
#define HAL_RTC_MODULE_ENABLED
#define HAL_SAI_MODULE_ENABLED
#define HAL_SMARTCARD_MODULE_ENABLED
#define HAL_SMBUS_MODULE_ENABLED
#define HAL_SPI_MODULE_ENABLED
#define HAL_SRAM_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
#define HAL_UART_MODULE_ENABLED
#define HAL_USART_MODULE_ENABLED
#define HAL_WWDG_MODULE_ENABLED
/* ########################## Register Callbacks selection ############################## */
/**
* @brief This is the list of modules where register callback can be used
*/
#define USE_HAL_ADC_REGISTER_CALLBACKS 0U
#define USE_HAL_COMP_REGISTER_CALLBACKS 0U
#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U
#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U
#define USE_HAL_DAC_REGISTER_CALLBACKS 0U
#define USE_HAL_EXTI_REGISTER_CALLBACKS 0U
#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U
#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U
#define USE_HAL_HRTIM_REGISTER_CALLBACKS 0U
#define USE_HAL_I2C_REGISTER_CALLBACKS 0U
#define USE_HAL_I2S_REGISTER_CALLBACKS 0U
#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U
#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U
#define USE_HAL_NAND_REGISTER_CALLBACKS 0U
#define USE_HAL_NOR_REGISTER_CALLBACKS 0U
#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U
#define USE_HAL_PCD_REGISTER_CALLBACKS 0U
#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U
#define USE_HAL_RNG_REGISTER_CALLBACKS 0U
#define USE_HAL_RTC_REGISTER_CALLBACKS 0U
#define USE_HAL_SAI_REGISTER_CALLBACKS 0U
#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U
#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U
#define USE_HAL_SPI_REGISTER_CALLBACKS 0U
#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U
#define USE_HAL_TIM_REGISTER_CALLBACKS 0U
#define USE_HAL_UART_REGISTER_CALLBACKS 0U
#define USE_HAL_USART_REGISTER_CALLBACKS 0U
#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U
/* ########################## Oscillator Values adaptation ####################*/
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */
#endif /* HSE_STARTUP_TIMEOUT */
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
* (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (16000000UL) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @brief Internal High Speed oscillator (HSI48) value for USB FS and RNG.
* This internal oscillator is mainly dedicated to provide a high precision clock to
* the USB peripheral by means of a special Clock Recovery System (CRS) circuitry.
* When the CRS is not used, the HSI48 RC oscillator runs on it default frequency
* which is subject to manufacturing process variations.
*/
#if !defined (HSI48_VALUE)
#define HSI48_VALUE (48000000UL) /*!< Value of the Internal High Speed oscillator for USB FS/RNG in Hz.
The real value my vary depending on manufacturing process variations.*/
#endif /* HSI48_VALUE */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
#if !defined (LSI_VALUE)
/*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations in voltage and temperature.*/
#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/
#endif /* LSI_VALUE */
/**
* @brief External Low Speed oscillator (LSE) value.
* This value is used by the UART, RTC HAL module to compute the system frequency
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/
#endif /* LSE_VALUE */
#if !defined (LSE_STARTUP_TIMEOUT)
#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */
#endif /* LSE_STARTUP_TIMEOUT */
/**
* @brief External clock source for I2S and SAI peripherals
* This value is used by the I2S and SAI HAL modules to compute the I2S and SAI clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
*/
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE (48000UL) /*!< Value of the External clock source in Hz*/
#endif /* EXTERNAL_CLOCK_VALUE */
/* Tip: To avoid modifying this file each time you need to use different HSE,
=== you can define the HSE value in your toolchain compiler preprocessor. */
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
*/
#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY (0x0FUL) /*!< tick interrupt priority */
#define USE_RTOS 0U
#define PREFETCH_ENABLE 0U
#define INSTRUCTION_CACHE_ENABLE 1U
#define DATA_CACHE_ENABLE 1U
/* ########################## Assert Selection ############################## */
/**
* @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/* #define USE_FULL_ASSERT 1U */
/* ################## SPI peripheral configuration ########################## */
/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
* Activated: CRC code is present inside driver
* Deactivated: CRC code cleaned from driver
*/
#define USE_SPI_CRC 1U
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
#include "stm32g4xx_hal_rcc.h"
#endif /* HAL_RCC_MODULE_ENABLED */
#ifdef HAL_GPIO_MODULE_ENABLED
#include "stm32g4xx_hal_gpio.h"
#endif /* HAL_GPIO_MODULE_ENABLED */
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32g4xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32g4xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
#ifdef HAL_ADC_MODULE_ENABLED
#include "stm32g4xx_hal_adc.h"
#endif /* HAL_ADC_MODULE_ENABLED */
#ifdef HAL_COMP_MODULE_ENABLED
#include "stm32g4xx_hal_comp.h"
#endif /* HAL_COMP_MODULE_ENABLED */
#ifdef HAL_CORDIC_MODULE_ENABLED
#include "stm32g4xx_hal_cordic.h"
#endif /* HAL_CORDIC_MODULE_ENABLED */
#ifdef HAL_CRC_MODULE_ENABLED
#include "stm32g4xx_hal_crc.h"
#endif /* HAL_CRC_MODULE_ENABLED */
#ifdef HAL_CRYP_MODULE_ENABLED
#include "stm32g4xx_hal_cryp.h"
#endif /* HAL_CRYP_MODULE_ENABLED */
#ifdef HAL_DAC_MODULE_ENABLED
#include "stm32g4xx_hal_dac.h"
#endif /* HAL_DAC_MODULE_ENABLED */
#ifdef HAL_EXTI_MODULE_ENABLED
#include "stm32g4xx_hal_exti.h"
#endif /* HAL_EXTI_MODULE_ENABLED */
#ifdef HAL_FDCAN_MODULE_ENABLED
#include "stm32g4xx_hal_fdcan.h"
#endif /* HAL_FDCAN_MODULE_ENABLED */
#ifdef HAL_FLASH_MODULE_ENABLED
#include "stm32g4xx_hal_flash.h"
#endif /* HAL_FLASH_MODULE_ENABLED */
#ifdef HAL_FMAC_MODULE_ENABLED
#include "stm32g4xx_hal_fmac.h"
#endif /* HAL_FMAC_MODULE_ENABLED */
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32g4xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
#ifdef HAL_IRDA_MODULE_ENABLED
#include "stm32g4xx_hal_irda.h"
#endif /* HAL_IRDA_MODULE_ENABLED */
#ifdef HAL_IWDG_MODULE_ENABLED
#include "stm32g4xx_hal_iwdg.h"
#endif /* HAL_IWDG_MODULE_ENABLED */
#ifdef HAL_I2C_MODULE_ENABLED
#include "stm32g4xx_hal_i2c.h"
#endif /* HAL_I2C_MODULE_ENABLED */
#ifdef HAL_I2S_MODULE_ENABLED
#include "stm32g4xx_hal_i2s.h"
#endif /* HAL_I2S_MODULE_ENABLED */
#ifdef HAL_LPTIM_MODULE_ENABLED
#include "stm32g4xx_hal_lptim.h"
#endif /* HAL_LPTIM_MODULE_ENABLED */
#ifdef HAL_NAND_MODULE_ENABLED
#include "stm32g4xx_hal_nand.h"
#endif /* HAL_NAND_MODULE_ENABLED */
#ifdef HAL_NOR_MODULE_ENABLED
#include "stm32g4xx_hal_nor.h"
#endif /* HAL_NOR_MODULE_ENABLED */
#ifdef HAL_OPAMP_MODULE_ENABLED
#include "stm32g4xx_hal_opamp.h"
#endif /* HAL_OPAMP_MODULE_ENABLED */
#ifdef HAL_PCD_MODULE_ENABLED
#include "stm32g4xx_hal_pcd.h"
#endif /* HAL_PCD_MODULE_ENABLED */
#ifdef HAL_PWR_MODULE_ENABLED
#include "stm32g4xx_hal_pwr.h"
#endif /* HAL_PWR_MODULE_ENABLED */
#ifdef HAL_QSPI_MODULE_ENABLED
#include "stm32g4xx_hal_qspi.h"
#endif /* HAL_QSPI_MODULE_ENABLED */
#ifdef HAL_RNG_MODULE_ENABLED
#include "stm32g4xx_hal_rng.h"
#endif /* HAL_RNG_MODULE_ENABLED */
#ifdef HAL_RTC_MODULE_ENABLED
#include "stm32g4xx_hal_rtc.h"
#endif /* HAL_RTC_MODULE_ENABLED */
#ifdef HAL_SAI_MODULE_ENABLED
#include "stm32g4xx_hal_sai.h"
#endif /* HAL_SAI_MODULE_ENABLED */
#ifdef HAL_SMARTCARD_MODULE_ENABLED
#include "stm32g4xx_hal_smartcard.h"
#endif /* HAL_SMARTCARD_MODULE_ENABLED */
#ifdef HAL_SMBUS_MODULE_ENABLED
#include "stm32g4xx_hal_smbus.h"
#endif /* HAL_SMBUS_MODULE_ENABLED */
#ifdef HAL_SPI_MODULE_ENABLED
#include "stm32g4xx_hal_spi.h"
#endif /* HAL_SPI_MODULE_ENABLED */
#ifdef HAL_SRAM_MODULE_ENABLED
#include "stm32g4xx_hal_sram.h"
#endif /* HAL_SRAM_MODULE_ENABLED */
#ifdef HAL_TIM_MODULE_ENABLED
#include "stm32g4xx_hal_tim.h"
#endif /* HAL_TIM_MODULE_ENABLED */
#ifdef HAL_UART_MODULE_ENABLED
#include "stm32g4xx_hal_uart.h"
#endif /* HAL_UART_MODULE_ENABLED */
#ifdef HAL_USART_MODULE_ENABLED
#include "stm32g4xx_hal_usart.h"
#endif /* HAL_USART_MODULE_ENABLED */
#ifdef HAL_WWDG_MODULE_ENABLED
#include "stm32g4xx_hal_wwdg.h"
#endif /* HAL_WWDG_MODULE_ENABLED */
/* Exported macro ------------------------------------------------------------*/
#ifdef USE_FULL_ASSERT
/**
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
* line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_failed(uint8_t *file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
#endif /* USE_FULL_ASSERT */
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_CONF_H */
| 12,780 | C | 32.545932 | 113 | 0.656964 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_wwdg.h | /**
******************************************************************************
* @file stm32g4xx_ll_wwdg.h
* @author MCD Application Team
* @brief Header file of WWDG LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_WWDG_H
#define STM32G4xx_LL_WWDG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (WWDG)
/** @defgroup WWDG_LL WWDG
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
* @{
*/
/** @defgroup WWDG_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
* @{
*/
#define LL_WWDG_CFR_EWI WWDG_CFR_EWI
/**
* @}
*/
/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
* @{
*/
#define LL_WWDG_PRESCALER_1 0x00000000u /*!< WWDG counter clock = (PCLK1/4096)/1 */
#define LL_WWDG_PRESCALER_2 WWDG_CFR_WDGTB_0 /*!< WWDG counter clock = (PCLK1/4096)/2 */
#define LL_WWDG_PRESCALER_4 WWDG_CFR_WDGTB_1 /*!< WWDG counter clock = (PCLK1/4096)/4 */
#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
#define LL_WWDG_PRESCALER_16 WWDG_CFR_WDGTB_2 /*!< WWDG counter clock = (PCLK1/4096)/16 */
#define LL_WWDG_PRESCALER_32 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/32 */
#define LL_WWDG_PRESCALER_64 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/64 */
#define LL_WWDG_PRESCALER_128 (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/128 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
* @{
*/
/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
* @{
*/
/**
* @brief Write a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in WWDG register
* @param __INSTANCE__ WWDG Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
* @{
*/
/** @defgroup WWDG_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
* @note It is enabled by setting the WDGA bit in the WWDG_CR register,
* then it cannot be disabled again except by a reset.
* This bit is set by software and only cleared by hardware after a reset.
* When WDGA = 1, the watchdog can generate a reset.
* @rmtoll CR WDGA LL_WWDG_Enable
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
}
/**
* @brief Checks if Window Watchdog is enabled
* @rmtoll CR WDGA LL_WWDG_IsEnabled
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);
}
/**
* @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
* @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
* This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
* A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
* Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
* @rmtoll CR T LL_WWDG_SetCounter
* @param WWDGx WWDG Instance
* @param Counter 0..0x7F (7 bit counter value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
{
MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
}
/**
* @brief Return current Watchdog Counter Value (7 bits counter value)
* @rmtoll CR T LL_WWDG_GetCounter
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Counter value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CR, WWDG_CR_T));
}
/**
* @brief Set the time base of the prescaler (WDGTB).
* @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
* is decremented every (4096 x 2expWDGTB) PCLK cycles
* @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
* @param WWDGx WWDG Instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
* @arg @ref LL_WWDG_PRESCALER_16
* @arg @ref LL_WWDG_PRESCALER_32
* @arg @ref LL_WWDG_PRESCALER_64
* @arg @ref LL_WWDG_PRESCALER_128
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
}
/**
* @brief Return current Watchdog Prescaler Value
* @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
* @param WWDGx WWDG Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_WWDG_PRESCALER_1
* @arg @ref LL_WWDG_PRESCALER_2
* @arg @ref LL_WWDG_PRESCALER_4
* @arg @ref LL_WWDG_PRESCALER_8
* @arg @ref LL_WWDG_PRESCALER_16
* @arg @ref LL_WWDG_PRESCALER_32
* @arg @ref LL_WWDG_PRESCALER_64
* @arg @ref LL_WWDG_PRESCALER_128
*/
__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
}
/**
* @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
* @note This window value defines when write in the WWDG_CR register
* to program Watchdog counter is allowed.
* Watchdog counter value update must occur only when the counter value
* is lower than the Watchdog window register value.
* Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
* (in the control register) is refreshed before the downcounter has reached
* the watchdog window register value.
* Physically is possible to set the Window lower then 0x40 but it is not recommended.
* To generate an immediate reset, it is possible to set the Counter lower than 0x40.
* @rmtoll CFR W LL_WWDG_SetWindow
* @param WWDGx WWDG Instance
* @param Window 0x00..0x7F (7 bit Window value)
* @retval None
*/
__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
{
MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
}
/**
* @brief Return current Watchdog Window Value (7 bits value)
* @rmtoll CFR W LL_WWDG_GetWindow
* @param WWDGx WWDG Instance
* @retval 7 bit Watchdog Window value
*/
__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
{
return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
* @note This bit is set by hardware when the counter has reached the value 0x40.
* It must be cleared by software by writing 0.
* A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
* @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);
}
/**
* @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
* @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
{
WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
}
/**
* @}
*/
/** @defgroup WWDG_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable the Early Wakeup Interrupt.
* @note When set, an interrupt occurs whenever the counter reaches value 0x40.
* This interrupt is only cleared by hardware after a reset
* @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
* @param WWDGx WWDG Instance
* @retval None
*/
__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
{
SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
}
/**
* @brief Check if Early Wakeup Interrupt is enabled
* @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
* @param WWDGx WWDG Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
{
return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* WWDG */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_WWDG_H */
| 11,071 | C | 32.653495 | 147 | 0.566977 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio.h | /**
******************************************************************************
* @file stm32g4xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_GPIO_H
#define STM32G4xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0x00WX00YZ
* - W : EXTI trigger detection on 3 bits
* - X : EXTI mode (IT or Event) on 2 bits
* - Y : Output type (Push Pull or Open Drain) on 1 bit
* - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits
* @{
*/
#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */
#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< range up to 5 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< range 5 MHz to 25 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< range 50 MHz to 120 MHz, please refer to the product datasheet */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__ specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
/**
* @brief Generate a Software interrupt on selected EXTI line.
* @param __EXTI_LINE__ specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE_Pos 0U
#define GPIO_MODE (0x3UL << GPIO_MODE_Pos)
#define MODE_INPUT (0x0UL << GPIO_MODE_Pos)
#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos)
#define MODE_AF (0x2UL << GPIO_MODE_Pos)
#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos)
#define OUTPUT_TYPE_Pos 4U
#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos)
#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos)
#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos)
#define EXTI_MODE_Pos 16U
#define EXTI_MODE (0x3UL << EXTI_MODE_Pos)
#define EXTI_IT (0x1UL << EXTI_MODE_Pos)
#define EXTI_EVT (0x2UL << EXTI_MODE_Pos)
#define TRIGGER_MODE_Pos 20U
#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos)
#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos)
#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos)
/**
* @}
*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
/**
* @}
*/
/* Include GPIO HAL Extended module */
#include "stm32g4xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
* @brief GPIO Exported Functions
* @{
*/
/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_GPIO_H */
| 13,939 | C | 41.629969 | 183 | 0.496951 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_exti.h | /**
******************************************************************************
* @file stm32g4xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_EXTI_H
#define STM32G4xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00UL
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* PendingCallback)(void); /*!< Exti pending callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00u)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01u)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02u)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03u)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04u)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05u)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06u)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07u)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08u)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09u)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0Au)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0Bu)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0Cu)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0Du)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0Eu)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0Fu)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10u)
#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11u)
#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12u)
#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13u)
#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14u)
#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15u)
#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16u)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17u)
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18u)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19u)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1Au)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1Bu)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1Cu)
#define EXTI_LINE_29 (EXTI_CONFIG | EXTI_REG1 | 0x1Du)
#define EXTI_LINE_30 (EXTI_CONFIG | EXTI_REG1 | 0x1Eu)
#define EXTI_LINE_31 (EXTI_CONFIG | EXTI_REG1 | 0x1Fu)
#define EXTI_LINE_32 (EXTI_CONFIG | EXTI_REG2 | 0x00u)
#define EXTI_LINE_33 (EXTI_CONFIG | EXTI_REG2 | 0x01u)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02u)
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03u)
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04u)
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05u)
#define EXTI_LINE_38 (EXTI_CONFIG | EXTI_REG2 | 0x06u)
#define EXTI_LINE_39 (EXTI_CONFIG | EXTI_REG2 | 0x07u)
#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_REG2 | 0x08u)
#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_REG2 | 0x09u)
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000U
#define EXTI_MODE_INTERRUPT 0x00000001U
#define EXTI_MODE_EVENT 0x00000002U
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000U
#define EXTI_TRIGGER_RISING 0x00000001U
#define EXTI_TRIGGER_FALLING 0x00000002U
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000U
#define EXTI_GPIOB 0x00000001U
#define EXTI_GPIOC 0x00000002U
#define EXTI_GPIOD 0x00000003U
#define EXTI_GPIOE 0x00000004U
#define EXTI_GPIOF 0x00000005U
#define EXTI_GPIOG 0x00000006U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24U
#define EXTI_DIRECT (0x01uL << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02uL << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04uL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08uL << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16U
#define EXTI_REG1 (0x00uL << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01uL << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define EXTI_PIN_MASK 0x0000001FU
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#define EXTI_LINE_NB 44UL
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) && \
((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32u) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32u))))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG))
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)
#define IS_EXTI_PENDING_EDGE(__EDGE__) (((__EDGE__) == EXTI_TRIGGER_RISING) || \
((__EDGE__) == EXTI_TRIGGER_FALLING)|| \
((__EDGE__) == EXTI_TRIGGER_RISING_FALLING))
#define IS_EXTI_CB(__CB__) ((__CB__) == HAL_EXTI_COMMON_CB_ID)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_EXTI_H */
| 12,351 | C | 38.088607 | 135 | 0.48239 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_smbus_ex.h
* @author MCD Application Team
* @brief Header file of SMBUS HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SMBUS_EX_H
#define STM32G4xx_HAL_SMBUS_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SMBUSEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMBUSEx_Exported_Constants SMBUS Extended Exported Constants
* @{
*/
/** @defgroup SMBUSEx_FastModePlus SMBUS Extended Fast Mode Plus
* @{
*/
#define SMBUS_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define SMBUS_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define SMBUS_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define SMBUS_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define SMBUS_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define SMBUS_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#define SMBUS_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#define SMBUS_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define SMBUS_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
#define SMBUS_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | SMBUS_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
#endif /* SYSCFG_CFGR1_I2C4_FMP */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup SMBUSEx_Exported_Macros SMBUS Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUSEx_Exported_Functions SMBUS Extended Exported Functions
* @{
*/
/** @addtogroup SMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_SMBUSEx_EnableWakeUp(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUSEx_DisableWakeUp(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_SMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_SMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup SMBUSEx_Private_Constants SMBUS Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMBUSEx_Private_Macro SMBUS Extended Private Macros
* @{
*/
#define IS_SMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & SMBUS_FMP_NOT_SUPPORTED) != SMBUS_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB6)) == SMBUS_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB7)) == SMBUS_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB8)) == SMBUS_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_PB9)) == SMBUS_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C1)) == SMBUS_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C2)) == SMBUS_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C3)) == SMBUS_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (SMBUS_FASTMODEPLUS_I2C4)) == SMBUS_FASTMODEPLUS_I2C4)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup SMBUSEx_Private_Functions SMBUS Extended Private Functions
* @{
*/
/* Private functions are defined in stm32g4xx_hal_smbus_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SMBUS_EX_H */
| 5,569 | C | 35.405229 | 134 | 0.486622 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lptim.h | /**
******************************************************************************
* @file stm32g4xx_ll_lptim.h
* @author MCD Application Team
* @brief Header file of LPTIM LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_LPTIM_H
#define STM32G4xx_LL_LPTIM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
/** @defgroup LPTIM_LL LPTIM
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure
* @{
*/
/**
* @brief LPTIM Init structure definition
*/
typedef struct
{
uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance.
This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.
This feature can be modified afterwards using unitary
function @ref LL_LPTIM_SetClockSource().*/
uint32_t Prescaler; /*!< Specifies the prescaler division ratio.
This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.
This feature can be modified afterwards using using unitary
function @ref LL_LPTIM_SetPrescaler().*/
uint32_t Waveform; /*!< Specifies the waveform shape.
This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.
This feature can be modified afterwards using unitary
function @ref LL_LPTIM_ConfigOutput().*/
uint32_t Polarity; /*!< Specifies waveform polarity.
This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.
This feature can be modified afterwards using unitary
function @ref LL_LPTIM_ConfigOutput().*/
} LL_LPTIM_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants
* @{
*/
/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_LPTIM_ReadReg function
* @{
*/
#define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */
#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */
#define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */
#define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */
#define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */
#define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */
#define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions
* @{
*/
#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */
#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */
#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */
#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */
#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */
#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */
#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode
* @{
*/
#define LL_LPTIM_OPERATING_MODE_CONTINUOUS LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/
#define LL_LPTIM_OPERATING_MODE_ONESHOT LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode
* @{
*/
#define LL_LPTIM_UPDATE_MODE_IMMEDIATE 0x00000000U /*!<Preload is disabled: registers are updated after each APB bus write access*/
#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode
* @{
*/
#define LL_LPTIM_COUNTER_MODE_INTERNAL 0x00000000U /*!<The counter is incremented following each internal clock pulse*/
#define LL_LPTIM_COUNTER_MODE_EXTERNAL LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type
* @{
*/
#define LL_LPTIM_OUTPUT_WAVEFORM_PWM 0x00000000U /*!<LPTIM generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINUOUS or SINGLE*/
#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE LPTIM_CFGR_WAVE /*!<LPTIM generates a Set Once waveform*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity
* @{
*/
#define LL_LPTIM_OUTPUT_POLARITY_REGULAR 0x00000000U /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
#define LL_LPTIM_OUTPUT_POLARITY_INVERSE LPTIM_CFGR_WAVPOL /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value
* @{
*/
#define LL_LPTIM_PRESCALER_DIV1 0x00000000U /*!<Prescaler division factor is set to 1*/
#define LL_LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 /*!<Prescaler division factor is set to 2*/
#define LL_LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 /*!<Prescaler division factor is set to 4*/
#define LL_LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/
#define LL_LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 /*!<Prescaler division factor is set to 16*/
#define LL_LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/
#define LL_LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/
#define LL_LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC /*!<Prescaler division factor is set to 128*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source
* @{
*/
#define LL_LPTIM_TRIG_SOURCE_GPIO 0x00000000U /*!<External input trigger is connected to TIMx_ETR input*/
#define LL_LPTIM_TRIG_SOURCE_RTCALARMA LPTIM_CFGR_TRIGSEL_0 /*!<External input trigger is connected to RTC Alarm A*/
#define LL_LPTIM_TRIG_SOURCE_RTCALARMB LPTIM_CFGR_TRIGSEL_1 /*!<External input trigger is connected to RTC Alarm B*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 1*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2 LPTIM_CFGR_TRIGSEL_2 /*!<External input trigger is connected to RTC Tamper 2*/
#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to RTC Tamper 3*/
#define LL_LPTIM_TRIG_SOURCE_COMP1 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP1 output*/
#define LL_LPTIM_TRIG_SOURCE_COMP2 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP2 output*/
#define LL_LPTIM_TRIG_SOURCE_COMP3 LPTIM_CFGR_TRIGSEL_3 /*!<External input trigger is connected to COMP3 output*/
#define LL_LPTIM_TRIG_SOURCE_COMP4 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP4 output*/
#if defined(COMP5)
#define LL_LPTIM_TRIG_SOURCE_COMP5 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1) /*!<External input trigger is connected to COMP5 output*/
#endif /* COMP5 */
#if defined(COMP6)
#define LL_LPTIM_TRIG_SOURCE_COMP6 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0) /*!<External input trigger is connected to COMP6 output*/
#endif /* COMP6 */
#if defined(COMP7)
#define LL_LPTIM_TRIG_SOURCE_COMP7 (LPTIM_CFGR_TRIGSEL_3 | LPTIM_CFGR_TRIGSEL_2) /*!<External input trigger is connected to COMP7 output*/
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter
* @{
*/
#define LL_LPTIM_TRIG_FILTER_NONE 0x00000000U /*!<Any trigger active level change is considered as a valid trigger*/
#define LL_LPTIM_TRIG_FILTER_2 LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_4 LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/
#define LL_LPTIM_TRIG_FILTER_8 LPTIM_CFGR_TRGFLT /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity
* @{
*/
#define LL_LPTIM_TRIG_POLARITY_RISING LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_FALLING LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/
#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN /*!<LPTIM counter starts when a rising or a falling edge is detected*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source
* @{
*/
#define LL_LPTIM_CLK_SOURCE_INTERNAL 0x00000000U /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/
#define LL_LPTIM_CLK_SOURCE_EXTERNAL LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter
* @{
*/
#define LL_LPTIM_CLK_FILTER_NONE 0x00000000U /*!<Any external clock signal level change is considered as a valid transition*/
#define LL_LPTIM_CLK_FILTER_2 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_4 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/
#define LL_LPTIM_CLK_FILTER_8 LPTIM_CFGR_CKFLT /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity
* @{
*/
#define LL_LPTIM_CLK_POLARITY_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LL_LPTIM_CLK_POLARITY_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LL_LPTIM_CLK_POLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode
* @{
*/
#define LL_LPTIM_ENCODER_MODE_RISING 0x00000000U /*!< The rising edge is the active edge used for counting*/
#define LL_LPTIM_ENCODER_MODE_FALLING LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/
#define LL_LPTIM_ENCODER_MODE_RISING_FALLING LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/
/**
* @}
*/
/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source
* @{
*/
#define LL_LPTIM_INPUT1_SRC_GPIO 0x00000000U
#define LL_LPTIM_INPUT1_SRC_COMP1 LPTIM_OR_IN1_0
#define LL_LPTIM_INPUT1_SRC_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
#if defined(COMP5)
#define LL_LPTIM_INPUT1_SRC_COMP5 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0)
#endif /* COMP5 */
#if defined(COMP7)
#define LL_LPTIM_INPUT1_SRC_COMP7 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0)
#endif /* COMP7 */
/**
* @}
*/
/** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source
* @{
*/
#define LL_LPTIM_INPUT2_SRC_GPIO 0x00000000U
#define LL_LPTIM_INPUT2_SRC_COMP2 LPTIM_OR_IN2_0
#define LL_LPTIM_INPUT2_SRC_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0)
#if defined(COMP6)
#define LL_LPTIM_INPUT2_SRC_COMP6 (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0)
#endif /* COMP6 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros
* @{
*/
/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in LPTIM register
* @param __INSTANCE__ LPTIM Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in LPTIM register
* @param __INSTANCE__ LPTIM Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions
* @{
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions
* @{
*/
ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);
void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);
void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration
* @{
*/
/**
* @brief Enable the LPTIM instance
* @note After setting the ENABLE bit, a delay of two counter clock is needed
* before the LPTIM instance is actually enabled.
* @rmtoll CR ENABLE LL_LPTIM_Enable
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);
}
/**
* @brief Indicates whether the LPTIM instance is enabled.
* @rmtoll CR ENABLE LL_LPTIM_IsEnabled
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));
}
/**
* @brief Starts the LPTIM counter in the desired mode.
* @note LPTIM instance must be enabled before starting the counter.
* @note It is possible to change on the fly from One Shot mode to
* Continuous mode.
* @rmtoll CR CNTSTRT LL_LPTIM_StartCounter\n
* CR SNGSTRT LL_LPTIM_StartCounter
* @param LPTIMx Low-Power Timer instance
* @param OperatingMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS
* @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)
{
MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);
}
/**
* @brief Enable reset after read.
* @note After calling this function any read access to LPTIM_CNT
* register will asynchronously reset the LPTIM_CNT register content.
* @rmtoll CR RSTARE LL_LPTIM_EnableResetAfterRead
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
}
/**
* @brief Disable reset after read.
* @rmtoll CR RSTARE LL_LPTIM_DisableResetAfterRead
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);
}
/**
* @brief Indicate whether the reset after read feature is enabled.
* @rmtoll CR RSTARE LL_LPTIM_IsEnabledResetAfterRead
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));
}
/**
* @brief Reset of the LPTIM_CNT counter register (synchronous).
* @note Due to the synchronous nature of this reset, it only takes
* place after a synchronization delay of 3 LPTIM core clock cycles
* (LPTIM core clock may be different from APB clock).
* @note COUNTRST is automatically cleared by hardware
* @rmtoll CR COUNTRST LL_LPTIM_ResetCounter\n
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);
}
/**
* @brief Set the LPTIM registers update mode (enable/disable register preload)
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR PRELOAD LL_LPTIM_SetUpdateMode
* @param LPTIMx Low-Power Timer instance
* @param UpdateMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);
}
/**
* @brief Get the LPTIM registers update mode
* @rmtoll CFGR PRELOAD LL_LPTIM_GetUpdateMode
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE
* @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));
}
/**
* @brief Set the auto reload value
* @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled
* @note After a write to the LPTIMx_ARR register a new write operation to the
* same register can only be performed when the previous write operation
* is completed. Any successive write before the ARROK flag is set, will
* lead to unpredictable results.
* @note autoreload value be strictly greater than the compare value.
* @rmtoll ARR ARR LL_LPTIM_SetAutoReload
* @param LPTIMx Low-Power Timer instance
* @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)
{
MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);
}
/**
* @brief Get actual auto reload value
* @rmtoll ARR ARR LL_LPTIM_GetAutoReload
* @param LPTIMx Low-Power Timer instance
* @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));
}
/**
* @brief Set the compare value
* @note After a write to the LPTIMx_CMP register a new write operation to the
* same register can only be performed when the previous write operation
* is completed. Any successive write before the CMPOK flag is set, will
* lead to unpredictable results.
* @rmtoll CMP CMP LL_LPTIM_SetCompare
* @param LPTIMx Low-Power Timer instance
* @param CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)
{
MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);
}
/**
* @brief Get actual compare value
* @rmtoll CMP CMP LL_LPTIM_GetCompare
* @param LPTIMx Low-Power Timer instance
* @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));
}
/**
* @brief Get actual counter value
* @note When the LPTIM instance is running with an asynchronous clock, reading
* the LPTIMx_CNT register may return unreliable values. So in this case
* it is necessary to perform two consecutive read accesses and verify
* that the two returned values are identical.
* @rmtoll CNT CNT LL_LPTIM_GetCounter
* @param LPTIMx Low-Power Timer instance
* @retval Counter value
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));
}
/**
* @brief Set the counter mode (selection of the LPTIM counter clock source).
* @note The counter mode can be set only when the LPTIM instance is disabled.
* @rmtoll CFGR COUNTMODE LL_LPTIM_SetCounterMode
* @param LPTIMx Low-Power Timer instance
* @param CounterMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);
}
/**
* @brief Get the counter mode
* @rmtoll CFGR COUNTMODE LL_LPTIM_GetCounterMode
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL
* @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));
}
/**
* @brief Configure the LPTIM instance output (LPTIMx_OUT)
* @note This function must be called when the LPTIM instance is disabled.
* @note Regarding the LPTIM output polarity the change takes effect
* immediately, so the output default value will change immediately after
* the polarity is re-configured, even before the timer is enabled.
* @rmtoll CFGR WAVE LL_LPTIM_ConfigOutput\n
* CFGR WAVPOL LL_LPTIM_ConfigOutput
* @param LPTIMx Low-Power Timer instance
* @param Waveform This parameter can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);
}
/**
* @brief Set waveform shape
* @rmtoll CFGR WAVE LL_LPTIM_SetWaveform
* @param LPTIMx Low-Power Timer instance
* @param Waveform This parameter can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);
}
/**
* @brief Get actual waveform shape
* @rmtoll CFGR WAVE LL_LPTIM_GetWaveform
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM
* @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));
}
/**
* @brief Set output polarity
* @rmtoll CFGR WAVPOL LL_LPTIM_SetPolarity
* @param LPTIMx Low-Power Timer instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);
}
/**
* @brief Get actual output polarity
* @rmtoll CFGR WAVPOL LL_LPTIM_GetPolarity
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR
* @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));
}
/**
* @brief Set actual prescaler division ratio.
* @note This function must be called when the LPTIM instance is disabled.
* @note When the LPTIM is configured to be clocked by an internal clock source
* and the LPTIM counter is configured to be updated by active edges
* detected on the LPTIM external Input1, the internal clock provided to
* the LPTIM must be not be prescaled.
* @rmtoll CFGR PRESC LL_LPTIM_SetPrescaler
* @param LPTIMx Low-Power Timer instance
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_LPTIM_PRESCALER_DIV1
* @arg @ref LL_LPTIM_PRESCALER_DIV2
* @arg @ref LL_LPTIM_PRESCALER_DIV4
* @arg @ref LL_LPTIM_PRESCALER_DIV8
* @arg @ref LL_LPTIM_PRESCALER_DIV16
* @arg @ref LL_LPTIM_PRESCALER_DIV32
* @arg @ref LL_LPTIM_PRESCALER_DIV64
* @arg @ref LL_LPTIM_PRESCALER_DIV128
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);
}
/**
* @brief Get actual prescaler division ratio.
* @rmtoll CFGR PRESC LL_LPTIM_GetPrescaler
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_PRESCALER_DIV1
* @arg @ref LL_LPTIM_PRESCALER_DIV2
* @arg @ref LL_LPTIM_PRESCALER_DIV4
* @arg @ref LL_LPTIM_PRESCALER_DIV8
* @arg @ref LL_LPTIM_PRESCALER_DIV16
* @arg @ref LL_LPTIM_PRESCALER_DIV32
* @arg @ref LL_LPTIM_PRESCALER_DIV64
* @arg @ref LL_LPTIM_PRESCALER_DIV128
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));
}
/**
* @brief Set LPTIM input 1 source (default GPIO).
* @rmtoll OR IN1 LL_LPTIM_SetInput1Src
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_INPUT1_SRC_GPIO
* @arg @ref LL_LPTIM_INPUT1_SRC_COMP1
* @arg @ref LL_LPTIM_INPUT1_SRC_COMP3
* @arg @ref LL_LPTIM_INPUT1_SRC_COMP5 (*)
* @arg @ref LL_LPTIM_INPUT1_SRC_COMP7 (*)
* (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN1, Src);
}
/**
* @brief Set LPTIM input 2 source (default GPIO).
* @rmtoll OR IN2 LL_LPTIM_SetInput2Src
* @param LPTIMx Low-Power Timer instance
* @param Src This parameter can be one of the following values:
* @arg @ref LL_LPTIM_INPUT2_SRC_GPIO
* @arg @ref LL_LPTIM_INPUT2_SRC_COMP2
* @arg @ref LL_LPTIM_INPUT2_SRC_COMP4
* @arg @ref LL_LPTIM_INPUT2_SRC_COMP6 (*)
* (*) Value not defined for all devices
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)
{
MODIFY_REG(LPTIMx->OR, LPTIM_OR_IN2, Src);
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration
* @{
*/
/**
* @brief Enable the timeout function
* @note This function must be called when the LPTIM instance is disabled.
* @note The first trigger event will start the timer, any successive trigger
* event will reset the counter and the timer will restart.
* @note The timeout value corresponds to the compare value; if no trigger
* occurs within the expected time frame, the MCU is waked-up by the
* compare match event.
* @rmtoll CFGR TIMOUT LL_LPTIM_EnableTimeout
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
}
/**
* @brief Disable the timeout function
* @note This function must be called when the LPTIM instance is disabled.
* @note A trigger event arriving when the timer is already started will be
* ignored.
* @rmtoll CFGR TIMOUT LL_LPTIM_DisableTimeout
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);
}
/**
* @brief Indicate whether the timeout function is enabled.
* @rmtoll CFGR TIMOUT LL_LPTIM_IsEnabledTimeout
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));
}
/**
* @brief Start the LPTIM counter
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR TRIGEN LL_LPTIM_TrigSw
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);
}
/**
* @brief Configure the external trigger used as a trigger event for the LPTIM.
* @note This function must be called when the LPTIM instance is disabled.
* @note An internal clock source must be present when a digital filter is
* required for the trigger.
* @rmtoll CFGR TRIGSEL LL_LPTIM_ConfigTrigger\n
* CFGR TRGFLT LL_LPTIM_ConfigTrigger\n
* CFGR TRIGEN LL_LPTIM_ConfigTrigger
* @param LPTIMx Low-Power Timer instance
* @param Source This parameter can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
*
* (*) Value not defined in all devices. \n
*
* @param Filter This parameter can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_FILTER_NONE
* @arg @ref LL_LPTIM_TRIG_FILTER_2
* @arg @ref LL_LPTIM_TRIG_FILTER_4
* @arg @ref LL_LPTIM_TRIG_FILTER_8
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);
}
/**
* @brief Get actual external trigger source.
* @rmtoll CFGR TRIGSEL LL_LPTIM_GetTriggerSource
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2
* @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP3
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP4
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP5 (*)
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP6 (*)
* @arg @ref LL_LPTIM_TRIG_SOURCE_COMP7 (*)
*
* (*) Value not defined in all devices. \n
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));
}
/**
* @brief Get actual external trigger filter.
* @rmtoll CFGR TRGFLT LL_LPTIM_GetTriggerFilter
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_FILTER_NONE
* @arg @ref LL_LPTIM_TRIG_FILTER_2
* @arg @ref LL_LPTIM_TRIG_FILTER_4
* @arg @ref LL_LPTIM_TRIG_FILTER_8
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));
}
/**
* @brief Get actual external trigger polarity.
* @rmtoll CFGR TRIGEN LL_LPTIM_GetTriggerPolarity
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING
* @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING
* @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration
* @{
*/
/**
* @brief Set the source of the clock used by the LPTIM instance.
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR CKSEL LL_LPTIM_SetClockSource
* @param LPTIMx Low-Power Timer instance
* @param ClockSource This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);
}
/**
* @brief Get actual LPTIM instance clock source.
* @rmtoll CFGR CKSEL LL_LPTIM_GetClockSource
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL
* @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));
}
/**
* @brief Configure the active edge or edges used by the counter when
the LPTIM is clocked by an external clock source.
* @note This function must be called when the LPTIM instance is disabled.
* @note When both external clock signal edges are considered active ones,
* the LPTIM must also be clocked by an internal clock source with a
* frequency equal to at least four times the external clock frequency.
* @note An internal clock source must be present when a digital filter is
* required for external clock.
* @rmtoll CFGR CKFLT LL_LPTIM_ConfigClock\n
* CFGR CKPOL LL_LPTIM_ConfigClock
* @param LPTIMx Low-Power Timer instance
* @param ClockFilter This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CLK_FILTER_NONE
* @arg @ref LL_LPTIM_CLK_FILTER_2
* @arg @ref LL_LPTIM_CLK_FILTER_4
* @arg @ref LL_LPTIM_CLK_FILTER_8
* @param ClockPolarity This parameter can be one of the following values:
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING
* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);
}
/**
* @brief Get actual clock polarity
* @rmtoll CFGR CKPOL LL_LPTIM_GetClockPolarity
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING
* @arg @ref LL_LPTIM_CLK_POLARITY_FALLING
* @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
}
/**
* @brief Get actual clock digital filter
* @rmtoll CFGR CKFLT LL_LPTIM_GetClockFilter
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_CLK_FILTER_NONE
* @arg @ref LL_LPTIM_CLK_FILTER_2
* @arg @ref LL_LPTIM_CLK_FILTER_4
* @arg @ref LL_LPTIM_CLK_FILTER_8
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode
* @{
*/
/**
* @brief Configure the encoder mode.
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR CKPOL LL_LPTIM_SetEncoderMode
* @param LPTIMx Low-Power Timer instance
* @param EncoderMode This parameter can be one of the following values:
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING
* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)
{
MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);
}
/**
* @brief Get actual encoder mode.
* @rmtoll CFGR CKPOL LL_LPTIM_GetEncoderMode
* @param LPTIMx Low-Power Timer instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING
* @arg @ref LL_LPTIM_ENCODER_MODE_FALLING
* @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING
*/
__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)
{
return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));
}
/**
* @brief Enable the encoder mode
* @note This function must be called when the LPTIM instance is disabled.
* @note In this mode the LPTIM instance must be clocked by an internal clock
* source. Also, the prescaler division ratio must be equal to 1.
* @note LPTIM instance must be configured in continuous mode prior enabling
* the encoder mode.
* @rmtoll CFGR ENC LL_LPTIM_EnableEncoderMode
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
}
/**
* @brief Disable the encoder mode
* @note This function must be called when the LPTIM instance is disabled.
* @rmtoll CFGR ENC LL_LPTIM_DisableEncoderMode
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);
}
/**
* @brief Indicates whether the LPTIM operates in encoder mode.
* @rmtoll CFGR ENC LL_LPTIM_IsEnabledEncoderMode
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Clear the compare match flag (CMPMCF)
* @rmtoll ICR CMPMCF LL_LPTIM_ClearFLAG_CMPM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);
}
/**
* @brief Inform application whether a compare match interrupt has occurred.
* @rmtoll ISR CMPM LL_LPTIM_IsActiveFlag_CMPM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));
}
/**
* @brief Clear the autoreload match flag (ARRMCF)
* @rmtoll ICR ARRMCF LL_LPTIM_ClearFLAG_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);
}
/**
* @brief Inform application whether a autoreload match interrupt has occurred.
* @rmtoll ISR ARRM LL_LPTIM_IsActiveFlag_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));
}
/**
* @brief Clear the external trigger valid edge flag(EXTTRIGCF).
* @rmtoll ICR EXTTRIGCF LL_LPTIM_ClearFlag_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);
}
/**
* @brief Inform application whether a valid edge on the selected external trigger input has occurred.
* @rmtoll ISR EXTTRIG LL_LPTIM_IsActiveFlag_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));
}
/**
* @brief Clear the compare register update interrupt flag (CMPOKCF).
* @rmtoll ICR CMPOKCF LL_LPTIM_ClearFlag_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully
completed. If so, a new one can be initiated.
* @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));
}
/**
* @brief Clear the autoreload register update interrupt flag (ARROKCF).
* @rmtoll ICR ARROKCF LL_LPTIM_ClearFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);
}
/**
* @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully
completed. If so, a new one can be initiated.
* @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));
}
/**
* @brief Clear the counter direction change to up interrupt flag (UPCF).
* @rmtoll ICR UPCF LL_LPTIM_ClearFlag_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);
}
/**
* @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance
operates in encoder mode).
* @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));
}
/**
* @brief Clear the counter direction change to down interrupt flag (DOWNCF).
* @rmtoll ICR DOWNCF LL_LPTIM_ClearFlag_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);
}
/**
* @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance
operates in encoder mode).
* @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));
}
/**
* @}
*/
/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management
* @{
*/
/**
* @brief Enable compare match interrupt (CMPMIE).
* @rmtoll IER CMPMIE LL_LPTIM_EnableIT_CMPM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
}
/**
* @brief Disable compare match interrupt (CMPMIE).
* @rmtoll IER CMPMIE LL_LPTIM_DisableIT_CMPM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);
}
/**
* @brief Indicates whether the compare match interrupt (CMPMIE) is enabled.
* @rmtoll IER CMPMIE LL_LPTIM_IsEnabledIT_CMPM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));
}
/**
* @brief Enable autoreload match interrupt (ARRMIE).
* @rmtoll IER ARRMIE LL_LPTIM_EnableIT_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
}
/**
* @brief Disable autoreload match interrupt (ARRMIE).
* @rmtoll IER ARRMIE LL_LPTIM_DisableIT_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);
}
/**
* @brief Indicates whether the autoreload match interrupt (ARRMIE) is enabled.
* @rmtoll IER ARRMIE LL_LPTIM_IsEnabledIT_ARRM
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));
}
/**
* @brief Enable external trigger valid edge interrupt (EXTTRIGIE).
* @rmtoll IER EXTTRIGIE LL_LPTIM_EnableIT_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
}
/**
* @brief Disable external trigger valid edge interrupt (EXTTRIGIE).
* @rmtoll IER EXTTRIGIE LL_LPTIM_DisableIT_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);
}
/**
* @brief Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.
* @rmtoll IER EXTTRIGIE LL_LPTIM_IsEnabledIT_EXTTRIG
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));
}
/**
* @brief Enable compare register write completed interrupt (CMPOKIE).
* @rmtoll IER CMPOKIE LL_LPTIM_EnableIT_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
}
/**
* @brief Disable compare register write completed interrupt (CMPOKIE).
* @rmtoll IER CMPOKIE LL_LPTIM_DisableIT_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);
}
/**
* @brief Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.
* @rmtoll IER CMPOKIE LL_LPTIM_IsEnabledIT_CMPOK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));
}
/**
* @brief Enable autoreload register write completed interrupt (ARROKIE).
* @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
}
/**
* @brief Disable autoreload register write completed interrupt (ARROKIE).
* @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);
}
/**
* @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.
* @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));
}
/**
* @brief Enable direction change to up interrupt (UPIE).
* @rmtoll IER UPIE LL_LPTIM_EnableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
}
/**
* @brief Disable direction change to up interrupt (UPIE).
* @rmtoll IER UPIE LL_LPTIM_DisableIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);
}
/**
* @brief Indicates whether the direction change to up interrupt (UPIE) is enabled.
* @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)
{
return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));
}
/**
* @brief Enable direction change to down interrupt (DOWNIE).
* @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
}
/**
* @brief Disable direction change to down interrupt (DOWNIE).
* @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval None
*/
__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);
}
/**
* @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled.
* @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN
* @param LPTIMx Low-Power Timer instance
* @retval State of bit(1 or 0).
*/
__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)
{
return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_LPTIM_H */
| 56,180 | C | 36.504005 | 193 | 0.644037 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_gpio_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_gpio_ex.h
* @author MCD Application Team
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_GPIO_EX_H
#define STM32G4xx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup GPIOEx GPIOEx
* @brief GPIO Extended HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
* @{
*/
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#if defined(TIM5)
#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */
#endif /* TIM5 */
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#define GPIO_AF1_TIM17_COMP1 ((uint8_t)0x01) /* TIM17/COMP1 Break in Alternate Function mapping */
#define GPIO_AF1_TIM15 ((uint8_t)0x01) /* TIM15 Alternate Function mapping */
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#if defined(TIM5)
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#endif /* TIM5 */
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
#define GPIO_AF2_TIM16 ((uint8_t)0x02) /* TIM16 Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF2_TIM20 ((uint8_t)0x02) /* TIM20 Alternate Function mapping */
#endif /* TIM20 */
#define GPIO_AF2_TIM1_COMP1 ((uint8_t)0x02) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF2_TIM15_COMP1 ((uint8_t)0x02) /* TIM15/COMP1 Break in Alternate Function mapping */
#define GPIO_AF2_TIM16_COMP1 ((uint8_t)0x02) /* TIM16/COMP1 Break in Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF2_TIM20_COMP1 ((uint8_t)0x02) /* TIM20/COMP1 Break in Alternate Function mapping */
#define GPIO_AF2_TIM20_COMP2 ((uint8_t)0x02) /* TIM20/COMP2 Break in Alternate Function mapping */
#endif /* TIM20 */
#define GPIO_AF2_I2C3 ((uint8_t)0x02) /* I2C3 Alternate Function mapping */
#define GPIO_AF2_COMP1 ((uint8_t)0x02) /* COMP1 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM15 ((uint8_t)0x03) /* TIM15 Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF3_TIM20 ((uint8_t)0x03) /* TIM20 Alternate Function mapping */
#endif /* TIM20 */
#define GPIO_AF3_UCPD1 ((uint8_t)0x03) /* UCPD1 Alternate Function mapping */
#define GPIO_AF3_I2C3 ((uint8_t)0x03) /* I2C3 Alternate Function mapping */
#if defined(I2C4)
#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */
#endif /* I2C4 */
#if defined(HRTIM1)
#define GPIO_AF3_HRTIM1 ((uint8_t)0x03) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#if defined(QUADSPI)
#define GPIO_AF3_QUADSPI ((uint8_t)0x03) /* QUADSPI Alternate Function mapping */
#endif /* QUADSPI */
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */
#define GPIO_AF3_COMP3 ((uint8_t)0x03) /* COMP3 Alternate Function mapping */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_TIM1 ((uint8_t)0x04) /* TIM1 Alternate Function mapping */
#define GPIO_AF4_TIM8 ((uint8_t)0x04) /* TIM8 Alternate Function mapping */
#define GPIO_AF4_TIM16 ((uint8_t)0x04) /* TIM16 Alternate Function mapping */
#define GPIO_AF4_TIM17 ((uint8_t)0x04) /* TIM17 Alternate Function mapping */
#define GPIO_AF4_TIM8_COMP1 ((uint8_t)0x04) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#if defined(I2C4)
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#endif /* I2C4 */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#if defined(SPI4)
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#endif /* SPI4 */
#define GPIO_AF5_IR ((uint8_t)0x05) /* IR Alternate Function mapping */
#define GPIO_AF5_TIM8 ((uint8_t)0x05) /* TIM8 Alternate Function mapping */
#define GPIO_AF5_TIM8_COMP1 ((uint8_t)0x05) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF5_UART4 ((uint8_t)0x05) /* UART4 Alternate Function mapping */
#if defined(UART5)
#define GPIO_AF5_UART5 ((uint8_t)0x05) /* UART5 Alternate Function mapping */
#endif /* UART5 */
#define GPIO_AF5_I2S2ext ((uint8_t)0x05) /* I2S2ext_SD Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#define GPIO_AF6_TIM1 ((uint8_t)0x06) /* TIM1 Alternate Function mapping */
#if defined(TIM5)
#define GPIO_AF6_TIM5 ((uint8_t)0x06) /* TIM5 Alternate Function mapping */
#endif /* TIM5 */
#define GPIO_AF6_TIM8 ((uint8_t)0x06) /* TIM8 Alternate Function mapping */
#if defined(TIM20)
#define GPIO_AF6_TIM20 ((uint8_t)0x06) /* TIM20 Alternate Function mapping */
#endif /* TIM20 */
#define GPIO_AF6_TIM1_COMP1 ((uint8_t)0x06) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF6_TIM1_COMP2 ((uint8_t)0x06) /* TIM1/COMP2 Break in Alternate Function mapping */
#define GPIO_AF6_TIM8_COMP2 ((uint8_t)0x06) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF6_IR ((uint8_t)0x06) /* IR Alternate Function mapping */
#define GPIO_AF6_I2S3ext ((uint8_t)0x06) /* I2S3ext_SD Alternate Function mapping */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#if defined(COMP5)
#define GPIO_AF7_COMP5 ((uint8_t)0x07) /* COMP5 Alternate Function mapping */
#endif /* COMP5 */
#if defined(COMP6)
#define GPIO_AF7_COMP6 ((uint8_t)0x07) /* COMP6 Alternate Function mapping */
#endif /* COMP6 */
#if defined(COMP7)
#define GPIO_AF7_COMP7 ((uint8_t)0x07) /* COMP7 Alternate Function mapping */
#endif /* COMP7 */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_COMP1 ((uint8_t)0x08) /* COMP1 Alternate Function mapping */
#define GPIO_AF8_COMP2 ((uint8_t)0x08) /* COMP2 Alternate Function mapping */
#define GPIO_AF8_COMP3 ((uint8_t)0x08) /* COMP3 Alternate Function mapping */
#define GPIO_AF8_COMP4 ((uint8_t)0x08) /* COMP4 Alternate Function mapping */
#if defined(COMP5)
#define GPIO_AF8_COMP5 ((uint8_t)0x08) /* COMP5 Alternate Function mapping */
#endif /* COMP5 */
#if defined(COMP6)
#define GPIO_AF8_COMP6 ((uint8_t)0x08) /* COMP6 Alternate Function mapping */
#endif /* COMP6 */
#if defined(COMP7)
#define GPIO_AF8_COMP7 ((uint8_t)0x08) /* COMP7 Alternate Function mapping */
#endif /* COMP7 */
#define GPIO_AF8_I2C3 ((uint8_t)0x08) /* I2C3 Alternate Function mapping */
#if defined(I2C4)
#define GPIO_AF8_I2C4 ((uint8_t)0x08) /* I2C4 Alternate Function mapping */
#endif /* I2C4 */
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#if defined(UART5)
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#endif /* UART5 */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_TIM1 ((uint8_t)0x09) /* TIM1 Alternate Function mapping */
#define GPIO_AF9_TIM8 ((uint8_t)0x09) /* TIM8 Alternate Function mapping */
#define GPIO_AF9_TIM15 ((uint8_t)0x09) /* TIM15 Alternate Function mapping */
#define GPIO_AF9_TIM1_COMP1 ((uint8_t)0x09) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF9_TIM8_COMP1 ((uint8_t)0x09) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF9_TIM15_COMP1 ((uint8_t)0x09) /* TIM15/COMP1 Break in Alternate Function mapping */
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#if defined(FDCAN2)
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#endif /* FDCAN2 */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_TIM2 ((uint8_t)0x0A) /* TIM2 Alternate Function mapping */
#define GPIO_AF10_TIM3 ((uint8_t)0x0A) /* TIM3 Alternate Function mapping */
#define GPIO_AF10_TIM4 ((uint8_t)0x0A) /* TIM4 Alternate Function mapping */
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
#define GPIO_AF10_TIM17 ((uint8_t)0x0A) /* TIM17 Alternate Function mapping */
#define GPIO_AF10_TIM8_COMP2 ((uint8_t)0x0A) /* TIM8/COMP2 Break in Alternate Function mapping */
#define GPIO_AF10_TIM17_COMP1 ((uint8_t)0x0A) /* TIM17/COMP1 Break in Alternate Function mapping */
#if defined(QUADSPI)
#define GPIO_AF10_QUADSPI ((uint8_t)0x0A) /* OctoSPI Manager Port 1 Alternate Function mapping */
#endif /* QUADSPI */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_FDCAN1 ((uint8_t)0x0B) /* FDCAN1 Alternate Function mapping */
#if defined(FDCAN3)
#define GPIO_AF11_FDCAN3 ((uint8_t)0x0B) /* FDCAN3 Alternate Function mapping */
#endif /* FDCAN3 */
#define GPIO_AF11_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */
#define GPIO_AF11_TIM8 ((uint8_t)0x0B) /* TIM8 Alternate Function mapping */
#define GPIO_AF11_TIM8_COMP1 ((uint8_t)0x0B) /* TIM8/COMP1 Break in Alternate Function mapping */
#define GPIO_AF11_LPTIM1 ((uint8_t)0x0B) /* LPTIM1 Alternate Function mapping */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_LPUART1 ((uint8_t)0x0C) /* LPUART1 Alternate Function mapping */
#define GPIO_AF12_TIM1 ((uint8_t)0x0C) /* TIM1 Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */
#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */
#if defined(HRTIM1)
#define GPIO_AF12_HRTIM1 ((uint8_t)0x0C) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#if defined(FMC_BANK1)
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#endif /* FMC_BANK1 */
#define GPIO_AF12_SAI1 ((uint8_t)0x0C) /* SAI1 Alternate Function mapping */
/**
* @brief AF 13 selection
*/
#if defined(HRTIM1)
#define GPIO_AF13_HRTIM1 ((uint8_t)0x0D) /* HRTIM1 Alternate Function mapping */
#endif /* HRTIM1 */
#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */
#define GPIO_AF14_UCPD1 ((uint8_t)0x0E) /* UCPD1 Alternate Function mapping */
#define GPIO_AF14_SAI1 ((uint8_t)0x0E) /* SAI1 Alternate Function mapping */
#define GPIO_AF14_UART4 ((uint8_t)0x0E) /* UART4 Alternate Function mapping */
#if defined(UART5)
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#endif /* UART5 */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
* @{
*/
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
* @{
*/
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0UL :\
((__GPIOx__) == (GPIOB))? 1UL :\
((__GPIOx__) == (GPIOC))? 2UL :\
((__GPIOx__) == (GPIOD))? 3UL :\
((__GPIOx__) == (GPIOE))? 4UL :\
((__GPIOx__) == (GPIOF))? 5UL : 6UL)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_GPIO_EX_H */
| 15,425 | C | 44.237537 | 111 | 0.599676 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_bus.h | /**
******************************************************************************
* @file stm32g4xx_ll_bus.h
* @author MCD Application Team
* @brief Header file of BUS LL module.
@verbatim
##### RCC Limitations #####
==============================================================================
[..]
A delay between an RCC peripheral clock enable and the effective peripheral
enabling should be taken into account in order to manage the peripheral read/write
from/to registers.
(+) This delay depends on the peripheral mapping.
(++) AHB & APB peripherals, 1 dummy read is necessary
[..]
Workarounds:
(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_BUS_H
#define STM32G4xx_LL_BUS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(RCC)
/** @defgroup BUS_LL BUS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
* @{
*/
/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
* @{
*/
#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN
#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN
#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
/**
* @}
*/
/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
* @{
*/
#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
#define LL_AHB2_GRP1_PERIPH_CCM RCC_AHB2SMENR_CCMSMEN
#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR_ADC12EN
#if defined(ADC345_COMMON)
#define LL_AHB2_GRP1_PERIPH_ADC345 RCC_AHB2ENR_ADC345EN
#endif /* ADC345_COMMON */
#define LL_AHB2_GRP1_PERIPH_DAC1 RCC_AHB2ENR_DAC1EN
#if defined(DAC2)
#define LL_AHB2_GRP1_PERIPH_DAC2 RCC_AHB2ENR_DAC2EN
#endif /* DAC2 */
#define LL_AHB2_GRP1_PERIPH_DAC3 RCC_AHB2ENR_DAC3EN
#if defined(DAC4)
#define LL_AHB2_GRP1_PERIPH_DAC4 RCC_AHB2ENR_DAC4EN
#endif /* DAC4 */
#if defined(AES)
#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
#endif /* AES */
#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
/**
* @}
*/
/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
* @{
*/
#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
#if defined(FMC_Bank1_R)
#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
#endif /* FMC_Bank1_R */
#if defined(QUADSPI)
#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
* @{
*/
#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
#if defined(TIM5)
#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
#endif /* TIM5 */
#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
#if defined(UART4)
#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
#endif /* UART4 */
#if defined(UART5)
#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
#endif /* UART5 */
#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBEN
#if defined(FDCAN1)
#define LL_APB1_GRP1_PERIPH_FDCAN RCC_APB1ENR1_FDCANEN
#endif /* FDCAN1 */
#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
/**
* @}
*/
/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
* @{
*/
#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
#if defined(I2C4)
#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
#endif /* I2C4 */
#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN
/**
* @}
*/
/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
* @{
*/
#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
#if defined(SPI4)
#define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
#endif /* SPI4 */
#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
#if defined(TIM20)
#define LL_APB2_GRP1_PERIPH_TIM20 RCC_APB2ENR_TIM20EN
#endif /* TIM20 */
#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
#if defined(HRTIM1)
#define LL_APB2_GRP1_PERIPH_HRTIM1 RCC_APB2ENR_HRTIM1EN
#endif /* HRTIM1 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
* @{
*/
/** @defgroup BUS_LL_EF_AHB1 AHB1
* @{
*/
/**
* @brief Enable AHB1 peripherals clock.
* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR DMAMMUXEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB1ENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB1 peripheral clock is enabled or not
* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR DMAMUXEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB1 peripherals clock.
* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR DMAMUXEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1ENR, Periphs);
}
/**
* @brief Force AHB1 peripherals reset.
* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR CORDICRST LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR FMACRST LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
* AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB1RSTR, Periphs);
}
/**
* @brief Release AHB1 peripherals reset.
* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR DMAMUXRST LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR CORDICRST LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR FMACRST LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
* AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1RSTR, Periphs);
}
/**
* @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB1SMENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
(void)tmpreg;
}
/**
* @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR DMAMUXSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
* AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1
* @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC
* @arg @ref LL_AHB1_GRP1_PERIPH_FMAC
* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
* @retval None
*/
__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB1SMENR, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_AHB2 AHB2
* @{
*/
/**
* @brief Enable AHB2 peripherals clock.
* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR ADC12EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR ADC345EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR DAC1EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR DAC2EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR DAC3EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR DAC4EN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB2ENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB2 peripheral clock is enabled or not
* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR ADC12EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR ADC345EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR DAC1EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR DAC2EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR DAC3EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR DAC4EN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB2 peripherals clock.
* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR ADC12EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR ADC345EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR DAC1EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR DAC2EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR DAC3EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR DAC4EN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2ENR, Periphs);
}
/**
* @brief Force AHB2 peripherals reset.
* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR ADC12RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR ADC345RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR DAC1RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR DAC2RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR DAC3RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR DAC4RST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB2RSTR, Periphs);
}
/**
* @brief Release AHB2 peripherals reset.
* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR ADC12RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR ADC345RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR DAC1RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR DAC2RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR DAC3RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR DAC4RST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2RSTR, Periphs);
}
/**
* @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR CCMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR ADC345SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR DAC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR DAC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR DAC3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR DAC4SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
* AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_CCM
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB2SMENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
(void)tmpreg;
}
/**
* @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR CCMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR ADC345SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR DAC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR DAC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR DAC3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR DAC4SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
* AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF
* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG
* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
* @arg @ref LL_AHB2_GRP1_PERIPH_CCM
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC12
* @arg @ref LL_AHB2_GRP1_PERIPH_ADC345 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC1
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC2 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC3
* @arg @ref LL_AHB2_GRP1_PERIPH_DAC4 (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB2SMENR, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_AHB3 AHB3
* @{
*/
/**
* @brief Enable AHB3 peripherals clock.
* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB3ENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if AHB3 peripheral clock is enabled or not
* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable AHB3 peripherals clock.
* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3ENR, Periphs);
}
/**
* @brief Force AHB3 peripherals reset.
* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->AHB3RSTR, Periphs);
}
/**
* @brief Release AHB3 peripherals reset.
* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3RSTR, Periphs);
}
/**
* @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
* AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->AHB3SMENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
(void)tmpreg;
}
/**
* @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
* AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->AHB3SMENR, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_APB1 APB1
* @{
*/
/**
* @brief Enable APB1 peripherals clock.
* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 USBEN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 FDCANEN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
* APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_USB
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1ENR1, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
(void)tmpreg;
}
/**
* @brief Enable APB1 peripherals clock.
* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
* APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
* APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1ENR2, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB1 peripheral clock is enabled or not
* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 USBEN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 FDCANEN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
* APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_USB
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Check if APB1 peripheral clock is enabled or not
* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
* APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
* APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB1 peripherals clock.
* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 USBEN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 FDCANEN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
* APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_USB
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1ENR1, Periphs);
}
/**
* @brief Disable APB1 peripherals clock.
* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
* APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
* APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1ENR2, Periphs);
}
/**
* @brief Force APB1 peripherals reset.
* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 USBRST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 FDCANRST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_USB
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB1RSTR1, Periphs);
}
/**
* @brief Force APB1 peripherals reset.
* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
* APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
* APB1RSTR2 UCPD1RST LL_APB1_GRP2_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB1RSTR2, Periphs);
}
/**
* @brief Release APB1 peripherals reset.
* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 USBRST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 FDCANRST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_USB
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1RSTR1, Periphs);
}
/**
* @brief Release APB1 peripherals reset.
* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
* APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
* APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1RSTR2, Periphs);
}
/**
* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 USBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 FDCANSMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_USB
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1SMENR1, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
(void)tmpreg;
}
/**
* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
* APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
* APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB1SMENR2, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
(void)tmpreg;
}
/**
* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 USBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 FDCANSMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
* @arg @ref LL_APB1_GRP1_PERIPH_TIM4
* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
* @arg @ref LL_APB1_GRP1_PERIPH_CRS
* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB
* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
* @arg @ref LL_APB1_GRP1_PERIPH_USART2
* @arg @ref LL_APB1_GRP1_PERIPH_USART3
* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
* @arg @ref LL_APB1_GRP1_PERIPH_I2C2
* @arg @ref LL_APB1_GRP1_PERIPH_USB
* @arg @ref LL_APB1_GRP1_PERIPH_FDCAN (*)
* @arg @ref LL_APB1_GRP1_PERIPH_PWR
* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1SMENR1, Periphs);
}
/**
* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
* APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
* APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
* @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB1SMENR2, Periphs);
}
/**
* @}
*/
/** @defgroup BUS_LL_EF_APB2 APB2
* @{
*/
/**
* @brief Enable APB2 peripherals clock.
* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
* APB2ENR TIM20EN LL_APB2_GRP1_EnableClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
* APB2ENR HRTIM1EN LL_APB2_GRP1_EnableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB2ENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
(void)tmpreg;
}
/**
* @brief Check if APB2 peripheral clock is enabled or not
* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR TIM20EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
* APB2ENR HRTIM1EN LL_APB2_GRP1_IsEnabledClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
*
* (*) value not defined in all devices.
* @retval State of Periphs (1 or 0).
*/
__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
{
return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL);
}
/**
* @brief Disable APB2 peripherals clock.
* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
* APB2ENR TIM20EN LL_APB2_GRP1_DisableClock\n
* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
* APB2ENR HRTIM1EN LL_APB2_GRP1_DisableClock
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2ENR, Periphs);
}
/**
* @brief Force APB2 peripherals reset.
* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
{
SET_BIT(RCC->APB2RSTR, Periphs);
}
/**
* @brief Release APB2 peripherals reset.
* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR TIM20RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
* APB2RSTR HRTIM1RST LL_APB2_GRP1_ForceReset
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2RSTR, Periphs);
}
/**
* @brief Enable APB2 peripheral clocks in Sleep and Stop modes
* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR SPI4SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR TIM20SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
* APB2SMENR HRTIM1SMEN LL_APB2_GRP1_EnableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
{
__IO uint32_t tmpreg;
SET_BIT(RCC->APB2SMENR, Periphs);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
(void)tmpreg;
}
/**
* @brief Disable APB2 peripheral clocks in Sleep and Stop modes
* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR SPI4SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR TIM20SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
* APB2SMENR HRTIM1SMEN LL_APB2_GRP1_DisableClockStopSleep
* @param Periphs This parameter can be a combination of the following values:
* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
* @arg @ref LL_APB2_GRP1_PERIPH_TIM8
* @arg @ref LL_APB2_GRP1_PERIPH_USART1
* @arg @ref LL_APB2_GRP1_PERIPH_SPI4 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
* @arg @ref LL_APB2_GRP1_PERIPH_TIM17
* @arg @ref LL_APB2_GRP1_PERIPH_TIM20 (*)
* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
* @arg @ref LL_APB2_GRP1_PERIPH_HRTIM1 (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
{
CLEAR_BIT(RCC->APB2SMENR, Periphs);
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RCC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_BUS_H */
| 74,749 | C | 43.467579 | 88 | 0.594309 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_cordic.h | /**
******************************************************************************
* @file stm32g4xx_ll_cordic.h
* @author MCD Application Team
* @brief Header file of CORDIC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_CORDIC_H
#define STM32G4xx_LL_CORDIC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(CORDIC)
/** @defgroup CORDIC_LL CORDIC
* @{
*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORDIC_LL_Exported_Constants CORDIC Exported Constants
* @{
*/
/** @defgroup CORDIC_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CORDIC_ReadReg function.
* @{
*/
#define LL_CORDIC_FLAG_RRDY CORDIC_CSR_RRDY
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CORDIC_ReadReg and LL_CORDIC_WriteReg functions.
* @{
*/
#define LL_CORDIC_IT_IEN CORDIC_CSR_IEN /*!< Result Ready interrupt enable */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_FUNCTION FUNCTION
* @{
*/
#define LL_CORDIC_FUNCTION_COSINE (0x00000000U) /*!< Cosine */
#define LL_CORDIC_FUNCTION_SINE ((uint32_t)(CORDIC_CSR_FUNC_0)) /*!< Sine */
#define LL_CORDIC_FUNCTION_PHASE ((uint32_t)(CORDIC_CSR_FUNC_1)) /*!< Phase */
#define LL_CORDIC_FUNCTION_MODULUS ((uint32_t)(CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0)) /*!< Modulus */
#define LL_CORDIC_FUNCTION_ARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2)) /*!< Arctangent */
#define LL_CORDIC_FUNCTION_HCOSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_0)) /*!< Hyperbolic Cosine */
#define LL_CORDIC_FUNCTION_HSINE ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1)) /*!< Hyperbolic Sine */
#define LL_CORDIC_FUNCTION_HARCTANGENT ((uint32_t)(CORDIC_CSR_FUNC_2 | CORDIC_CSR_FUNC_1 | CORDIC_CSR_FUNC_0))/*!< Hyperbolic Arctangent */
#define LL_CORDIC_FUNCTION_NATURALLOG ((uint32_t)(CORDIC_CSR_FUNC_3)) /*!< Natural Logarithm */
#define LL_CORDIC_FUNCTION_SQUAREROOT ((uint32_t)(CORDIC_CSR_FUNC_3 | CORDIC_CSR_FUNC_0)) /*!< Square Root */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_PRECISION PRECISION
* @{
*/
#define LL_CORDIC_PRECISION_1CYCLE ((uint32_t)(CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_2CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1))
#define LL_CORDIC_PRECISION_3CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_4CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2))
#define LL_CORDIC_PRECISION_5CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_6CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define LL_CORDIC_PRECISION_7CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_2\
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_8CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3))
#define LL_CORDIC_PRECISION_9CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_10CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_1))
#define LL_CORDIC_PRECISION_11CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_1 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_12CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3 | CORDIC_CSR_PRECISION_2))
#define LL_CORDIC_PRECISION_13CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_0))
#define LL_CORDIC_PRECISION_14CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1))
#define LL_CORDIC_PRECISION_15CYCLES ((uint32_t)(CORDIC_CSR_PRECISION_3\
| CORDIC_CSR_PRECISION_2 | CORDIC_CSR_PRECISION_1\
| CORDIC_CSR_PRECISION_0))
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_SCALE SCALE
* @{
*/
#define LL_CORDIC_SCALE_0 (0x00000000U)
#define LL_CORDIC_SCALE_1 ((uint32_t)(CORDIC_CSR_SCALE_0))
#define LL_CORDIC_SCALE_2 ((uint32_t)(CORDIC_CSR_SCALE_1))
#define LL_CORDIC_SCALE_3 ((uint32_t)(CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
#define LL_CORDIC_SCALE_4 ((uint32_t)(CORDIC_CSR_SCALE_2))
#define LL_CORDIC_SCALE_5 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_0))
#define LL_CORDIC_SCALE_6 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1))
#define LL_CORDIC_SCALE_7 ((uint32_t)(CORDIC_CSR_SCALE_2 | CORDIC_CSR_SCALE_1 | CORDIC_CSR_SCALE_0))
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_NBWRITE NBWRITE
* @{
*/
#define LL_CORDIC_NBWRITE_1 (0x00000000U) /*!< One 32-bits write containing either only one
32-bit data input (Q1.31 format), or two
16-bit data input (Q1.15 format) packed
in one 32 bits Data */
#define LL_CORDIC_NBWRITE_2 CORDIC_CSR_NARGS /*!< Two 32-bit write containing two 32-bits data input
(Q1.31 format) */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_NBREAD NBREAD
* @{
*/
#define LL_CORDIC_NBREAD_1 (0x00000000U) /*!< One 32-bits read containing either only one
32-bit data output (Q1.31 format), or two
16-bit data output (Q1.15 format) packed
in one 32 bits Data */
#define LL_CORDIC_NBREAD_2 CORDIC_CSR_NRES /*!< Two 32-bit Data containing two 32-bits data output
(Q1.31 format) */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_INSIZE INSIZE
* @{
*/
#define LL_CORDIC_INSIZE_32BITS (0x00000000U) /*!< 32 bits input data size (Q1.31 format) */
#define LL_CORDIC_INSIZE_16BITS CORDIC_CSR_ARGSIZE /*!< 16 bits input data size (Q1.15 format) */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_OUTSIZE OUTSIZE
* @{
*/
#define LL_CORDIC_OUTSIZE_32BITS (0x00000000U) /*!< 32 bits output data size (Q1.31 format) */
#define LL_CORDIC_OUTSIZE_16BITS CORDIC_CSR_RESSIZE /*!< 16 bits output data size (Q1.15 format) */
/**
* @}
*/
/** @defgroup CORDIC_LL_EC_DMA_REG_DATA DMA register data
* @{
*/
#define LL_CORDIC_DMA_REG_DATA_IN (0x00000000U) /*!< Get address of input data register */
#define LL_CORDIC_DMA_REG_DATA_OUT (0x00000001U) /*!< Get address of output data register */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CORDIC_LL_Exported_Macros CORDIC Exported Macros
* @{
*/
/** @defgroup CORDIC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CORDIC register.
* @param __INSTANCE__ CORDIC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CORDIC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CORDIC register.
* @param __INSTANCE__ CORDIC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CORDIC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORDIC_LL_Exported_Functions CORDIC Exported Functions
* @{
*/
/** @defgroup CORDIC_LL_EF_Configuration CORDIC Configuration functions
* @{
*/
/**
* @brief Configure the CORDIC processing.
* @note This function set all parameters of CORDIC processing.
* These parameters can also be set individually using
* dedicated functions:
* - @ref LL_CORDIC_SetFunction()
* - @ref LL_CORDIC_SetPrecision()
* - @ref LL_CORDIC_SetScale()
* - @ref LL_CORDIC_SetNbWrite()
* - @ref LL_CORDIC_SetNbRead()
* - @ref LL_CORDIC_SetInSize()
* - @ref LL_CORDIC_SetOutSize()
* @rmtoll CSR FUNC LL_CORDIC_Configure\n
* CSR PRECISION LL_CORDIC_Configure\n
* CSR SCALE LL_CORDIC_Configure\n
* CSR NARGS LL_CORDIC_Configure\n
* CSR NRES LL_CORDIC_Configure\n
* CSR ARGSIZE LL_CORDIC_Configure\n
* CSR RESIZE LL_CORDIC_Configure
* @param CORDICx CORDIC instance
* @param Function parameter can be one of the following values:
* @arg @ref LL_CORDIC_FUNCTION_COSINE
* @arg @ref LL_CORDIC_FUNCTION_SINE
* @arg @ref LL_CORDIC_FUNCTION_PHASE
* @arg @ref LL_CORDIC_FUNCTION_MODULUS
* @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_HCOSINE
* @arg @ref LL_CORDIC_FUNCTION_HSINE
* @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
* @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
* @param Precision parameter can be one of the following values:
* @arg @ref LL_CORDIC_PRECISION_1CYCLE
* @arg @ref LL_CORDIC_PRECISION_2CYCLES
* @arg @ref LL_CORDIC_PRECISION_3CYCLES
* @arg @ref LL_CORDIC_PRECISION_4CYCLES
* @arg @ref LL_CORDIC_PRECISION_5CYCLES
* @arg @ref LL_CORDIC_PRECISION_6CYCLES
* @arg @ref LL_CORDIC_PRECISION_7CYCLES
* @arg @ref LL_CORDIC_PRECISION_8CYCLES
* @arg @ref LL_CORDIC_PRECISION_9CYCLES
* @arg @ref LL_CORDIC_PRECISION_10CYCLES
* @arg @ref LL_CORDIC_PRECISION_11CYCLES
* @arg @ref LL_CORDIC_PRECISION_12CYCLES
* @arg @ref LL_CORDIC_PRECISION_13CYCLES
* @arg @ref LL_CORDIC_PRECISION_14CYCLES
* @arg @ref LL_CORDIC_PRECISION_15CYCLES
* @param Scale parameter can be one of the following values:
* @arg @ref LL_CORDIC_SCALE_0
* @arg @ref LL_CORDIC_SCALE_1
* @arg @ref LL_CORDIC_SCALE_2
* @arg @ref LL_CORDIC_SCALE_3
* @arg @ref LL_CORDIC_SCALE_4
* @arg @ref LL_CORDIC_SCALE_5
* @arg @ref LL_CORDIC_SCALE_6
* @arg @ref LL_CORDIC_SCALE_7
* @param NbWrite parameter can be one of the following values:
* @arg @ref LL_CORDIC_NBWRITE_1
* @arg @ref LL_CORDIC_NBWRITE_2
* @param NbRead parameter can be one of the following values:
* @arg @ref LL_CORDIC_NBREAD_1
* @arg @ref LL_CORDIC_NBREAD_2
* @param InSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_INSIZE_32BITS
* @arg @ref LL_CORDIC_INSIZE_16BITS
* @param OutSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_OUTSIZE_32BITS
* @arg @ref LL_CORDIC_OUTSIZE_16BITS
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_Config(CORDIC_TypeDef *CORDICx, uint32_t Function, uint32_t Precision, uint32_t Scale,
uint32_t NbWrite, uint32_t NbRead, uint32_t InSize, uint32_t OutSize)
{
MODIFY_REG(CORDICx->CSR,
CORDIC_CSR_FUNC | CORDIC_CSR_PRECISION | CORDIC_CSR_SCALE |
CORDIC_CSR_NARGS | CORDIC_CSR_NRES | CORDIC_CSR_ARGSIZE | CORDIC_CSR_RESSIZE,
Function | Precision | Scale |
NbWrite | NbRead | InSize | OutSize);
}
/**
* @brief Configure function.
* @rmtoll CSR FUNC LL_CORDIC_SetFunction
* @param CORDICx CORDIC Instance
* @param Function parameter can be one of the following values:
* @arg @ref LL_CORDIC_FUNCTION_COSINE
* @arg @ref LL_CORDIC_FUNCTION_SINE
* @arg @ref LL_CORDIC_FUNCTION_PHASE
* @arg @ref LL_CORDIC_FUNCTION_MODULUS
* @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_HCOSINE
* @arg @ref LL_CORDIC_FUNCTION_HSINE
* @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
* @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetFunction(CORDIC_TypeDef *CORDICx, uint32_t Function)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_FUNC, Function);
}
/**
* @brief Return function.
* @rmtoll CSR FUNC LL_CORDIC_GetFunction
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_FUNCTION_COSINE
* @arg @ref LL_CORDIC_FUNCTION_SINE
* @arg @ref LL_CORDIC_FUNCTION_PHASE
* @arg @ref LL_CORDIC_FUNCTION_MODULUS
* @arg @ref LL_CORDIC_FUNCTION_ARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_HCOSINE
* @arg @ref LL_CORDIC_FUNCTION_HSINE
* @arg @ref LL_CORDIC_FUNCTION_HARCTANGENT
* @arg @ref LL_CORDIC_FUNCTION_NATURALLOG
* @arg @ref LL_CORDIC_FUNCTION_SQUAREROOT
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetFunction(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_FUNC));
}
/**
* @brief Configure precision in cycles number.
* @rmtoll CSR PRECISION LL_CORDIC_SetPrecision
* @param CORDICx CORDIC Instance
* @param Precision parameter can be one of the following values:
* @arg @ref LL_CORDIC_PRECISION_1CYCLE
* @arg @ref LL_CORDIC_PRECISION_2CYCLES
* @arg @ref LL_CORDIC_PRECISION_3CYCLES
* @arg @ref LL_CORDIC_PRECISION_4CYCLES
* @arg @ref LL_CORDIC_PRECISION_5CYCLES
* @arg @ref LL_CORDIC_PRECISION_6CYCLES
* @arg @ref LL_CORDIC_PRECISION_7CYCLES
* @arg @ref LL_CORDIC_PRECISION_8CYCLES
* @arg @ref LL_CORDIC_PRECISION_9CYCLES
* @arg @ref LL_CORDIC_PRECISION_10CYCLES
* @arg @ref LL_CORDIC_PRECISION_11CYCLES
* @arg @ref LL_CORDIC_PRECISION_12CYCLES
* @arg @ref LL_CORDIC_PRECISION_13CYCLES
* @arg @ref LL_CORDIC_PRECISION_14CYCLES
* @arg @ref LL_CORDIC_PRECISION_15CYCLES
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetPrecision(CORDIC_TypeDef *CORDICx, uint32_t Precision)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_PRECISION, Precision);
}
/**
* @brief Return precision in cycles number.
* @rmtoll CSR PRECISION LL_CORDIC_GetPrecision
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_PRECISION_1CYCLE
* @arg @ref LL_CORDIC_PRECISION_2CYCLES
* @arg @ref LL_CORDIC_PRECISION_3CYCLES
* @arg @ref LL_CORDIC_PRECISION_4CYCLES
* @arg @ref LL_CORDIC_PRECISION_5CYCLES
* @arg @ref LL_CORDIC_PRECISION_6CYCLES
* @arg @ref LL_CORDIC_PRECISION_7CYCLES
* @arg @ref LL_CORDIC_PRECISION_8CYCLES
* @arg @ref LL_CORDIC_PRECISION_9CYCLES
* @arg @ref LL_CORDIC_PRECISION_10CYCLES
* @arg @ref LL_CORDIC_PRECISION_11CYCLES
* @arg @ref LL_CORDIC_PRECISION_12CYCLES
* @arg @ref LL_CORDIC_PRECISION_13CYCLES
* @arg @ref LL_CORDIC_PRECISION_14CYCLES
* @arg @ref LL_CORDIC_PRECISION_15CYCLES
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetPrecision(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_PRECISION));
}
/**
* @brief Configure scaling factor.
* @rmtoll CSR SCALE LL_CORDIC_SetScale
* @param CORDICx CORDIC Instance
* @param Scale parameter can be one of the following values:
* @arg @ref LL_CORDIC_SCALE_0
* @arg @ref LL_CORDIC_SCALE_1
* @arg @ref LL_CORDIC_SCALE_2
* @arg @ref LL_CORDIC_SCALE_3
* @arg @ref LL_CORDIC_SCALE_4
* @arg @ref LL_CORDIC_SCALE_5
* @arg @ref LL_CORDIC_SCALE_6
* @arg @ref LL_CORDIC_SCALE_7
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetScale(CORDIC_TypeDef *CORDICx, uint32_t Scale)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_SCALE, Scale);
}
/**
* @brief Return scaling factor.
* @rmtoll CSR SCALE LL_CORDIC_GetScale
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_SCALE_0
* @arg @ref LL_CORDIC_SCALE_1
* @arg @ref LL_CORDIC_SCALE_2
* @arg @ref LL_CORDIC_SCALE_3
* @arg @ref LL_CORDIC_SCALE_4
* @arg @ref LL_CORDIC_SCALE_5
* @arg @ref LL_CORDIC_SCALE_6
* @arg @ref LL_CORDIC_SCALE_7
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetScale(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_SCALE));
}
/**
* @brief Configure number of 32-bit write expected for one calculation.
* @rmtoll CSR NARGS LL_CORDIC_SetNbWrite
* @param CORDICx CORDIC Instance
* @param NbWrite parameter can be one of the following values:
* @arg @ref LL_CORDIC_NBWRITE_1
* @arg @ref LL_CORDIC_NBWRITE_2
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetNbWrite(CORDIC_TypeDef *CORDICx, uint32_t NbWrite)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NARGS, NbWrite);
}
/**
* @brief Return number of 32-bit write expected for one calculation.
* @rmtoll CSR NARGS LL_CORDIC_GetNbWrite
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_NBWRITE_1
* @arg @ref LL_CORDIC_NBWRITE_2
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetNbWrite(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NARGS));
}
/**
* @brief Configure number of 32-bit read expected after one calculation.
* @rmtoll CSR NRES LL_CORDIC_SetNbRead
* @param CORDICx CORDIC Instance
* @param NbRead parameter can be one of the following values:
* @arg @ref LL_CORDIC_NBREAD_1
* @arg @ref LL_CORDIC_NBREAD_2
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetNbRead(CORDIC_TypeDef *CORDICx, uint32_t NbRead)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_NRES, NbRead);
}
/**
* @brief Return number of 32-bit read expected after one calculation.
* @rmtoll CSR NRES LL_CORDIC_GetNbRead
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_NBREAD_1
* @arg @ref LL_CORDIC_NBREAD_2
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetNbRead(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_NRES));
}
/**
* @brief Configure width of input data.
* @rmtoll CSR ARGSIZE LL_CORDIC_SetInSize
* @param CORDICx CORDIC Instance
* @param InSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_INSIZE_32BITS
* @arg @ref LL_CORDIC_INSIZE_16BITS
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetInSize(CORDIC_TypeDef *CORDICx, uint32_t InSize)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_ARGSIZE, InSize);
}
/**
* @brief Return width of input data.
* @rmtoll CSR ARGSIZE LL_CORDIC_GetInSize
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_INSIZE_32BITS
* @arg @ref LL_CORDIC_INSIZE_16BITS
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetInSize(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_ARGSIZE));
}
/**
* @brief Configure width of output data.
* @rmtoll CSR RESIZE LL_CORDIC_SetOutSize
* @param CORDICx CORDIC Instance
* @param OutSize parameter can be one of the following values:
* @arg @ref LL_CORDIC_OUTSIZE_32BITS
* @arg @ref LL_CORDIC_OUTSIZE_16BITS
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_SetOutSize(CORDIC_TypeDef *CORDICx, uint32_t OutSize)
{
MODIFY_REG(CORDICx->CSR, CORDIC_CSR_RESSIZE, OutSize);
}
/**
* @brief Return width of output data.
* @rmtoll CSR RESIZE LL_CORDIC_GetOutSize
* @param CORDICx CORDIC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_CORDIC_OUTSIZE_32BITS
* @arg @ref LL_CORDIC_OUTSIZE_16BITS
*/
__STATIC_INLINE uint32_t LL_CORDIC_GetOutSize(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_BIT(CORDICx->CSR, CORDIC_CSR_RESSIZE));
}
/**
* @}
*/
/** @defgroup CORDIC_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable CORDIC result ready interrupt
* @rmtoll CSR IEN LL_CORDIC_EnableIT
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_EnableIT(CORDIC_TypeDef *CORDICx)
{
SET_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
}
/**
* @brief Disable CORDIC result ready interrupt
* @rmtoll CSR IEN LL_CORDIC_DisableIT
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_DisableIT(CORDIC_TypeDef *CORDICx)
{
CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_IEN);
}
/**
* @brief Check CORDIC result ready interrupt state.
* @rmtoll CSR IEN LL_CORDIC_IsEnabledIT
* @param CORDICx CORDIC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledIT(CORDIC_TypeDef *CORDICx)
{
return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_IEN) == (CORDIC_CSR_IEN)) ? 1U : 0U);
}
/**
* @}
*/
/** @defgroup CORDIC_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable CORDIC DMA read channel request.
* @rmtoll CSR DMAREN LL_CORDIC_EnableDMAReq_RD
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_EnableDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
}
/**
* @brief Disable CORDIC DMA read channel request.
* @rmtoll CSR DMAREN LL_CORDIC_DisableDMAReq_RD
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_DisableDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN);
}
/**
* @brief Check CORDIC DMA read channel request state.
* @rmtoll CSR DMAREN LL_CORDIC_IsEnabledDMAReq_RD
* @param CORDICx CORDIC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_RD(CORDIC_TypeDef *CORDICx)
{
return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAREN) == (CORDIC_CSR_DMAREN)) ? 1U : 0U);
}
/**
* @brief Enable CORDIC DMA write channel request.
* @rmtoll CSR DMAWEN LL_CORDIC_EnableDMAReq_WR
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_EnableDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
SET_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
}
/**
* @brief Disable CORDIC DMA write channel request.
* @rmtoll CSR DMAWEN LL_CORDIC_DisableDMAReq_WR
* @param CORDICx CORDIC Instance
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_DisableDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
CLEAR_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN);
}
/**
* @brief Check CORDIC DMA write channel request state.
* @rmtoll CSR DMAWEN LL_CORDIC_IsEnabledDMAReq_WR
* @param CORDICx CORDIC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CORDIC_IsEnabledDMAReq_WR(CORDIC_TypeDef *CORDICx)
{
return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_DMAWEN) == (CORDIC_CSR_DMAWEN)) ? 1U : 0U);
}
/**
* @brief Get the CORDIC data register address used for DMA transfer.
* @rmtoll RDATA RES LL_CORDIC_DMA_GetRegAddr\n
* @rmtoll WDATA ARG LL_CORDIC_DMA_GetRegAddr
* @param CORDICx CORDIC Instance
* @param Direction parameter can be one of the following values:
* @arg @ref LL_CORDIC_DMA_REG_DATA_IN
* @arg @ref LL_CORDIC_DMA_REG_DATA_OUT
* @retval Address of data register
*/
__STATIC_INLINE uint32_t LL_CORDIC_DMA_GetRegAddr(CORDIC_TypeDef *CORDICx, uint32_t Direction)
{
uint32_t data_reg_addr;
if (Direction == LL_CORDIC_DMA_REG_DATA_OUT)
{
/* return address of RDATA register */
data_reg_addr = (uint32_t) &(CORDICx->RDATA);
}
else
{
/* return address of WDATA register */
data_reg_addr = (uint32_t) &(CORDICx->WDATA);
}
return data_reg_addr;
}
/**
* @}
*/
/** @defgroup CORDIC_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check CORDIC result ready flag state.
* @rmtoll CSR RRDY LL_CORDIC_IsActiveFlag_RRDY
* @param CORDICx CORDIC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CORDIC_IsActiveFlag_RRDY(CORDIC_TypeDef *CORDICx)
{
return ((READ_BIT(CORDICx->CSR, CORDIC_CSR_RRDY) == (CORDIC_CSR_RRDY)) ? 1U : 0U);
}
/**
* @}
*/
/** @defgroup CORDIC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write 32-bit input data for the CORDIC processing.
* @rmtoll WDATA ARG LL_CORDIC_WriteData
* @param CORDICx CORDIC Instance
* @param InData 0 .. 0xFFFFFFFF : 32-bit value to be provided as input data for CORDIC processing.
* @retval None
*/
__STATIC_INLINE void LL_CORDIC_WriteData(CORDIC_TypeDef *CORDICx, uint32_t InData)
{
WRITE_REG(CORDICx->WDATA, InData);
}
/**
* @brief Return 32-bit output data of CORDIC processing.
* @rmtoll RDATA RES LL_CORDIC_ReadData
* @param CORDICx CORDIC Instance
* @retval 32-bit output data of CORDIC processing.
*/
__STATIC_INLINE uint32_t LL_CORDIC_ReadData(CORDIC_TypeDef *CORDICx)
{
return (uint32_t)(READ_REG(CORDICx->RDATA));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CORDIC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CORDIC_DeInit(CORDIC_TypeDef *CORDICx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CORDIC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_CORDIC_H */
| 28,287 | C | 35.081633 | 143 | 0.583554 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmac.h | /**
******************************************************************************
* @file stm32g4xx_ll_fmac.h
* @author MCD Application Team
* @brief Header file of FMAC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_FMAC_H
#define STM32G4xx_LL_FMAC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(FMAC)
/** @defgroup FMAC_LL FMAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Constants FMAC Exported Constants
* @{
*/
/** @defgroup FMAC_LL_EC_GET_FLAG Get Flag Defines
* @brief Flag defines which can be used with LL_FMAC_ReadReg function
* @{
*/
#define LL_FMAC_SR_SAT FMAC_SR_SAT /*!< Saturation Error Flag (this helps in debugging a filter) */
#define LL_FMAC_SR_UNFL FMAC_SR_UNFL /*!< Underflow Error Flag */
#define LL_FMAC_SR_OVFL FMAC_SR_OVFL /*!< Overflow Error Flag */
#define LL_FMAC_SR_X1FULL FMAC_SR_X1FULL /*!< X1 Buffer Full Flag */
#define LL_FMAC_SR_YEMPTY FMAC_SR_YEMPTY /*!< Y Buffer Empty Flag */
/**
* @}
*/
/** @defgroup FMAC_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_FMAC_ReadReg and LL_FMAC_WriteReg functions
* @{
*/
#define LL_FMAC_CR_SATIEN FMAC_CR_SATIEN /*!< Saturation Error Interrupt Enable (this helps in debugging a filter) */
#define LL_FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN /*!< Underflow Error Interrupt Enable */
#define LL_FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN /*!< Overflow Error Interrupt Enable */
#define LL_FMAC_CR_WIEN FMAC_CR_WIEN /*!< Write Interrupt Enable */
#define LL_FMAC_CR_RIEN FMAC_CR_RIEN /*!< Read Interrupt Enable */
/**
* @}
*/
/** @defgroup FMAC_LL_EC_WM FMAC watermarks
* @brief Watermark defines that can be used for buffer full (input) or buffer empty (output)
* @{
*/
#define LL_FMAC_WM_0_THRESHOLD_1 0x00000000U /*!< Buffer full/empty flag set if there is less than 1 free/unread space. */
#define LL_FMAC_WM_1_THRESHOLD_2 0x01000000U /*!< Buffer full/empty flag set if there are less than 2 free/unread spaces. */
#define LL_FMAC_WM_2_THRESHOLD_4 0x02000000U /*!< Buffer full/empty flag set if there are less than 4 free/unread spaces. */
#define LL_FMAC_WM_3_THRESHOLD_8 0x03000000U /*!< Buffer full/empty flag set if there are less than 8 free/empty spaces. */
/**
* @}
*/
/** @defgroup FMAC_LL_EC_FUNC FMAC functions
* @{
*/
#define LL_FMAC_FUNC_LOAD_X1 (FMAC_PARAM_FUNC_0) /*!< Load X1 buffer */
#define LL_FMAC_FUNC_LOAD_X2 (FMAC_PARAM_FUNC_1) /*!< Load X2 buffer */
#define LL_FMAC_FUNC_LOAD_Y (FMAC_PARAM_FUNC_1 | FMAC_PARAM_FUNC_0) /*!< Load Y buffer */
#define LL_FMAC_FUNC_CONVO_FIR (FMAC_PARAM_FUNC_3) /*!< Convolution (FIR filter) */
#define LL_FMAC_FUNC_IIR_DIRECT_FORM_1 (FMAC_PARAM_FUNC_3 | FMAC_PARAM_FUNC_0) /*!< IIR filter (direct form 1) */
/**
* @}
*/
/** @defgroup FMAC_LL_EC_PROCESSING FMAC processing
* @{
*/
#define LL_FMAC_PROCESSING_STOP 0x00U /*!< Stop FMAC Processing */
#define LL_FMAC_PROCESSING_START 0x01U /*!< Start FMAC Processing */
/**
* @}
*/
/**
* @}
*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Macros FMAC Exported Macros
* @{
*/
/** @defgroup FMAC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in FMAC register
* @param __INSTANCE__ FMAC Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_FMAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in FMAC register
* @param __INSTANCE__ FMAC Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_FMAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup FMAC_LL_Exported_Functions FMAC Exported Functions
* @{
*/
/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
* @{
*/
/**
* @brief Configure X1 full watermark.
* @rmtoll X1BUFCFG FULL_WM LL_FMAC_SetX1FullWatermark
* @param FMACx FMAC instance
* @param Watermark This parameter can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1FullWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM, Watermark);
}
/**
* @brief Return X1 full watermark.
* @rmtoll X1BUFCFG FULL_WM LL_FMAC_GetX1FullWatermark
* @param FMACx FMAC instance
* @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
*/
__STATIC_INLINE uint32_t LL_FMAC_GetX1FullWatermark(FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM));
}
/**
* @brief Configure X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_SetX1BufferSize
* @param FMACx FMAC instance
* @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
}
/**
* @brief Return X1 buffer size.
* @rmtoll X1BUFCFG X1_BUF_SIZE LL_FMAC_GetX1BufferSize
* @param FMACx FMAC instance
* @retval uint8_t Number of 16-bit words allocated to the input buffer
* (including the optional "headroom") (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1BufferSize(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BUF_SIZE) >> FMAC_X1BUFCFG_X1_BUF_SIZE_Pos);
}
/**
* @brief Configure X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_SetX1Base
* @param FMACx FMAC instance
* @param Base Base address of the input buffer (X1) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX1Base(FMAC_TypeDef *FMACx, uint8_t Base)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE, ((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos);
}
/**
* @brief Return X1 base.
* @rmtoll X1BUFCFG X1_BASE LL_FMAC_GetX1Base
* @param FMACx FMAC instance
* @retval uint8_t Base address of the input buffer (X1) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX1Base(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X1BUFCFG, FMAC_X1BUFCFG_X1_BASE) >> FMAC_X1BUFCFG_X1_BASE_Pos);
}
/**
* @brief Configure X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_SetX2BufferSize
* @param FMACx FMAC instance
* @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX2BufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
}
/**
* @brief Return X2 buffer size.
* @rmtoll X2BUFCFG X2_BUF_SIZE LL_FMAC_GetX2BufferSize
* @param FMACx FMAC instance
* @retval uint8_t Number of 16-bit words allocated to the coefficient buffer
* (value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2BufferSize(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BUF_SIZE) >> FMAC_X2BUFCFG_X2_BUF_SIZE_Pos);
}
/**
* @brief Configure X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_SetX2Base
* @param FMACx FMAC instance
* @param Base Base address of the coefficient buffer (X2) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetX2Base(FMAC_TypeDef *FMACx, uint8_t Base)
{
MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE, ((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos);
}
/**
* @brief Return X2 base.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_GetX2Base
* @param FMACx FMAC instance
* @retval uint8_t Base address of the coefficient buffer (X2) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetX2Base(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE) >> FMAC_X2BUFCFG_X2_BASE_Pos);
}
/**
* @brief Configure Y empty watermark.
* @rmtoll YBUFCFG EMPTY_WM LL_FMAC_SetYEmptyWatermark
* @param FMACx FMAC instance
* @param Watermark This parameter can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYEmptyWatermark(FMAC_TypeDef *FMACx, uint32_t Watermark)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM, Watermark);
}
/**
* @brief Return Y empty watermark.
* @rmtoll YBUFCFG EMPTY_WM LL_FMAC_GetYEmptyWatermark
* @param FMACx FMAC instance
* @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
*/
__STATIC_INLINE uint32_t LL_FMAC_GetYEmptyWatermark(FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM));
}
/**
* @brief Configure Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_SetYBufferSize
* @param FMACx FMAC instance
* @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYBufferSize(FMAC_TypeDef *FMACx, uint8_t BufferSize)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE, ((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
}
/**
* @brief Return Y buffer size.
* @rmtoll YBUFCFG Y_BUF_SIZE LL_FMAC_GetYBufferSize
* @param FMACx FMAC instance
* @retval uint8_t Number of 16-bit words allocated to the output buffer
* (including the optional "headroom" - value between Min_Data=0x01 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBufferSize(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BUF_SIZE) >> FMAC_YBUFCFG_Y_BUF_SIZE_Pos);
}
/**
* @brief Configure Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_SetYBase
* @param FMACx FMAC instance
* @param Base Base address of the output buffer (Y) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetYBase(FMAC_TypeDef *FMACx, uint8_t Base)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE, ((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos);
}
/**
* @brief Return Y base.
* @rmtoll YBUFCFG Y_BASE LL_FMAC_GetYBase
* @param FMACx FMAC instance
* @retval uint8_t Base address of the output buffer (Y) within the internal memory
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetYBase(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->YBUFCFG, FMAC_YBUFCFG_Y_BASE) >> FMAC_YBUFCFG_Y_BASE_Pos);
}
/**
* @brief Start FMAC processing.
* @rmtoll PARAM START LL_FMAC_EnableStart
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableStart(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->PARAM, FMAC_PARAM_START);
}
/**
* @brief Stop FMAC processing.
* @rmtoll PARAM START LL_FMAC_DisableStart
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableStart(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->PARAM, FMAC_PARAM_START);
}
/**
* @brief Check the state of FMAC processing.
* @rmtoll PARAM START LL_FMAC_IsEnabledStart
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledStart(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->PARAM, FMAC_PARAM_START) == (FMAC_PARAM_START)) ? 1UL : 0UL);
}
/**
* @brief Configure function.
* @rmtoll PARAM FUNC LL_FMAC_SetFunction
* @param FMACx FMAC instance
* @param Function This parameter can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetFunction(FMAC_TypeDef *FMACx, uint32_t Function)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_FUNC, Function);
}
/**
* @brief Return function.
* @rmtoll PARAM FUNC LL_FMAC_GetFunction
* @param FMACx FMAC instance
* @retval uint32_t Returned value can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
*/
__STATIC_INLINE uint32_t LL_FMAC_GetFunction(FMAC_TypeDef *FMACx)
{
return (uint32_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_FUNC));
}
/**
* @brief Configure input parameter R.
* @rmtoll PARAM R LL_FMAC_SetParamR
* @param FMACx FMAC instance
* @param Param Parameter R (gain, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamR(FMAC_TypeDef *FMACx, uint8_t Param)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_R, ((uint32_t)Param) << FMAC_PARAM_R_Pos);
}
/**
* @brief Return input parameter R.
* @rmtoll PARAM R LL_FMAC_GetParamR
* @param FMACx FMAC instance
* @retval uint8_t Parameter R (gain, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamR(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_R) >> FMAC_PARAM_R_Pos);
}
/**
* @brief Configure input parameter Q.
* @rmtoll PARAM Q LL_FMAC_SetParamQ
* @param FMACx FMAC instance
* @param Param Parameter Q (vector length, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamQ(FMAC_TypeDef *FMACx, uint8_t Param)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_Q, ((uint32_t)Param) << FMAC_PARAM_Q_Pos);
}
/**
* @brief Return input parameter Q.
* @rmtoll PARAM Q LL_FMAC_GetParamQ
* @param FMACx FMAC instance
* @retval uint8_t Parameter Q (vector length, etc.) (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamQ(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_Q) >> FMAC_PARAM_Q_Pos);
}
/**
* @brief Configure input parameter P.
* @rmtoll PARAM P LL_FMAC_SetParamP
* @param FMACx FMAC instance
* @param Param Parameter P (vector length, number of filter taps, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_SetParamP(FMAC_TypeDef *FMACx, uint8_t Param)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_P, ((uint32_t)Param));
}
/**
* @brief Return input parameter P.
* @rmtoll PARAM P LL_FMAC_GetParamP
* @param FMACx FMAC instance
* @retval uint8_t Parameter P (vector length, number of filter taps, etc.)
* (value between Min_Data=0x00 and Max_Data=0xFF).
*/
__STATIC_INLINE uint8_t LL_FMAC_GetParamP(FMAC_TypeDef *FMACx)
{
return (uint8_t)(READ_BIT(FMACx->PARAM, FMAC_PARAM_P));
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_Reset_Management Reset_Management
* @{
*/
/**
* @brief Start the FMAC reset.
* @rmtoll CR RESET LL_FMAC_EnableReset
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableReset(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_RESET);
}
/**
* @brief Check the state of the FMAC reset.
* @rmtoll CR RESET LL_FMAC_IsEnabledReset
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledReset(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_RESET) == (FMAC_CR_RESET)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
* @{
*/
/**
* @brief Enable Clipping.
* @rmtoll CR CLIPEN LL_FMAC_EnableClipping
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableClipping(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_CLIPEN);
}
/**
* @brief Disable Clipping.
* @rmtoll CR CLIPEN LL_FMAC_DisableClipping
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableClipping(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_CLIPEN);
}
/**
* @brief Check Clipping State.
* @rmtoll CR CLIPEN LL_FMAC_IsEnabledClipping
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledClipping(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_CLIPEN) == (FMAC_CR_CLIPEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_DMA_Management DMA_Management
* @{
*/
/**
* @brief Enable FMAC DMA write channel request.
* @rmtoll CR DMAWEN LL_FMAC_EnableDMAReq_WRITE
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableDMAReq_WRITE(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_DMAWEN);
}
/**
* @brief Disable FMAC DMA write channel request.
* @rmtoll CR DMAWEN LL_FMAC_DisableDMAReq_WRITE
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableDMAReq_WRITE(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_DMAWEN);
}
/**
* @brief Check FMAC DMA write channel request state.
* @rmtoll CR DMAWEN LL_FMAC_IsEnabledDMAReq_WRITE
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_WRITE(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_DMAWEN) == (FMAC_CR_DMAWEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC DMA read channel request.
* @rmtoll CR DMAREN LL_FMAC_EnableDMAReq_READ
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableDMAReq_READ(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_DMAREN);
}
/**
* @brief Disable FMAC DMA read channel request.
* @rmtoll CR DMAREN LL_FMAC_DisableDMAReq_READ
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableDMAReq_READ(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_DMAREN);
}
/**
* @brief Check FMAC DMA read channel request state.
* @rmtoll CR DMAREN LL_FMAC_IsEnabledDMAReq_READ
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledDMAReq_READ(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_DMAREN) == (FMAC_CR_DMAREN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable FMAC saturation error interrupt.
* @rmtoll CR SATIEN LL_FMAC_EnableIT_SAT
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_SAT(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_SATIEN);
}
/**
* @brief Disable FMAC saturation error interrupt.
* @rmtoll CR SATIEN LL_FMAC_DisableIT_SAT
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_SAT(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_SATIEN);
}
/**
* @brief Check FMAC saturation error interrupt state.
* @rmtoll CR SATIEN LL_FMAC_IsEnabledIT_SAT
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_SAT(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_SATIEN) == (FMAC_CR_SATIEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC underflow error interrupt.
* @rmtoll CR UNFLIEN LL_FMAC_EnableIT_UNFL
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_UNFL(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
}
/**
* @brief Disable FMAC underflow error interrupt.
* @rmtoll CR UNFLIEN LL_FMAC_DisableIT_UNFL
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_UNFL(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_UNFLIEN);
}
/**
* @brief Check FMAC underflow error interrupt state.
* @rmtoll CR UNFLIEN LL_FMAC_IsEnabledIT_UNFL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_UNFL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_UNFLIEN) == (FMAC_CR_UNFLIEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC overflow error interrupt.
* @rmtoll CR OVFLIEN LL_FMAC_EnableIT_OVFL
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_OVFL(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
}
/**
* @brief Disable FMAC overflow error interrupt.
* @rmtoll CR OVFLIEN LL_FMAC_DisableIT_OVFL
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_OVFL(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_OVFLIEN);
}
/**
* @brief Check FMAC overflow error interrupt state.
* @rmtoll CR OVFLIEN LL_FMAC_IsEnabledIT_OVFL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_OVFL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_OVFLIEN) == (FMAC_CR_OVFLIEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC write interrupt.
* @rmtoll CR WIEN LL_FMAC_EnableIT_WR
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_WR(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_WIEN);
}
/**
* @brief Disable FMAC write interrupt.
* @rmtoll CR WIEN LL_FMAC_DisableIT_WR
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_WR(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_WIEN);
}
/**
* @brief Check FMAC write interrupt state.
* @rmtoll CR WIEN LL_FMAC_IsEnabledIT_WR
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_WR(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_WIEN) == (FMAC_CR_WIEN)) ? 1UL : 0UL);
}
/**
* @brief Enable FMAC read interrupt.
* @rmtoll CR RIEN LL_FMAC_EnableIT_RD
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_EnableIT_RD(FMAC_TypeDef *FMACx)
{
SET_BIT(FMACx->CR, FMAC_CR_RIEN);
}
/**
* @brief Disable FMAC read interrupt.
* @rmtoll CR RIEN LL_FMAC_DisableIT_RD
* @param FMACx FMAC instance
* @retval None
*/
__STATIC_INLINE void LL_FMAC_DisableIT_RD(FMAC_TypeDef *FMACx)
{
CLEAR_BIT(FMACx->CR, FMAC_CR_RIEN);
}
/**
* @brief Check FMAC read interrupt state.
* @rmtoll CR RIEN LL_FMAC_IsEnabledIT_RD
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsEnabledIT_RD(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->CR, FMAC_CR_RIEN) == (FMAC_CR_RIEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check FMAC saturation error flag state.
* @rmtoll SR SAT LL_FMAC_IsActiveFlag_SAT
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_SAT(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_SAT) == (FMAC_SR_SAT)) ? 1UL : 0UL);
}
/**
* @brief Check FMAC underflow error flag state.
* @rmtoll SR UNFL LL_FMAC_IsActiveFlag_UNFL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_UNFL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_UNFL) == (FMAC_SR_UNFL)) ? 1UL : 0UL);
}
/**
* @brief Check FMAC overflow error flag state.
* @rmtoll SR OVFL LL_FMAC_IsActiveFlag_OVFL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_OVFL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_OVFL) == (FMAC_SR_OVFL)) ? 1UL : 0UL);
}
/**
* @brief Check FMAC X1 buffer full flag state.
* @rmtoll SR X1FULL LL_FMAC_IsActiveFlag_X1FULL
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_X1FULL(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_X1FULL) == (FMAC_SR_X1FULL)) ? 1UL : 0UL);
}
/**
* @brief Check FMAC Y buffer empty flag state.
* @rmtoll SR YEMPTY LL_FMAC_IsActiveFlag_YEMPTY
* @param FMACx FMAC instance
* @retval uint32_t State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_FMAC_IsActiveFlag_YEMPTY(FMAC_TypeDef *FMACx)
{
return ((READ_BIT(FMACx->SR, FMAC_SR_YEMPTY) == (FMAC_SR_YEMPTY)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_Data_Management Data_Management
* @{
*/
/**
* @brief Write 16-bit input data for the FMAC processing.
* @rmtoll WDATA WDATA LL_FMAC_WriteData
* @param FMACx FMAC instance
* @param InData 16-bit value to be provided as input data for FMAC processing.
* This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_WriteData(FMAC_TypeDef *FMACx, uint16_t InData)
{
WRITE_REG(FMACx->WDATA, InData);
}
/**
* @brief Return 16-bit output data of FMAC processing.
* @rmtoll RDATA RDATA LL_FMAC_ReadData
* @param FMACx FMAC instance
* @retval uint16_t 16-bit output data of FMAC processing (value between Min_Data=0x0000 and Max_Data=0xFFFF).
*/
__STATIC_INLINE uint16_t LL_FMAC_ReadData(FMAC_TypeDef *FMACx)
{
return (uint16_t)(READ_REG(FMACx->RDATA));
}
/**
* @}
*/
/** @defgroup FMAC_LL_EF_Configuration FMAC Configuration functions
* @{
*/
/**
* @brief Configure memory for X1 buffer.
* @rmtoll X1BUFCFG FULL_WM LL_FMAC_ConfigX1\n
* X1BUFCFG X1_BASE LL_FMAC_ConfigX1\n
* X1BUFCFG X1_BUF_SIZE LL_FMAC_ConfigX1
* @param FMACx FMAC instance
* @param Watermark This parameter can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
* @param Base Base address of the input buffer (X1) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param BufferSize Number of 16-bit words allocated to the input buffer (including the optional "headroom").
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigX1(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X1BUFCFG, FMAC_X1BUFCFG_FULL_WM | FMAC_X1BUFCFG_X1_BASE | FMAC_X1BUFCFG_X1_BUF_SIZE,
Watermark | (((uint32_t)Base) << FMAC_X1BUFCFG_X1_BASE_Pos) |
(((uint32_t)BufferSize) << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos));
}
/**
* @brief Configure memory for X2 buffer.
* @rmtoll X2BUFCFG X2_BASE LL_FMAC_ConfigX2\n
* X2BUFCFG X2_BUF_SIZE LL_FMAC_ConfigX2
* @param FMACx FMAC instance
* @param Base Base address of the coefficient buffer (X2) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param BufferSize Number of 16-bit words allocated to the coefficient buffer.
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigX2(FMAC_TypeDef *FMACx, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->X2BUFCFG, FMAC_X2BUFCFG_X2_BASE | FMAC_X2BUFCFG_X2_BUF_SIZE,
(((uint32_t)Base) << FMAC_X2BUFCFG_X2_BASE_Pos) |
(((uint32_t)BufferSize) << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos));
}
/**
* @brief Configure memory for Y buffer.
* @rmtoll YBUFCFG EMPTY_WM LL_FMAC_ConfigY\n
* YBUFCFG Y_BASE LL_FMAC_ConfigY\n
* YBUFCFG Y_BUF_SIZE LL_FMAC_ConfigY
* @param FMACx FMAC instance
* @param Watermark This parameter can be one of the following values:
* @arg @ref LL_FMAC_WM_0_THRESHOLD_1
* @arg @ref LL_FMAC_WM_1_THRESHOLD_2
* @arg @ref LL_FMAC_WM_2_THRESHOLD_4
* @arg @ref LL_FMAC_WM_3_THRESHOLD_8
* @param Base Base address of the output buffer (Y) within the internal memory.
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param BufferSize Number of 16-bit words allocated to the output buffer (including the optional "headroom").
* This parameter must be a number between Min_Data=0x01 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigY(FMAC_TypeDef *FMACx, uint32_t Watermark, uint8_t Base, uint8_t BufferSize)
{
MODIFY_REG(FMACx->YBUFCFG, FMAC_YBUFCFG_EMPTY_WM | FMAC_YBUFCFG_Y_BASE | FMAC_YBUFCFG_Y_BUF_SIZE,
Watermark | (((uint32_t)Base) << FMAC_YBUFCFG_Y_BASE_Pos) |
(((uint32_t)BufferSize) << FMAC_YBUFCFG_Y_BUF_SIZE_Pos));
}
/**
* @brief Configure the FMAC processing.
* @rmtoll PARAM START LL_FMAC_ConfigFunc\n
* PARAM FUNC LL_FMAC_ConfigFunc\n
* PARAM P LL_FMAC_ConfigFunc\n
* PARAM Q LL_FMAC_ConfigFunc\n
* PARAM R LL_FMAC_ConfigFunc
* @param FMACx FMAC instance
* @param Start This parameter can be one of the following values:
* @arg @ref LL_FMAC_PROCESSING_STOP
* @arg @ref LL_FMAC_PROCESSING_START
* @param Function This parameter can be one of the following values:
* @arg @ref LL_FMAC_FUNC_LOAD_X1
* @arg @ref LL_FMAC_FUNC_LOAD_X2
* @arg @ref LL_FMAC_FUNC_LOAD_Y
* @arg @ref LL_FMAC_FUNC_CONVO_FIR
* @arg @ref LL_FMAC_FUNC_IIR_DIRECT_FORM_1
* @param ParamP Parameter P (vector length, number of filter taps, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param ParamQ Parameter Q (vector length, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @param ParamR Parameter R (gain, etc.).
* This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
* @retval None
*/
__STATIC_INLINE void LL_FMAC_ConfigFunc(FMAC_TypeDef *FMACx, uint8_t Start, uint32_t Function, uint8_t ParamP,
uint8_t ParamQ, uint8_t ParamR)
{
MODIFY_REG(FMACx->PARAM, FMAC_PARAM_START | FMAC_PARAM_FUNC | FMAC_PARAM_P | FMAC_PARAM_Q | FMAC_PARAM_R,
(((uint32_t)Start) << FMAC_PARAM_START_Pos) | Function | (((uint32_t)ParamP) << FMAC_PARAM_P_Pos) |
(((uint32_t)ParamQ) << FMAC_PARAM_Q_Pos) | (((uint32_t)ParamR) << FMAC_PARAM_R_Pos));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup FMAC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_FMAC_Init(FMAC_TypeDef *FMACx);
ErrorStatus LL_FMAC_DeInit(FMAC_TypeDef *FMACx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(FMAC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_FMAC_H */
| 35,102 | C | 31.991541 | 137 | 0.620449 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_fmc.h | /**
******************************************************************************
* @file stm32g4xx_ll_fmc.h
* @author MCD Application Team
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_FMC_H
#define STM32G4xx_LL_FMC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup FMC_LL
* @{
*/
/** @addtogroup FMC_LL_Private_Macros
* @{
*/
#if defined(FMC_BANK1)
#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
((__BANK__) == FMC_NORSRAM_BANK2) || \
((__BANK__) == FMC_NORSRAM_BANK3) || \
((__BANK__) == FMC_NORSRAM_BANK4))
#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
((__SIZE__) == FMC_PAGE_SIZE_128) || \
((__SIZE__) == FMC_PAGE_SIZE_256) || \
((__SIZE__) == FMC_PAGE_SIZE_512) || \
((__SIZE__) == FMC_PAGE_SIZE_1024))
#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
((__MODE__) == FMC_ACCESS_MODE_B) || \
((__MODE__) == FMC_ACCESS_MODE_C) || \
((__MODE__) == FMC_ACCESS_MODE_D))
#define IS_FMC_NBL_SETUPTIME(__NBL__) (((__NBL__) == FMC_NBL_SETUPTIME_0) || \
((__NBL__) == FMC_NBL_SETUPTIME_1) || \
((__NBL__) == FMC_NBL_SETUPTIME_2) || \
((__NBL__) == FMC_NBL_SETUPTIME_3))
#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
((__BURST__) == FMC_WRITE_BURST_ENABLE))
#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
#define IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 65535U))
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))
#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \
((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))
#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
((__STATE__) == FMC_NAND_ECC_ENABLE))
#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
#endif /* FMC_BANK3 */
/**
* @}
*/
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types
* @{
*/
#if defined(FMC_BANK1)
#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
#endif /* FMC_BANK3 */
#if defined(FMC_BANK1)
#define FMC_NORSRAM_DEVICE FMC_Bank1_R
#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E_R
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
#define FMC_NAND_DEVICE FMC_Bank3_R
#endif /* FMC_BANK3 */
#if defined(FMC_BANK1)
/**
* @brief FMC NORSRAM Configuration Structure definition
*/
typedef struct
{
uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
This parameter can be a value of @ref FMC_NORSRAM_Bank */
uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
multiplexed on the data bus or not.
This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
uint32_t MemoryType; /*!< Specifies the type of external memory attached to
the corresponding memory device.
This parameter can be a value of @ref FMC_Memory_Type */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
valid only with synchronous burst Flash memories.
This parameter can be a value of @ref FMC_Burst_Access_Mode */
uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
the Flash memory in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
clock cycle before the wait state or during the wait state,
valid only when accessing memories in burst mode.
This parameter can be a value of @ref FMC_Wait_Timing */
uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
This parameter can be a value of @ref FMC_Write_Operation */
uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
signal, valid for Flash memory access in burst mode.
This parameter can be a value of @ref FMC_Wait_Signal */
uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
This parameter can be a value of @ref FMC_Extended_Mode */
uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
valid only with asynchronous Flash memories.
This parameter can be a value of @ref FMC_AsynchronousWait */
uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
This parameter can be a value of @ref FMC_Write_Burst */
uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
This parameter is only enabled through the FMC_BCR1 register,
and don't care through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Continous_Clock */
uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
This parameter is only enabled through the FMC_BCR1 register,
and don't care through FMC_BCR2..4 registers.
This parameter can be a value of @ref FMC_Write_FIFO */
uint32_t PageSize; /*!< Specifies the memory page size.
This parameter can be a value of @ref FMC_Page_Size */
uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number
This parameter can be a value of @ref FMC_Byte_Lane */
FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this
NSBank for PSRAM refresh.
This parameter can be set to ENABLE or DISABLE */
uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for
synchronous accesses and in HCLK cycles for asynchronous accesses,
valid only if MaxChipSelectPulse is ENABLE.
This parameter can be a value between Min_Data = 1 and Max_Data = 65535.
@note: This parameter is common to all NSBank. */
} FMC_NORSRAM_InitTypeDef;
/**
* @brief FMC NORSRAM Timing parameters structure definition
*/
typedef struct
{
uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address setup time.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the address hold time.
This parameter can be a value between Min_Data = 1 and Max_Data = 15.
@note This parameter is not used with synchronous NOR Flash memories. */
uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data setup time.
This parameter can be a value between Min_Data = 1 and Max_Data = 255.
@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
NOR Flash memories. */
uint32_t DataHoldTime; /*!< Defines the number of HCLK cycles to configure
the duration of the data hold time.
This parameter can be a value between Min_Data = 0 and Max_Data = 3.
@note This parameter is used for used in asynchronous accesses. */
uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
the duration of the bus turnaround.
This parameter can be a value between Min_Data = 0 and Max_Data = 15.
@note This parameter is only used for multiplexed NOR Flash memories. */
uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
HCLK cycles. This parameter can be a value between Min_Data = 2 and
Max_Data = 16.
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
accesses. */
uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
to the memory before getting the first data.
The parameter value depends on the memory type as shown below:
- It must be set to 0 in case of a CRAM
- It is don't care in asynchronous NOR, SRAM or ROM accesses
- It may assume a value between Min_Data = 2 and Max_Data = 17
in NOR Flash memories with synchronous burst mode enable */
uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
This parameter can be a value of @ref FMC_Access_Mode */
} FMC_NORSRAM_TimingTypeDef;
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/**
* @brief FMC NAND Configuration Structure definition
*/
typedef struct
{
uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
This parameter can be a value of @ref FMC_NAND_Bank */
uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
This parameter can be any value of @ref FMC_Wait_feature */
uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
This parameter can be any value of @ref FMC_NAND_Data_Width */
uint32_t EccComputation; /*!< Enables or disables the ECC computation.
This parameter can be any value of @ref FMC_ECC */
uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
This parameter can be any value of @ref FMC_ECC_Page_Size */
uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between CLE low and RE low.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
delay between ALE low and RE low.
This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
} FMC_NAND_InitTypeDef;
#endif
#if defined(FMC_BANK3)
/**
* @brief FMC NAND Timing parameters structure definition
*/
typedef struct
{
uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
the command assertion for NAND-Flash read or write access
to common/Attribute or I/O memory space (depending on
the memory space timing to be configured).
This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
command for NAND-Flash read or write access to
common/Attribute or I/O memory space (depending on the
memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
(and data for write access) after the command de-assertion
for NAND-Flash read or write access to common/Attribute
or I/O memory space (depending on the memory space timing
to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
data bus is kept in HiZ after the start of a NAND-Flash
write access to common/Attribute or I/O memory space (depending
on the memory space timing to be configured).
This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
} FMC_NAND_PCC_TimingTypeDef;
#endif /* FMC_BANK3 */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
* @{
*/
#if defined(FMC_BANK1)
/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
* @{
*/
/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
* @{
*/
#define FMC_NORSRAM_BANK1 (0x00000000U)
#define FMC_NORSRAM_BANK2 (0x00000002U)
#define FMC_NORSRAM_BANK3 (0x00000004U)
#define FMC_NORSRAM_BANK4 (0x00000006U)
/**
* @}
*/
/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
* @{
*/
#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
/**
* @}
*/
/** @defgroup FMC_Memory_Type FMC Memory Type
* @{
*/
#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
#define FMC_MEMORY_TYPE_NOR (0x00000008U)
/**
* @}
*/
/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
* @{
*/
#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
/**
* @}
*/
/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
* @{
*/
#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
/**
* @}
*/
/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
* @{
*/
#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
/**
* @}
*/
/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
* @{
*/
#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
/**
* @}
*/
/** @defgroup FMC_Wait_Timing FMC Wait Timing
* @{
*/
#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
/**
* @}
*/
/** @defgroup FMC_Write_Operation FMC Write Operation
* @{
*/
#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
/**
* @}
*/
/** @defgroup FMC_Wait_Signal FMC Wait Signal
* @{
*/
#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
/**
* @}
*/
/** @defgroup FMC_Extended_Mode FMC Extended Mode
* @{
*/
#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
/**
* @}
*/
/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
* @{
*/
#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
/**
* @}
*/
/** @defgroup FMC_Page_Size FMC Page Size
* @{
*/
#define FMC_PAGE_SIZE_NONE (0x00000000U)
#define FMC_PAGE_SIZE_128 FMC_BCRx_CPSIZE_0
#define FMC_PAGE_SIZE_256 FMC_BCRx_CPSIZE_1
#define FMC_PAGE_SIZE_512 (FMC_BCRx_CPSIZE_0\
| FMC_BCRx_CPSIZE_1)
#define FMC_PAGE_SIZE_1024 FMC_BCRx_CPSIZE_2
/**
* @}
*/
/** @defgroup FMC_Write_Burst FMC Write Burst
* @{
*/
#define FMC_WRITE_BURST_DISABLE (0x00000000U)
#define FMC_WRITE_BURST_ENABLE (0x00080000U)
/**
* @}
*/
/** @defgroup FMC_Continous_Clock FMC Continuous Clock
* @{
*/
#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
/**
* @}
*/
/** @defgroup FMC_Write_FIFO FMC Write FIFO
* @{
*/
#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
/**
* @}
*/
/** @defgroup FMC_Access_Mode FMC Access Mode
* @{
*/
#define FMC_ACCESS_MODE_A (0x00000000U)
#define FMC_ACCESS_MODE_B (0x10000000U)
#define FMC_ACCESS_MODE_C (0x20000000U)
#define FMC_ACCESS_MODE_D (0x30000000U)
/**
* @}
*/
/** @defgroup FMC_Byte_Lane FMC Byte Lane(NBL) Setup
* @{
*/
#define FMC_NBL_SETUPTIME_0 (0x00000000U)
#define FMC_NBL_SETUPTIME_1 (0x00400000U)
#define FMC_NBL_SETUPTIME_2 (0x00800000U)
#define FMC_NBL_SETUPTIME_3 (0x00C00000U)
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
* @{
*/
/** @defgroup FMC_NAND_Bank FMC NAND Bank
* @{
*/
#define FMC_NAND_BANK3 (0x00000100U)
/**
* @}
*/
/** @defgroup FMC_Wait_feature FMC Wait feature
* @{
*/
#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U)
#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U)
/**
* @}
*/
/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
* @{
*/
#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
/**
* @}
*/
/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
* @{
*/
#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U)
#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U)
/**
* @}
*/
/** @defgroup FMC_ECC FMC ECC
* @{
*/
#define FMC_NAND_ECC_DISABLE (0x00000000U)
#define FMC_NAND_ECC_ENABLE (0x00000040U)
/**
* @}
*/
/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
* @{
*/
#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK3 */
/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
* @{
*/
#if defined(FMC_BANK3)
#define FMC_IT_RISING_EDGE (0x00000008U)
#define FMC_IT_LEVEL (0x00000010U)
#define FMC_IT_FALLING_EDGE (0x00000020U)
#endif /* FMC_BANK3 */
/**
* @}
*/
/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
* @{
*/
#if defined(FMC_BANK3)
#define FMC_FLAG_RISING_EDGE (0x00000001U)
#define FMC_FLAG_LEVEL (0x00000002U)
#define FMC_FLAG_FALLING_EDGE (0x00000004U)
#define FMC_FLAG_FEMPT (0x00000040U)
#endif /* FMC_BANK3 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
* @{
*/
#if defined(FMC_BANK1)
/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
* @brief macros to handle NOR device enable/disable and read/write operations
* @{
*/
/**
* @brief Enable the NORSRAM device access.
* @param __INSTANCE__ FMC_NORSRAM Instance
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
|= FMC_BCRx_MBKEN)
/**
* @brief Disable the NORSRAM device access.
* @param __INSTANCE__ FMC_NORSRAM Instance
* @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
&= ~FMC_BCRx_MBKEN)
/**
* @}
*/
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
* @brief macros to handle NAND device enable/disable
* @{
*/
/**
* @brief Enable the NAND device access.
* @param __INSTANCE__ FMC_NAND Instance
* @retval None
*/
#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
/**
* @brief Disable the NAND device access.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
/**
* @}
*/
#endif
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt
* @brief macros to handle NAND interrupts
* @{
*/
/**
* @brief Enable the NAND device interrupt.
* @param __INSTANCE__ FMC_NAND instance
* @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
/**
* @brief Disable the NAND device interrupt.
* @param __INSTANCE__ FMC_NAND Instance
* @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
* @retval None
*/
#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
/**
* @brief Get flag status of the NAND device.
* @param __INSTANCE__ FMC_NAND Instance
* @param __BANK__ FMC_NAND Bank
* @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval The state of FLAG (SET or RESET).
*/
#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the NAND device.
* @param __INSTANCE__ FMC_NAND Instance
* @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
* @arg FMC_FLAG_FEMPT: FIFO empty flag.
* @retval None
*/
#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
/**
* @}
*/
#endif /* FMC_BANK3 */
/**
* @}
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
* @{
*/
#if defined(FMC_BANK1)
/** @defgroup FMC_LL_NORSRAM NOR SRAM
* @{
*/
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
uint32_t ExtendedMode);
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
/**
* @}
*/
/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
* @{
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK1 */
#if defined(FMC_BANK3)
/** @defgroup FMC_LL_NAND NAND
* @{
*/
/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
* @{
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
/**
* @}
*/
/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
* @{
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
#endif /* FMC_BANK3 */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_FMC_H */
| 35,204 | C | 40.127336 | 120 | 0.509828 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_i2c_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_i2c_ex.h
* @author MCD Application Team
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_I2C_EX_H
#define STM32G4xx_HAL_I2C_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup I2CEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
* @{
*/
/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE 0x00000000U
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#if defined(SYSCFG_CFGR1_I2C4_FMP)
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_CFGR1_I2C4_FMP /*!< Enable Fast Mode Plus on I2C4 pins */
#else
#define I2C_FASTMODEPLUS_I2C4 (uint32_t)(0x00000800U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C4 not supported */
#endif /* SYSCFG_CFGR1_I2C4_FMP */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
* @{
*/
/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions
* @{
*/
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions
* @{
*/
HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions
* @{
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros
* @{
*/
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \
((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C4)) == I2C_FASTMODEPLUS_I2C4)))
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
* @{
*/
/* Private functions are defined in stm32g4xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_I2C_EX_H */
| 6,175 | C | 34.090909 | 130 | 0.496518 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rcc.h | /**
******************************************************************************
* @file stm32g4xx_ll_rcc.h
* @author MCD Application Team
* @brief Header file of RCC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file in
* the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_RCC_H
#define STM32G4xx_LL_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
/** @defgroup RCC_LL RCC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup RCC_LL_Private_Variables RCC Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RCC_LL_Private_Constants RCC Private Constants
* @{
*/
/* Defines used to perform offsets*/
/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
#define RCC_OFFSET_CCIPR 0U
#define RCC_OFFSET_CCIPR2 0x14U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_Private_Macros RCC Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_Exported_Types RCC Exported Types
* @{
*/
/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
* @{
*/
/**
* @brief RCC Clocks Frequency Structure
*/
typedef struct
{
uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
} LL_RCC_ClocksTypeDef;
/**
* @}
*/
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
* @{
*/
/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
* @brief Defines used to adapt values of different oscillators
* @note These values could be modified in the user environment according to
* HW set-up.
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
#endif /* HSI_VALUE */
#if !defined (LSE_VALUE)
#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
#endif /* LSE_VALUE */
#if !defined (LSI_VALUE)
#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
#endif /* LSI_VALUE */
#if !defined (HSI48_VALUE)
#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
#endif /* HSI48_VALUE */
#if !defined (EXTERNAL_CLOCK_VALUE)
#define EXTERNAL_CLOCK_VALUE 48000U /*!< Value of the I2S_CKIN, I2S and SAI1 external clock source in Hz */
#endif /* EXTERNAL_CLOCK_VALUE */
/**
* @}
*/
/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_RCC_WriteReg function
* @{
*/
#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */
#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */
#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */
#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */
#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */
#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /*!< HSI48 Ready Interrupt Clear */
#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */
#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */
/**
* @}
*/
/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RCC_ReadReg function
* @{
*/
#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */
#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */
#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */
#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */
#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */
#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */
#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */
#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */
#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */
#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
/**
* @}
*/
/** @defgroup RCC_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
* @{
*/
#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */
#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */
#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */
#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */
#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */
#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /*!< HSI48 Ready Interrupt Enable */
#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /*!< LSE CSS Interrupt Enable */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
* @{
*/
#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */
#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */
#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
* @{
*/
#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */
#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
* @{
*/
#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
* @{
*/
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
* @{
*/
#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
* @{
*/
#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
* @{
*/
#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
* @{
*/
#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */
#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI16 selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */
#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /*!< HSI48 selection as MCO1 source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
* @{
*/
#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO not divided */
#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO divided by 2 */
#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO divided by 4 */
#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO divided by 8 */
#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO divided by 16 */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
* @{
*/
#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
* @{
*/
#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /*!< PCLK2 clock used as USART1 clock source */
#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) | RCC_CCIPR_USART1SEL) /*!< LSE clock used as USART1 clock source */
#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /*!< PCLK1 clock used as USART2 clock source */
#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) | RCC_CCIPR_USART2SEL) /*!< LSE clock used as USART2 clock source */
#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /*!< PCLK1 clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) | RCC_CCIPR_USART3SEL) /*!< LSE clock used as USART3 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
* @{
*/
#if defined(RCC_CCIPR_UART4SEL)
#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */
#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) | RCC_CCIPR_UART4SEL) /*!< LSE clock used as UART4 clock source */
#endif /* RCC_CCIPR_UART4SEL */
#if defined(RCC_CCIPR_UART5SEL)
#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */
#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) | RCC_CCIPR_UART5SEL) /*!< LSE clock used as UART5 clock source */
#endif /* RCC_CCIPR_UART5SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
* @{
*/
#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */
#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /*!< LSE clock used as LPUART1 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
* @{
*/
#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */
#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */
#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */
#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */
#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */
#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */
#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C3 clock source */
#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */
#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */
#if defined(RCC_CCIPR2_I2C4SEL)
#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */
#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */
#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */
#endif /* RCC_CCIPR2_I2C4SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
* @{
*/
#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock source */
#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0 /*!< LSI clock used as LPTIM1 clock source */
#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 /*!< HSI clock used as LPTIM1 clock source */
#define LL_RCC_LPTIM1_CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL /*!< LSE clock used as LPTIM1 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
* @{
*/
#define LL_RCC_SAI1_CLKSOURCE_SYSCLK 0x00000000U /*!< System clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_PLL RCC_CCIPR_SAI1SEL_0 /*!< PLL clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_PIN RCC_CCIPR_SAI1SEL_1 /*!< EXT clock used as SAI1 clock source */
#define LL_RCC_SAI1_CLKSOURCE_HSI (RCC_CCIPR_SAI1SEL_0 | RCC_CCIPR_SAI1SEL_1) /*!< HSI clock used as SAI1 clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_I2S_CLKSOURCE Peripheral I2S clock source selection
* @{
*/
#define LL_RCC_I2S_CLKSOURCE_SYSCLK 0x00000000U /*!< System clock used as I2S clock source */
#define LL_RCC_I2S_CLKSOURCE_PLL RCC_CCIPR_I2S23SEL_0 /*!< PLL clock used as I2S clock source */
#define LL_RCC_I2S_CLKSOURCE_PIN RCC_CCIPR_I2S23SEL_1 /*!< EXT clock used as I2S clock source */
#define LL_RCC_I2S_CLKSOURCE_HSI (RCC_CCIPR_I2S23SEL_0 | RCC_CCIPR_I2S23SEL_1) /*!< HSI clock used as I2S clock source */
/**
* @}
*/
#if defined(FDCAN1)
/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
* @{
*/
#define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN clock source */
#define LL_RCC_FDCAN_CLKSOURCE_PLL RCC_CCIPR_FDCANSEL_0 /*!< PLL clock used as FDCAN clock source */
#define LL_RCC_FDCAN_CLKSOURCE_PCLK1 RCC_CCIPR_FDCANSEL_1 /*!< PCLK1 clock used as FDCAN clock source */
/**
* @}
*/
#endif /* FDCAN1 */
/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
* @{
*/
#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */
#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as RNG clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
* @{
*/
#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */
#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /*!< PLL clock used as USB clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
* @{
*/
#define LL_RCC_ADC12_CLKSOURCE_NONE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U)) /*!< No clock used as ADC12 clock source */
#define LL_RCC_ADC12_CLKSOURCE_PLL ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_0 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< PLL clock used as ADC12 clock source */
#define LL_RCC_ADC12_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL_1 >> RCC_CCIPR_ADC12SEL_Pos)) /*!< SYSCLK clock used as ADC12 clock source */
#if defined(RCC_CCIPR_ADC345SEL)
#define LL_RCC_ADC345_CLKSOURCE_NONE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U)) /*!< No clock used as ADC345 clock source */
#define LL_RCC_ADC345_CLKSOURCE_PLL ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_0 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< PLL clock used as ADC345 clock source */
#define LL_RCC_ADC345_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL_1 >> RCC_CCIPR_ADC345SEL_Pos)) /*!< SYSCLK clock used as ADC345 clock source */
#endif /* RCC_CCIPR_ADC345SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
* @{
*/
#define LL_RCC_QUADSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK used as QuadSPI clock source */
#define LL_RCC_QUADSPI_CLKSOURCE_HSI RCC_CCIPR2_QSPISEL_0 /*!< HSI used as QuadSPI clock source */
#define LL_RCC_QUADSPI_CLKSOURCE_PLL RCC_CCIPR2_QSPISEL_1 /*!< PLL used as QuadSPI clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
* @{
*/
#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /*!< USART1 Clock source selection */
#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /*!< USART2 Clock source selection */
#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /*!< USART3 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
* @{
*/
#if defined(RCC_CCIPR_UART4SEL)
#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /*!< UART4 Clock source selection */
#endif /* RCC_CCIPR_UART4SEL */
#if defined(RCC_CCIPR_UART5SEL)
#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /*!< UART5 Clock source selection */
#endif /* RCC_CCIPR_UART5SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
* @{
*/
#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /*!< LPUART1 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
* @{
*/
#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C1SEL_Pos << 16U) | (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */
#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C2SEL_Pos << 16U) | (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */
#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_I2C3SEL_Pos << 16U) | (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */
#if defined(RCC_CCIPR2_I2C4SEL)
#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C4SEL_Pos << 16U) | (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */
#endif /* RCC_CCIPR2_I2C4SEL */
/**
* @}
*/
/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
* @{
*/
#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /*!< LPTIM1 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
* @{
*/
#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /*!< SAI1 Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_I2S Peripheral I2S get clock source
* @{
*/
#define LL_RCC_I2S_CLKSOURCE RCC_CCIPR_I2S23SEL /*!< I2S Clock source selection */
/**
* @}
*/
#if defined(FDCAN1)
/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
* @{
*/
#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR_FDCANSEL /*!< FDCAN Clock source selection */
#endif /* FDCAN1 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
* @{
*/
#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< RNG Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
* @{
*/
#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /*!< USB Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
* @{
*/
#define LL_RCC_ADC12_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC12SEL_Pos << 16U) | (RCC_CCIPR_ADC12SEL >> RCC_CCIPR_ADC12SEL_Pos)) /*!< ADC12 Clock source selection */
#if defined(RCC_CCIPR_ADC345SEL_Pos)
#define LL_RCC_ADC345_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) | (RCC_CCIPR_ADC345SEL_Pos << 16U) | (RCC_CCIPR_ADC345SEL >> RCC_CCIPR_ADC345SEL_Pos)) /*!< ADC345 Clock source selection */
#endif /* RCC_CCIPR_ADC345SEL_Pos */
/**
* @}
*/
/** @defgroup RCC_LL_EC_QUADSPI Peripheral QUADSPI get clock source
* @{
*/
#define LL_RCC_QUADSPI_CLKSOURCE RCC_CCIPR2_QSPISEL /*!< QuadSPI Clock source selection */
/**
* @}
*/
/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
* @{
*/
#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source
* @{
*/
#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */
#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
* @{
*/
#define LL_RCC_PLLM_DIV_1 0x00000000U /*!< PLL division factor by 1 */
#define LL_RCC_PLLM_DIV_2 RCC_PLLCFGR_PLLM_0 /*!< PLL division factor by 2 */
#define LL_RCC_PLLM_DIV_3 RCC_PLLCFGR_PLLM_1 /*!< PLL division factor by 3 */
#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 4 */
#define LL_RCC_PLLM_DIV_5 RCC_PLLCFGR_PLLM_2 /*!< PLL division factor by 5 */
#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 6 */
#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 7 */
#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 8 */
#define LL_RCC_PLLM_DIV_9 RCC_PLLCFGR_PLLM_3 /*!< PLL division factor by 9 */
#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 10 */
#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 11 */
#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 12 */
#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL division factor by 13 */
#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 14 */
#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL division factor by 15 */
#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL division factor by 16 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
* @{
*/
#define LL_RCC_PLLR_DIV_2 0x00000000U /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 8 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
* @{
*/
#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 2 */
#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 3 */
#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 4 */
#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 5 */
#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 6 */
#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 7 */
#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 8 */
#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 9 */
#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 10 */
#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 11 */
#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 12 */
#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 13 */
#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 14 */
#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 15 */
#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /*!< Main PLL division factor for PLLP output by 16 */
#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 17 */
#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 18 */
#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 19 */
#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 20 */
#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 21 */
#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 22 */
#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 23 */
#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3) /*!< Main PLL division factor for PLLP output by 24 */
#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 25 */
#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 26 */
#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 27 */
#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2) /*!< Main PLL division factor for PLLP output by 28 */
#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 29 */
#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1) /*!< Main PLL division factor for PLLP output by 30 */
#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4|RCC_PLLCFGR_PLLPDIV_3|RCC_PLLCFGR_PLLPDIV_2|RCC_PLLCFGR_PLLPDIV_1|RCC_PLLCFGR_PLLPDIV_0) /*!< Main PLL division factor for PLLP output by 31 */
/**
* @}
*/
/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
* @{
*/
#define LL_RCC_PLLQ_DIV_2 0x00000000U /*!< Main PLL division factor for PLLQ output by 2 */
#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 4 */
#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /*!< Main PLL division factor for PLLQ output by 8 */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
* @{
*/
/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in RCC register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, __VALUE__)
/**
* @brief Read a value in RCC register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
/**
* @}
*/
/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
* @{
*/
/**
* @brief Helper macro to calculate the PLLCLK frequency on system domain
* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
* @param __PLLM__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_1
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
* @param __PLLR__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLR_DIV_2
* @arg @ref LL_RCC_PLLR_DIV_4
* @arg @ref LL_RCC_PLLR_DIV_6
* @arg @ref LL_RCC_PLLR_DIV_8
* @retval PLL clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
/**
* @brief Helper macro to calculate the PLLCLK frequency used on ADC domain
* @note ex: @ref __LL_RCC_CALC_PLLCLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
* @param __PLLM__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_1
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
* @param __PLLP__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_3
* @arg @ref LL_RCC_PLLP_DIV_4
* @arg @ref LL_RCC_PLLP_DIV_5
* @arg @ref LL_RCC_PLLP_DIV_6
* @arg @ref LL_RCC_PLLP_DIV_7
* @arg @ref LL_RCC_PLLP_DIV_8
* @arg @ref LL_RCC_PLLP_DIV_9
* @arg @ref LL_RCC_PLLP_DIV_10
* @arg @ref LL_RCC_PLLP_DIV_11
* @arg @ref LL_RCC_PLLP_DIV_12
* @arg @ref LL_RCC_PLLP_DIV_13
* @arg @ref LL_RCC_PLLP_DIV_14
* @arg @ref LL_RCC_PLLP_DIV_15
* @arg @ref LL_RCC_PLLP_DIV_16
* @arg @ref LL_RCC_PLLP_DIV_17
* @arg @ref LL_RCC_PLLP_DIV_18
* @arg @ref LL_RCC_PLLP_DIV_19
* @arg @ref LL_RCC_PLLP_DIV_20
* @arg @ref LL_RCC_PLLP_DIV_21
* @arg @ref LL_RCC_PLLP_DIV_22
* @arg @ref LL_RCC_PLLP_DIV_23
* @arg @ref LL_RCC_PLLP_DIV_24
* @arg @ref LL_RCC_PLLP_DIV_25
* @arg @ref LL_RCC_PLLP_DIV_26
* @arg @ref LL_RCC_PLLP_DIV_27
* @arg @ref LL_RCC_PLLP_DIV_28
* @arg @ref LL_RCC_PLLP_DIV_29
* @arg @ref LL_RCC_PLLP_DIV_30
* @arg @ref LL_RCC_PLLP_DIV_31
* @retval PLL clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLCLK_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
/**
* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
* @param __PLLM__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_1
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @param __PLLN__ Between Min_Data = 8 and Max_Data = 127
* @param __PLLQ__ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
* @arg @ref LL_RCC_PLLQ_DIV_4
* @arg @ref LL_RCC_PLLQ_DIV_6
* @arg @ref LL_RCC_PLLQ_DIV_8
* @retval PLL clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) * (__PLLN__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) / \
((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
/**
* @brief Helper macro to calculate the HCLK frequency
* @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
* @param __AHBPRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval HCLK clock frequency (in Hz)
*/
#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU))
/**
* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
* @param __HCLKFREQ__ HCLK frequency
* @param __APB1PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval PCLK1 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos] & 0x1FU))
/**
* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
* @param __HCLKFREQ__ HCLK frequency
* @param __APB2PRESCALER__ This parameter can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
* @retval PCLK2 clock frequency (in Hz)
*/
#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> (APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos] & 0x1FU))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
* @{
*/
/** @defgroup RCC_LL_EF_HSE HSE
* @{
*/
/**
* @brief Enable the Clock Security System.
* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
{
SET_BIT(RCC->CR, RCC_CR_CSSON);
}
/**
* @brief Enable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
{
SET_BIT(RCC->CR, RCC_CR_HSEBYP);
}
/**
* @brief Disable HSE external oscillator (HSE Bypass)
* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
}
/**
* @brief Enable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_HSEON);
}
/**
* @brief Disable HSE crystal oscillator (HSE ON)
* @rmtoll CR HSEON LL_RCC_HSE_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSE_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
}
/**
* @brief Check if HSE oscillator Ready
* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_HSI HSI
* @{
*/
/**
* @brief Enable HSI even in stop mode
* @note HSI oscillator is forced ON even in Stop mode
* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
{
SET_BIT(RCC->CR, RCC_CR_HSIKERON);
}
/**
* @brief Disable HSI in stop mode
* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
}
/**
* @brief Enable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_HSION);
}
/**
* @brief Disable HSI oscillator
* @rmtoll CR HSION LL_RCC_HSI_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_HSION);
}
/**
* @brief Check if HSI clock is ready
* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
}
/**
* @brief Get HSI Calibration value
* @note When HSITRIM is written, HSICAL is updated with the sum of
* HSITRIM and the factory trim value
* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
{
return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
}
/**
* @brief Set HSI Calibration trimming
* @note user-programmable trimming value that is added to the HSICAL
* @note Default value is 16, which, when added to the HSICAL value,
* should trim the HSI to 16 MHz +/- 1 %
* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
* @param Value Between Min_Data = 0 and Max_Data = 127
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
{
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
}
/**
* @brief Get HSI Calibration trimming
* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
* @retval Between Min_Data = 0 and Max_Data = 127
*/
__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
{
return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_HSI48 HSI48
* @{
*/
/**
* @brief Enable HSI48
* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
{
SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
}
/**
* @brief Disable HSI48
* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
{
CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
}
/**
* @brief Check if HSI48 oscillator Ready
* @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
{
return ((READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY)) ? 1UL : 0UL);
}
/**
* @brief Get HSI48 Calibration value
* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
* @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
*/
__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
{
return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_LSE LSE
* @{
*/
/**
* @brief Enable Low Speed External (LSE) crystal.
* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_Enable(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
/**
* @brief Disable Low Speed External (LSE) crystal.
* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_Disable(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
}
/**
* @brief Enable external clock source (LSE bypass).
* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
/**
* @brief Disable external clock source (LSE bypass).
* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
}
/**
* @brief Set LSE oscillator drive capability
* @note The oscillator is in Xtal mode when it is not in bypass mode.
* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
* @param LSEDrive This parameter can be one of the following values:
* @arg @ref LL_RCC_LSEDRIVE_LOW
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
* @arg @ref LL_RCC_LSEDRIVE_HIGH
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
{
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
}
/**
* @brief Get LSE oscillator drive capability
* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LSEDRIVE_LOW
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
* @arg @ref LL_RCC_LSEDRIVE_HIGH
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
{
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
}
/**
* @brief Enable Clock security system on LSE.
* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
}
/**
* @brief Disable Clock security system on LSE.
* @note Clock security system can be disabled only after a LSE
* failure detection. In that case it MUST be disabled by software.
* @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
}
/**
* @brief Check if LSE oscillator Ready
* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
}
/**
* @brief Check if CSS on LSE failure Detection
* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_LSI LSI
* @{
*/
/**
* @brief Enable LSI Oscillator
* @rmtoll CSR LSION LL_RCC_LSI_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSI_Enable(void)
{
SET_BIT(RCC->CSR, RCC_CSR_LSION);
}
/**
* @brief Disable LSI Oscillator
* @rmtoll CSR LSION LL_RCC_LSI_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSI_Disable(void)
{
CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
}
/**
* @brief Check if LSI is Ready
* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_LSCO LSCO
* @{
*/
/**
* @brief Enable Low speed clock
* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
}
/**
* @brief Disable Low speed clock
* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
}
/**
* @brief Configure Low speed clock selection
* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
{
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
}
/**
* @brief Get Low speed clock selection
* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
{
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_System System
* @{
*/
/**
* @brief Configure the system clock source
* @rmtoll CFGR SW LL_RCC_SetSysClkSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
}
/**
* @brief Get the system clock source
* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
*/
__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
}
/**
* @brief Set AHB prescaler
* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
}
/**
* @brief Set APB1 prescaler
* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
}
/**
* @brief Set APB2 prescaler
* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
* @param Prescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
}
/**
* @brief Get AHB prescaler
* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SYSCLK_DIV_1
* @arg @ref LL_RCC_SYSCLK_DIV_2
* @arg @ref LL_RCC_SYSCLK_DIV_4
* @arg @ref LL_RCC_SYSCLK_DIV_8
* @arg @ref LL_RCC_SYSCLK_DIV_16
* @arg @ref LL_RCC_SYSCLK_DIV_64
* @arg @ref LL_RCC_SYSCLK_DIV_128
* @arg @ref LL_RCC_SYSCLK_DIV_256
* @arg @ref LL_RCC_SYSCLK_DIV_512
*/
__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
}
/**
* @brief Get APB1 prescaler
* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_APB1_DIV_1
* @arg @ref LL_RCC_APB1_DIV_2
* @arg @ref LL_RCC_APB1_DIV_4
* @arg @ref LL_RCC_APB1_DIV_8
* @arg @ref LL_RCC_APB1_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
}
/**
* @brief Get APB2 prescaler
* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_APB2_DIV_1
* @arg @ref LL_RCC_APB2_DIV_2
* @arg @ref LL_RCC_APB2_DIV_4
* @arg @ref LL_RCC_APB2_DIV_8
* @arg @ref LL_RCC_APB2_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
{
return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_MCO MCO
* @{
*/
/**
* @brief Configure MCOx
* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
* CFGR MCOPRE LL_RCC_ConfigMCO
* @param MCOxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
* @arg @ref LL_RCC_MCO1SOURCE_HSI
* @arg @ref LL_RCC_MCO1SOURCE_HSE
* @arg @ref LL_RCC_MCO1SOURCE_HSI48
* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
* @arg @ref LL_RCC_MCO1SOURCE_LSI
* @arg @ref LL_RCC_MCO1SOURCE_LSE
*
* (*) value not defined in all devices.
* @param MCOxPrescaler This parameter can be one of the following values:
* @arg @ref LL_RCC_MCO1_DIV_1
* @arg @ref LL_RCC_MCO1_DIV_2
* @arg @ref LL_RCC_MCO1_DIV_4
* @arg @ref LL_RCC_MCO1_DIV_8
* @arg @ref LL_RCC_MCO1_DIV_16
* @retval None
*/
__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
* @{
*/
/**
* @brief Configure USARTx clock source
* @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
* @param USARTxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
{
MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
}
#if defined(UART4)
/**
* @brief Configure UARTx clock source
* @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
* @param UARTxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
{
MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
}
#endif /* UART4 */
/**
* @brief Configure LPUART1x clock source
* @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
* @param LPUARTxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
}
/**
* @brief Configure I2Cx clock source
* @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
* @param I2CxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
{
__IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
MODIFY_REG(*reg, 3UL << ((I2CxSource & 0x001F0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x001F0000U) >> 16U)));
}
/**
* @brief Configure LPTIMx clock source
* @rmtoll CCIPR LPTIM1SEL LL_RCC_SetLPTIMClockSource
* @param LPTIMxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, LPTIMxSource);
}
/**
* @brief Configure SAIx clock source
* @rmtoll CCIPR SAI1SEL LL_RCC_SetSAIClockSource
* @param SAIxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
* @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SAI1SEL, SAIxSource);
}
/**
* @brief Configure I2S clock source
* @rmtoll CCIPR I2S23SEL LL_RCC_SetI2SClockSource
* @param I2SxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
* @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
* @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t I2SxSource)
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S23SEL, I2SxSource);
}
#if defined(FDCAN1)
/**
* @brief Configure FDCAN clock source
* @rmtoll CCIPR FDCANSEL LL_RCC_SetFDCANClockSource
* @param FDCANxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource)
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_FDCANSEL, FDCANxSource);
}
#endif /* FDCAN1 */
/**
* @brief Configure RNG clock source
* @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
* @param RNGxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
}
/**
* @brief Configure USB clock source
* @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
* @param USBxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
{
MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
}
/**
* @brief Configure ADC clock source
* @rmtoll CCIPR ADC12SEL LL_RCC_SetADCClockSource\n
* CCIPR ADC345SEL LL_RCC_SetADCClockSource
* @param ADCxSource This parameter can be one of the following values:
* @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
* @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
* @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
* @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
* @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
*
* (*) value not defined in all devices.
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
{
MODIFY_REG(RCC->CCIPR, 3U << ((ADCxSource & 0x001F0000U) >> 16U), ((ADCxSource & 0x000000FFU) << ((ADCxSource & 0x001F0000U) >> 16U)));
}
#if defined(QUADSPI)
/**
* @brief Configure QUADSPI clock source
* @rmtoll CCIPR2 QSPISEL LL_RCC_SetQUADSPIClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
* @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetQUADSPIClockSource(uint32_t Source)
{
MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_QSPISEL, Source);
}
#endif /* QUADSPI */
/**
* @brief Get USARTx clock source
* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
* @param USARTx This parameter can be one of the following values:
* @arg @ref LL_RCC_USART1_CLKSOURCE
* @arg @ref LL_RCC_USART2_CLKSOURCE
* @arg @ref LL_RCC_USART3_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16U));
}
#if defined(UART4)
/**
* @brief Get UARTx clock source
* @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
* @param UARTx This parameter can be one of the following values:
* @arg @ref LL_RCC_UART4_CLKSOURCE (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE (*)
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 (*)
* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK (*)
* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI (*)
* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI (*)
* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) | (UARTx << 16U));
}
#endif /* UART4 */
/**
* @brief Get LPUARTx clock source
* @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
* @param LPUARTx This parameter can be one of the following values:
* @arg @ref LL_RCC_LPUART1_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
}
/**
* @brief Get I2Cx clock source
* @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
* @param I2Cx This parameter can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE
* @arg @ref LL_RCC_I2C2_CLKSOURCE
* @arg @ref LL_RCC_I2C3_CLKSOURCE
* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
*
* (*) value not defined in all devices.
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
{
__IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
return (uint32_t)((READ_BIT(*reg, 3UL << ((I2Cx & 0x001F0000U) >> 16U)) >> ((I2Cx & 0x001F0000U) >> 16U)) | (I2Cx & 0xFFFF0000U));
}
/**
* @brief Get LPTIMx clock source
* @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
* @param LPTIMx This parameter can be one of the following values:
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
*/
__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx));
}
/**
* @brief Get SAIx clock source
* @rmtoll CCIPR SAI1SEL LL_RCC_GetSAIClockSource
* @param SAIx This parameter can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE
*
* (*) value not defined in all devices.
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_SAI1_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
* @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx));
}
/**
* @brief Get I2Sx clock source
* @rmtoll CCIPR I2S23SEL LL_RCC_GetI2SClockSource
* @param I2Sx This parameter can be one of the following values:
* @arg @ref LL_RCC_I2S_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_I2S_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_I2S_CLKSOURCE_PLL
* @arg @ref LL_RCC_I2S_CLKSOURCE_PIN
* @arg @ref LL_RCC_I2S_CLKSOURCE_HSI
*/
__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, I2Sx));
}
#if defined(FDCAN1)
/**
* @brief Get FDCANx clock source
* @rmtoll CCIPR FDCANSEL LL_RCC_GetFDCANClockSource
* @param FDCANx This parameter can be one of the following values:
* @arg @ref LL_RCC_FDCAN_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL
* @arg @ref LL_RCC_FDCAN_CLKSOURCE_PCLK1
* @retval None
*/
__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, FDCANx));
}
#endif /* FDCAN1 */
/**
* @brief Get RNGx clock source
* @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
* @param RNGx This parameter can be one of the following values:
* @arg @ref LL_RCC_RNG_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
*/
__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
}
/**
* @brief Get USBx clock source
* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
* @param USBx This parameter can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
*/
__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
}
/**
* @brief Get ADCx clock source
* @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
* @param ADCx This parameter can be one of the following values:
* @arg @ref LL_RCC_ADC12_CLKSOURCE
* @arg @ref LL_RCC_ADC345_CLKSOURCE (*)
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_ADC12_CLKSOURCE_NONE
* @arg @ref LL_RCC_ADC12_CLKSOURCE_PLL
* @arg @ref LL_RCC_ADC12_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_ADC345_CLKSOURCE_NONE (*)
* @arg @ref LL_RCC_ADC345_CLKSOURCE_PLL (*)
* @arg @ref LL_RCC_ADC345_CLKSOURCE_SYSCLK (*)
*
* (*) value not defined in all devices.
*/
__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
{
return (uint32_t)((READ_BIT(RCC->CCIPR, 3UL << ((ADCx & 0x001F0000U) >> 16U)) >> ((ADCx & 0x001F0000U) >> 16U)) | (ADCx & 0xFFFF0000U));
}
#if defined(QUADSPI)
/**
* @brief Get QUADSPI clock source
* @rmtoll CCIPR2 QSPISEL LL_RCC_GetQUADSPIClockSource
* @param QUADSPIx This parameter can be one of the following values:
* @arg @ref LL_RCC_QUADSPI_CLKSOURCE
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_QUADSPI_CLKSOURCE_SYSCLK
* @arg @ref LL_RCC_QUADSPI_CLKSOURCE_HSI
* @arg @ref LL_RCC_QUADSPI_CLKSOURCE_PLL
*/
__STATIC_INLINE uint32_t LL_RCC_GetQUADSPIClockSource(uint32_t QUADSPIx)
{
return (uint32_t)(READ_BIT(RCC->CCIPR2, QUADSPIx));
}
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup RCC_LL_EF_RTC RTC
* @{
*/
/**
* @brief Set RTC Clock Source
* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
* set). The BDRST bit can be used to reset them.
* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
* @retval None
*/
__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
{
MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
}
/**
* @brief Get RTC Clock Source
* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
*/
__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
{
return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
}
/**
* @brief Enable RTC
* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableRTC(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
}
/**
* @brief Disable RTC
* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableRTC(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
}
/**
* @brief Check if RTC has been enabled or not
* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
{
return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
}
/**
* @brief Force the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
{
SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
}
/**
* @brief Release the Backup domain reset
* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
* @retval None
*/
__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
{
CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_PLL PLL
* @{
*/
/**
* @brief Enable PLL
* @rmtoll CR PLLON LL_RCC_PLL_Enable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Enable(void)
{
SET_BIT(RCC->CR, RCC_CR_PLLON);
}
/**
* @brief Disable PLL
* @note Cannot be disabled if the PLL clock is used as the system clock
* @rmtoll CR PLLON LL_RCC_PLL_Disable
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_Disable(void)
{
CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
}
/**
* @brief Check if PLL Ready
* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
{
return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL);
}
/**
* @brief Configure PLL used for SYSCLK Domain
* @note PLL Source and PLLM Divider can be written only when PLL
* is disabled.
* @note PLLN/PLLR can be written only when PLL is disabled.
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @param PLLM This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_1
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @param PLLN Between Min_Data = 8 and Max_Data = 127
* @param PLLR This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLR_DIV_2
* @arg @ref LL_RCC_PLLR_DIV_4
* @arg @ref LL_RCC_PLLR_DIV_6
* @arg @ref LL_RCC_PLLR_DIV_8
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLR);
}
/**
* @brief Configure PLL used for ADC domain clock
* @note PLL Source and PLLM Divider can be written only when PLL
* is disabled.
* @note PLLN/PLLP can be written only when PLL is disabled.
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_ADC\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_ADC\n
* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_ADC\n
* PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_ADC
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @param PLLM This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_1
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @param PLLN Between Min_Data = 8 and Max_Data = 127
* @param PLLP This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_3
* @arg @ref LL_RCC_PLLP_DIV_4
* @arg @ref LL_RCC_PLLP_DIV_5
* @arg @ref LL_RCC_PLLP_DIV_6
* @arg @ref LL_RCC_PLLP_DIV_7
* @arg @ref LL_RCC_PLLP_DIV_8
* @arg @ref LL_RCC_PLLP_DIV_9
* @arg @ref LL_RCC_PLLP_DIV_10
* @arg @ref LL_RCC_PLLP_DIV_11
* @arg @ref LL_RCC_PLLP_DIV_12
* @arg @ref LL_RCC_PLLP_DIV_13
* @arg @ref LL_RCC_PLLP_DIV_14
* @arg @ref LL_RCC_PLLP_DIV_15
* @arg @ref LL_RCC_PLLP_DIV_16
* @arg @ref LL_RCC_PLLP_DIV_17
* @arg @ref LL_RCC_PLLP_DIV_18
* @arg @ref LL_RCC_PLLP_DIV_19
* @arg @ref LL_RCC_PLLP_DIV_20
* @arg @ref LL_RCC_PLLP_DIV_21
* @arg @ref LL_RCC_PLLP_DIV_22
* @arg @ref LL_RCC_PLLP_DIV_23
* @arg @ref LL_RCC_PLLP_DIV_24
* @arg @ref LL_RCC_PLLP_DIV_25
* @arg @ref LL_RCC_PLLP_DIV_26
* @arg @ref LL_RCC_PLLP_DIV_27
* @arg @ref LL_RCC_PLLP_DIV_28
* @arg @ref LL_RCC_PLLP_DIV_29
* @arg @ref LL_RCC_PLLP_DIV_30
* @arg @ref LL_RCC_PLLP_DIV_31
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLPDIV,
Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLP);
}
/**
* @brief Configure PLL used for 48Mhz domain clock
* @note PLL Source and PLLM Divider can be written only when PLL,
* is disabled.
* @note PLLN/PLLQ can be written only when PLL is disabled.
* @note This can be selected for USB, RNG
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
* @param Source This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @param PLLM This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_1
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
* @param PLLN Between Min_Data = 8 and Max_Data = 127
* @param PLLQ This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
* @arg @ref LL_RCC_PLLQ_DIV_4
* @arg @ref LL_RCC_PLLQ_DIV_6
* @arg @ref LL_RCC_PLLQ_DIV_8
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
Source | PLLM | (PLLN << RCC_PLLCFGR_PLLN_Pos) | PLLQ);
}
/**
* @brief Configure PLL clock source
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
* @param PLLSource This parameter can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
{
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
}
/**
* @brief Get the oscillator used as PLL clock source.
* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLSOURCE_NONE
* @arg @ref LL_RCC_PLLSOURCE_HSI
* @arg @ref LL_RCC_PLLSOURCE_HSE
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
}
/**
* @brief Get Main PLL multiplication factor for VCO
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
* @retval Between Min_Data = 8 and Max_Data = 127
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
}
/**
* @brief Get Main PLL division factor for PLLP
* @note Used for PLLADCCLK (ADC clock)
* @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP\n
* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLP_DIV_2
* @arg @ref LL_RCC_PLLP_DIV_3
* @arg @ref LL_RCC_PLLP_DIV_4
* @arg @ref LL_RCC_PLLP_DIV_5
* @arg @ref LL_RCC_PLLP_DIV_6
* @arg @ref LL_RCC_PLLP_DIV_7
* @arg @ref LL_RCC_PLLP_DIV_8
* @arg @ref LL_RCC_PLLP_DIV_9
* @arg @ref LL_RCC_PLLP_DIV_10
* @arg @ref LL_RCC_PLLP_DIV_11
* @arg @ref LL_RCC_PLLP_DIV_12
* @arg @ref LL_RCC_PLLP_DIV_13
* @arg @ref LL_RCC_PLLP_DIV_14
* @arg @ref LL_RCC_PLLP_DIV_15
* @arg @ref LL_RCC_PLLP_DIV_16
* @arg @ref LL_RCC_PLLP_DIV_17
* @arg @ref LL_RCC_PLLP_DIV_18
* @arg @ref LL_RCC_PLLP_DIV_19
* @arg @ref LL_RCC_PLLP_DIV_20
* @arg @ref LL_RCC_PLLP_DIV_21
* @arg @ref LL_RCC_PLLP_DIV_22
* @arg @ref LL_RCC_PLLP_DIV_23
* @arg @ref LL_RCC_PLLP_DIV_24
* @arg @ref LL_RCC_PLLP_DIV_25
* @arg @ref LL_RCC_PLLP_DIV_26
* @arg @ref LL_RCC_PLLP_DIV_27
* @arg @ref LL_RCC_PLLP_DIV_28
* @arg @ref LL_RCC_PLLP_DIV_29
* @arg @ref LL_RCC_PLLP_DIV_30
* @arg @ref LL_RCC_PLLP_DIV_31
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
{
return (uint32_t) ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) != 0U) ? READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV) : ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP) == RCC_PLLCFGR_PLLP) ? LL_RCC_PLLP_DIV_17 : LL_RCC_PLLP_DIV_7) );
}
/**
* @brief Get Main PLL division factor for PLLQ
* @note Used for PLL48M1CLK selected for USB, RNG (48 MHz clock)
* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLQ_DIV_2
* @arg @ref LL_RCC_PLLQ_DIV_4
* @arg @ref LL_RCC_PLLQ_DIV_6
* @arg @ref LL_RCC_PLLQ_DIV_8
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
}
/**
* @brief Get Main PLL division factor for PLLR
* @note Used for PLLCLK (system clock)
* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLR_DIV_2
* @arg @ref LL_RCC_PLLR_DIV_4
* @arg @ref LL_RCC_PLLR_DIV_6
* @arg @ref LL_RCC_PLLR_DIV_8
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
}
/**
* @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_RCC_PLLM_DIV_1
* @arg @ref LL_RCC_PLLM_DIV_2
* @arg @ref LL_RCC_PLLM_DIV_3
* @arg @ref LL_RCC_PLLM_DIV_4
* @arg @ref LL_RCC_PLLM_DIV_5
* @arg @ref LL_RCC_PLLM_DIV_6
* @arg @ref LL_RCC_PLLM_DIV_7
* @arg @ref LL_RCC_PLLM_DIV_8
* @arg @ref LL_RCC_PLLM_DIV_9
* @arg @ref LL_RCC_PLLM_DIV_10
* @arg @ref LL_RCC_PLLM_DIV_11
* @arg @ref LL_RCC_PLLM_DIV_12
* @arg @ref LL_RCC_PLLM_DIV_13
* @arg @ref LL_RCC_PLLM_DIV_14
* @arg @ref LL_RCC_PLLM_DIV_15
* @arg @ref LL_RCC_PLLM_DIV_16
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
{
return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
}
/**
* @brief Enable PLL output mapped on ADC domain clock
* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_ADC
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_ADC(void)
{
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
}
/**
* @brief Disable PLL output mapped on ADC domain clock
* @note Cannot be disabled if the PLL clock is used as the system
* clock
* @note In order to save power, when the PLLCLK of the PLL is
* not used, should be 0
* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_ADC
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_ADC(void)
{
CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
}
/**
* @brief Check if PLL output mapped on ADC domain clock is enabled
* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_IsEnabledDomain_ADC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_ADC(void)
{
return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN) == (RCC_PLLCFGR_PLLPEN)) ? 1UL : 0UL);
}
/**
* @brief Enable PLL output mapped on 48MHz domain clock
* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
{
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
}
/**
* @brief Disable PLL output mapped on 48MHz domain clock
* @note Cannot be disabled if the PLL clock is used as the system
* clock
* @note In order to save power, when the PLLCLK of the PLL is
* not used, should be 0
* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
{
CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
}
/**
* @brief Check if PLL output mapped on 48MHz domain clock is enabled
* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_IsEnabledDomain_48M
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_48M(void)
{
return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN) == (RCC_PLLCFGR_PLLQEN)) ? 1UL : 0UL);
}
/**
* @brief Enable PLL output mapped on SYSCLK domain
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
{
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
}
/**
* @brief Disable PLL output mapped on SYSCLK domain
* @note Cannot be disabled if the PLL clock is used as the system
* clock
* @note In order to save power, when the PLLCLK of the PLL is
* not used, Main PLL should be 0
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
* @retval None
*/
__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
{
CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
}
/**
* @brief Check if PLL output mapped on SYSCLK domain clock is enabled
* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_IsEnabledDomain_SYS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_PLL_IsEnabledDomain_SYS(void)
{
return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN) == (RCC_PLLCFGR_PLLREN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Clear LSI ready interrupt flag
* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
}
/**
* @brief Clear LSE ready interrupt flag
* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
}
/**
* @brief Clear HSI ready interrupt flag
* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
}
/**
* @brief Clear HSE ready interrupt flag
* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
}
/**
* @brief Clear PLL ready interrupt flag
* @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
}
/**
* @brief Clear HSI48 ready interrupt flag
* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
{
SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
}
/**
* @brief Clear Clock security system interrupt flag
* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
{
SET_BIT(RCC->CICR, RCC_CICR_CSSC);
}
/**
* @brief Clear LSE Clock security system interrupt flag
* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
{
SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
}
/**
* @brief Check if LSI ready interrupt occurred or not
* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
}
/**
* @brief Check if LSE ready interrupt occurred or not
* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
}
/**
* @brief Check if HSI ready interrupt occurred or not
* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
}
/**
* @brief Check if HSE ready interrupt occurred or not
* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
}
/**
* @brief Check if PLL ready interrupt occurred or not
* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
}
/**
* @brief Check if HSI48 ready interrupt occurred or not
* @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
}
/**
* @brief Check if Clock security system interrupt occurred or not
* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL);
}
/**
* @brief Check if LSE Clock security system interrupt occurred or not
* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
{
return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Independent Watchdog reset is set or not.
* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Low Power reset is set or not.
* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Option byte reset is set or not.
* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Pin reset is set or not.
* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Software reset is set or not.
* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag Window Watchdog reset is set or not.
* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL);
}
/**
* @brief Check if RCC flag BOR reset is set or not.
* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
{
return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)) ? 1UL : 0UL);
}
/**
* @brief Set RMVF bit to clear the reset flags.
* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
* @retval None
*/
__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
{
SET_BIT(RCC->CSR, RCC_CSR_RMVF);
}
/**
* @}
*/
/** @defgroup RCC_LL_EF_IT_Management IT Management
* @{
*/
/**
* @brief Enable LSI ready interrupt
* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
}
/**
* @brief Enable LSE ready interrupt
* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
}
/**
* @brief Enable HSI ready interrupt
* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
}
/**
* @brief Enable HSE ready interrupt
* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
}
/**
* @brief Enable PLL ready interrupt
* @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
}
/**
* @brief Enable HSI48 ready interrupt
* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
{
SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
}
/**
* @brief Enable LSE clock security system interrupt
* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
{
SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
}
/**
* @brief Disable LSI ready interrupt
* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
}
/**
* @brief Disable LSE ready interrupt
* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
}
/**
* @brief Disable HSI ready interrupt
* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
}
/**
* @brief Disable HSE ready interrupt
* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
}
/**
* @brief Disable PLL ready interrupt
* @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
}
/**
* @brief Disable HSI48 ready interrupt
* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
}
/**
* @brief Disable LSE clock security system interrupt
* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
* @retval None
*/
__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
{
CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
}
/**
* @brief Checks if LSI ready interrupt source is enabled or disabled.
* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL);
}
/**
* @brief Checks if LSE ready interrupt source is enabled or disabled.
* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL);
}
/**
* @brief Checks if HSI ready interrupt source is enabled or disabled.
* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL);
}
/**
* @brief Checks if HSE ready interrupt source is enabled or disabled.
* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL);
}
/**
* @brief Checks if PLL ready interrupt source is enabled or disabled.
* @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL);
}
/**
* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE)) ? 1UL : 0UL);
}
/**
* @brief Checks if LSECSS interrupt source is enabled or disabled.
* @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
{
return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RCC_LL_EF_Init De-initialization function
* @{
*/
ErrorStatus LL_RCC_DeInit(void);
/**
* @}
*/
/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
* @{
*/
void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
#if defined(UART4)
uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
#endif /* UART4 */
uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
#if defined(FDCAN1)
uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
#endif /* FDCAN1 */
uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
#if defined(QUADSPI)
uint32_t LL_RCC_GetQUADSPIClockFreq(uint32_t QUADSPIxSource);
#endif /* QUADSPI */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_RCC_H */
| 112,763 | C | 36.600533 | 229 | 0.599106 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_opamp_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_opamp_ex.h
* @author MCD Application Team
* @brief Header file of OPAMP HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_OPAMP_EX_H
#define STM32G4xx_HAL_OPAMP_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup OPAMPEx OPAMPEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup OPAMPEx_Exported_Functions OPAMP Extended Exported Functions
* @{
*/
/** @addtogroup OPAMPEx_Exported_Functions_Group1 Extended Input and Output operation functions
* @{
*/
/* I/O operation functions *****************************************************/
#if defined(STM32G473xx) || defined(STM32G474xx) || defined(STM32G483xx) || defined(STM32G484xx)
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp4, OPAMP_HandleTypeDef *hopamp5, OPAMP_HandleTypeDef *hopamp6);
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
OPAMP_HandleTypeDef *hopamp3);
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2,
OPAMP_HandleTypeDef *hopamp3, OPAMP_HandleTypeDef *hopamp6);
#endif
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_OPAMP_EX_H */
| 2,750 | C | 30.988372 | 167 | 0.512 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_rtc.h | /**
******************************************************************************
* @file stm32g4xx_ll_rtc.h
* @author MCD Application Team
* @brief Header file of RTC LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_RTC_H
#define STM32G4xx_LL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined(RTC)
/** @defgroup RTC_LL RTC
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTC_LL_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
#define RTC_LL_INIT_MASK 0xFFFFFFFFU
#define RTC_LL_RSF_MASK 0xFFFFFF5FU
/* Write protection defines */
#define RTC_WRITE_PROTECTION_DISABLE (uint8_t)0xFF
#define RTC_WRITE_PROTECTION_ENABLE_1 (uint8_t)0xCA
#define RTC_WRITE_PROTECTION_ENABLE_2 (uint8_t)0x53
/* Defines used to combine date & time */
#define RTC_OFFSET_WEEKDAY 24U
#define RTC_OFFSET_DAY 16U
#define RTC_OFFSET_MONTH 8U
#define RTC_OFFSET_HOUR 16U
#define RTC_OFFSET_MINUTE 8U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_Private_Macros RTC Private Macros
* @{
*/
/**
* @}
*/
#endif /*USE_FULL_LL_DRIVER*/
#if !defined (UNUSED)
#define UNUSED(x) ((void)(x))
#endif
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure
* @{
*/
/**
* @brief RTC Init structures definition
*/
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hours Format.
This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetHourFormat(). */
uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetAsynchPrescaler(). */
uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF
This feature can be modified afterwards using unitary function
@ref LL_RTC_SetSynchPrescaler(). */
} LL_RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT
This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */
uint8_t Hours; /*!< Specifies the RTC Time Hours.
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.
This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59
This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59
This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */
} LL_RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_LL_EC_WEEKDAY
This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */
uint8_t Month; /*!< Specifies the RTC Date Month.
This parameter can be a value of @ref RTC_LL_EC_MONTH
This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */
uint8_t Day; /*!< Specifies the RTC Date Day.
This parameter must be a number between Min_Data = 1 and Max_Data = 31
This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99
This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */
} LL_RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.
This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A
or @ref LL_RTC_ALMB_SetMask() for ALARM B
*/
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay.
This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B
This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()
for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B
*/
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Day/WeekDay.
If AlarmDateWeekDaySel set to day, this parameter must be a number between Min_Data = 1 and Max_Data = 31.
This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()
for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.
If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.
This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()
for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.
*/
} LL_RTC_AlarmTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants
* @{
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_EC_FORMAT FORMAT
* @{
*/
#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */
#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay
* @{
*/
#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm A Date is selected */
#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /*!< Alarm A WeekDay is selected */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay
* @{
*/
#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE 0x00000000U /*!< Alarm B Date is selected */
#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL /*!< Alarm B WeekDay is selected */
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_RTC_ReadReg function
* @{
*/
#define LL_RTC_SCR_ITSF RTC_SCR_CITSF
#define LL_RTC_SCR_TSOVF RTC_SCR_CTSOVF
#define LL_RTC_SCR_TSF RTC_SCR_CTSF
#define LL_RTC_SCR_WUTF RTC_SCR_CWUTF
#define LL_RTC_SCR_ALRBF RTC_SCR_CALRBF
#define LL_RTC_CSR_ALRAF RTC_SCR_CALRAF
#define LL_RTC_ICSR_RECALPF RTC_ICSR_RECALPF
#define LL_RTC_ICSR_INITF RTC_ICSR_INITF
#define LL_RTC_ICSR_RSF RTC_ICSR_RSF
#define LL_RTC_ICSR_INITS RTC_ICSR_INITS
#define LL_RTC_ICSR_SHPF RTC_ICSR_SHPF
#define LL_RTC_ICSR_WUTWF RTC_ICSR_WUTWF
#define LL_RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF
#define LL_RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF
/**
* @}
*/
/** @defgroup RTC_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_RTC_ReadReg and LL_RTC_WriteReg functions
* @{
*/
#define LL_RTC_CR_TSIE RTC_CR_TSIE
#define LL_RTC_CR_WUTIE RTC_CR_WUTIE
#define LL_RTC_CR_ALRBIE RTC_CR_ALRBIE
#define LL_RTC_CR_ALRAIE RTC_CR_ALRAIE
/**
* @}
*/
/** @defgroup RTC_LL_EC_WEEKDAY WEEK DAY
* @{
*/
#define LL_RTC_WEEKDAY_MONDAY (uint8_t)0x01 /*!< Monday */
#define LL_RTC_WEEKDAY_TUESDAY (uint8_t)0x02 /*!< Tuesday */
#define LL_RTC_WEEKDAY_WEDNESDAY (uint8_t)0x03 /*!< Wednesday */
#define LL_RTC_WEEKDAY_THURSDAY (uint8_t)0x04 /*!< Thrusday */
#define LL_RTC_WEEKDAY_FRIDAY (uint8_t)0x05 /*!< Friday */
#define LL_RTC_WEEKDAY_SATURDAY (uint8_t)0x06 /*!< Saturday */
#define LL_RTC_WEEKDAY_SUNDAY (uint8_t)0x07 /*!< Sunday */
/**
* @}
*/
/** @defgroup RTC_LL_EC_MONTH MONTH
* @{
*/
#define LL_RTC_MONTH_JANUARY (uint8_t)0x01 /*!< January */
#define LL_RTC_MONTH_FEBRUARY (uint8_t)0x02 /*!< February */
#define LL_RTC_MONTH_MARCH (uint8_t)0x03 /*!< March */
#define LL_RTC_MONTH_APRIL (uint8_t)0x04 /*!< April */
#define LL_RTC_MONTH_MAY (uint8_t)0x05 /*!< May */
#define LL_RTC_MONTH_JUNE (uint8_t)0x06 /*!< June */
#define LL_RTC_MONTH_JULY (uint8_t)0x07 /*!< July */
#define LL_RTC_MONTH_AUGUST (uint8_t)0x08 /*!< August */
#define LL_RTC_MONTH_SEPTEMBER (uint8_t)0x09 /*!< September */
#define LL_RTC_MONTH_OCTOBER (uint8_t)0x10 /*!< October */
#define LL_RTC_MONTH_NOVEMBER (uint8_t)0x11 /*!< November */
#define LL_RTC_MONTH_DECEMBER (uint8_t)0x12 /*!< December */
/**
* @}
*/
/** @defgroup RTC_LL_EC_HOURFORMAT HOUR FORMAT
* @{
*/
#define LL_RTC_HOURFORMAT_24HOUR 0x00000000U /*!< 24 hour/day format */
#define LL_RTC_HOURFORMAT_AMPM RTC_CR_FMT /*!< AM/PM hour format */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALARMOUT ALARM OUTPUT
* @{
*/
#define LL_RTC_ALARMOUT_DISABLE 0x00000000U /*!< Output disabled */
#define LL_RTC_ALARMOUT_ALMA RTC_CR_OSEL_0 /*!< Alarm A output enabled */
#define LL_RTC_ALARMOUT_ALMB RTC_CR_OSEL_1 /*!< Alarm B output enabled */
#define LL_RTC_ALARMOUT_WAKEUP RTC_CR_OSEL /*!< Wakeup output enabled */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE ALARM OUTPUT TYPE
* @{
*/
#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */
#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */
/**
* @}
*/
/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN
* @{
*/
#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH 0x00000000U /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/
#define LL_RTC_OUTPUTPOLARITY_PIN_LOW RTC_CR_POL /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT
* @{
*/
#define LL_RTC_TIME_FORMAT_AM_OR_24 0x00000000U /*!< AM or 24-hour format */
#define LL_RTC_TIME_FORMAT_PM RTC_TR_PM /*!< PM */
/**
* @}
*/
/** @defgroup RTC_LL_EC_SHIFT_SECOND SHIFT SECOND
* @{
*/
#define LL_RTC_SHIFT_SECOND_DELAY 0x00000000U /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */
#define LL_RTC_SHIFT_SECOND_ADVANCE RTC_SHIFTR_ADD1S /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMA_MASK ALARMA MASK
* @{
*/
#define LL_RTC_ALMA_MASK_NONE 0x00000000U /*!< No masks applied on Alarm A*/
#define LL_RTC_ALMA_MASK_DATEWEEKDAY RTC_ALRMAR_MSK4 /*!< Date/day do not care in Alarm A comparison */
#define LL_RTC_ALMA_MASK_HOURS RTC_ALRMAR_MSK3 /*!< Hours do not care in Alarm A comparison */
#define LL_RTC_ALMA_MASK_MINUTES RTC_ALRMAR_MSK2 /*!< Minutes do not care in Alarm A comparison */
#define LL_RTC_ALMA_MASK_SECONDS RTC_ALRMAR_MSK1 /*!< Seconds do not care in Alarm A comparison */
#define LL_RTC_ALMA_MASK_ALL (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT ALARMA TIME FORMAT
* @{
*/
#define LL_RTC_ALMA_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
#define LL_RTC_ALMA_TIME_FORMAT_PM RTC_ALRMAR_PM /*!< PM */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK
* @{
*/
#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/
#define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */
#define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */
/**
* @}
*/
/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT ALARMB TIME FORMAT
* @{
*/
#define LL_RTC_ALMB_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
#define LL_RTC_ALMB_TIME_FORMAT_PM RTC_ALRMBR_PM /*!< PM */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE TIMESTAMP EDGE
* @{
*/
#define LL_RTC_TIMESTAMP_EDGE_RISING 0x00000000U /*!< RTC_TS input rising edge generates a time-stamp event */
#define LL_RTC_TIMESTAMP_EDGE_FALLING RTC_CR_TSEDGE /*!< RTC_TS input falling edge generates a time-stamp even */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TS_TIME_FORMAT TIMESTAMP TIME FORMAT
* @{
*/
#define LL_RTC_TS_TIME_FORMAT_AM 0x00000000U /*!< AM or 24-hour format */
#define LL_RTC_TS_TIME_FORMAT_PM RTC_TSTR_PM /*!< PM */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER TAMPER
* @{
*/
#define LL_RTC_TAMPER_1 TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */
#define LL_RTC_TAMPER_2 TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */
#if (RTC_TAMP_NB == 3)
#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */
#elif (RTC_TAMP_NB == 8)
#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */
#define LL_RTC_TAMPER_3 TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */
#define LL_RTC_TAMPER_4 TAMP_CR1_TAMP4E /*!< Tamper 4 input detection */
#define LL_RTC_TAMPER_5 TAMP_CR1_TAMP5E /*!< Tamper 5 input detection */
#define LL_RTC_TAMPER_6 TAMP_CR1_TAMP6E /*!< Tamper 6 input detection */
#define LL_RTC_TAMPER_7 TAMP_CR1_TAMP7E /*!< Tamper 7 input detection */
#define LL_RTC_TAMPER_8 TAMP_CR1_TAMP8E /*!< Tamper 8 input detection */
#else
#warning "RTC_TAMP_NB is not correct"
#endif /* (RTC_TAMP_NB) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK
* @{
*/
#define LL_RTC_TAMPER_MASK_TAMPER1 TAMP_CR2_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
#define LL_RTC_TAMPER_MASK_TAMPER2 TAMP_CR2_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
#if (RTC_TAMP_NB == 3)
#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
#elif (RTC_TAMP_NB == 8)
#define LL_RTC_TAMPER_MASK_TAMPER3 TAMP_CR2_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
#define LL_RTC_TAMPER_MASK_TAMPER4 TAMP_CR2_TAMP4MF /*!< Tamper 4 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
#define LL_RTC_TAMPER_MASK_TAMPER5 TAMP_CR2_TAMP5MF /*!< Tamper 5 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
#define LL_RTC_TAMPER_MASK_TAMPER6 TAMP_CR2_TAMP6MF /*!< Tamper 6 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */
#define LL_RTC_TAMPER_MASK_TAMPER7 TAMP_CR2_TAMP7MF /*!< Tamper 7 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
#define LL_RTC_TAMPER_MASK_TAMPER8 TAMP_CR2_TAMP8MF /*!< Tamper 8 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */
#else
#warning "RTC_TAMP_NB is not correct"
#endif /* (RTC_TAMP_NB) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE
* @{
*/
#define LL_RTC_TAMPER_NOERASE_TAMPER1 TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER2 TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */
#if (RTC_TAMP_NB == 3)
#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
#elif (RTC_TAMP_NB == 8)
#define LL_RTC_TAMPER_NOERASE_TAMPER3 TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER4 TAMP_CR2_TAMP4NOERASE /*!< Tamper 4 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER5 TAMP_CR2_TAMP5NOERASE /*!< Tamper 5 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER6 TAMP_CR2_TAMP6NOERASE /*!< Tamper 6 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER7 TAMP_CR2_TAMP7NOERASE /*!< Tamper 7 event does not erase the backup registers. */
#define LL_RTC_TAMPER_NOERASE_TAMPER8 TAMP_CR2_TAMP8NOERASE /*!< Tamper 8 event does not erase the backup registers. */
#else
#warning "RTC_TAMP_NB is not correct"
#endif /* (RTC_TAMP_NB) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION
* @{
*/
#define LL_RTC_TAMPER_DURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle */
#define LL_RTC_TAMPER_DURATION_2RTCCLK TAMP_FLTCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */
#define LL_RTC_TAMPER_DURATION_4RTCCLK TAMP_FLTCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */
#define LL_RTC_TAMPER_DURATION_8RTCCLK TAMP_FLTCR_TAMPPRCH /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER
* @{
*/
#define LL_RTC_TAMPER_FILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */
#define LL_RTC_TAMPER_FILTER_2SAMPLE TAMP_FLTCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */
#define LL_RTC_TAMPER_FILTER_4SAMPLE TAMP_FLTCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */
#define LL_RTC_TAMPER_FILTER_8SAMPLE TAMP_FLTCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active level. */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER
* @{
*/
#define LL_RTC_TAMPER_SAMPLFREQDIV_32768 0x00000000U /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 32768 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_16384 TAMP_FLTCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 16384 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_8192 TAMP_FLTCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 8192 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_4096 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 4096 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_2048 TAMP_FLTCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 2048 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_1024 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 1024 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_512 (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */
#define LL_RTC_TAMPER_SAMPLFREQDIV_256 TAMP_FLTCR_TAMPFREQ /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */
/**
* @}
*/
/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL
* @{
*/
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#if (RTC_TAMP_NB == 3)
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#elif (RTC_TAMP_NB == 8)
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3 TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP4 TAMP_CR2_TAMP4TRG /*!< Tamper 4 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP5 TAMP_CR2_TAMP5TRG /*!< Tamper 5 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP6 TAMP_CR2_TAMP6TRG /*!< Tamper 6 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP7 TAMP_CR2_TAMP7TRG /*!< Tamper 7 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP8 TAMP_CR2_TAMP8TRG /*!< Tamper 8 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */
#endif /* (RTC_TAMP_NB) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_INTERNAL INTERNAL TAMPER
* @{
*/
#define LL_RTC_TAMPER_ITAMP1 TAMP_CR1_ITAMP1E /*!< Internal tamper 1: RTC supply voltage monitoring */
#if defined (RTC_TAMP_INT_2_SUPPORT)
#define LL_RTC_TAMPER_ITAMP2 TAMP_CR1_ITAMP2E /*!< Internal tamper 2: temperature monitoring */
#endif /* RTC_TAMP_INT_2_SUPPORT */
#define LL_RTC_TAMPER_ITAMP3 TAMP_CR1_ITAMP3E /*!< Internal tamper 3: LSE monitoring */
#define LL_RTC_TAMPER_ITAMP4 TAMP_CR1_ITAMP4E /*!< Internal tamper 4: HSE monitoring */
#define LL_RTC_TAMPER_ITAMP5 TAMP_CR1_ITAMP5E /*!< Internal tamper 5: RTC calendar overflow */
#if defined (RTC_TAMP_INT_6_SUPPORT)
#define LL_RTC_TAMPER_ITAMP6 TAMP_CR1_ITAMP6E /*!< Internal tamper 6: Test mode entry */
#endif /* RTC_TAMP_INT_6_SUPPORT */
#if defined (RTC_TAMP_INT_7_SUPPORT)
#define LL_RTC_TAMPER_ITAMP7 TAMP_CR1_ITAMP7E /*!< Internal tamper 7: Readout protection level decrease */
#endif /* RTC_TAMP_INT_7_SUPPORT */
#if defined (RTC_TAMP_INT_8_SUPPORT)
#define LL_RTC_TAMPER_ITAMP8 TAMP_CR1_ITAMP8E /*!< Internal tamper 8: Monotonic counter overflow */
#endif /* RTC_TAMP_INT_8_SUPPORT */
/**
* @}
*/
/** @defgroup RTC_LL_EC_BKP BACKUP
* @{
*/
#define LL_RTC_BKP_NUMBER RTC_BACKUP_NB
#if (LL_RTC_BKP_NUMBER == 5)
#define LL_RTC_BKP_DR0 0x00U
#define LL_RTC_BKP_DR1 0x01U
#define LL_RTC_BKP_DR2 0x02U
#define LL_RTC_BKP_DR3 0x03U
#define LL_RTC_BKP_DR4 0x04U
#elif (LL_RTC_BKP_NUMBER == 16)
#define LL_RTC_BKP_DR0 0x00U
#define LL_RTC_BKP_DR1 0x01U
#define LL_RTC_BKP_DR2 0x02U
#define LL_RTC_BKP_DR3 0x03U
#define LL_RTC_BKP_DR4 0x04U
#define LL_RTC_BKP_DR5 0x05U
#define LL_RTC_BKP_DR6 0x06U
#define LL_RTC_BKP_DR7 0x07U
#define LL_RTC_BKP_DR8 0x08U
#define LL_RTC_BKP_DR9 0x09U
#define LL_RTC_BKP_DR10 0x0AU
#define LL_RTC_BKP_DR11 0x0BU
#define LL_RTC_BKP_DR12 0x0CU
#define LL_RTC_BKP_DR13 0x0DU
#define LL_RTC_BKP_DR14 0x0EU
#define LL_RTC_BKP_DR15 0x0FU
#elif (LL_RTC_BKP_NUMBER == 32)
#define LL_RTC_BKP_DR0 0x00U
#define LL_RTC_BKP_DR1 0x01U
#define LL_RTC_BKP_DR2 0x02U
#define LL_RTC_BKP_DR3 0x03U
#define LL_RTC_BKP_DR4 0x04U
#define LL_RTC_BKP_DR5 0x05U
#define LL_RTC_BKP_DR6 0x06U
#define LL_RTC_BKP_DR7 0x07U
#define LL_RTC_BKP_DR8 0x08U
#define LL_RTC_BKP_DR9 0x09U
#define LL_RTC_BKP_DR10 0x0AU
#define LL_RTC_BKP_DR11 0x0BU
#define LL_RTC_BKP_DR12 0x0CU
#define LL_RTC_BKP_DR13 0x0DU
#define LL_RTC_BKP_DR14 0x0EU
#define LL_RTC_BKP_DR15 0x0FU
#define LL_RTC_BKP_DR16 0x10U
#define LL_RTC_BKP_DR17 0x11U
#define LL_RTC_BKP_DR18 0x12U
#define LL_RTC_BKP_DR19 0x13U
#define LL_RTC_BKP_DR20 0x14U
#define LL_RTC_BKP_DR21 0x15U
#define LL_RTC_BKP_DR22 0x16U
#define LL_RTC_BKP_DR23 0x17U
#define LL_RTC_BKP_DR24 0x18U
#define LL_RTC_BKP_DR25 0x19U
#define LL_RTC_BKP_DR26 0x1AU
#define LL_RTC_BKP_DR27 0x1BU
#define LL_RTC_BKP_DR28 0x1CU
#define LL_RTC_BKP_DR29 0x1DU
#define LL_RTC_BKP_DR30 0x1EU
#define LL_RTC_BKP_DR31 0x1FU
#else
#error "no LL Backup Registers Definition"
#endif /* (LL_RTC_BKP_NUMBER) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV WAKEUP CLOCK DIV
* @{
*/
#define LL_RTC_WAKEUPCLOCK_DIV_16 0x00000000U /*!< RTC/16 clock is selected */
#define LL_RTC_WAKEUPCLOCK_DIV_8 RTC_CR_WUCKSEL_0 /*!< RTC/8 clock is selected */
#define LL_RTC_WAKEUPCLOCK_DIV_4 RTC_CR_WUCKSEL_1 /*!< RTC/4 clock is selected */
#define LL_RTC_WAKEUPCLOCK_DIV_2 (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */
#define LL_RTC_WAKEUPCLOCK_CKSPRE RTC_CR_WUCKSEL_2 /*!< ck_spre (usually 1 Hz) clock is selected */
#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/
/**
* @}
*/
/** @defgroup RTC_LL_EC_CALIB_OUTPUT Calibration output
* @{
*/
#define LL_RTC_CALIB_OUTPUT_NONE 0x00000000U /*!< Calibration output disabled */
#define LL_RTC_CALIB_OUTPUT_1HZ (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */
#define LL_RTC_CALIB_OUTPUT_512HZ RTC_CR_COE /*!< Calibration output is 512 Hz */
/**
* @}
*/
/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion
* @{
*/
#define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */
#define LL_RTC_CALIB_INSERTPULSE_SET RTC_CALR_CALP /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */
/**
* @}
*/
/** @defgroup RTC_LL_EC_CALIB_PERIOD Calibration period
* @{
*/
#define LL_RTC_CALIB_PERIOD_32SEC 0x00000000U /*!< Use a 32-second calibration cycle period */
#define LL_RTC_CALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< Use a 16-second calibration cycle period */
#define LL_RTC_CALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< Use a 8-second calibration cycle period */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup RTC_LL_EM_Convert Convert helper Macros
* @{
*/
/**
* @brief Helper macro to convert a value from 2 digit decimal format to BCD format
* @param __VALUE__ Byte to be converted
* @retval Converted byte
*/
#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))
/**
* @brief Helper macro to convert a value from BCD format to 2 digit decimal format
* @param __VALUE__ BCD value to be converted
* @retval Converted byte
*/
#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU)))
/**
* @}
*/
/** @defgroup RTC_LL_EM_Date Date helper Macros
* @{
*/
/**
* @brief Helper macro to retrieve weekday.
* @param __RTC_DATE__ Date returned by @ref LL_RTC_DATE_Get function.
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)
/**
* @brief Helper macro to retrieve Year in BCD format
* @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
* @retval Year in BCD format (0x00 . . . 0x99)
*/
#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)
/**
* @brief Helper macro to retrieve Month in BCD format
* @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
*/
#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)
/**
* @brief Helper macro to retrieve Day in BCD format
* @param __RTC_DATE__ Value returned by @ref LL_RTC_DATE_Get
* @retval Day in BCD format (0x01 . . . 0x31)
*/
#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)
/**
* @}
*/
/** @defgroup RTC_LL_EM_Time Time helper Macros
* @{
*/
/**
* @brief Helper macro to retrieve hour in BCD format
* @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
* @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)
*/
#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)
/**
* @brief Helper macro to retrieve minute in BCD format
* @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
* @retval Minutes in BCD format (0x00. . .0x59)
*/
#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)
/**
* @brief Helper macro to retrieve second in BCD format
* @param __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function
* @retval Seconds in format (0x00. . .0x59)
*/
#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Set Hours format (24 hour/day or AM/PM hour format)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @rmtoll RTC_CR FMT LL_RTC_SetHourFormat
* @param RTCx RTC Instance
* @param HourFormat This parameter can be one of the following values:
* @arg @ref LL_RTC_HOURFORMAT_24HOUR
* @arg @ref LL_RTC_HOURFORMAT_AMPM
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)
{
MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);
}
/**
* @brief Get Hours format (24 hour/day or AM/PM hour format)
* @rmtoll RTC_CR FMT LL_RTC_GetHourFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_HOURFORMAT_24HOUR
* @arg @ref LL_RTC_HOURFORMAT_AMPM
*/
__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));
}
/**
* @brief Select the flag to be routed to RTC_ALARM output
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR OSEL LL_RTC_SetAlarmOutEvent
* @param RTCx RTC Instance
* @param AlarmOutput This parameter can be one of the following values:
* @arg @ref LL_RTC_ALARMOUT_DISABLE
* @arg @ref LL_RTC_ALARMOUT_ALMA
* @arg @ref LL_RTC_ALARMOUT_ALMB
* @arg @ref LL_RTC_ALARMOUT_WAKEUP
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)
{
MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);
}
/**
* @brief Get the flag to be routed to RTC_ALARM output
* @rmtoll RTC_CR OSEL LL_RTC_GetAlarmOutEvent
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_ALARMOUT_DISABLE
* @arg @ref LL_RTC_ALARMOUT_ALMA
* @arg @ref LL_RTC_ALARMOUT_ALMB
* @arg @ref LL_RTC_ALARMOUT_WAKEUP
*/
__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));
}
/**
* @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output)
* @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
* @param RTCx RTC Instance
* @param Output This parameter can be one of the following values:
* @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
* @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)
{
MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);
}
/**
* @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output)
* @rmtoll RTC_CR TAMPALRM_TYPE LL_RTC_SetAlarmOutputType
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN
* @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL
*/
__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));
}
/**
* @brief Enable initialization mode
* @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR)
* and prescaler register (RTC_PRER).
* Counters are stopped and start counting from the new value when INIT is reset.
* @rmtoll RTC_ICSR INIT LL_RTC_EnableInitMode
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)
{
/* Set the Initialization mode */
WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);
}
/**
* @brief Disable initialization mode (Free running mode)
* @rmtoll RTC_ICSR INIT LL_RTC_DisableInitMode
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)
{
/* Exit Initialization mode */
WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);
}
/**
* @brief Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR POL LL_RTC_SetOutputPolarity
* @param RTCx RTC Instance
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
* @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)
{
MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);
}
/**
* @brief Get Output polarity
* @rmtoll RTC_CR POL LL_RTC_GetOutputPolarity
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH
* @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW
*/
__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));
}
/**
* @brief Enable Bypass the shadow registers
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR BYPSHAD LL_RTC_EnableShadowRegBypass
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);
}
/**
* @brief Disable Bypass the shadow registers
* @rmtoll RTC_CR BYPSHAD LL_RTC_DisableShadowRegBypass
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);
}
/**
* @brief Check if Shadow registers bypass is enabled or not.
* @rmtoll RTC_CR BYPSHAD LL_RTC_IsShadowRegBypassEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U);
}
/**
* @brief Enable RTC_REFIN reference clock detection (50 or 60 Hz)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @rmtoll RTC_CR REFCKON LL_RTC_EnableRefClock
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_REFCKON);
}
/**
* @brief Disable RTC_REFIN reference clock detection (50 or 60 Hz)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @rmtoll RTC_CR REFCKON LL_RTC_DisableRefClock
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);
}
/**
* @brief Set Asynchronous prescaler factor
* @rmtoll RTC_PRER PREDIV_A LL_RTC_SetAsynchPrescaler
* @param RTCx RTC Instance
* @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)
{
MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);
}
/**
* @brief Set Synchronous prescaler factor
* @rmtoll RTC_PRER PREDIV_S LL_RTC_SetSynchPrescaler
* @param RTCx RTC Instance
* @param SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)
{
MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);
}
/**
* @brief Get Asynchronous prescaler factor
* @rmtoll RTC_PRER PREDIV_A LL_RTC_GetAsynchPrescaler
* @param RTCx RTC Instance
* @retval Value between Min_Data = 0 and Max_Data = 0x7F
*/
__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);
}
/**
* @brief Get Synchronous prescaler factor
* @rmtoll RTC_PRER PREDIV_S LL_RTC_GetSynchPrescaler
* @param RTCx RTC Instance
* @retval Value between Min_Data = 0 and Max_Data = 0x7FFF
*/
__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));
}
/**
* @brief Enable the write protection for RTC registers.
* @rmtoll RTC_WPR KEY LL_RTC_EnableWriteProtection
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);
}
/**
* @brief Disable the write protection for RTC registers.
* @rmtoll RTC_WPR KEY LL_RTC_DisableWriteProtection
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);
WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);
}
/**
* @brief Enable tamper output.
* @note When the tamper output is enabled, all external and internal tamper flags
* are ORed and routed to the TAMPALRM output.
* @rmtoll RTC_CR TAMPOE LL_RTC_EnableTamperOutput
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TAMPOE);
}
/**
* @brief Disable tamper output.
* @rmtoll RTC_CR TAMPOE LL_RTC_DisableTamperOutput
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);
}
/**
* @brief Check if tamper output is enabled or not.
* @rmtoll RTC_CR TAMPOE LL_RTC_IsTamperOutputEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U);
}
/**
* @brief Enable internal pull-up in output mode.
* @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
}
/**
* @brief Disable internal pull-up in output mode.
* @rmtoll RTC_CR TAMPALRM_PU LL_RTC_EnableAlarmPullUp
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);
}
/**
* @brief Check if internal pull-up in output mode is enabled or not.
* @rmtoll RTC_CR TAMPALRM_PU LL_RTC_IsAlarmPullUpEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U);
}
/**
* @brief Enable RTC_OUT2 output
* @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)
* and COE (@ref LL_RTC_CAL_SetOutputFreq) settings.
* @note RTC_OUT2 is not available ins VBAT mode.
* @rmtoll RTC_CR OUT2EN LL_RTC_EnableOutput2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_OUT2EN);
}
/**
* @brief Disable RTC_OUT2 output
* @rmtoll RTC_CR OUT2EN LL_RTC_DisableOutput2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);
}
/**
* @brief Check if RTC_OUT2 output is enabled or not.
* @rmtoll RTC_CR OUT2EN LL_RTC_IsOutput2Enabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Time Time
* @{
*/
/**
* @brief Set time format (AM/24-hour or PM notation)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @rmtoll RTC_TR PM LL_RTC_TIME_SetFormat
* @param RTCx RTC Instance
* @param TimeFormat This parameter can be one of the following values:
* @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
* @arg @ref LL_RTC_TIME_FORMAT_PM
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
{
MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);
}
/**
* @brief Get time format (AM or PM notation)
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @rmtoll RTC_TR PM LL_RTC_TIME_GetFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
* @arg @ref LL_RTC_TIME_FORMAT_PM
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));
}
/**
* @brief Set Hours in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format
* @rmtoll RTC_TR HT LL_RTC_TIME_SetHour\n
* RTC_TR HU LL_RTC_TIME_SetHour
* @param RTCx RTC Instance
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
{
MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));
}
/**
* @brief Get Hours in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to
* Binary format
* @rmtoll RTC_TR HT LL_RTC_TIME_GetHour\n
* RTC_TR HU LL_RTC_TIME_GetHour
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);
}
/**
* @brief Set Minutes in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
* @rmtoll RTC_TR MNT LL_RTC_TIME_SetMinute\n
* RTC_TR MNU LL_RTC_TIME_SetMinute
* @param RTCx RTC Instance
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
{
MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),
(((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));
}
/**
* @brief Get Minutes in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD
* to Binary format
* @rmtoll RTC_TR MNT LL_RTC_TIME_GetMinute\n
* RTC_TR MNU LL_RTC_TIME_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);
}
/**
* @brief Set Seconds in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
* @rmtoll RTC_TR ST LL_RTC_TIME_SetSecond\n
* RTC_TR SU LL_RTC_TIME_SetSecond
* @param RTCx RTC Instance
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
{
MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),
(((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));
}
/**
* @brief Get Seconds in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD
* to Binary format
* @rmtoll RTC_TR ST LL_RTC_TIME_GetSecond\n
* RTC_TR SU LL_RTC_TIME_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);
}
/**
* @brief Set time (hour, minute and second) in BCD format
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)
* @note TimeFormat and Hours should follow the same format
* @rmtoll RTC_TR PM LL_RTC_TIME_Config\n
* RTC_TR HT LL_RTC_TIME_Config\n
* RTC_TR HU LL_RTC_TIME_Config\n
* RTC_TR MNT LL_RTC_TIME_Config\n
* RTC_TR MNU LL_RTC_TIME_Config\n
* RTC_TR ST LL_RTC_TIME_Config\n
* RTC_TR SU LL_RTC_TIME_Config
* @param RTCx RTC Instance
* @param Format12_24 This parameter can be one of the following values:
* @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24
* @arg @ref LL_RTC_TIME_FORMAT_PM
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
uint32_t Seconds)
{
uint32_t temp;
temp = Format12_24 | \
(((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));
MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);
}
/**
* @brief Get time (hour, minute and second) in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar
* shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).
* @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
* are available to get independently each parameter.
* @rmtoll RTC_TR HT LL_RTC_TIME_Get\n
* RTC_TR HU LL_RTC_TIME_Get\n
* RTC_TR MNT LL_RTC_TIME_Get\n
* RTC_TR MNU LL_RTC_TIME_Get\n
* RTC_TR ST LL_RTC_TIME_Get\n
* RTC_TR SU LL_RTC_TIME_Get
* @param RTCx RTC Instance
* @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)
{
uint32_t temp;
temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));
return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \
(((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \
((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));
}
/**
* @brief Memorize whether the daylight saving time change has been performed
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR BKP LL_RTC_TIME_EnableDayLightStore
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_BKP);
}
/**
* @brief Disable memorization whether the daylight saving time change has been performed.
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR BKP LL_RTC_TIME_DisableDayLightStore
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_BKP);
}
/**
* @brief Check if RTC Day Light Saving stored operation has been enabled or not
* @rmtoll RTC_CR BKP LL_RTC_TIME_IsDayLightStoreEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U);
}
/**
* @brief Subtract 1 hour (winter time change)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR SUB1H LL_RTC_TIME_DecHour
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_SUB1H);
}
/**
* @brief Add 1 hour (summer time change)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ADD1H LL_RTC_TIME_IncHour
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ADD1H);
}
/**
* @brief Get Sub second value in the synchronous prescaler counter.
* @note You can use both SubSeconds value and SecondFraction (PREDIV_S through
* LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar
* SubSeconds value in second fraction ratio with time unit following
* generic formula:
* ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit
* This conversion can be performed only if no shift operation is pending
* (ie. SHFP=0) when PREDIV_S >= SS.
* @rmtoll RTC_SSR SS LL_RTC_TIME_GetSubSecond
* @param RTCx RTC Instance
* @retval Sub second value (number between 0 and 65535)
*/
__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));
}
/**
* @brief Synchronize to a remote clock with a high degree of precision.
* @note This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note When REFCKON is set, firmware must not write to Shift control register.
* @rmtoll RTC_SHIFTR ADD1S LL_RTC_TIME_Synchronize\n
* RTC_SHIFTR SUBFS LL_RTC_TIME_Synchronize
* @param RTCx RTC Instance
* @param ShiftSecond This parameter can be one of the following values:
* @arg @ref LL_RTC_SHIFT_SECOND_DELAY
* @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE
* @param Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)
* @retval None
*/
__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)
{
WRITE_REG(RTCx->SHIFTR, (ShiftSecond | Fraction));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Date Date
* @{
*/
/**
* @brief Set Year in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format
* @rmtoll RTC_DR YT LL_RTC_DATE_SetYear\n
* RTC_DR YU LL_RTC_DATE_SetYear
* @param RTCx RTC Instance
* @param Year Value between Min_Data=0x00 and Max_Data=0x99
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)
{
MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));
}
/**
* @brief Get Year in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format
* @rmtoll RTC_DR YT LL_RTC_DATE_GetYear\n
* RTC_DR YU LL_RTC_DATE_GetYear
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x99
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);
}
/**
* @brief Set Week day
* @rmtoll RTC_DR WDU LL_RTC_DATE_SetWeekDay
* @param RTCx RTC Instance
* @param WeekDay This parameter can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
{
MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);
}
/**
* @brief Get Week day
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @rmtoll RTC_DR WDU LL_RTC_DATE_GetWeekDay
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);
}
/**
* @brief Set Month in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format
* @rmtoll RTC_DR MT LL_RTC_DATE_SetMonth\n
* RTC_DR MU LL_RTC_DATE_SetMonth
* @param RTCx RTC Instance
* @param Month This parameter can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)
{
MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),
(((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));
}
/**
* @brief Get Month in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
* @rmtoll RTC_DR MT LL_RTC_DATE_GetMonth\n
* RTC_DR MU LL_RTC_DATE_GetMonth
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);
}
/**
* @brief Set Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
* @rmtoll RTC_DR DT LL_RTC_DATE_SetDay\n
* RTC_DR DU LL_RTC_DATE_SetDay
* @param RTCx RTC Instance
* @param Day Value between Min_Data=0x01 and Max_Data=0x31
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
{
MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),
(((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));
}
/**
* @brief Get Day in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_DR DT LL_RTC_DATE_GetDay\n
* RTC_DR DU LL_RTC_DATE_GetDay
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x31
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);
}
/**
* @brief Set date (WeekDay, Day, Month and Year) in BCD format
* @rmtoll RTC_DR WDU LL_RTC_DATE_Config\n
* RTC_DR MT LL_RTC_DATE_Config\n
* RTC_DR MU LL_RTC_DATE_Config\n
* RTC_DR DT LL_RTC_DATE_Config\n
* RTC_DR DU LL_RTC_DATE_Config\n
* RTC_DR YT LL_RTC_DATE_Config\n
* RTC_DR YU LL_RTC_DATE_Config
* @param RTCx RTC Instance
* @param WeekDay This parameter can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
* @param Day Value between Min_Data=0x01 and Max_Data=0x31
* @param Month This parameter can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
* @param Year Value between Min_Data=0x00 and Max_Data=0x99
* @retval None
*/
__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month,
uint32_t Year)
{
uint32_t temp;
temp = (WeekDay << RTC_DR_WDU_Pos) | \
(((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \
(((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \
(((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));
MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);
}
/**
* @brief Get date (WeekDay, Day, Month and Year) in BCD format
* @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set
* before reading this bit
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,
* and __LL_RTC_GET_DAY are available to get independently each parameter.
* @rmtoll RTC_DR WDU LL_RTC_DATE_Get\n
* RTC_DR MT LL_RTC_DATE_Get\n
* RTC_DR MU LL_RTC_DATE_Get\n
* RTC_DR DT LL_RTC_DATE_Get\n
* RTC_DR DU LL_RTC_DATE_Get\n
* RTC_DR YT LL_RTC_DATE_Get\n
* RTC_DR YU LL_RTC_DATE_Get
* @param RTCx RTC Instance
* @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).
*/
__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)
{
uint32_t temp;
temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));
return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \
(((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \
(((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \
((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_ALARMA ALARMA
* @{
*/
/**
* @brief Enable Alarm A
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ALRAE);
}
/**
* @brief Disable Alarm A
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRAE LL_RTC_ALMA_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);
}
/**
* @brief Specify the Alarm A masks.
* @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_SetMask\n
* RTC_ALRMAR MSK3 LL_RTC_ALMA_SetMask\n
* RTC_ALRMAR MSK2 LL_RTC_ALMA_SetMask\n
* RTC_ALRMAR MSK1 LL_RTC_ALMA_SetMask
* @param RTCx RTC Instance
* @param Mask This parameter can be a combination of the following values:
* @arg @ref LL_RTC_ALMA_MASK_NONE
* @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
* @arg @ref LL_RTC_ALMA_MASK_HOURS
* @arg @ref LL_RTC_ALMA_MASK_MINUTES
* @arg @ref LL_RTC_ALMA_MASK_SECONDS
* @arg @ref LL_RTC_ALMA_MASK_ALL
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);
}
/**
* @brief Get the Alarm A masks.
* @rmtoll RTC_ALRMAR MSK4 LL_RTC_ALMA_GetMask\n
* RTC_ALRMAR MSK3 LL_RTC_ALMA_GetMask\n
* RTC_ALRMAR MSK2 LL_RTC_ALMA_GetMask\n
* RTC_ALRMAR MSK1 LL_RTC_ALMA_GetMask
* @param RTCx RTC Instance
* @retval Returned value can be can be a combination of the following values:
* @arg @ref LL_RTC_ALMA_MASK_NONE
* @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY
* @arg @ref LL_RTC_ALMA_MASK_HOURS
* @arg @ref LL_RTC_ALMA_MASK_MINUTES
* @arg @ref LL_RTC_ALMA_MASK_SECONDS
* @arg @ref LL_RTC_ALMA_MASK_ALL
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));
}
/**
* @brief Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
* @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_EnableWeekday
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
}
/**
* @brief Disable AlarmA Week day selection (DU[3:0] represents the date )
* @rmtoll RTC_ALRMAR WDSEL LL_RTC_ALMA_DisableWeekday
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);
}
/**
* @brief Set ALARM A Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
* @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_SetDay\n
* RTC_ALRMAR DU LL_RTC_ALMA_SetDay
* @param RTCx RTC Instance
* @param Day Value between Min_Data=0x01 and Max_Data=0x31
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
{
MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),
(((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));
}
/**
* @brief Get ALARM A Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_ALRMAR DT LL_RTC_ALMA_GetDay\n
* RTC_ALRMAR DU LL_RTC_ALMA_GetDay
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x31
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);
}
/**
* @brief Set ALARM A Weekday
* @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_SetWeekDay
* @param RTCx RTC Instance
* @param WeekDay This parameter can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
{
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);
}
/**
* @brief Get ALARM A Weekday
* @rmtoll RTC_ALRMAR DU LL_RTC_ALMA_GetWeekDay
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);
}
/**
* @brief Set Alarm A time format (AM/24-hour or PM notation)
* @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_SetTimeFormat
* @param RTCx RTC Instance
* @param TimeFormat This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
{
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);
}
/**
* @brief Get Alarm A time format (AM or PM notation)
* @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_GetTimeFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));
}
/**
* @brief Set ALARM A Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
* @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_SetHour\n
* RTC_ALRMAR HU LL_RTC_ALMA_SetHour
* @param RTCx RTC Instance
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
{
MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),
(((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));
}
/**
* @brief Get ALARM A Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
* @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetHour\n
* RTC_ALRMAR HU LL_RTC_ALMA_GetHour
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);
}
/**
* @brief Set ALARM A Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
* @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_SetMinute\n
* RTC_ALRMAR MNU LL_RTC_ALMA_SetMinute
* @param RTCx RTC Instance
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
{
MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));
}
/**
* @brief Get ALARM A Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
* @rmtoll RTC_ALRMAR MNT LL_RTC_ALMA_GetMinute\n
* RTC_ALRMAR MNU LL_RTC_ALMA_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);
}
/**
* @brief Set ALARM A Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
* @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_SetSecond\n
* RTC_ALRMAR SU LL_RTC_ALMA_SetSecond
* @param RTCx RTC Instance
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
{
MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),
(((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));
}
/**
* @brief Get ALARM A Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
* @rmtoll RTC_ALRMAR ST LL_RTC_ALMA_GetSecond\n
* RTC_ALRMAR SU LL_RTC_ALMA_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);
}
/**
* @brief Set Alarm A Time (hour, minute and second) in BCD format
* @rmtoll RTC_ALRMAR PM LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR HT LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR HU LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR MNT LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR MNU LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR ST LL_RTC_ALMA_ConfigTime\n
* RTC_ALRMAR SU LL_RTC_ALMA_ConfigTime
* @param RTCx RTC Instance
* @param Format12_24 This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
uint32_t Seconds)
{
uint32_t temp;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));
MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST
| RTC_ALRMAR_SU, temp);
}
/**
* @brief Get Alarm B Time (hour, minute and second) in BCD format
* @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
* are available to get independently each parameter.
* @rmtoll RTC_ALRMAR HT LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR HU LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR MNT LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR MNU LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR ST LL_RTC_ALMA_GetTime\n
* RTC_ALRMAR SU LL_RTC_ALMA_GetTime
* @param RTCx RTC Instance
* @retval Combination of hours, minutes and seconds.
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)
{
return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));
}
/**
* @brief Set Alarm A Mask the most-significant bits starting at this bit
* @note This register can be written only when ALRAE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask
* @param RTCx RTC Instance
* @param Mask Value between Min_Data=0x00 and Max_Data=0xF
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);
}
/**
* @brief Get Alarm A Mask the most-significant bits starting at this bit
* @rmtoll RTC_ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);
}
/**
* @brief Set Alarm A Sub seconds value
* @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_SetSubSecond
* @param RTCx RTC Instance
* @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
{
MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);
}
/**
* @brief Get Alarm A Sub seconds value
* @rmtoll RCT_ALRMASSR SS LL_RTC_ALMA_GetSubSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
*/
__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_ALARMB ALARMB
* @{
*/
/**
* @brief Enable Alarm B
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ALRBE);
}
/**
* @brief Disable Alarm B
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRBE LL_RTC_ALMB_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);
}
/**
* @brief Specify the Alarm B masks.
* @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_SetMask\n
* RTC_ALRMBR MSK3 LL_RTC_ALMB_SetMask\n
* RTC_ALRMBR MSK2 LL_RTC_ALMB_SetMask\n
* RTC_ALRMBR MSK1 LL_RTC_ALMB_SetMask
* @param RTCx RTC Instance
* @param Mask This parameter can be a combination of the following values:
* @arg @ref LL_RTC_ALMB_MASK_NONE
* @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
* @arg @ref LL_RTC_ALMB_MASK_HOURS
* @arg @ref LL_RTC_ALMB_MASK_MINUTES
* @arg @ref LL_RTC_ALMB_MASK_SECONDS
* @arg @ref LL_RTC_ALMB_MASK_ALL
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);
}
/**
* @brief Get the Alarm B masks.
* @rmtoll RTC_ALRMBR MSK4 LL_RTC_ALMB_GetMask\n
* RTC_ALRMBR MSK3 LL_RTC_ALMB_GetMask\n
* RTC_ALRMBR MSK2 LL_RTC_ALMB_GetMask\n
* RTC_ALRMBR MSK1 LL_RTC_ALMB_GetMask
* @param RTCx RTC Instance
* @retval Returned value can be can be a combination of the following values:
* @arg @ref LL_RTC_ALMB_MASK_NONE
* @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY
* @arg @ref LL_RTC_ALMB_MASK_HOURS
* @arg @ref LL_RTC_ALMB_MASK_MINUTES
* @arg @ref LL_RTC_ALMB_MASK_SECONDS
* @arg @ref LL_RTC_ALMB_MASK_ALL
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));
}
/**
* @brief Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)
* @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_EnableWeekday
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
}
/**
* @brief Disable AlarmB Week day selection (DU[3:0] represents the date )
* @rmtoll RTC_ALRMBR WDSEL LL_RTC_ALMB_DisableWeekday
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);
}
/**
* @brief Set ALARM B Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format
* @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_SetDay\n
* RTC_ALRMBR DU LL_RTC_ALMB_SetDay
* @param RTCx RTC Instance
* @param Day Value between Min_Data=0x01 and Max_Data=0x31
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)
{
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),
(((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));
}
/**
* @brief Get ALARM B Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_ALRMBR DT LL_RTC_ALMB_GetDay\n
* RTC_ALRMBR DU LL_RTC_ALMB_GetDay
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x31
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);
}
/**
* @brief Set ALARM B Weekday
* @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_SetWeekDay
* @param RTCx RTC Instance
* @param WeekDay This parameter can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)
{
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);
}
/**
* @brief Get ALARM B Weekday
* @rmtoll RTC_ALRMBR DU LL_RTC_ALMB_GetWeekDay
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);
}
/**
* @brief Set ALARM B time format (AM/24-hour or PM notation)
* @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_SetTimeFormat
* @param RTCx RTC Instance
* @param TimeFormat This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)
{
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);
}
/**
* @brief Get ALARM B time format (AM or PM notation)
* @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_GetTimeFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));
}
/**
* @brief Set ALARM B Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format
* @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_SetHour\n
* RTC_ALRMBR HU LL_RTC_ALMB_SetHour
* @param RTCx RTC Instance
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)
{
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),
(((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));
}
/**
* @brief Get ALARM B Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
* @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetHour\n
* RTC_ALRMBR HU LL_RTC_ALMB_GetHour
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);
}
/**
* @brief Set ALARM B Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format
* @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_SetMinute\n
* RTC_ALRMBR MNU LL_RTC_ALMB_SetMinute
* @param RTCx RTC Instance
* @param Minutes between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)
{
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));
}
/**
* @brief Get ALARM B Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
* @rmtoll RTC_ALRMBR MNT LL_RTC_ALMB_GetMinute\n
* RTC_ALRMBR MNU LL_RTC_ALMB_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);
}
/**
* @brief Set ALARM B Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format
* @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_SetSecond\n
* RTC_ALRMBR SU LL_RTC_ALMB_SetSecond
* @param RTCx RTC Instance
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)
{
MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),
(((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));
}
/**
* @brief Get ALARM B Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
* @rmtoll RTC_ALRMBR ST LL_RTC_ALMB_GetSecond\n
* RTC_ALRMBR SU LL_RTC_ALMB_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);
}
/**
* @brief Set Alarm B Time (hour, minute and second) in BCD format
* @rmtoll RTC_ALRMBR PM LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR HT LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR HU LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR MNT LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR MNU LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR ST LL_RTC_ALMB_ConfigTime\n
* RTC_ALRMBR SU LL_RTC_ALMB_ConfigTime
* @param RTCx RTC Instance
* @param Format12_24 This parameter can be one of the following values:
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM
* @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM
* @param Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
* @param Minutes Value between Min_Data=0x00 and Max_Data=0x59
* @param Seconds Value between Min_Data=0x00 and Max_Data=0x59
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes,
uint32_t Seconds)
{
uint32_t temp;
temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \
(((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \
(((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));
MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST
| RTC_ALRMBR_SU, temp);
}
/**
* @brief Get Alarm B Time (hour, minute and second) in BCD format
* @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
* are available to get independently each parameter.
* @rmtoll RTC_ALRMBR HT LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR HU LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR MNT LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR MNU LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR ST LL_RTC_ALMB_GetTime\n
* RTC_ALRMBR SU LL_RTC_ALMB_GetTime
* @param RTCx RTC Instance
* @retval Combination of hours, minutes and seconds.
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)
{
return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));
}
/**
* @brief Set Alarm B Mask the most-significant bits starting at this bit
* @note This register can be written only when ALRBE is reset in RTC_CR register,
* or in initialization mode.
* @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask
* @param RTCx RTC Instance
* @param Mask Value between Min_Data=0x00 and Max_Data=0xF
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);
}
/**
* @brief Get Alarm B Mask the most-significant bits starting at this bit
* @rmtoll RTC_ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xF
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos);
}
/**
* @brief Set Alarm B Sub seconds value
* @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_SetSubSecond
* @param RTCx RTC Instance
* @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)
{
MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);
}
/**
* @brief Get Alarm B Sub seconds value
* @rmtoll RTC_ALRMBSSR SS LL_RTC_ALMB_GetSubSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x7FFF
*/
__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Timestamp Timestamp
* @{
*/
/**
* @brief Enable internal event timestamp
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ITSE LL_RTC_TS_EnableInternalEvent
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ITSE);
}
/**
* @brief Disable internal event timestamp
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ITSE LL_RTC_TS_DisableInternalEvent
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);
}
/**
* @brief Enable Timestamp
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ITSE LL_RTC_TS_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TSE);
}
/**
* @brief Disable Timestamp
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ITSE LL_RTC_TS_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TSE);
}
/**
* @brief Set Time-stamp event active edge
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting
* @rmtoll RTC_CR ITSEDGE LL_RTC_TS_SetActiveEdge
* @param RTCx RTC Instance
* @param Edge This parameter can be one of the following values:
* @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
* @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)
{
MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);
}
/**
* @brief Get Time-stamp event active edge
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ITSEDGE LL_RTC_TS_GetActiveEdge
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING
* @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));
}
/**
* @brief Get Timestamp AM/PM notation (AM or 24-hour format)
* @rmtoll RTC_TSTR PM LL_RTC_TS_GetTimeFormat
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TS_TIME_FORMAT_AM
* @arg @ref LL_RTC_TS_TIME_FORMAT_PM
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));
}
/**
* @brief Get Timestamp Hours in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format
* @rmtoll RTC_TSTR HT LL_RTC_TS_GetHour\n
* RTC_TSTR HU LL_RTC_TS_GetHour
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);
}
/**
* @brief Get Timestamp Minutes in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format
* @rmtoll RTC_TSTR MNT LL_RTC_TS_GetMinute\n
* RTC_TSTR HU LL_RTC_TS_GetMinute
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);
}
/**
* @brief Get Timestamp Seconds in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format
* @rmtoll RTC_TSTR ST LL_RTC_TS_GetSecond\n
* RTC_TSTR HU LL_RTC_TS_GetSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0x59
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));
}
/**
* @brief Get Timestamp time (hour, minute and second) in BCD format
* @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND
* are available to get independently each parameter.
* @rmtoll RTC_TSTR HT LL_RTC_TS_GetTime\n
* RTC_TSTR HU LL_RTC_TS_GetTime\n
* RTC_TSTR MNT LL_RTC_TS_GetTime\n
* RTC_TSTR MNU LL_RTC_TS_GetTime\n
* RTC_TSTR ST LL_RTC_TS_GetTime\n
* RTC_TSTR SU LL_RTC_TS_GetTime
* @param RTCx RTC Instance
* @retval Combination of hours, minutes and seconds.
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSTR,
RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));
}
/**
* @brief Get Timestamp Week day
* @rmtoll RTC_TSDR WDU LL_RTC_TS_GetWeekDay
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WEEKDAY_MONDAY
* @arg @ref LL_RTC_WEEKDAY_TUESDAY
* @arg @ref LL_RTC_WEEKDAY_WEDNESDAY
* @arg @ref LL_RTC_WEEKDAY_THURSDAY
* @arg @ref LL_RTC_WEEKDAY_FRIDAY
* @arg @ref LL_RTC_WEEKDAY_SATURDAY
* @arg @ref LL_RTC_WEEKDAY_SUNDAY
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);
}
/**
* @brief Get Timestamp Month in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format
* @rmtoll RTC_TSDR MT LL_RTC_TS_GetMonth\n
* RTC_TSDR MU LL_RTC_TS_GetMonth
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_MONTH_JANUARY
* @arg @ref LL_RTC_MONTH_FEBRUARY
* @arg @ref LL_RTC_MONTH_MARCH
* @arg @ref LL_RTC_MONTH_APRIL
* @arg @ref LL_RTC_MONTH_MAY
* @arg @ref LL_RTC_MONTH_JUNE
* @arg @ref LL_RTC_MONTH_JULY
* @arg @ref LL_RTC_MONTH_AUGUST
* @arg @ref LL_RTC_MONTH_SEPTEMBER
* @arg @ref LL_RTC_MONTH_OCTOBER
* @arg @ref LL_RTC_MONTH_NOVEMBER
* @arg @ref LL_RTC_MONTH_DECEMBER
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);
}
/**
* @brief Get Timestamp Day in BCD format
* @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format
* @rmtoll RTC_TSDR DT LL_RTC_TS_GetDay\n
* RTC_TSDR DU LL_RTC_TS_GetDay
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x01 and Max_Data=0x31
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));
}
/**
* @brief Get Timestamp date (WeekDay, Day and Month) in BCD format
* @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,
* and __LL_RTC_GET_DAY are available to get independently each parameter.
* @rmtoll RTC_TSDR WDU LL_RTC_TS_GetDate\n
* RTC_TSDR MT LL_RTC_TS_GetDate\n
* RTC_TSDR MU LL_RTC_TS_GetDate\n
* RTC_TSDR DT LL_RTC_TS_GetDate\n
* RTC_TSDR DU LL_RTC_TS_GetDate
* @param RTCx RTC Instance
* @retval Combination of Weekday, Day and Month
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));
}
/**
* @brief Get time-stamp sub second value
* @rmtoll RTC_TSDR SS LL_RTC_TS_GetSubSecond
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));
}
/**
* @brief Activate timestamp on tamper detection event
* @rmtoll RTC_CR TAMPTS LL_RTC_TS_EnableOnTamper
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TAMPTS);
}
/**
* @brief Disable timestamp on tamper detection event
* @rmtoll RTC_CR TAMPTS LL_RTC_TS_DisableOnTamper
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Tamper Tamper
* @{
*/
/**
* @brief Enable TAMPx input detection
* @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Enable\n
* TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Enable
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_1
* @arg @ref LL_RTC_TAMPER_2
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR1, Tamper);
}
/**
* @brief Clear TAMPx input detection
* @rmtoll TAMP_CR1 TAMP1E LL_RTC_TAMPER_Disable\n
* TAMP_CR1 TAMP2E... LL_RTC_TAMPER_Disable
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_1
* @arg @ref LL_RTC_TAMPER_2
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR1, Tamper);
}
/**
* @brief Enable Tamper mask flag
* @note Associated Tamper IT must not enabled when tamper mask is set.
* @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_EnableMask\n
* TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_EnableMask
* @param RTCx RTC Instance
* @param Mask This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
* @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR2, Mask);
}
/**
* @brief Disable Tamper mask flag
* @rmtoll TAMP_CR2 TAMP1MF LL_RTC_TAMPER_DisableMask\n
* TAMP_CR2 TAMP2MF... LL_RTC_TAMPER_DisableMask
* @param RTCx RTC Instance
* @param Mask This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_MASK_TAMPER1
* @arg @ref LL_RTC_TAMPER_MASK_TAMPER2
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR2, Mask);
}
/**
* @brief Enable backup register erase after Tamper event detection
* @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_EnableEraseBKP\n
* TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_EnableEraseBKP
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
* @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR2, Tamper);
}
/**
* @brief Disable backup register erase after Tamper event detection
* @rmtoll TAMP_CR2 TAMP1NOERASE LL_RTC_TAMPER_DisableEraseBKP\n
* TAMP_CR2 TAMP2NOERASE... LL_RTC_TAMPER_DisableEraseBKP
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1
* @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR2, Tamper);
}
/**
* @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)
* @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
}
/**
* @brief Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)
* @rmtoll TAMP_FLTCR TAMPPUDIS LL_RTC_TAMPER_EnablePullUp
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS);
}
/**
* @brief Set RTC_TAMPx precharge duration
* @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge
* @param RTCx RTC Instance
* @param Duration This parameter can be one of the following values:
* @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);
}
/**
* @brief Get RTC_TAMPx precharge duration
* @rmtoll TAMP_FLTCR TAMPPRCH LL_RTC_TAMPER_GetPrecharge
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK
* @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH));
}
/**
* @brief Set RTC_TAMPx filter count
* @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_SetFilterCount
* @param RTCx RTC Instance
* @param FilterCount This parameter can be one of the following values:
* @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
* @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
* @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
* @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);
}
/**
* @brief Get RTC_TAMPx filter count
* @rmtoll TAMP_FLTCR TAMPFLT LL_RTC_TAMPER_GetFilterCount
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TAMPER_FILTER_DISABLE
* @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE
* @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE
* @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT));
}
/**
* @brief Set Tamper sampling frequency
* @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq
* @param RTCx RTC Instance
* @param SamplingFreq This parameter can be one of the following values:
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)
{
UNUSED(RTCx);
MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);
}
/**
* @brief Get Tamper sampling frequency
* @rmtoll TAMP_FLTCR TAMPFREQ LL_RTC_TAMPER_GetSamplingFreq
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512
* @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256
*/
__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ));
}
/**
* @brief Enable Active level for Tamper input
* @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_EnableActiveLevel\n
* TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_EnableActiveLevel
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR2, Tamper);
}
/**
* @brief Disable Active level for Tamper input
* @rmtoll TAMP_CR2 TAMP1TRG LL_RTC_TAMPER_DisableActiveLevel\n
* TAMP_CR2 TAMP2TRG... LL_RTC_TAMPER_DisableActiveLevel
* @param RTCx RTC Instance
* @param Tamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1
* @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR2, Tamper);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Internal_Tamper Internal Tamper
* @{
*/
/**
* @brief Enable internal tamper detection.
* @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Enable\n
* TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Enable\n
* TAMP_CR1 ITAMP4E LL_RTC_TAMPER_ITAMP_Enable\n
* TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Enable\n
* TAMP_CR1 ITAMP6E LL_RTC_TAMPER_ITAMP_Enable\n
* TAMP_CR1 ITAMP7E... LL_RTC_TAMPER_ITAMP_Enable
* @param RTCx RTC Instance
* @param InternalTamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_ITAMP1
* @arg @ref LL_RTC_TAMPER_ITAMP3
* @arg @ref LL_RTC_TAMPER_ITAMP4
* @arg @ref LL_RTC_TAMPER_ITAMP5
* @arg @ref LL_RTC_TAMPER_ITAMP6
@if RTC_TAMP_INT_7_SUPPORT
* @arg @ref LL_RTC_TAMPER_ITAMP7
@endif
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
{
UNUSED(RTCx);
SET_BIT(TAMP->CR1, InternalTamper);
}
/**
* @brief Disable internal tamper detection.
* @rmtoll TAMP_CR1 ITAMP1E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP3E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP4E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP5E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP6E LL_RTC_TAMPER_ITAMP_Disable\n
* TAMP_CR1 ITAMP7E... LL_RTC_TAMPER_ITAMP_Disable
* @param RTCx RTC Instance
* @param InternalTamper This parameter can be a combination of the following values:
* @arg @ref LL_RTC_TAMPER_ITAMP1
* @arg @ref LL_RTC_TAMPER_ITAMP3
* @arg @ref LL_RTC_TAMPER_ITAMP4
* @arg @ref LL_RTC_TAMPER_ITAMP5
* @arg @ref LL_RTC_TAMPER_ITAMP6
@if RTC_TAMP_INT_7_SUPPORT
* @arg @ref LL_RTC_TAMPER_ITAMP7
@endif
*
* @retval None
*/
__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->CR1, InternalTamper);
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Wakeup Wakeup
* @{
*/
/**
* @brief Enable Wakeup timer
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Enable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_WUTE);
}
/**
* @brief Disable Wakeup timer
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_Disable
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);
}
/**
* @brief Check if Wakeup timer is enabled or not
* @rmtoll RTC_CR WUTE LL_RTC_WAKEUP_IsEnabled
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U);
}
/**
* @brief Select Wakeup clock
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ICSR WUTWF bit = 1
* @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_SetClock
* @param RTCx RTC Instance
* @param WakeupClock This parameter can be one of the following values:
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)
{
MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);
}
/**
* @brief Get Wakeup clock
* @rmtoll RTC_CR WUCKSEL LL_RTC_WAKEUP_GetClock
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4
* @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE
* @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT
*/
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));
}
/**
* @brief Set Wakeup auto-reload value
* @note Bit can be written only when WUTWF is set to 1 in RTC_ICSR
* @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_SetAutoReload
* @param RTCx RTC Instance
* @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)
{
MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);
}
/**
* @brief Get Wakeup auto-reload value
* @rmtoll RTC_WUTR WUT LL_RTC_WAKEUP_GetAutoReload
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers
* @{
*/
/**
* @brief Writes a data in a specified Backup data register.
* @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_SetRegister
* @param RTCx RTC Instance
* @param BackupRegister This parameter can be one of the following values:
* @arg @ref LL_RTC_BKP_DR0
* @arg @ref LL_RTC_BKP_DR1
* @arg @ref LL_RTC_BKP_DR2
* @arg @ref LL_RTC_BKP_DR3
* ...
* @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
* @retval None
*/
__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)
{
__IO uint32_t *tmp;
UNUSED(RTCx);
tmp = &(TAMP->BKP0R) + BackupRegister;
/* Write the specified register */
*tmp = Data;
}
/**
* @brief Reads data from the specified RTC Backup data Register.
* @rmtoll TAMP_BKPxR BKP LL_RTC_BKP_GetRegister
* @param RTCx RTC Instance
* @param BackupRegister This parameter can be one of the following values:
* @arg @ref LL_RTC_BKP_DR0
* @arg @ref LL_RTC_BKP_DR1
* @arg @ref LL_RTC_BKP_DR2
* @arg @ref LL_RTC_BKP_DR3
* ...
* @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)
{
const __IO uint32_t *tmp;
UNUSED(RTCx);
tmp = &(TAMP->BKP0R) + BackupRegister;
/* Read the specified register */
return *tmp;
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_Calibration Calibration
* @{
*/
/**
* @brief Set Calibration output frequency (1 Hz or 512 Hz)
* @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR COE LL_RTC_CAL_SetOutputFreq\n
* RTC_CR COSEL LL_RTC_CAL_SetOutputFreq
* @param RTCx RTC Instance
* @param Frequency This parameter can be one of the following values:
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)
{
MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);
}
/**
* @brief Get Calibration output frequency (1 Hz or 512 Hz)
* @rmtoll RTC_CR COE LL_RTC_CAL_GetOutputFreq\n
* RTC_CR COSEL LL_RTC_CAL_GetOutputFreq
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_CALIB_OUTPUT_NONE
* @arg @ref LL_RTC_CALIB_OUTPUT_1HZ
* @arg @ref LL_RTC_CALIB_OUTPUT_512HZ
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));
}
/**
* @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
* @rmtoll RTC_CALR CALP LL_RTC_CAL_SetPulse
* @param RTCx RTC Instance
* @param Pulse This parameter can be one of the following values:
* @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE
* @arg @ref LL_RTC_CALIB_INSERTPULSE_SET
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)
{
MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);
}
/**
* @brief Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)
* @rmtoll RTC_CALR CALP LL_RTC_CAL_IsPulseInserted
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U);
}
/**
* @brief Set the calibration cycle period
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
* @rmtoll RTC_CALR CALW8 LL_RTC_CAL_SetPeriod\n
* RTC_CALR CALW16 LL_RTC_CAL_SetPeriod
* @param RTCx RTC Instance
* @param Period This parameter can be one of the following values:
* @arg @ref LL_RTC_CALIB_PERIOD_32SEC
* @arg @ref LL_RTC_CALIB_PERIOD_16SEC
* @arg @ref LL_RTC_CALIB_PERIOD_8SEC
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)
{
MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);
}
/**
* @brief Get the calibration cycle period
* @rmtoll RTC_CALR CALW8 LL_RTC_CAL_GetPeriod\n
* RTC_CALR CALW16 LL_RTC_CAL_GetPeriod
* @param RTCx RTC Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_RTC_CALIB_PERIOD_32SEC
* @arg @ref LL_RTC_CALIB_PERIOD_16SEC
* @arg @ref LL_RTC_CALIB_PERIOD_8SEC
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));
}
/**
* @brief Set Calibration minus
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @note Bit can be written only when RECALPF is set to 0 in RTC_ICSR
* @rmtoll RTC_CALR CALM LL_RTC_CAL_SetMinus
* @param RTCx RTC Instance
* @param CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF
* @retval None
*/
__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)
{
MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);
}
/**
* @brief Get Calibration minus
* @rmtoll RTC_CALR CALM LL_RTC_CAL_GetMinus
* @param RTCx RTC Instance
* @retval Value between Min_Data=0x00 and Max_Data= 0x1FF
*/
__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)
{
return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));
}
/**
* @}
*/
/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Get Internal Time-stamp flag
* @rmtoll RTC_SR ITSF LL_RTC_IsActiveFlag_ITS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U);
}
/**
* @brief Get Recalibration pending Flag
* @rmtoll RTC_ICSR RECALPF LL_RTC_IsActiveFlag_RECALP
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U);
}
/**
* @brief Get Time-stamp overflow flag
* @rmtoll RTC_SR TSOVF LL_RTC_IsActiveFlag_TSOV
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U);
}
/**
* @brief Get Time-stamp flag
* @rmtoll RTC_SR TSF LL_RTC_IsActiveFlag_TS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U);
}
/**
* @brief Get Wakeup timer flag
* @rmtoll RTC_SR WUTF LL_RTC_IsActiveFlag_WUT
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U);
}
/**
* @brief Get Alarm B flag
* @rmtoll RTC_SR ALRBF LL_RTC_IsActiveFlag_ALRB
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U);
}
/**
* @brief Get Alarm A flag
* @rmtoll RTC_SR ALRAF LL_RTC_IsActiveFlag_ALRA
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U);
}
/**
* @brief Clear Internal Time-stamp flag
* @rmtoll RTC_SCR CITSF LL_RTC_ClearFlag_ITS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CITSF);
}
/**
* @brief Clear Time-stamp overflow flag
* @rmtoll RTC_SCR CTSOVF LL_RTC_ClearFlag_TSOV
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);
}
/**
* @brief Clear Time-stamp flag
* @rmtoll RTC_SCR CTSF LL_RTC_ClearFlag_TS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CTSF);
}
/**
* @brief Clear Wakeup timer flag
* @rmtoll RTC_SCR CWUTF LL_RTC_ClearFlag_WUT
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);
}
/**
* @brief Clear Alarm B flag
* @rmtoll RTC_SCR CALRBF LL_RTC_ClearFlag_ALRB
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);
}
/**
* @brief Clear Alarm A flag
* @rmtoll RTC_SCR CALRAF LL_RTC_ClearFlag_ALRA
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->SCR, RTC_SCR_CALRAF);
}
/**
* @brief Get Initialization flag
* @rmtoll RTC_ICSR INITF LL_RTC_IsActiveFlag_INIT
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U);
}
/**
* @brief Get Registers synchronization flag
* @rmtoll RTC_ICSR RSF LL_RTC_IsActiveFlag_RS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U);
}
/**
* @brief Clear Registers synchronization flag
* @rmtoll RTC_ICSR RSF LL_RTC_ClearFlag_RS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)
{
WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));
}
/**
* @brief Get Initialization status flag
* @rmtoll RTC_ICSR INITS LL_RTC_IsActiveFlag_INITS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U);
}
/**
* @brief Get Shift operation pending flag
* @rmtoll RTC_ICSR SHPF LL_RTC_IsActiveFlag_SHP
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U);
}
/**
* @brief Get Wakeup timer write flag
* @rmtoll RTC_ICSR WUTWF LL_RTC_IsActiveFlag_WUTW
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U);
}
/**
* @brief Get Alarm B write flag
* @rmtoll RTC_ICSR ALRBWF LL_RTC_IsActiveFlag_ALRBW
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1U : 0U);
}
/**
* @brief Get Alarm A write flag
* @rmtoll RTC_ICSR ALRAWF LL_RTC_IsActiveFlag_ALRAW
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1U : 0U);
}
/**
* @brief Get Alarm A masked flag.
* @rmtoll RTC_MISR ALRAMF LL_RTC_IsActiveFlag_ALRAM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U);
}
/**
* @brief Get Alarm B masked flag.
* @rmtoll RTC_MISR ALRBMF LL_RTC_IsActiveFlag_ALRBM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U);
}
/**
* @brief Get Wakeup timer masked flag.
* @rmtoll RTC_MISR WUTMF LL_RTC_IsActiveFlag_WUTM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U);
}
/**
* @brief Get Time-stamp masked flag.
* @rmtoll RTC_MISR TSMF LL_RTC_IsActiveFlag_TSM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U);
}
/**
* @brief Get Time-stamp overflow masked flag.
* @rmtoll RTC_MISR TSOVMF LL_RTC_IsActiveFlag_TSOVM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U);
}
/**
* @brief Get Internal Time-stamp masked flag.
* @rmtoll RTC_MISR ITSMF LL_RTC_IsActiveFlag_ITSM
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U);
}
/**
* @brief Get tamper 1 detection flag.
* @rmtoll TAMP_SR TAMP1F LL_RTC_IsActiveFlag_TAMP1
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U);
}
/**
* @brief Get tamper 2 detection flag.
* @rmtoll TAMP_SR TAMP2F LL_RTC_IsActiveFlag_TAMP2
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U);
}
#if (RTC_TAMP_NB==3)
/**
* @brief Get tamper 3 detection flag.
* @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U);
}
#elif (RTC_TAMP_NB==8)
/**
* @brief Get tamper 3 detection flag.
* @rmtoll TAMP_SR TAMP3F LL_RTC_IsActiveFlag_TAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U);
}
/**
* @brief Get tamper 4 detection flag.
* @rmtoll TAMP_SR TAMP4F LL_RTC_IsActiveFlag_TAMP4
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U);
}
/**
* @brief Get tamper 5 detection flag.
* @rmtoll TAMP_SR TAMP5F LL_RTC_IsActiveFlag_TAMP5
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U);
}
/**
* @brief Get tamper 6 detection flag.
* @rmtoll TAMP_SR TAMP6F LL_RTC_IsActiveFlag_TAMP6
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U);
}
/**
* @brief Get tamper 7 detection flag.
* @rmtoll TAMP_SR TAMP7F LL_RTC_IsActiveFlag_TAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP7F) == (TAMP_SR_TAMP7F)) ? 1U : 0U);
}
/**
* @brief Get tamper 8 detection flag.
* @rmtoll TAMP_SR TAMP8F LL_RTC_IsActiveFlag_TAMP8
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP8F) == (TAMP_SR_TAMP8F)) ? 1U : 0U);
}
#endif /* RTC_TAMP_NB */
#if defined (RTC_TAMP_INT_1_SUPPORT)
/**
* @brief Get internal tamper 1 detection flag.
* @rmtoll TAMP_SR ITAMP1F LL_RTC_IsActiveFlag_ITAMP1
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_1_SUPPORT */
#if defined (RTC_TAMP_INT_2_SUPPORT)
/**
* @brief Get internal tamper 2 detection flag.
* @rmtoll TAMP_SR ITAMP2F LL_RTC_IsActiveFlag_ITAMP2
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_2_SUPPORT */
/**
* @brief Get internal tamper 3 detection flag.
* @rmtoll TAMP_SR ITAMP3F LL_RTC_IsActiveFlag_ITAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 4 detection flag.
* @rmtoll TAMP_SR ITAMP4F LL_RTC_IsActiveFlag_ITAMP4
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP4F) == (TAMP_SR_ITAMP4F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 5 detection flag.
* @rmtoll TAMP_SR ITAMP5F LL_RTC_IsActiveFlag_ITAMP5
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U);
}
#if defined (RTC_TAMP_INT_6_SUPPORT)
/**
* @brief Get internal tamper 6 detection flag.
* @rmtoll TAMP_SR ITAMP6F LL_RTC_IsActiveFlag_ITAMP6
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_6_SUPPORT */
#if defined (RTC_TAMP_INT_7_SUPPORT)
/**
* @brief Get internal tamper 7 detection flag.
* @rmtoll TAMP_SR ITAMP7F LL_RTC_IsActiveFlag_ITAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP7F) == (TAMP_SR_ITAMP7F)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_7_SUPPORT */
#if defined (RTC_TAMP_INT_8_SUPPORT)
/**
* @brief Get internal tamper 8 detection flag.
* @rmtoll TAMP_SR ITAMP8F LL_RTC_IsActiveFlag_ITAMP8
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_8_SUPPORT */
#if 0
/**
* @brief Get internal tamper 9 detection flag.
* @rmtoll TAMP_SR ITAMP9F LL_RTC_IsActiveFlag_ITAMP9
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP9F) == (TAMP_SR_ITAMP9F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 10 detection flag.
* @rmtoll TAMP_SR ITAMP10F LL_RTC_IsActiveFlag_ITAMP10
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP10(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP10F) == (TAMP_SR_ITAMP10F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 11 detection flag.
* @rmtoll TAMP_SR ITAMP11F LL_RTC_IsActiveFlag_ITAMP11
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP11F) == (TAMP_SR_ITAMP11F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 12 detection flag.
* @rmtoll TAMP_SR ITAMP7F LL_RTC_IsActiveFlag_ITAMP12
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP12F) == (TAMP_SR_ITAMP12F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 13 detection flag.
* @rmtoll TAMP_SR ITAMP13F LL_RTC_IsActiveFlag_ITAMP13
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP13F) == (TAMP_SR_ITAMP13F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 14 detection flag.
* @rmtoll TAMP_SR ITAMP14F LL_RTC_IsActiveFlag_ITAMP14
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP14(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP14F) == (TAMP_SR_ITAMP14F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 15 detection flag.
* @rmtoll TAMP_SR ITAMP15F LL_RTC_IsActiveFlag_ITAMP15
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP15(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP15F) == (TAMP_SR_ITAMP15F)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 16 detection flag.
* @rmtoll TAMP_SR ITAMP7F LL_RTC_IsActiveFlag_ITAMP16
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP16(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP16F) == (TAMP_SR_ITAMP16F)) ? 1U : 0U);
}
#endif /* 0 */
/**
* @brief Get tamper 1 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP1MF LL_RTC_IsActiveFlag_TAMP1M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 2 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP2MF LL_RTC_IsActiveFlag_TAMP2M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U);
}
#if (RTC_TAMP_NB ==3)
/**
* @brief Get tamper 3 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U);
}
#elif (RTC_TAMP_NB==8)
/**
* @brief Get tamper 3 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP3M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 4 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP4MF LL_RTC_IsActiveFlag_TAMP4M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 5 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP5MF LL_RTC_IsActiveFlag_TAMP5M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 6 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP3MF LL_RTC_IsActiveFlag_TAMP6M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 7 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP7MF LL_RTC_IsActiveFlag_TAMP7M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP7MF) == (TAMP_MISR_TAMP7MF)) ? 1U : 0U);
}
/**
* @brief Get tamper 8 interrupt masked flag.
* @rmtoll TAMP_MISR TAMP8MF LL_RTC_IsActiveFlag_TAMP8M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP8MF) == (TAMP_MISR_TAMP8MF)) ? 1U : 0U);
}
#endif /* RTC_TAMP_NB */
#if defined (RTC_TAMP_INT_1_SUPPORT)
/**
* @brief Get internal tamper 1 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP1MF LL_RTC_IsActiveFlag_ITAMP1M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_1_SUPPORT */
#if defined (RTC_TAMP_INT_2_SUPPORT)
/**
* @brief Get internal tamper 2 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP2MF LL_RTC_IsActiveFlag_ITAMP2M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_2_SUPPORT */
/**
* @brief Get internal tamper 3 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP3MF LL_RTC_IsActiveFlag_ITAMP3M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 4 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP4MF LL_RTC_IsActiveFlag_ITAMP4M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP4M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP4MF) == (TAMP_MISR_ITAMP4MF)) ? 1U : 0U);
}
/**
* @brief Get internal tamper 5 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP5MF LL_RTC_IsActiveFlag_ITAMP5M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U);
}
#if defined (RTC_TAMP_INT_6_SUPPORT)
/**
* @brief Get internal tamper 6 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP6MF LL_RTC_IsActiveFlag_ITAMP6M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_6_SUPPORT */
#if defined (RTC_TAMP_INT_7_SUPPORT)
/**
* @brief Get internal tamper 7 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP7MF LL_RTC_IsActiveFlag_ITAMP7M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP7M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP7MF) == (TAMP_MISR_ITAMP7MF)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_7_SUPPORT */
#if defined (RTC_TAMP_INT_8_SUPPORT)
/**
* @brief Get internal tamper 8 interrupt masked flag.
* @rmtoll TAMP_MISR ITAMP8MF LL_RTC_IsActiveFlag_ITAMP8M
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_8_SUPPORT */
/**
* @brief Clear tamper 1 detection flag.
* @rmtoll TAMP_SCR CTAMP1F LL_RTC_ClearFlag_TAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP1F);
}
/**
* @brief Clear tamper 2 detection flag.
* @rmtoll TAMP_SCR CTAMP2F LL_RTC_ClearFlag_TAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP2F);
}
#if (RTC_TAMP_NB == 3)
/**
* @brief Clear tamper 3 detection flag.
* @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP3F);
}
#elif (RTC_TAMP_NB == 8)
/**
* @brief Clear tamper 3 detection flag.
* @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP3F);
}
/**
* @brief Clear tamper 4 detection flag.
* @rmtoll TAMP_SCR CTAMP3F LL_RTC_ClearFlag_TAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP4F);
}
/**
* @brief Clear tamper 5 detection flag.
* @rmtoll TAMP_SCR CTAMP5F LL_RTC_ClearFlag_TAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP5F);
}
/**
* @brief Clear tamper 6 detection flag.
* @rmtoll TAMP_SCR CTAMP6F LL_RTC_ClearFlag_TAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP6F);
}
/**
* @brief Clear tamper 7 detection flag.
* @rmtoll TAMP_SCR CTAMP7F LL_RTC_ClearFlag_TAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP7F);
}
/**
* @brief Clear tamper 8 detection flag.
* @rmtoll TAMP_SCR CTAMP8F LL_RTC_ClearFlag_TAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CTAMP8F);
}
#endif /* RTC_TAMP_NB */
#if defined (RTC_TAMP_INT_1_SUPPORT)
/**
* @brief Clear internal tamper 1 detection flag.
* @rmtoll TAMP_SCR CITAMP1F LL_RTC_ClearFlag_ITAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP1F);
}
#endif /* RTC_TAMP_INT_1_SUPPORT */
#if defined (RTC_TAMP_INT_2_SUPPORT)
/**
* @brief Clear internal tamper 2 detection flag.
* @rmtoll TAMP_SCR CITAMP2F LL_RTC_ClearFlag_ITAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP2F);
}
#endif /* RTC_TAMP_INT_2_SUPPORT */
/**
* @brief Clear internal tamper 3 detection flag.
* @rmtoll TAMP_SCR CITAMP3F LL_RTC_ClearFlag_ITAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP3F);
}
/**
* @brief Clear internal tamper 4 detection flag.
* @rmtoll TAMP_SCR CITAMP4F LL_RTC_ClearFlag_ITAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP4F);
}
/**
* @brief Clear internal tamper 5 detection flag.
* @rmtoll TAMP_SCR CITAMP5F LL_RTC_ClearFlag_ITAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP5F);
}
#if defined (RTC_TAMP_INT_6_SUPPORT)
/**
* @brief Clear internal tamper 6 detection flag.
* @rmtoll TAMP_SCR CITAMP6F LL_RTC_ClearFlag_ITAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP6F);
}
#endif /* (RTC_TAMP_INT_2_SUPPORT)*/
#if defined (RTC_TAMP_INT_7_SUPPORT)
/**
* @brief Clear internal tamper 7 detection flag.
* @rmtoll TAMP_SCR CITAMP7F LL_RTC_ClearFlag_ITAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP7F);
}
#endif /* (RTC_TAMP_INT_7_SUPPORT) */
#if defined (RTC_TAMP_INT_8_SUPPORT)
/**
* @brief Clear internal tamper 8 detection flag.
* @rmtoll TAMP_SCR CITAMP8F LL_RTC_ClearFlag_ITAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->SCR, TAMP_SCR_CITAMP8F);
}
#endif /* (RTC_TAMP_INT_8_SUPPORT) */
/**
* @}
*/
/** @defgroup RTC_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable Time-stamp interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR LL_RTC_EnableIT_TS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_TSIE);
}
/**
* @brief Disable Time-stamp interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR LL_RTC_DisableIT_TS
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);
}
/**
* @brief Enable Wakeup timer interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR LL_RTC_EnableIT_WUT
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_WUTIE);
}
/**
* @brief Disable Wakeup timer interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR LL_RTC_DisableIT_WUT
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);
}
/**
* @brief Enable Alarm B interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRBIE LL_RTC_EnableIT_ALRB
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ALRBIE);
}
/**
* @brief Disable Alarm B interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRBIE LL_RTC_DisableIT_ALRB
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);
}
/**
* @brief Enable Alarm A interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRAIE LL_RTC_EnableIT_ALRA
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)
{
SET_BIT(RTCx->CR, RTC_CR_ALRAIE);
}
/**
* @brief Disable Alarm A interrupt
* @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.
* @rmtoll RTC_CR ALRAIE LL_RTC_DisableIT_ALRA
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)
{
CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);
}
/**
* @brief Check if Time-stamp interrupt is enabled or not
* @rmtoll RTC_CR TSIE LL_RTC_IsEnabledIT_TS
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U);
}
/**
* @brief Check if Wakeup timer interrupt is enabled or not
* @rmtoll RTC_CR WUTIE LL_RTC_IsEnabledIT_WUT
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U);
}
/**
* @brief Check if Alarm B interrupt is enabled or not
* @rmtoll RTC_CR ALRBIE LL_RTC_IsEnabledIT_ALRB
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U);
}
/**
* @brief Check if Alarm A interrupt is enabled or not
* @rmtoll RTC_CR ALRAIE LL_RTC_IsEnabledIT_ALRA
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)
{
return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U);
}
/**
* @brief Enable tamper 1 interrupt.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_EnableIT_TAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
}
/**
* @brief Disable tamper 1 interrupt.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_TAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE);
}
/**
* @brief Enable tamper 2 interrupt.
* @rmtoll TAMP_IER TAMP2IE LL_RTC_EnableIT_TAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
}
/**
* @brief Disable tamper 2 interrupt.
* @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_TAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE);
}
#if (RTC_TAMP_NB == 3)
/**
* @brief Enable tamper 3 interrupt.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
}
/**
* @brief Disable tamper 3 interrupt.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
}
#elif (RTC_TAMP_NB == 8)
/**
* @brief Enable tamper 3 interrupt.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_EnableIT_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
}
/**
* @brief Disable tamper 3 interrupt.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_TAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE);
}
/**
* @brief Enable tamper 4 interrupt.
* @rmtoll TAMP_IER TAMP4IE LL_RTC_EnableIT_TAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
}
/**
* @brief Disable tamper 4 interrupt.
* @rmtoll TAMP_IER TAMP4IE LL_RTC_DisableIT_TAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE);
}
/**
* @brief Enable tamper 5 interrupt.
* @rmtoll TAMP_IER TAMP5IE LL_RTC_EnableIT_TAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
}
/**
* @brief Disable tamper 5 interrupt.
* @rmtoll TAMP_IER TAMP5IE LL_RTC_DisableIT_TAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE);
}
/**
* @brief Enable tamper 6 interrupt.
* @rmtoll TAMP_IER TAMP6IE LL_RTC_EnableIT_TAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
}
/**
* @brief Disable tamper 6 interrupt.
* @rmtoll TAMP_IER TAMP6IE LL_RTC_DisableIT_TAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE);
}
/**
* @brief Enable tamper 7 interrupt.
* @rmtoll TAMP_IER TAMP7IE LL_RTC_EnableIT_TAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
}
/**
* @brief Disable tamper 7 interrupt.
* @rmtoll TAMP_IER TAMP7IE LL_RTC_DisableIT_TAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP7IE);
}
/**
* @brief Enable tamper 8 interrupt.
* @rmtoll TAMP_IER TAMP8IE LL_RTC_EnableIT_TAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP8IE);
}
/**
* @brief Disable tamper 8 interrupt.
* @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_TAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP8IE);
}
#endif /* RTC_TAMP_NB */
#if 0
/**
* @brief Enable tamper 92 interrupt.
* @rmtoll TAMP_IER TAMP9IE LL_RTC_EnableIT_TAMP9
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP9IE);
}
/**
* @brief Disable tamper 9 interrupt.
* @rmtoll TAMP_IER TAMP9IE LL_RTC_DisableIT_TAMP9
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP9IE);
}
/**
* @brief Enable tamper 10 interrupt.
* @rmtoll TAMP_IER TAMP10IE LL_RTC_EnableIT_TAMP10
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP10(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP10IE);
}
/**
* @brief Disable tamper 10 interrupt.
* @rmtoll TAMP_IER TAMP10IE LL_RTC_DisableIT_TAMP10
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP10(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP10IE);
}
/**
* @brief Enable tamper 11 interrupt.
* @rmtoll TAMP_IER TAMP11IE LL_RTC_EnableIT_TAMP11
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP11IE);
}
/**
* @brief Disable tamper 11 interrupt.
* @rmtoll TAMP_IER TAMP11IE LL_RTC_DisableIT_TAMP11
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP11IE);
}
/**
* @brief Enable tamper 12 interrupt.
* @rmtoll TAMP_IER TAMP12IE LL_RTC_EnableIT_TAMP12
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP12IE);
}
/**
* @brief Disable tamper 12 interrupt.
* @rmtoll TAMP_IER TAMP12IE LL_RTC_DisableIT_TAMP12
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP12IE);
}
/**
* @brief Enable tamper 13 interrupt.
* @rmtoll TAMP_IER TAMP13IE LL_RTC_EnableIT_TAMP13
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP13IE);
}
/**
* @brief Disable tamper 13 interrupt.
* @rmtoll TAMP_IER TAMP13IE LL_RTC_DisableIT_TAMP13
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP13IE);
}
/**
* @brief Enable tamper 14 interrupt.
* @rmtoll TAMP_IER TAMP14IE LL_RTC_EnableIT_TAMP14
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP14(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP14IE);
}
/**
* @brief Disable tamper 14 interrupt.
* @rmtoll TAMP_IER TAMP14IE LL_RTC_DisableIT_TAMP14
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP14(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP14IE);
}
/**
* @brief Enable tamper 15 interrupt.
* @rmtoll TAMP_IER TAMP15IE LL_RTC_EnableIT_TAMP15
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP15(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP15IE);
}
/**
* @brief Disable tamper 15 interrupt.
* @rmtoll TAMP_IER TAMP15IE LL_RTC_DisableIT_TAMP15
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP15(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP15IE);
}
/**
* @brief Enable tamper 16 interrupt.
* @rmtoll TAMP_IER TAMP16IE LL_RTC_EnableIT_TAMP16
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_TAMP16(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_TAMP16IE);
}
/**
* @brief Disable tamper 16 interrupt.
* @rmtoll TAMP_IER TAMP16IE LL_RTC_DisableIT_TAMP16
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_TAMP16(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP16IE);
}
#endif /* 0 */
#if defined (RTC_TAMP_INT_1_SUPPORT)
/**
* @brief Enable internal tamper 1 interrupt.
* @rmtoll TAMP_IER ITAMP1IE LL_RTC_EnableIT_ITAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
}
/**
* @brief Disable internal tamper 1 interrupt.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_DisableIT_ITAMP1
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE);
}
#endif /* RTC_TAMP_INT_1_SUPPORT */
#if defined (RTC_TAMP_INT_2_SUPPORT)
/**
* @brief Enable internal tamper 2 interrupt.
* @rmtoll TAMP_IER ITAMP2IE LL_RTC_EnableIT_ITAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
}
/**
* @brief Disable internal tamper 2 interrupt.
* @rmtoll TAMP_IER TAMP2IE LL_RTC_DisableIT_ITAMP2
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE);
}
#endif /* RTC_TAMP_INT_2_SUPPORT */
/**
* @brief Enable internal tamper 3 interrupt.
* @rmtoll TAMP_IER ITAMP3IE LL_RTC_EnableIT_ITAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
}
/**
* @brief Disable internal tamper 3 interrupt.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_DisableIT_ITAMP3
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE);
}
/**
* @brief Enable internal tamper 4 interrupt.
* @rmtoll TAMP_IER ITAMP4IE LL_RTC_EnableIT_ITAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP4IE);
}
/**
* @brief Disable internal tamper 4 interrupt.
* @rmtoll TAMP_IER TAMP4IE LL_RTC_DisableIT_ITAMP4
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP4IE);
}
/**
* @brief Enable internal tamper 5 interrupt.
* @rmtoll TAMP_IER ITAMP5IE LL_RTC_EnableIT_ITAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
}
/**
* @brief Disable internal tamper 5 interrupt.
* @rmtoll TAMP_IER TAMP5IE LL_RTC_DisableIT_ITAMP5
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE);
}
#if defined (RTC_TAMP_INT_6_SUPPORT)
/**
* @brief Enable internal tamper 6 interrupt.
* @rmtoll TAMP_IER ITAMP6IE LL_RTC_EnableIT_ITAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
}
/**
* @brief Disable internal tamper 6 interrupt.
* @rmtoll TAMP_IER TAMP6IE LL_RTC_DisableIT_ITAMP6
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE);
}
#endif /* (RTC_TAMP_INT_2_SUPPORT) */
#if defined (RTC_TAMP_INT_7_SUPPORT)
/**
* @brief Enable internal tamper 7 interrupt.
* @rmtoll TAMP_IER ITAMP7IE LL_RTC_EnableIT_ITAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
}
/**
* @brief Disable internal tamper 7 interrupt.
* @rmtoll TAMP_IER TAMP7IE LL_RTC_DisableIT_ITAMP7
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP7IE);
}
#endif /* (RTC_TAMP_INT_7_SUPPORT)*/
#if defined (RTC_TAMP_INT_8_SUPPORT)
/**
* @brief Enable internal tamper 8 interrupt.
* @rmtoll TAMP_IER ITAMP8IE LL_RTC_EnableIT_ITAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
}
/**
* @brief Disable internal tamper 8 interrupt.
* @rmtoll TAMP_IER TAMP8IE LL_RTC_DisableIT_ITAMP8
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE);
}
#endif /* (RTC_TAMP_INT_8_SUPPORT)*/
#if 0
/**
* @brief Enable internal tamper 9 interrupt.
* @rmtoll TAMP_IER ITAMP7IE LL_RTC_EnableIT_ITAMP9
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
}
/**
* @brief Disable internal tamper 9 interrupt.
* @rmtoll TAMP_IER TAMP9IE LL_RTC_DisableIT_ITAMP9
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP9(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP9IE);
}
/**
* @brief Enable internal tamper 10 interrupt.
* @rmtoll TAMP_IER ITAMP10IE LL_RTC_EnableIT_ITAMP10
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP10(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP10IE);
}
/**
* @brief Disable internal tamper 10 interrupt.
* @rmtoll TAMP_IER TAMP10IE LL_RTC_DisableIT_ITAMP10
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP10(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP10IE);
}
/**
* @brief Enable internal tamper 11 interrupt.
* @rmtoll TAMP_IER ITAMP11IE LL_RTC_EnableIT_ITAMP11
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
}
/**
* @brief Disable internal tamper 11 interrupt.
* @rmtoll TAMP_IER TAMP11IE LL_RTC_DisableIT_ITAMP11
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP11(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP11IE);
}
/**
* @brief Enable internal tamper 12 interrupt.
* @rmtoll TAMP_IER ITAMP12IE LL_RTC_EnableIT_ITAMP12
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP12IE);
}
/**
* @brief Disable internal tamper 12 interrupt.
* @rmtoll TAMP_IER TAMP12IE LL_RTC_DisableIT_ITAMP12
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP12(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP12IE);
}
/**
* @brief Enable internal tamper 13 interrupt.
* @rmtoll TAMP_IER ITAMP13IE LL_RTC_EnableIT_ITAMP13
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP13IE);
}
/**
* @brief Disable internal tamper 13 interrupt.
* @rmtoll TAMP_IER TAMP13IE LL_RTC_DisableIT_ITAMP13
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP13(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP13IE);
}
/**
* @brief Enable internal tamper 14 interrupt.
* @rmtoll TAMP_IER ITAMP14IE LL_RTC_EnableIT_ITAMP14
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP14(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP14IE);
}
/**
* @brief Disable internal tamper 14 interrupt.
* @rmtoll TAMP_IER TAMP14IE LL_RTC_DisableIT_ITAMP14
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP14(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP14IE);
}
/**
* @brief Enable internal tamper 15 interrupt.
* @rmtoll TAMP_IER ITAMP15IE LL_RTC_EnableIT_ITAMP15
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP15(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP15IE);
}
/**
* @brief Disable internal tamper 15 interrupt.
* @rmtoll TAMP_IER TAMP15IE LL_RTC_DisableIT_ITAMP15
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP15(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP15IE);
}
/**
* @brief Enable internal tamper 16 interrupt.
* @rmtoll TAMP_IER ITAMP16IE LL_RTC_EnableIT_ITAMP16
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_EnableIT_ITAMP16(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
SET_BIT(TAMP->IER, TAMP_IER_ITAMP16IE);
}
/**
* @brief Disable internal tamper 16 interrupt.
* @rmtoll TAMP_IER TAMP16IE LL_RTC_DisableIT_ITAMP16
* @param RTCx RTC Instance
* @retval None
*/
__STATIC_INLINE void LL_RTC_DisableIT_ITAMP16(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP16IE);
}
#endif /* 0 */
/**
* @brief Check if tamper 1 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP1
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 2 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP2IE LL_RTC_IsEnabledIT_TAMP2
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U);
}
#if (RTC_TAMP_NB == 3)
/**
* @brief Check if tamper 3 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U);
}
#elif (RTC_TAMP_NB == 8)
/**
* @brief Check if tamper 3 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP3IE LL_RTC_IsEnabledIT_TAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 4 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP4IE LL_RTC_IsEnabledIT_TAMP4
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 5 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP5
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 6 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP6IE LL_RTC_IsEnabledIT_TAMP6
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 7 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP1IE LL_RTC_IsEnabledIT_TAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP7IE) == (TAMP_IER_TAMP7IE)) ? 1U : 0U);
}
/**
* @brief Check if tamper 8 interrupt is enabled or not.
* @rmtoll TAMP_IER TAMP8IE LL_RTC_IsEnabledIT_TAMP8
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP8IE) == (TAMP_IER_TAMP8IE)) ? 1U : 0U);
}
#endif /* RTC_TAMP_NB */
#if defined (RTC_TAMP_INT_1_SUPPORT)
/**
* @brief Check if internal tamper 1 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP1IE LL_RTC_IsEnabledIT_ITAMP1
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_1_SUPPORT */
#if defined (RTC_TAMP_INT_2_SUPPORT)
/**
* @brief Check if internal tamper 2 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP2IE LL_RTC_IsEnabledIT_ITAMP2
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_2_SUPPORT */
/**
* @brief Check if internal tamper 3 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP3IE LL_RTC_IsEnabledIT_ITAMP3
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 4 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP4IE LL_RTC_IsEnabledIT_ITAMP4
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP4(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP4IE) == (TAMP_IER_ITAMP4IE)) ? 1U : 0U);
}
/**
* @brief Check if internal tamper 5 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP5IE LL_RTC_IsEnabledIT_ITAMP5
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U);
}
#if defined (RTC_TAMP_INT_6_SUPPORT)
/**
* @brief Check if internal tamper 6 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP6IE LL_RTC_IsEnabledIT_ITAMP6
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_6_SUPPORT */
#if defined (RTC_TAMP_INT_7_SUPPORT)
/**
* @brief Check if internal tamper 7 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP7IE LL_RTC_IsEnabledIT_ITAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_7_SUPPORT */
#if defined (RTC_TAMP_INT_8_SUPPORT)
/**
* @brief Check if internal tamper 7 interrupt is enabled or not.
* @rmtoll TAMP_IER ITAMP7IE LL_RTC_IsEnabledIT_ITAMP7
* @param RTCx RTC Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP7(RTC_TypeDef *RTCx)
{
UNUSED(RTCx);
return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP7IE) == (TAMP_IER_ITAMP7IE)) ? 1U : 0U);
}
#endif /* RTC_TAMP_INT_8_SUPPORT */
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);
void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);
ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);
void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);
ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);
void LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);
ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
void LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
void LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);
ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);
ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(RTC) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_RTC_H */
| 196,539 | C | 34.279124 | 199 | 0.622691 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_dac_ex.h
* @author MCD Application Team
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_DAC_EX_H
#define STM32G4xx_HAL_DAC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL State structures definition
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
/**
* @}
*/
/** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode
* @{
*/
#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */
#define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
#if defined(STM32G474xx) || defined(STM32G484xx)
#define IS_DAC_TRIGGER(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG1) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG2) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG3) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG4) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG5) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG6) || \
(((DACX) == DAC1) && \
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \
) || \
(((DACX) == DAC2) && \
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG02)) \
) || \
(((DACX) == DAC3) && \
(((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG03)) \
) || \
(((DACX) == DAC4) && \
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \
) \
)
#else
#define IS_DAC_TRIGGER(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
(((DACX) == DAC3) ? \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
: ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) \
)
#endif
#if defined(STM32G474xx) || defined(STM32G484xx)
#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG1) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG2) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG3) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG4) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG5) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG6) || \
(((DACX) == DAC1) && \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) || \
(((DACX) == DAC2) && \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) || \
(((DACX) == DAC3) && \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
) || \
(((DACX) == DAC4) && \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) \
)
#else
#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
(((DACX) == DAC3) ? \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
:((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) \
)
#endif
#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
((CONNECT) == DAC_CHIPCONNECT_BOTH))
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
((TRIMMING) == DAC_TRIMMING_USER))
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
#define IS_DAC_SAWTOOTH_POLARITY(POLARITY) (((POLARITY) == DAC_SAWTOOTH_POLARITY_DECREMENT) || \
((POLARITY) == DAC_SAWTOOTH_POLARITY_INCREMENT))
#define IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL)
#define IS_DAC_STEP_DATA(DATA) ((DATA) <= 0x0000FFFFUL)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Extended features functions ***********************************************/
/** @addtogroup DACEx_Exported_Functions
* @{
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,
uint32_t ResetData, uint32_t StepData);
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DACEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DACEx_Private_Functions
* @{
*/
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
/* are called by HAL_DAC_Start_DMA */
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_DAC_EX_H */
| 17,403 | C | 49.300578 | 178 | 0.476929 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal.h | /**
******************************************************************************
* @file stm32g4xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_H
#define STM32G4xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_conf.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup HAL HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
#define HAL_TICK_FREQ_10HZ 100U
#define HAL_TICK_FREQ_100HZ 10U
#define HAL_TICK_FREQ_1KHZ 1U
#define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_BOOT_MAINFLASH 0x00000000U
#define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMMEMRMP_MODE_0
#if defined (FMC_BANK1)
#define SYSCFG_BOOT_FMC SYSCFG_MEMMEMRMP_MODE_1
#endif /* FMC_BANK1 */
#define SYSCFG_BOOT_SRAM (SYSCFG_MEMMEMRMP_MODE_1 | SYSCFG_MEMMEMRMP_MODE_0)
#if defined (QUADSPI)
#define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMMEMRMP_MODE_2 | SYSCFG_MEMMEMRMP_MODE_1)
#endif /* QUADSPI */
/**
* @}
*/
/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
* @{
*/
#define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
#define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
#define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
#define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
#define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
#define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
/**
* @}
*/
/** @defgroup SYSCFG_CCMSRAMWRP CCM Write protection
* @{
*/
#define SYSCFG_CCMSRAMWRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_CCMSRAMWRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_CCMSRAMWRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_CCMSRAMWRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_CCMSRAMWRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_CCMSRAMWRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_CCMSRAMWRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_CCMSRAMWRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_CCMSRAMWRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_CCMSRAMWRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_CCMSRAMWRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< CCMSRAM Write protection page 10 */
#define SYSCFG_CCMSRAMWRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< CCMSRAM Write protection page 11 */
#define SYSCFG_CCMSRAMWRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< CCMSRAM Write protection page 12 */
#define SYSCFG_CCMSRAMWRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< CCMSRAM Write protection page 13 */
#define SYSCFG_CCMSRAMWRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< CCMSRAM Write protection page 14 */
#define SYSCFG_CCMSRAMWRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< CCMSRAM Write protection page 15 */
#define SYSCFG_CCMSRAMWRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< CCMSRAM Write protection page 16 */
#define SYSCFG_CCMSRAMWRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< CCMSRAM Write protection page 17 */
#define SYSCFG_CCMSRAMWRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< CCMSRAM Write protection page 18 */
#define SYSCFG_CCMSRAMWRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< CCMSRAM Write protection page 19 */
#define SYSCFG_CCMSRAMWRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< CCMSRAM Write protection page 20 */
#define SYSCFG_CCMSRAMWRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< CCMSRAM Write protection page 21 */
#define SYSCFG_CCMSRAMWRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< CCMSRAM Write protection page 22 */
#define SYSCFG_CCMSRAMWRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< CCMSRAM Write protection page 23 */
#define SYSCFG_CCMSRAMWRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< CCMSRAM Write protection page 24 */
#define SYSCFG_CCMSRAMWRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< CCMSRAM Write protection page 25 */
#define SYSCFG_CCMSRAMWRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< CCMSRAM Write protection page 26 */
#define SYSCFG_CCMSRAMWRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< CCMSRAM Write protection page 27 */
#define SYSCFG_CCMSRAMWRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< CCMSRAM Write protection page 28 */
#define SYSCFG_CCMSRAMWRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< CCMSRAM Write protection page 29 */
#define SYSCFG_CCMSRAMWRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< CCMSRAM Write protection page 30 */
#define SYSCFG_CCMSRAMWRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< CCMSRAM Write protection page 31 */
/**
* @}
*/
#if defined(VREFBUF)
/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0x00000000U /*!< Voltage reference scale 0 (VREFBUF_OUT = 2.048V) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREFBUF_OUT = 2.5V) */
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREFBUF_OUT = 2.9V) */
/**
* @}
*/
/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SYSCFG_flags_definition Flags
* @{
*/
#define SYSCFG_FLAG_SRAM_PE SYSCFG_CFGR2_SPF /*!< SRAM parity error (first 32kB of SRAM1 + CCM SRAM) */
#define SYSCFG_FLAG_CCMSRAM_BUSY SYSCFG_SCSR_CCMBSY /*!< CCMSRAM busy by erase operation */
/**
* @}
*/
/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_RTC_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C3_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_LPTIM1_STOP */
#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM1_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM8_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM15_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM16_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM17_STOP */
#if defined(DBGMCU_APB2FZ_DBG_TIM20_STOP)
#define __HAL_DBGMCU_FREEZE_TIM20() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM20() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM20_STOP)
#endif /* DBGMCU_APB2FZ_DBG_TIM20_STOP */
#if defined(DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_HRTIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_HRTIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_HRTIM1_STOP)
#endif /* DBGMCU_APB2FZ_DBG_HRTIM1_STOP */
/**
* @}
*/
/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
* @{
*/
/** @brief Main Flash memory mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief System Flash memory mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
/** @brief Embedded SRAM mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
#if defined (FMC_BANK1)
/** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
#endif /* FMC_BANK1 */
#if defined (QUADSPI)
/** @brief QUADSPI mapped at 0x00000000.
*/
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
#endif /* QUADSPI */
/**
* @brief Return the boot mode as configured by user.
* @retval The boot mode as configured by user. The returned value can be one
* of the following values:
* @arg @ref SYSCFG_BOOT_MAINFLASH
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH
* @arg @ref SYSCFG_BOOT_FMC (*)
* @arg @ref SYSCFG_BOOT_QUADSPI (*)
* @arg @ref SYSCFG_BOOT_SRAM
* @note (*) availability depends on devices
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
/** @brief CCMSRAM page write protection enable macro
* @param __CCMSRAMWRP__: This parameter can be a value of @ref SYSCFG_CCMSRAMWRP
* @note write protection can only be disabled by a system reset
* @retval None
*/
/* Legacy define */
#define __HAL_SYSCFG_CCMSRAM_WRP_1_31_ENABLE __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE
#define __HAL_SYSCFG_CCMSRAM_WRP_0_31_ENABLE(__CCMSRAMWRP__) do {assert_param(IS_SYSCFG_CCMSRAMWRP_PAGE((__CCMSRAMWRP__)));\
SET_BIT(SYSCFG->SWPR,(__CCMSRAMWRP__));\
}while(0)
/** @brief CCMSRAM page write protection unlock prior to erase
* @note Writing a wrong key reactivates the write protection
*/
#define __HAL_SYSCFG_CCMSRAM_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\
SYSCFG->SKR = 0x53;\
}while(0)
/** @brief CCMSRAM erase
* @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_CCMSRAM_BUSY) may be used to check end of erase
*/
#define __HAL_SYSCFG_CCMSRAM_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_CCMER)
/** @brief Floating Point Unit interrupt enable/disable macros
* @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
*/
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
}while(0)
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
}while(0)
/** @brief SYSCFG Break ECC lock.
* Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
/** @brief SYSCFG Break Cortex-M4 Lockup lock.
* Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
/** @brief SYSCFG Break PVD lock.
* Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
/** @brief SYSCFG Break SRAM parity lock.
* Enable and lock the SRAM parity error (first 32kB of SRAM1 + CCM SRAM) signal connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked by system reset.
*/
#define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
/** @brief Check SYSCFG flag is set or not.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SYSCFG_FLAG_SRAM_PE SRAM Parity Error Flag
* @arg @ref SYSCFG_FLAG_CCMSRAM_BUSY CCMSRAM Erase Ongoing
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_CCMBSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\
& (__FLAG__))!= 0U) ? 1U : 0U)
/** @brief Set the SPF bit to clear the SRAM Parity Error Flag.
*/
#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__: This parameter can be a value of :
* @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
}while(0)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
* @{
*/
#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
(((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \
((__CONFIG__) == SYSCFG_BREAK_PVD) || \
((__CONFIG__) == SYSCFG_BREAK_SRAMPARITY) || \
((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
#if (CCMSRAM_SIZE == 0x00008000UL) || (CCMSRAM_SIZE == 0x00004000UL)
#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) ((__PAGE__) > 0U)
#elif (CCMSRAM_SIZE == 0x00002800UL)
#define IS_SYSCFG_CCMSRAMWRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0x000003FFU))
#endif /* CCMSRAM_SIZE */
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2))
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#endif /* VREFBUF */
#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#elif defined(SYSCFG_FASTMODEPLUS_PB8)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
#elif defined(SYSCFG_FASTMODEPLUS_PB9)
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#else
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
#endif /* SYSCFG_FASTMODEPLUS_PB */
/**
* @}
*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and Configuration functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq);
uint32_t HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @{
*/
/* DBGMCU Peripheral Control functions *****************************************/
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/* Exported variables ---------------------------------------------------------*/
/** @addtogroup HAL_Exported_Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern uint32_t uwTickFreq;
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group4
* @{
*/
/* SYSCFG Control functions ****************************************************/
void HAL_SYSCFG_CCMSRAMErase(void);
void HAL_SYSCFG_EnableMemorySwappingBank(void);
void HAL_SYSCFG_DisableMemorySwappingBank(void);
#if defined(VREFBUF)
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void);
#endif /* VREFBUF */
void HAL_SYSCFG_EnableIOSwitchBooster(void);
void HAL_SYSCFG_DisableIOSwitchBooster(void);
void HAL_SYSCFG_EnableIOSwitchVDD(void);
void HAL_SYSCFG_DisableIOSwitchVDD(void);
void HAL_SYSCFG_CCMSRAM_WriteProtectionEnable(uint32_t Page);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_H */
| 27,896 | C | 43.6352 | 150 | 0.619515 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_spi_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_spi_ex.h
* @author MCD Application Team
* @brief Header file of SPI HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SPI_EX_H
#define STM32G4xx_HAL_SPI_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SPIEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SPIEx_Exported_Functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
/* IO operation functions *****************************************************/
/** @addtogroup SPIEx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SPI_EX_H */
| 1,858 | C | 24.121621 | 80 | 0.412809 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dma_ex.h | /**
******************************************************************************
* @file stm32g4xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32G4xx_HAL_DMA_EX_H
#define __STM32G4xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @{
*/
/**
* @brief HAL DMA Synchro definition
*/
/**
* @brief HAL DMAMUX Synchronization configuration structure definition
*/
typedef struct
{
uint32_t SyncSignalID; /*!< Specifies the synchronization signal gating the DMA request in periodic mode.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncSignalID_selection */
uint32_t SyncPolarity; /*!< Specifies the polarity of the signal on which the DMA request is synchronized.
This parameter can be a value of @ref DMAEx_DMAMUX_SyncPolarity_selection */
FunctionalState SyncEnable; /*!< Specifies if the synchronization shall be enabled or disabled
This parameter can take the value ENABLE or DISABLE*/
FunctionalState EventEnable; /*!< Specifies if an event shall be generated once the RequestNumber is reached.
This parameter can take the value ENABLE or DISABLE */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
} HAL_DMA_MuxSyncConfigTypeDef;
/**
* @brief HAL DMAMUX request generator parameters structure definition
*/
typedef struct
{
uint32_t SignalID; /*!< Specifies the ID of the signal used for DMAMUX request generator
This parameter can be a value of @ref DMAEx_DMAMUX_SignalGeneratorID_selection */
uint32_t Polarity; /*!< Specifies the polarity of the signal on which the request is generated.
This parameter can be a value of @ref DMAEx_DMAMUX_RequestGeneneratorPolarity_selection */
uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be generated after a signal event
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
} HAL_DMA_MuxRequestGeneratorConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @{
*/
/** @defgroup DMAEx_DMAMUX_SyncSignalID_selection DMAMUX SyncSignalID selection
* @{
*/
#define HAL_DMAMUX1_SYNC_EXTI0 0U /*!< Synchronization Signal is EXTI0 IT */
#define HAL_DMAMUX1_SYNC_EXTI1 1U /*!< Synchronization Signal is EXTI1 IT */
#define HAL_DMAMUX1_SYNC_EXTI2 2U /*!< Synchronization Signal is EXTI2 IT */
#define HAL_DMAMUX1_SYNC_EXTI3 3U /*!< Synchronization Signal is EXTI3 IT */
#define HAL_DMAMUX1_SYNC_EXTI4 4U /*!< Synchronization Signal is EXTI4 IT */
#define HAL_DMAMUX1_SYNC_EXTI5 5U /*!< Synchronization Signal is EXTI5 IT */
#define HAL_DMAMUX1_SYNC_EXTI6 6U /*!< Synchronization Signal is EXTI6 IT */
#define HAL_DMAMUX1_SYNC_EXTI7 7U /*!< Synchronization Signal is EXTI7 IT */
#define HAL_DMAMUX1_SYNC_EXTI8 8U /*!< Synchronization Signal is EXTI8 IT */
#define HAL_DMAMUX1_SYNC_EXTI9 9U /*!< Synchronization Signal is EXTI9 IT */
#define HAL_DMAMUX1_SYNC_EXTI10 10U /*!< Synchronization Signal is EXTI10 IT */
#define HAL_DMAMUX1_SYNC_EXTI11 11U /*!< Synchronization Signal is EXTI11 IT */
#define HAL_DMAMUX1_SYNC_EXTI12 12U /*!< Synchronization Signal is EXTI12 IT */
#define HAL_DMAMUX1_SYNC_EXTI13 13U /*!< Synchronization Signal is EXTI13 IT */
#define HAL_DMAMUX1_SYNC_EXTI14 14U /*!< Synchronization Signal is EXTI14 IT */
#define HAL_DMAMUX1_SYNC_EXTI15 15U /*!< Synchronization Signal is EXTI15 IT */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 16U /*!< Synchronization Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 17U /*!< Synchronization Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 18U /*!< Synchronization Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH3_EVT 19U /*!< Synchronization Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_SYNC_LPTIM1_OUT 20U /*!< Synchronization Signal is LPTIM1 OUT */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_SyncPolarity_selection DMAMUX SyncPolarity selection
* @{
*/
#define HAL_DMAMUX_SYNC_NO_EVENT 0U /*!< block synchronization events */
#define HAL_DMAMUX_SYNC_RISING ((uint32_t)DMAMUX_CxCR_SPOL_0) /*!< synchronize with rising edge events */
#define HAL_DMAMUX_SYNC_FALLING ((uint32_t)DMAMUX_CxCR_SPOL_1) /*!< synchronize with falling edge events */
#define HAL_DMAMUX_SYNC_RISING_FALLING ((uint32_t)DMAMUX_CxCR_SPOL) /*!< synchronize with rising and falling edge events */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_SignalGeneratorID_selection DMAMUX SignalGeneratorID selection
* @{
*/
#define HAL_DMAMUX1_REQ_GEN_EXTI0 0U /*!< Request generator Signal is EXTI0 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI1 1U /*!< Request generator Signal is EXTI1 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI2 2U /*!< Request generator Signal is EXTI2 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI3 3U /*!< Request generator Signal is EXTI3 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI4 4U /*!< Request generator Signal is EXTI4 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI5 5U /*!< Request generator Signal is EXTI5 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI6 6U /*!< Request generator Signal is EXTI6 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI7 7U /*!< Request generator Signal is EXTI7 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI8 8U /*!< Request generator Signal is EXTI8 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI9 9U /*!< Request generator Signal is EXTI9 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI10 10U /*!< Request generator Signal is EXTI10 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI11 11U /*!< Request generator Signal is EXTI11 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI12 12U /*!< Request generator Signal is EXTI12 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI13 13U /*!< Request generator Signal is EXTI13 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI14 14U /*!< Request generator Signal is EXTI14 IT */
#define HAL_DMAMUX1_REQ_GEN_EXTI15 15U /*!< Request generator Signal is EXTI15 IT */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 16U /*!< Request generator Signal is DMAMUX1 Channel0 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 17U /*!< Request generator Signal is DMAMUX1 Channel1 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 18U /*!< Request generator Signal is DMAMUX1 Channel2 Event */
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT 19U /*!< Request generator Signal is DMAMUX1 Channel3 Event */
#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT 20U /*!< Request generator Signal is LPTIM1 OUT */
/**
* @}
*/
/** @defgroup DMAEx_DMAMUX_RequestGeneneratorPolarity_selection DMAMUX RequestGeneneratorPolarity selection
* @{
*/
#define HAL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< block request generator events */
#define HAL_DMAMUX_REQ_GEN_RISING DMAMUX_RGxCR_GPOL_0 /*!< generate request on rising edge events */
#define HAL_DMAMUX_REQ_GEN_FALLING DMAMUX_RGxCR_GPOL_1 /*!< generate request on falling edge events */
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING DMAMUX_RGxCR_GPOL /*!< generate request on rising and falling edge events */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DMAEx_Exported_Functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup DMAEx_Exported_Functions_Group1
* @{
*/
/* ------------------------- REQUEST -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator(DMA_HandleTypeDef *hdma,
HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);
HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator(DMA_HandleTypeDef *hdma);
/* -------------------------------------------------------------------------- */
/* ------------------------- SYNCHRO -----------------------------------------*/
HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);
/* -------------------------------------------------------------------------- */
void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
* @brief DMAEx private macros
* @{
*/
#define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_LPTIM1_OUT)
#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING) || \
((POLARITY) == HAL_DMAMUX_SYNC_FALLING) || \
((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))
#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE) || ((SYNC) == ENABLE))
#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE) || \
((EVENT) == ENABLE))
#define IS_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT)
#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))
#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING) || \
((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32G4xx_HAL_DMA_EX_H */
| 12,347 | C | 45.596226 | 124 | 0.561027 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_rtc.h | /**
******************************************************************************
* @file stm32g4xx_hal_rtc.h
* @author MCD Application Team
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_RTC_H
#define STM32G4xx_HAL_RTC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @defgroup RTC RTC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup RTC_Exported_Types RTC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
} HAL_RTCStateTypeDef;
/**
* @brief RTC Configuration Structure definition
*/
typedef struct
{
uint32_t HourFormat; /*!< Specifies the RTC Hour Format.
This parameter can be a value of @ref RTC_Hour_Formats */
uint32_t AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output.
This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
uint32_t OutPutRemap; /*!< Specifies the remap for RTC output.
This parameter can be a value of @ref RTC_Output_ALARM_OUT_Remap */
uint32_t OutPutPolarity; /*!< Specifies the polarity of the output signal.
This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode.
This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
uint32_t OutPutPullUp; /*!< Specifies the RTC Output Pull-Up mode.
This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
} RTC_InitTypeDef;
/**
* @brief RTC Time structure definition
*/
typedef struct
{
uint8_t Hours; /*!< Specifies the RTC Time Hour.
This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
uint8_t Minutes; /*!< Specifies the RTC Time Minutes.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time,
please use HAL_RTC_DST_xxx functions */
uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time,
please use HAL_RTC_DST_xxx functions */
} RTC_TimeTypeDef;
/**
* @brief RTC Date structure definition
*/
typedef struct
{
uint8_t WeekDay; /*!< Specifies the RTC Date WeekDay.
This parameter can be a value of @ref RTC_WeekDay_Definitions */
uint8_t Month; /*!< Specifies the RTC Date Month (in BCD format).
This parameter can be a value of @ref RTC_Month_Date_Definitions */
uint8_t Date; /*!< Specifies the RTC Date.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
uint8_t Year; /*!< Specifies the RTC Date Year.
This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
} RTC_DateTypeDef;
/**
* @brief RTC Alarm structure definition
*/
typedef struct
{
RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members */
uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks.
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
uint32_t AlarmSubSecondMask; /*!< Specifies the RTC Alarm SubSeconds Masks.
This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
uint32_t Alarm; /*!< Specifies the alarm .
This parameter can be a value of @ref RTC_Alarms_Definitions */
} RTC_AlarmTypeDef;
/**
* @brief RTC Handle Structure definition
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
typedef struct __RTC_HandleTypeDef
#else
typedef struct
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
{
RTC_TypeDef *Instance; /*!< Legacy register base address. Not used anymore,
the driver directly uses cmsis base address */
RTC_InitTypeDef Init; /*!< RTC required parameters */
HAL_LockTypeDef Lock; /*!< RTC locking object */
__IO HAL_RTCStateTypeDef State; /*!< Time communication state */
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */
void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */
void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC TimeStamp Event callback */
void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */
void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */
void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */
#if (RTC_TAMP_NB == 3)
void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 3 Event callback */
#endif /* RTC_TAMP_NB */
void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 1 Event callback */
#ifdef RTC_TAMP_INT_2_SUPPORT
void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 2 Event callback */
#endif /* RTC_TAMP_INT_2_SUPPORT */
void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 3 Event callback */
void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 4 Event callback */
void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 5 Event callback */
#ifdef RTC_TAMP_INT_6_SUPPORT
void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 6 Event callback */
#endif /* RTC_TAMP_INT_6_SUPPORT */
#ifdef RTC_TAMP_INT_7_SUPPORT
void (* InternalTamper7EventCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Internal Tamper 7 Event callback */
#endif /* RTC_TAMP_INT_7_SUPPORT */
void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */
void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */
#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
} RTC_HandleTypeDef;
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL LPTIM Callback ID enumeration definition
*/
typedef enum
{
HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID = 0x07U, /*!< RTC Internal Tamper 1 Callback ID */
HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID = 0x08U, /*!< RTC Internal Tamper 2 Callback ID */
HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID = 0x09U, /*!< RTC Internal Tamper 3 Callback ID */
HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID = 0x0AU, /*!< RTC Internal Tamper 4 Callback ID */
HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID = 0x0BU, /*!< RTC Internal Tamper 5 Callback ID */
HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID = 0x0CU, /*!< RTC Internal Tamper 6 Callback ID */
HAL_RTC_INTERNAL_TAMPER7_EVENT_CB_ID = 0x0DU, /*!< RTC Internal Tamper 7 Callback ID */
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
} HAL_RTC_CallbackIDTypeDef;
/**
* @brief HAL RTC Callback pointer definition
*/
typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup RTC_Exported_Constants RTC Exported Constants
* @{
*/
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 0x00000000U
#define RTC_HOURFORMAT_12 RTC_CR_FMT
/**
* @}
*/
/** @defgroup RTCEx_Output_selection_Definitions RTCEx Output Selection Definition
* @{
*/
#define RTC_OUTPUT_DISABLE 0x00000000U
#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0
#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1
#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL
#define RTC_OUTPUT_TAMPER RTC_CR_TAMPOE
/**
* @}
*/
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH 0x00000000U
#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL
/**
* @}
*/
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_PUSHPULL 0x00000000U
#define RTC_OUTPUT_TYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE
/**
* @}
*/
/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
* @{
*/
#define RTC_OUTPUT_PULLUP_NONE 0x00000000U
#define RTC_OUTPUT_PULLUP_ON RTC_CR_TAMPALRM_PU
/**
* @}
*/
/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
* @{
*/
#define RTC_OUTPUT_REMAP_NONE 0x00000000U
#define RTC_OUTPUT_REMAP_POS1 RTC_CR_OUT2EN
/**
* @}
*/
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM 0x0U
#define RTC_HOURFORMAT12_PM 0x1U
/**
* @}
*/
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H
#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H
#define RTC_DAYLIGHTSAVING_NONE 0x00000000U
/**
* @}
*/
/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET 0x00000000U
#define RTC_STOREOPERATION_SET RTC_CR_BKP
/**
* @}
*/
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
#define RTC_FORMAT_BIN 0x00000000U
#define RTC_FORMAT_BCD 0x00000001U
/**
* @}
*/
/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
* @{
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
#define RTC_MONTH_MAY ((uint8_t)0x05U)
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
#define RTC_MONTH_JULY ((uint8_t)0x07U)
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
/**
* @}
*/
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL
/**
* @}
*/
/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE 0x00000000U
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | RTC_ALARMMASK_HOURS | \
RTC_ALARMMASK_MINUTES | RTC_ALARMMASK_SECONDS)
/**
* @}
*/
/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
* @{
*/
#define RTC_ALARM_A RTC_CR_ALRAE
#define RTC_ALARM_B RTC_CR_ALRBE
/**
* @}
*/
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] not used in Alarm
comparison. Only SS[0] is compared. */
#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] not used in Alarm
comparison. Only SS[1:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) /*!< SS[14:3] not used in Alarm
comparison. Only SS[2:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] not used in Alarm
comparison. Only SS[3:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:5] not used in Alarm
comparison. Only SS[4:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:6] not used in Alarm
comparison. Only SS[5:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) /*!< SS[14:7] not used in Alarm
comparison. Only SS[6:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] not used in Alarm
comparison. Only SS[7:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:9] not used in Alarm
comparison. Only SS[8:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:10] not used in Alarm
comparison. Only SS[9:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:11] not used in Alarm
comparison. Only SS[10:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:12] not used in Alarm
comparison.Only SS[11:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14:13] not used in Alarm
comparison. Only SS[12:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) /*!< SS[14] not used in Alarm
comparison. Only SS[13:0] are compared */
#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match
to activate alarm. */
/**
* @}
*/
/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
* @{
*/
#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */
#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */
#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */
#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */
/**
* @}
*/
/** @defgroup RTC_Flag_Mask RTC Flag Mask (5bits) describe in RTC_Flags_Definitions
* @{
*/
#define RTC_FLAG_MASK 0x001FU /*!< RTC flags mask (5bits) */
/**
* @}
*/
/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
* Elements values convention: 000000XX000YYYYYb
* - YYYYY : Interrupt flag position in the XX register (5bits)
* - XX : Interrupt status register (2bits)
* - 01: ICSR register
* - 10: SR or SCR or MISR registers
* @{
*/
#define RTC_FLAG_RECALPF (0x00000100U | RTC_ICSR_RECALPF_Pos) /*!< Recalibration pending Flag */
#define RTC_FLAG_INITF (0x00000100U | RTC_ICSR_INITF_Pos) /*!< Initialization flag */
#define RTC_FLAG_RSF (0x00000100U | RTC_ICSR_RSF_Pos) /*!< Registers synchronization flag */
#define RTC_FLAG_INITS (0x00000100U | RTC_ICSR_INITS_Pos) /*!< Initialization status flag */
#define RTC_FLAG_SHPF (0x00000100U | RTC_ICSR_SHPF_Pos) /*!< Shift operation pending flag */
#define RTC_FLAG_WUTWF (0x00000100U | RTC_ICSR_WUTWF_Pos) /*!< Wakeup timer write flag */
#define RTC_FLAG_ALRBWF (0x00000100U | RTC_ICSR_ALRBWF_Pos) /*!< Alarm B write flag */
#define RTC_FLAG_ALRAWF (0x00000100U | RTC_ICSR_ALRAWF_Pos) /*!< Alarm A write flag */
#define RTC_FLAG_ITSF (0x00000200U | RTC_SR_ITSF_Pos) /*!< Internal Time-stamp flag */
#define RTC_FLAG_TSOVF (0x00000200U | RTC_SR_TSOVF_Pos) /*!< Time-stamp overflow flag */
#define RTC_FLAG_TSF (0x00000200U | RTC_SR_TSF_Pos) /*!< Time-stamp flag */
#define RTC_FLAG_WUTF (0x00000200U | RTC_SR_WUTF_Pos) /*!< Wakeup timer flag */
#define RTC_FLAG_ALRBF (0x00000200U | RTC_SR_ALRBF_Pos) /*!< Alarm B flag */
#define RTC_FLAG_ALRAF (0x00000200U | RTC_SR_ALRAF_Pos) /*!< Alarm A flag */
/**
* @}
*/
/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
* @{
*/
#define RTC_CLEAR_ITSF RTC_SCR_CITSF /*!< Clear Internal Time-stamp flag */
#define RTC_CLEAR_TSOVF RTC_SCR_CTSOVF /*!< Clear Time-stamp overflow flag */
#define RTC_CLEAR_TSF RTC_SCR_CTSF /*!< Clear Time-stamp flag */
#define RTC_CLEAR_WUTF RTC_SCR_CWUTF /*!< Clear Wakeup timer flag */
#define RTC_CLEAR_ALRBF RTC_SCR_CALRBF /*!< Clear Alarm B flag */
#define RTC_CLEAR_ALRAF RTC_SCR_CALRAF /*!< Clear Alarm A flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup RTC_Exported_Macros RTC Exported Macros
* @{
*/
/** @brief Reset RTC handle state
* @param __HANDLE__ RTC handle.
* @retval None
*/
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
(__HANDLE__)->State = HAL_RTC_STATE_RESET;\
(__HANDLE__)->MspInitCallback = NULL;\
(__HANDLE__)->MspDeInitCallback = NULL;\
}while(0)
#else
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @brief Disable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xCAU; \
(__HANDLE__)->Instance->WPR = 0x53U; \
} while(0U)
/**
* @brief Enable the write protection for RTC registers.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
do{ \
(__HANDLE__)->Instance->WPR = 0xFFU; \
} while(0U)
/**
* @brief Add 1 hour (summer time change).
* @note This interface is deprecated.
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
* @param __HANDLE__ specifies the RTC handle.
* @param __BKP__ Backup
* This parameter can be:
* @arg @ref RTC_STOREOPERATION_RESET
* @arg @ref RTC_STOREOPERATION_SET
* @retval None
*/
#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \
do { \
__HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H); \
MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
__HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
} while(0);
/**
* @brief Subtract 1 hour (winter time change).
* @note This interface is deprecated.
* To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions
* @param __HANDLE__ specifies the RTC handle.
* @param __BKP__ Backup
* This parameter can be:
* @arg @ref RTC_STOREOPERATION_RESET
* @arg @ref RTC_STOREOPERATION_SET
* @retval None
*/
#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \
do { \
__HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \
SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H); \
MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
__HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \
} while(0);
/**
* @brief Enable the RTC ALARMA peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
/**
* @brief Disable the RTC ALARMA peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
/**
* @brief Enable the RTC ALARMB peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
/**
* @brief Disable the RTC ALARMB peripheral.
* @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
/**
* @brief Enable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg @ref RTC_IT_ALRA Alarm A interrupt
* @arg @ref RTC_IT_ALRB Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the RTC Alarm interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg @ref RTC_IT_ALRA Alarm A interrupt
* @arg @ref RTC_IT_ALRB Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg @ref RTC_IT_ALRA Alarm A interrupt
* @arg @ref RTC_IT_ALRB Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg @ref RTC_IT_ALRA Alarm A interrupt
* @arg @ref RTC_IT_ALRB Alarm B interrupt
* @retval None
*/
#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)
/**
* @brief Get the selected RTC Alarms flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Alarm Flag sources to check.
* This parameter can be:
* @arg @ref RTC_FLAG_ALRAF
* @arg @ref RTC_FLAG_ALRBF
* @arg @ref RTC_FLAG_ALRAWF
* @arg @ref RTC_FLAG_ALRBWF
* @retval None
*/
#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))
/**
* @brief Clear the RTC Alarms pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Alarm Flag sources to clear.
* This parameter can be:
* @arg @ref RTC_FLAG_ALRAF
* @arg @ref RTC_FLAG_ALRBF
* @retval None
*/
#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? (((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRAF))) : \
((__HANDLE__)->Instance->SCR = (RTC_CLEAR_ALRBF)))
/**
* @brief Enable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable event on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable event on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief Disable rising edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
/**
* @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
__HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief set rising edge interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_RISING_IT() (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief set rising edge interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_FALLING_IT() (EXTI->FSTR1 |= RTC_EXTI_LINE_ALARM_EVENT)
/**
* @brief clear interrupt on the RTC Alarm associated Exti line.
* @retval None
*/
#define __HAL_RTC_ALARM_EXTI_CLEAR_IT() (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
/**
* @}
*/
/* Include RTC HAL Extended module */
#include "stm32g4xx_hal_rtc_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @defgroup RTC_Exported_Functions RTC Exported Functions
* @{
*/
/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID,
pRTC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
* @{
*/
/* RTC Time and Date functions ************************************************/
HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc);
void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc);
uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
* @{
*/
/* RTC Alarm functions ********************************************************/
HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
* @{
*/
/* Peripheral State functions *************************************************/
HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup RTC_Private_Constants RTC Private Constants
* @{
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \
RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \
RTC_TR_SU)
#define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \
RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \
RTC_DR_DU)
#define RTC_INIT_MASK 0xFFFFFFFFU
#define RTC_TIMEOUT_VALUE 1000U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup RTC_Private_Macros RTC Private Macros
* @{
*/
/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
* @{
*/
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
((OUTPUT) == RTC_OUTPUT_ALARMA) || \
((OUTPUT) == RTC_OUTPUT_ALARMB) || \
((OUTPUT) == RTC_OUTPUT_WAKEUP) || \
((OUTPUT) == RTC_OUTPUT_TAMPER))
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \
((FORMAT) == RTC_HOURFORMAT_24))
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
((POL) == RTC_OUTPUT_POLARITY_LOW))
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
((TYPE) == RTC_OUTPUT_PULLUP_ON))
#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
((REMAP) == RTC_OUTPUT_REMAP_POS1))
#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \
((PM) == RTC_HOURFORMAT12_PM))
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
((SAVE) == RTC_DAYLIGHTSAVING_NONE))
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
((OPERATION) == RTC_STOREOPERATION_SET))
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
((FORMAT) == RTC_FORMAT_BCD))
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99u)
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1u) && ((MONTH) <= 12u))
#define IS_RTC_DATE(DATE) (((DATE) >= 1u) && ((DATE) <= 31u))
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >0u) && ((DATE) <= 31u))
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \
((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \
((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \
((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0UL)
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || \
((ALARM) == RTC_ALARM_B))
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \
(((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0u) && ((HOUR) <= 12u))
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23u)
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59u)
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59u)
/**
* @}
*/
/**
* @}
*/
/* Private functions -------------------------------------------------------------*/
/** @defgroup RTC_Private_Functions RTC Private Functions
* @{
*/
HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc);
uint8_t RTC_ByteToBcd2(uint8_t Value);
uint8_t RTC_Bcd2ToByte(uint8_t Value);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_RTC_H */
| 45,363 | C | 43.781836 | 164 | 0.529374 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h | /**
******************************************************************************
* @file stm32g4xx_hal_comp.h
* @author MCD Application Team
* @brief Header file of COMP HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_COMP_H
#define STM32G4xx_HAL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#include "stm32g4xx_ll_exti.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup COMP
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types
* @{
*/
/**
* @brief COMP Init structure definition
*/
typedef struct
{
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
This parameter can be a value of @ref COMP_InputPlus */
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
This parameter can be a value of @ref COMP_InputMinus */
uint32_t Hysteresis; /*!< Set comparator hysteresis mode of the input minus.
This parameter can be a value of @ref COMP_Hysteresis */
uint32_t OutputPol; /*!< Set comparator output polarity.
This parameter can be a value of @ref COMP_OutputPolarity */
uint32_t BlankingSrce; /*!< Set comparator blanking source.
This parameter can be a value of @ref COMP_BlankingSrce */
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
This parameter can be a value of @ref COMP_EXTI_TriggerMode */
} COMP_InitTypeDef;
/**
* @brief HAL COMP state machine: HAL COMP states definition
*/
#define COMP_STATE_BITFIELD_LOCK (0x10U)
typedef enum
{
HAL_COMP_STATE_RESET = 0x00U, /*!< COMP not yet initialized */
HAL_COMP_STATE_RESET_LOCKED = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
HAL_COMP_STATE_READY = 0x01U, /*!< COMP initialized and ready for use */
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
} HAL_COMP_StateTypeDef;
/**
* @brief COMP Handle Structure definition
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
typedef struct __COMP_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
{
COMP_TypeDef *Instance; /*!< Register base address */
COMP_InitTypeDef Init; /*!< COMP required parameters */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */
__IO uint32_t ErrorCode; /*!< COMP error code */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP trigger callback */
void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp Init callback */
void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
} COMP_HandleTypeDef;
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/**
* @brief HAL COMP Callback ID enumeration definition
*/
typedef enum
{
HAL_COMP_TRIGGER_CB_ID = 0x00U, /*!< COMP trigger callback ID */
HAL_COMP_MSPINIT_CB_ID = 0x01U, /*!< COMP Msp Init callback ID */
HAL_COMP_MSPDEINIT_CB_ID = 0x02U /*!< COMP Msp DeInit callback ID */
} HAL_COMP_CallbackIDTypeDef;
/**
* @brief HAL COMP Callback pointer definition
*/
typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_Error_Code COMP Error Code
* @{
*/
#define HAL_COMP_ERROR_NONE (0x00UL) /*!< No error */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL) /*!< Invalid Callback error */
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
* @{
*/
#define COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL) /*!< Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
/**
* @}
*/
/** @defgroup COMP_InputMinus COMP input minus (inverting input)
* @{
*/
#define COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
#define COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
#define COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
/**
* @}
*/
/** @defgroup COMP_Hysteresis COMP hysteresis
* @{
*/
#define COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
#define COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0) /*!< Hysteresis level 10mV */
#define COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 ) /*!< Hysteresis level 20mV */
#define COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 30mV */
#define COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 ) /*!< Hysteresis level 40mV */
#define COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0) /*!< Hysteresis level 50mV */
#define COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 ) /*!< Hysteresis level 60mV */
#define COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 70mV */
#define COMP_HYSTERESIS_LOW COMP_HYSTERESIS_10MV /*!< Hysteresis level low */
#define COMP_HYSTERESIS_MEDIUM COMP_HYSTERESIS_40MV /*!< Hysteresis level medium */
#define COMP_HYSTERESIS_HIGH COMP_HYSTERESIS_70MV /*!< Hysteresis level high */
/**
* @}
*/
/** @defgroup COMP_OutputPolarity COMP output Polarity
* @{
*/
#define COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
#define COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output level is inverted (comparator output is low when the input plus is at a higher voltage than the input minus) */
/**
* @}
*/
/** @defgroup COMP_BlankingSrce COMP blanking source
* @{
*/
#define COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
#define COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
#define COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM20 OC5 (Common to all COMP instances) */
#define COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM15 OC1 (Common to all COMP instances) */
#define COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM4 OC3 (Common to all COMP instances) */
/**
* @}
*/
/** @defgroup COMP_OutputLevel COMP Output Level
* @{
*/
/* Note: Comparator output level values are fixed to "0" and "1", */
/* corresponding COMP register bit is managed by HAL function to match */
/* with these values (independently of bit position in register). */
/* When output polarity is not inverted, comparator output is low when
the input plus is at a lower voltage than the input minus */
#define COMP_OUTPUT_LEVEL_LOW (0x00000000UL)
/* When output polarity is not inverted, comparator output is high when
the input plus is at a higher voltage than the input minus */
#define COMP_OUTPUT_LEVEL_HIGH (0x00000001UL)
/**
* @}
*/
/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
* @{
*/
#define COMP_TRIGGERMODE_NONE (0x00000000UL) /*!< Comparator output triggering no External Interrupt Line */
#define COMP_TRIGGERMODE_IT_RISING (COMP_EXTI_IT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
#define COMP_TRIGGERMODE_IT_FALLING (COMP_EXTI_IT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
#define COMP_TRIGGERMODE_IT_RISING_FALLING (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
#define COMP_TRIGGERMODE_EVENT_RISING (COMP_EXTI_EVENT | COMP_EXTI_RISING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
#define COMP_TRIGGERMODE_EVENT_FALLING (COMP_EXTI_EVENT | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING) /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Macros COMP Exported Macros
* @{
*/
/** @defgroup COMP_Handle_Management COMP Handle Management
* @{
*/
/** @brief Reset COMP handle state.
* @param __HANDLE__ COMP handle
* @retval None
*/
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
* @param __HANDLE__ COMP handle
* @retval None
*/
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/**
* @brief Enable the specified comparator.
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
/**
* @brief Disable the specified comparator.
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
/**
* @brief Lock the specified comparator configuration.
* @note Using this macro induce HAL COMP handle state machine being no
* more in line with COMP instance state.
* To keep HAL COMP handle state machine updated, it is recommended
* to use function "HAL_COMP_Lock')".
* @param __HANDLE__ COMP handle
* @retval None
*/
#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
/**
* @brief Check whether the specified comparator is locked.
* @param __HANDLE__ COMP handle
* @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
*/
#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
/**
* @}
*/
/** @defgroup COMP_Exti_Management COMP external interrupt line management
* @{
*/
/**
* @brief Enable the COMP1 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
} while(0)
/**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
} while(0)
/**
* @brief Enable the COMP1 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Generate a software interrupt on the COMP1 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP1 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Disable the COMP1 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Check whether the COMP1 EXTI line flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP1_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Clear the COMP1 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
/**
* @brief Enable the COMP2 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
} while(0)
/**
* @brief Disable the COMP2 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \
} while(0)
/**
* @brief Enable the COMP2 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Generate a software interrupt on the COMP2 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP2 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Disable the COMP2 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Check whether the COMP2 EXTI line flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP2_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Clear the COMP2 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
/**
* @brief Enable the COMP3 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Disable the COMP3 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Enable the COMP3 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Disable the COMP3 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Enable the COMP3 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
} while(0)
/**
* @brief Disable the COMP3 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3); \
} while(0)
/**
* @brief Enable the COMP3 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Disable the COMP3 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Generate a software interrupt on the COMP3 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Enable the COMP3 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Disable the COMP3 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Check whether the COMP3 EXTI line flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP3_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Clear the COMP3 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP3)
/**
* @brief Enable the COMP4 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Disable the COMP4 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Enable the COMP4 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Disable the COMP4 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Enable the COMP4 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
} while(0)
/**
* @brief Disable the COMP4 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4); \
} while(0)
/**
* @brief Enable the COMP4 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Disable the COMP4 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Generate a software interrupt on the COMP4 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Enable the COMP4 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Disable the COMP4 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Check whether the COMP4 EXTI line flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP4_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP4)
/**
* @brief Clear the COMP4 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP5 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Disable the COMP5 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Enable the COMP5 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Disable the COMP5 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Enable the COMP5 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \
} while(0)
/**
* @brief Disable the COMP5 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5); \
} while(0)
/**
* @brief Enable the COMP5 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Disable the COMP5 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Generate a software interrupt on the COMP5 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Enable the COMP5 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Disable the COMP5 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Check whether the COMP5 EXTI line flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP5_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP5)
/**
* @brief Clear the COMP5 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP5)
#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP6 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Disable the COMP6 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Enable the COMP6 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Disable the COMP6 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Enable the COMP6 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \
LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
} while(0)
/**
* @brief Disable the COMP6 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6); \
LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
} while(0)
/**
* @brief Enable the COMP6 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Disable the COMP6 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Generate a software interrupt on the COMP6 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Enable the COMP6 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Disable the COMP6 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Check whether the COMP6 EXTI line flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP6_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_32_63(COMP_EXTI_LINE_COMP6)
/**
* @brief Clear the COMP6 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP6)
#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
/**
* @brief Enable the COMP7 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE() LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Disable the COMP7 EXTI line rising edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE() LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Enable the COMP7 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE() LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Disable the COMP7 EXTI line falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE() LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Enable the COMP7 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \
LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
} while(0)
/**
* @brief Disable the COMP7 EXTI line rising & falling edge trigger.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7); \
LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
} while(0)
/**
* @brief Enable the COMP7 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Disable the COMP7 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Generate a software interrupt on the COMP7 EXTI line.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Enable the COMP7 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Disable the COMP7 EXTI line in event mode.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Check whether the COMP7 EXTI line flag is set.
* @retval RESET or SET
*/
#define __HAL_COMP_COMP7_EXTI_GET_FLAG() LL_EXTI_IsActiveFlag_32_63(COMP_EXTI_LINE_COMP7)
/**
* @brief Clear the COMP7 EXTI flag.
* @retval None
*/
#define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP7)
#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup COMP_Private_Constants COMP Private Constants
* @{
*/
/** @defgroup COMP_ExtiLine COMP EXTI Lines
* @{
*/
#define COMP_EXTI_LINE_COMP1 (LL_EXTI_LINE_21) /*!< EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP2 (LL_EXTI_LINE_22) /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP3 (LL_EXTI_LINE_29) /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP4 (LL_EXTI_LINE_30) /*!< EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet */
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define COMP_EXTI_LINE_COMP5 (LL_EXTI_LINE_31) /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP6 (LL_EXTI_LINE_32) /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */
#define COMP_EXTI_LINE_COMP7 (LL_EXTI_LINE_33) /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */
#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/**
* @}
*/
/** @defgroup COMP_ExtiLine COMP EXTI Lines
* @{
*/
#define COMP_EXTI_IT (0x00000001UL) /*!< EXTI line event with interruption */
#define COMP_EXTI_EVENT (0x00000002UL) /*!< EXTI line event only (without interruption) */
#define COMP_EXTI_RISING (0x00000010UL) /*!< EXTI line event on rising edge */
#define COMP_EXTI_FALLING (0x00000020UL) /*!< EXTI line event on falling edge */
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup COMP_Private_Macros COMP Private Macros
* @{
*/
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
* @{
*/
/**
* @brief Get the specified EXTI line for a comparator instance.
* @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine
*/
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
:((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
:((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 \
:((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 \
:((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 \
: COMP_EXTI_LINE_COMP7)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
:((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
:((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
: COMP_EXTI_LINE_COMP4)
#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
/**
* @}
*/
/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
* @{
*/
#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
(((__COMP_INSTANCE__) == COMP1) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP2) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP3) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP4) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP5) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP6) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP7) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1)) \
))
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2) || \
(((__COMP_INSTANCE__) == COMP1) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP2) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
) || \
(((__COMP_INSTANCE__) == COMP3) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1)) \
) || \
(((__COMP_INSTANCE__) == COMP4) && \
(((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1) || \
((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2)) \
))
#endif
#define IS_COMP_HYSTERESIS(__HYSTERESIS__) (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_10MV) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_20MV) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_30MV) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_40MV) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_50MV) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_60MV) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_70MV) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_LOW) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
#define IS_COMP_OUTPUTPOL(__POL__) (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
((__POL__) == COMP_OUTPUTPOL_INVERTED))
/* Note: Output blanking source depends on COMP instances */
/* Better use IS_COMP_BLANKINGSRC_INSTANCE instead */
/* Macro kept for compatibility with other STM32 series */
#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \
( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
|| \
(((__INSTANCE__) == COMP2) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
|| \
(((__INSTANCE__) == COMP3) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
|| \
(((__INSTANCE__) == COMP4) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
|| \
(((__INSTANCE__) == COMP5) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5))) \
|| \
(((__INSTANCE__) == COMP6) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6))) \
|| \
(((__INSTANCE__) == COMP7) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7))) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
|| \
(((__INSTANCE__) == COMP2) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
|| \
(((__INSTANCE__) == COMP3) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
|| \
(((__INSTANCE__) == COMP4) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
#elif defined(STM32G491xx) || defined(STM32G4A1xx)
#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \
((((__INSTANCE__) == COMP1) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1))) \
|| \
(((__INSTANCE__) == COMP2) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2))) \
|| \
(((__INSTANCE__) == COMP3) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3))) \
|| \
(((__INSTANCE__) == COMP4) && \
(((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4) || \
((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4))) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1) \
|| ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3) \
)
#endif /* STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
#define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING) || \
((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW) || \
((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup COMP_Exported_Functions
* @{
*/
/** @addtogroup COMP_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/**
* @}
*/
/* IO operation functions *****************************************************/
/** @addtogroup COMP_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral Control functions ************************************************/
/** @addtogroup COMP_Exported_Functions_Group3
* @{
*/
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
/* Callback in interrupt mode */
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/* Peripheral State functions **************************************************/
/** @addtogroup COMP_Exported_Functions_Group4
* @{
*/
HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_COMP_H */
| 74,792 | C | 54.361214 | 392 | 0.530859 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_opamp.h | /**
******************************************************************************
* @file stm32g4xx_ll_opamp.h
* @author MCD Application Team
* @brief Header file of OPAMP LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_OPAMP_H
#define STM32G4xx_LL_OPAMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (OPAMP1) || defined (OPAMP2) || defined (OPAMP3) || defined (OPAMP4) || defined (OPAMP5) || defined (OPAMP6)
/** @defgroup OPAMP_LL OPAMP
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants
* @{
*/
/* Internal mask for OPAMP trimming of transistors differential pair NMOS */
/* or PMOS. */
/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for: */
/* - OPAMP trimming selection of transistors differential pair */
/* - OPAMP trimming values of transistors differential pair */
#define OPAMP_TRIMMING_SELECT_MASK (OPAMP_CSR_CALSEL)
#define OPAMP_TRIMMING_VALUE_MASK (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_TRIMOFFSETP)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros
* @{
*/
/**
* @brief Driver macro reserved for internal use: set a pointer to
* a register from a register basis from which an offset
* is applied.
* @param __REG__ Register basis from which the offset is applied.
* @param __REG_OFFSET__ Offset to be applied (unit: number of registers).
* @retval Register address
*/
#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__) \
((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2))))
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of OPAMP instance.
*/
typedef struct
{
uint32_t PowerMode; /*!< Set OPAMP power mode.
This parameter can be a value of @ref OPAMP_LL_EC_POWERMODE
This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */
uint32_t FunctionalMode; /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...
This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE
@note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().
This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */
uint32_t InputNonInverting; /*!< Set OPAMP input non-inverting connection.
This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING
This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */
uint32_t InputInverting; /*!< Set OPAMP inverting input connection.
This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING
@note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.
This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */
} LL_OPAMP_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants
* @{
*/
/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.
* @{
*/
#define LL_OPAMP_MODE_FUNCTIONAL (0x00000000UL) /*!< OPAMP functional mode */
#define LL_OPAMP_MODE_CALIBRATION (OPAMP_CSR_CALON) /*!< OPAMP calibration mode */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode
* @{
*/
#define LL_OPAMP_MODE_STANDALONE (0x00000000UL) /*!< OPAMP functional mode, OPAMP operation in standalone */
#define LL_OPAMP_MODE_FOLLOWER (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0) /*!< OPAMP functional mode, OPAMP operation in follower */
#define LL_OPAMP_MODE_PGA (OPAMP_CSR_VMSEL_1) /*!< OPAMP functional mode, OPAMP operation in PGA */
#define LL_OPAMP_MODE_PGA_IO0 (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_VMSEL_1) /*!< In PGA mode, the inverting input is connected to VINM0 for filtering */
#define LL_OPAMP_MODE_PGA_IO0_BIAS (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1) /*!< In PGA mode, the inverting input is connected to VINM0
- Input signal on VINM0, bias on VINPx: negative gain
- Bias on VINM0, input signal on VINPx: positive gain */
#define LL_OPAMP_MODE_PGA_IO0_IO1_BIAS (OPAMP_CSR_PGGAIN_4|OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1) /*!< In PGA mode, the inverting input is connected to VINM0
- Input signal on VINM0, bias on VINPx: negative gain
- Bias on VINM0, input signal on VINPx: positive gain
And VINM1 is connected too for filtering */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)
* @note Gain sign:
* - is positive if the @ref OPAMP_LL_EC_FUNCTIONAL_MODE configuration is
* @ref LL_OPAMP_MODE_PGA or LL_OPAMP_MODE_PGA_IO0
* - may be positive or negative if the @ref OPAMP_LL_EC_FUNCTIONAL_MODE configuration is
* @ref LL_OPAMP_MODE_PGA_IO0_BIAS or LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
* see @ref OPAMP_LL_EC_FUNCTIONAL_MODE for more details
* @{
*/
#define LL_OPAMP_PGA_GAIN_2_OR_MINUS_1 (0x00000000UL) /*!< OPAMP PGA gain 2 or -1 */
#define LL_OPAMP_PGA_GAIN_4_OR_MINUS_3 ( OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4 or -3 */
#define LL_OPAMP_PGA_GAIN_8_OR_MINUS_7 ( OPAMP_CSR_PGGAIN_1 ) /*!< OPAMP PGA gain 8 or -7 */
#define LL_OPAMP_PGA_GAIN_16_OR_MINUS_15 ( OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 16 or -15 */
#define LL_OPAMP_PGA_GAIN_32_OR_MINUS_31 (OPAMP_CSR_PGGAIN_2 ) /*!< OPAMP PGA gain 32 or -31 */
#define LL_OPAMP_PGA_GAIN_64_OR_MINUS_63 (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 64 or -63 */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting
* @{
*/
#define LL_OPAMP_INPUT_NONINVERT_IO0 (0x00000000UL) /*!< OPAMP non inverting input connected to I/O VINP0
(PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_NONINVERT_IO1 OPAMP_CSR_VPSEL_0 /*!< OPAMP non inverting input connected to I/O VINP1
(PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_NONINVERT_IO2 OPAMP_CSR_VPSEL_1 /*!< OPAMP non inverting input connected to I/O VINP2
(PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_NONINVERT_IO3 OPAMP_CSR_VPSEL /*!< OPAMP non inverting input connected to I/O VINP3
(PD14 for OPAMP2) */
#define LL_OPAMP_INPUT_NONINVERT_DAC OPAMP_CSR_VPSEL /*!< OPAMP non inverting input connected internally to DAC channel
(DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting
* @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias.
* Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
* @{
*/
#define LL_OPAMP_INPUT_INVERT_IO0 (0x00000000UL) /*!< OPAMP inverting input connected to I/O VINM0
(PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_INVERT_IO1 OPAMP_CSR_VMSEL_0 /*!< OPAMP inverting input connected to I/0 VINM1
(PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_INVERT_CONNECT_NO OPAMP_CSR_VMSEL_1 /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias).
Note: On this STM32 series, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING_SECONDARY OPAMP input non-inverting secondary
* @{
*/
#define LL_OPAMP_INPUT_NONINVERT_IO0_SEC (0x00000000UL) /*!< OPAMP secondary non inverting input connected to I/O VINP0
(PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4, PB14 for OPAMP5, PB12 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_NONINVERT_IO1_SEC OPAMP_TCMR_VPSSEL_0 /*!< OPAMP secondary non inverting input connected to I/O VINP1
(PA3 for OPAMP1, PB14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4, PD12 for OPAMP5, PD9 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_NONINVERT_IO2_SEC OPAMP_TCMR_VPSSEL_1 /*!< OPAMP secondary non inverting input connected to I/O VINP2
(PA7 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PB11 for OPAMP4, PC3 for OPAMP5, PB13 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_NONINVERT_IO3_SEC OPAMP_TCMR_VPSSEL /*!< OPAMP secondary non inverting input connected to I/O VINP3
(PD14 for OPAMP2) */
#define LL_OPAMP_INPUT_NONINVERT_DAC_SEC OPAMP_TCMR_VPSSEL /*!< OPAMP secondary non inverting input connected internally to DAC channel
(DAC3_CH1 for OPAMP1, DAC3_CH2 for OPAMP3, DAC4_CH1 for OPAMP4, DAC4_CH2 for OPAMP5, DAC3_CH1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_INVERTING_SECONDARY OPAMP input inverting secondary
* @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias.
* Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).
* @{
*/
#define LL_OPAMP_INPUT_INVERT_IO0_SEC (0x00000000UL) /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref LL_OPAMP_MODE_STANDALONE
has been configured by call to @ref LL_OPAMP_Init() or @ref LL_OPAMP_SetFunctionalMode().
OPAMP secondary inverting input connected to I/O VINM0.
(PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PB10 for OPAMP4, PB15 for OPAMP5, PA1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_INVERT_IO1_SEC OPAMP_TCMR_VMSSEL /*!< OPAMP secondary mode is standalone mode - Only applicable if @ref LL_OPAMP_MODE_STANDALONE
has been configured by call to @ref LL_OPAMP_Init() or @ref LL_OPAMP_SetFunctionalMode().
OPAMP secondary inverting input connected to I/0 VINM1
(PC5 for OPAMP1, PC5 for OPAMP2, PB10 for OPAMP3, PB8 for OPAMP4, PA3 for OPAMP5, PB1 for OPAMP6)
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
#define LL_OPAMP_INPUT_INVERT_PGA_SEC (0x00000000UL) /*!< OPAMP secondary mode is PGA mode - Only applicable if configured mode through call to @ref LL_OPAMP_Init()
or @ref LL_OPAMP_SetFunctionalMode() is NOT @ref LL_OPAMP_MODE_STANDALONE.
OPAMP secondary inverting input is:
- Not connected if configured mode is @ref LL_OPAMP_MODE_FOLLOWER or @ref LL_OPAMP_MODE_PGA
- Connected to VINM0 and possibly VINM1 if any of the other modes as been configured
(see @ref OPAMP_LL_EC_FUNCTIONAL_MODE description for more details on PGA connection modes) */
#define LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC OPAMP_TCMR_VMSSEL /*!< OPAMP secondary mode is Follower mode - Only applicable if configured mode through call to @ref LL_OPAMP_Init()
or @ref LL_OPAMP_SetFunctionalMode() is NOT @ref LL_OPAMP_MODE_STANDALONE.
OPAMP secondary inverting input is not connected. */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INTERNAL_OUPUT_MODE OPAMP internal output mode
* @{
*/
#define LL_OPAMP_INTERNAL_OUPUT_DISABLED (0x00000000UL) /*!< OPAMP internal output to ADC disabled. */
#define LL_OPAMP_INTERNAL_OUPUT_ENABLED OPAMP_CSR_OPAMPINTEN /*!< OPAMP internal output to ADC enabled.
- OPAMP1 internal output is connected to ADC1/Channel13
- OPAMP2 internal output is connected to ADC2/Channel16
- OPAMP3 internal output is connected to ADC2/Channel18 & ADC3/Channel13
- OPAMP4 internal output is connected to ADC5/Channel5
- OPAMP5 internal output is connected to ADC5/Channel3
- OPAMP6 internal output is connected to ADC4/Channel17
Note: On this STM32 series, all OPAMPx are not available on all devices. Refer to device datasheet for more details */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_INPUT_MUX_MODE OPAMP inputs multiplexer mode
* @note The switch can be controlled either by a single timer or a combination of them,
* in this case application has to 'ORed' the values below
* ex LL_OPAMP_INPUT_MUX_TIM1_CH6 | LL_OPAMP_INPUT_MUX_TIM20_CH6
* @{
*/
#define LL_OPAMP_INPUT_MUX_DISABLE (0x00000000UL) /*!< OPAMP inputs timer controlled multiplexer mode disabled. */
#define LL_OPAMP_INPUT_MUX_TIM1_CH6 OPAMP_TCMR_T1CMEN /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM1 OC6. */
#define LL_OPAMP_INPUT_MUX_TIM8_CH6 OPAMP_TCMR_T8CMEN /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM8 OC6. */
#define LL_OPAMP_INPUT_MUX_TIM20_CH6 OPAMP_TCMR_T20CMEN /*!< OPAMP inputs timer controlled multiplexer mode enabled, controlled by TIM20 OC6.
Note: On this STM32 series, TIM20 is not available on all devices. Refer to device datasheet for more details */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_POWER_MODE OPAMP PowerMode
* @{
*/
#define LL_OPAMP_POWERMODE_NORMALSPEED (0x00000000UL) /*!< OPAMP output in normal mode */
#define LL_OPAMP_POWERMODE_HIGHSPEED OPAMP_CSR_HIGHSPEEDEN /*!< OPAMP output in highspeed mode */
#define LL_OPAMP_POWERMODE_NORMAL LL_OPAMP_POWERMODE_NORMALSPEED /*!< OPAMP power mode normal - Old Naming for compatibility */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode
* @{
*/
#define LL_OPAMP_TRIMMING_FACTORY (0x00000000UL) /*!< OPAMP trimming factors set to factory values */
#define LL_OPAMP_TRIMMING_USER OPAMP_CSR_USERTRIM /*!< OPAMP trimming factors set to user values */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS
* @{
*/
#define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
#define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA (OPAMP_CSR_TRIMOFFSETN | OPAMP_CSR_CALSEL_1 ) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */
#define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA (OPAMP_CSR_TRIMOFFSETP | OPAMP_CSR_CALSEL_0) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
#define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_CSR_TRIMOFFSETP ) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */
#define LL_OPAMP_TRIMMING_NMOS (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
#define LL_OPAMP_TRIMMING_PMOS (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA) /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */
/**
* @}
*/
/** @defgroup OPAMP_LL_EC_HW_DELAYS Definitions of OPAMP hardware constraints delays
* @note Only OPAMP peripheral HW delays are defined in OPAMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for OPAMP startup time (transition from state disable to enable). */
/* Note: OPAMP startup time depends on board application environment: */
/* impedance connected to OPAMP output. */
/* The delay below is specified under conditions: */
/* - OPAMP in functional mode follower */
/* - load impedance of 4kOhm (min), 50pF (max) */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
#define LL_OPAMP_DELAY_STARTUP_US (6) /*!< Delay for OPAMP startup time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros
* @{
*/
/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro
* @{
*/
/**
* @brief Write a value in OPAMP register
* @param __INSTANCE__ OPAMP Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in OPAMP register
* @param __INSTANCE__ OPAMP Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions
* @{
*/
/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance
* @{
*/
/**
* @brief Set OPAMP mode calibration or functional.
* @note OPAMP mode corresponds to functional or calibration mode:
* - functional mode: OPAMP operation in standalone, follower, ...
* Set functional mode using function
* @ref LL_OPAMP_SetFunctionalMode().
* - calibration mode: offset calibration of the selected
* transistors differential pair NMOS or PMOS.
* @rmtoll CSR CALON LL_OPAMP_SetMode
* @param OPAMPx OPAMP instance
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_MODE_FUNCTIONAL
* @arg @ref LL_OPAMP_MODE_CALIBRATION
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);
}
/**
* @brief Get OPAMP mode calibration or functional.
* @note OPAMP mode corresponds to functional or calibration mode:
* - functional mode: OPAMP operation in standalone, follower, ...
* Set functional mode using function
* @ref LL_OPAMP_SetFunctionalMode().
* - calibration mode: offset calibration of the selected
* transistors differential pair NMOS or PMOS.
* @rmtoll CSR CALON LL_OPAMP_GetMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_MODE_FUNCTIONAL
* @arg @ref LL_OPAMP_MODE_CALIBRATION
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));
}
/**
* @brief Set OPAMP functional mode by setting internal connections.
* OPAMP operation in standalone, follower, ...
* @note This function reset bit of calibration mode to ensure
* to be in functional mode, in order to have OPAMP parameters
* (inputs selection, ...) set with the corresponding OPAMP mode
* to be effective.
* @rmtoll CSR VMSEL LL_OPAMP_SetFunctionalMode
* @param OPAMPx OPAMP instance
* @param FunctionalMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_MODE_STANDALONE
* @arg @ref LL_OPAMP_MODE_FOLLOWER
* @arg @ref LL_OPAMP_MODE_PGA
* @arg @ref LL_OPAMP_MODE_PGA_IO0
* @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS
* @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)
{
/* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_4 | OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);
}
/**
* @brief Get OPAMP functional mode from setting of internal connections.
* OPAMP operation in standalone, follower, ...
* @rmtoll CSR VMSEL LL_OPAMP_GetFunctionalMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_MODE_STANDALONE
* @arg @ref LL_OPAMP_MODE_FOLLOWER
* @arg @ref LL_OPAMP_MODE_PGA
* @arg @ref LL_OPAMP_MODE_PGA_IO0
* @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS
* @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_4 | OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_VMSEL));
}
/**
* @brief Set OPAMP PGA gain.
* @note Preliminarily, OPAMP must be set in mode PGA
* using function @ref LL_OPAMP_SetFunctionalMode().
* @rmtoll CSR PGGAIN LL_OPAMP_SetPGAGain
* @param OPAMPx OPAMP instance
* @param PGAGain This parameter can be one of the following values:
* @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
* @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
* @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
* @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
* @arg @ref LL_OPAMP_PGA_GAIN_32_OR_MINUS_31
* @arg @ref LL_OPAMP_PGA_GAIN_64_OR_MINUS_63
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);
}
/**
* @brief Get OPAMP PGA gain.
* @note Preliminarily, OPAMP must be set in mode PGA
* using function @ref LL_OPAMP_SetFunctionalMode().
* @rmtoll CSR PGGAIN LL_OPAMP_GetPGAGain
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1
* @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3
* @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7
* @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15
* @arg @ref LL_OPAMP_PGA_GAIN_32_OR_MINUS_31
* @arg @ref LL_OPAMP_PGA_GAIN_64_OR_MINUS_63
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));
}
/**
* @brief Set OPAMP power mode normal or highspeed.
* @note OPAMP highspeed mode allows output stage to have a better slew rate.
* @rmtoll CSR HIGHSPEEDEN LL_OPAMP_SetPowerMode
* @param OPAMPx OPAMP instance
* @param PowerMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_POWERMODE_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_HIGHSPEEDEN, PowerMode);
}
/**
* @brief Get OPAMP power mode normal or highspeed.
* @note OPAMP highspeed mode allows output stage to have a better slew rate.
* @rmtoll CSR HIGHSPEEDEN LL_OPAMP_GetPowerMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_POWERMODE_NORMALSPEED
* @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_HIGHSPEEDEN));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs
* @{
*/
/**
* @brief Set OPAMP non-inverting input connection.
* @rmtoll CSR VPSEL LL_OPAMP_SetInputNonInverting
* @param OPAMPx OPAMP instance
* @param InputNonInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
* @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);
}
/**
* @brief Get OPAMP non-inverting input connection.
* @rmtoll CSR VPSEL LL_OPAMP_GetInputNonInverting
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3
* @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));
}
/**
* @brief Set OPAMP inverting input connection.
* @note OPAMP inverting input is used with OPAMP in mode standalone
* or PGA with external capacitors for filtering circuit.
* Otherwise (OPAMP in mode follower), OPAMP inverting input
* is not used (not connected to GPIO pin).
* @rmtoll CSR VMSEL LL_OPAMP_SetInputInverting
* @param OPAMPx OPAMP instance
* @param InputInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1
* @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
{
/* Manage cases of OPAMP inverting input not connected (0x10 and 0x11) */
/* to not modify OPAMP mode follower or PGA. */
/* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */
MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);
}
/**
* @brief Get OPAMP inverting input connection.
* @rmtoll CSR VMSEL LL_OPAMP_GetInputInverting
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1
* @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)
{
uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);
/* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting */
/* input not connected. */
return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));
}
/**
* @brief Set OPAMP non-inverting input secondary connection.
* @rmtoll TCMR VPSSEL LL_OPAMP_SetInputNonInvertingSecondary
* @param OPAMPx OPAMP instance
* @param InputNonInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC_SEC
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)
{
MODIFY_REG(OPAMPx->TCMR, OPAMP_TCMR_VPSSEL, InputNonInverting);
}
/**
* @brief Get OPAMP non-inverting input secondary connection.
* @rmtoll TCMR VPSSEL LL_OPAMP_GetInputNonInvertingSecondary
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO1_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO2_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_IO3_SEC
* @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC_SEC
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInvertingSecondary(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->TCMR, OPAMP_TCMR_VPSSEL));
}
/**
* @brief Set OPAMP inverting input secondary connection.
* @note OPAMP inverting input is used with OPAMP in mode standalone
* or PGA with external capacitors for filtering circuit.
* Otherwise (OPAMP in mode follower), OPAMP inverting input
* is not used (not connected to GPIO pin).
* @rmtoll TCMR VMSSEL LL_OPAMP_SetInputInvertingSecondary
* @param OPAMPx OPAMP instance
* @param InputInverting This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
* @arg @ref LL_OPAMP_INPUT_INVERT_PGA_SEC
* @arg @ref LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)
{
MODIFY_REG(OPAMPx->TCMR, OPAMP_TCMR_VMSSEL, InputInverting);
}
/**
* @brief Get OPAMP inverting input secondary connection.
* @rmtoll TCMR VMSSEL LL_OPAMP_GetInputInvertingSecondary
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_INVERT_IO0_SEC
* @arg @ref LL_OPAMP_INPUT_INVERT_IO1_SEC
* @arg @ref LL_OPAMP_INPUT_INVERT_PGA_SEC
* @arg @ref LL_OPAMP_INPUT_INVERT_FOLLOWER_SEC
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputInvertingSecondary(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->TCMR, OPAMP_TCMR_VMSSEL));
}
/**
* @brief Set OPAMP inputs multiplexer mode.
* @rmtoll TCMR TCMEN LL_OPAMP_SetInputsMuxMode
* @param OPAMPx OPAMP instance
* @param InputsMuxMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
* @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
* @arg @ref LL_OPAMP_INPUT_MUX_TIM8_CH6
* @arg @ref LL_OPAMP_INPUT_MUX_TIM20_CH6 (1)
* On this STM32 series, this value is not available on all devices. Refer to datasheet for details.
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInputsMuxMode(OPAMP_TypeDef *OPAMPx, uint32_t InputsMuxMode)
{
MODIFY_REG(OPAMPx->TCMR, OPAMP_TCMR_T1CMEN | OPAMP_TCMR_T8CMEN | OPAMP_TCMR_T20CMEN, InputsMuxMode);
}
/**
* @brief Get OPAMP inputs multiplexer mode.
* @rmtoll TCMR TCMEN LL_OPAMP_GetInputsMuxMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INPUT_MUX_DISABLE
* @arg @ref LL_OPAMP_INPUT_MUX_TIM1_CH6
* @arg @ref LL_OPAMP_INPUT_MUX_TIM8_CH6
* @arg @ref LL_OPAMP_INPUT_MUX_TIM20_CH6 (1)
* On this STM32 series, this value is not available on all devices. Refer to datasheet for details.
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInputsMuxMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->TCMR, OPAMP_TCMR_T1CMEN | OPAMP_TCMR_T8CMEN | OPAMP_TCMR_T20CMEN));
}
/**
* @brief Set OPAMP internal output.
* @note OPAMP internal output is used to link OPAMP output to ADC input internally.
* @rmtoll CSR OPAMPINTEN LL_OPAMP_SetInternalOutput
* @param OPAMPx OPAMP instance
* @param InternalOutput This parameter can be one of the following values:
* @arg @ref LL_OPAMP_INTERNAL_OUPUT_DISABLED
* @arg @ref LL_OPAMP_INTERNAL_OUPUT_ENABLED
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetInternalOutput(OPAMP_TypeDef *OPAMPx, uint32_t InternalOutput)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAMPINTEN, InternalOutput);
}
/**
* @brief Get OPAMP internal output state.
* @rmtoll CSR OPAMPINTEN LL_OPAMP_GetInternalOutput
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_INTERNAL_OUPUT_DISABLED
* @arg @ref LL_OPAMP_INTERNAL_OUPUT_ENABLED
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetInternalOutput(OPAMP_TypeDef *OPAMPx)
{
return READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPINTEN);
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming
* @{
*/
/**
* @brief Set OPAMP trimming mode.
* @rmtoll CSR USERTRIM LL_OPAMP_SetTrimmingMode
* @param OPAMPx OPAMP instance
* @param TrimmingMode This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_FACTORY
* @arg @ref LL_OPAMP_TRIMMING_USER
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)
{
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);
}
/**
* @brief Get OPAMP trimming mode.
* @rmtoll CSR USERTRIM LL_OPAMP_GetTrimmingMode
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_FACTORY
* @arg @ref LL_OPAMP_TRIMMING_USER
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));
}
/**
* @brief Set OPAMP offset to calibrate the selected transistors
* differential pair NMOS or PMOS.
* @note Preliminarily, OPAMP must be set in mode calibration
* using function @ref LL_OPAMP_SetMode().
* @rmtoll CSR CALSEL LL_OPAMP_SetCalibrationSelection
* @param OPAMPx OPAMP instance
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
* @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
* @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
* @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
*
* (1) Default parameters to be used for calibration
* using two trimming steps (one with each transistors differential
* pair NMOS and PMOS)
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
{
/* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because */
/* containing other bits reserved for other purpose. */
MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, (TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK));
}
/**
* @brief Get OPAMP offset to calibrate the selected transistors
* differential pair NMOS or PMOS.
* @note Preliminarily, OPAMP must be set in mode calibration
* using function @ref LL_OPAMP_SetMode().
* @rmtoll CSR CALSEL LL_OPAMP_GetCalibrationSelection
* @param OPAMPx OPAMP instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS (1)
* @arg @ref LL_OPAMP_TRIMMING_PMOS (1)
* @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA
* @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA
*
* (1) Default parameters to be used for calibration
* using two trimming steps (one with each transistors differential
* pair NMOS and PMOS)
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)
{
uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));
return (CalibrationSelection |
(((CalibrationSelection & OPAMP_CSR_CALSEL_1) == 0UL) ? OPAMP_CSR_TRIMOFFSETP : OPAMP_CSR_TRIMOFFSETN));
}
/**
* @brief Get OPAMP calibration result of toggling output.
* @note This functions returns:
* 0 if OPAMP calibration output is reset
* 1 if OPAMP calibration output is set
* @rmtoll CSR OUTCAL LL_OPAMP_IsCalibrationOutputSet
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OUTCAL) == OPAMP_CSR_OUTCAL) ? 1UL : 0UL);
}
/**
* @brief Set OPAMP trimming factor for the selected transistors
* differential pair NMOS or PMOS, corresponding to the selected
* power mode.
* @rmtoll CSR TRIMOFFSETN LL_OPAMP_SetTrimmingValue\n
* CSR TRIMOFFSETP LL_OPAMP_SetTrimmingValue
* @param OPAMPx OPAMP instance
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
* @arg @ref LL_OPAMP_TRIMMING_PMOS
* @param TrimmingValue 0x00...0x1F
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair,
uint32_t TrimmingValue)
{
MODIFY_REG(OPAMPx->CSR,
(TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK),
TrimmingValue << ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos));
}
/**
* @brief Get OPAMP trimming factor for the selected transistors
* differential pair NMOS or PMOS, corresponding to the selected
* power mode.
* @rmtoll CSR TRIMOFFSETN LL_OPAMP_GetTrimmingValue\n
* CSR TRIMOFFSETP LL_OPAMP_GetTrimmingValue
* @param OPAMPx OPAMP instance
* @param TransistorsDiffPair This parameter can be one of the following values:
* @arg @ref LL_OPAMP_TRIMMING_NMOS
* @arg @ref LL_OPAMP_TRIMMING_PMOS
* @retval 0x0...0x1F
*/
__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)
{
return (uint32_t)(READ_BIT(OPAMPx->CSR, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))
>> ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_CSR_TRIMOFFSETN_Pos : OPAMP_CSR_TRIMOFFSETP_Pos));
}
/**
* @}
*/
/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance
* @{
*/
/**
* @brief Enable OPAMP instance.
* @note After enable from off state, OPAMP requires a delay
* to fulfill wake up time specification.
* Refer to device datasheet, parameter "tWAKEUP".
* @rmtoll CSR OPAMPXEN LL_OPAMP_Enable
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)
{
SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
}
/**
* @brief Disable OPAMP instance.
* @rmtoll CSR OPAMPXEN LL_OPAMP_Disable
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)
{
CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);
}
/**
* @brief Get OPAMP instance enable state
* (0: OPAMP is disabled, 1: OPAMP is enabled)
* @rmtoll CSR OPAMPXEN LL_OPAMP_IsEnabled
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN)) ? 1UL : 0UL);
}
/**
* @brief Lock OPAMP instance.
* @note Once locked, OPAMP configuration can be accessed in read-only.
* @note The only way to unlock the OPAMP is a device hardware reset.
* @rmtoll CSR LOCK LL_OPAMP_Lock
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_Lock(OPAMP_TypeDef *OPAMPx)
{
SET_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK);
}
/**
* @brief Get OPAMP lock state
* (0: OPAMP is unlocked, 1: OPAMP is locked).
* @note Once locked, OPAMP configuration can be accessed in read-only.
* @note The only way to unlock the OPAMP is a device hardware reset.
* @rmtoll CSR LOCK LL_OPAMP_IsLocked
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsLocked(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_LOCK) == (OPAMP_CSR_LOCK)) ? 1UL : 0UL);
}
/**
* @brief Lock OPAMP instance timer controlled mux
* @note Once locked, OPAMP timer controlled mux configuration can be accessed in read-only.
* @note The only way to unlock the OPAMP timer controlled mux is a device hardware reset.
* @rmtoll TCMR LOCK LL_OPAMP_LockTimerMux
* @param OPAMPx OPAMP instance
* @retval None
*/
__STATIC_INLINE void LL_OPAMP_LockTimerMux(OPAMP_TypeDef *OPAMPx)
{
SET_BIT(OPAMPx->TCMR, OPAMP_TCMR_LOCK);
}
/**
* @brief Get OPAMP timer controlled mux lock state
* (0: OPAMP timer controlled mux is unlocked, 1: OPAMP timer controlled mux is locked).
* @note Once locked, OPAMP timer controlled mux configuration can be accessed in read-only.
* @note The only way to unlock the OPAMP timer controlled mux is a device hardware reset.
* @rmtoll TCMR LOCK LL_OPAMP_IsTimerMuxLocked
* @param OPAMPx OPAMP instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_OPAMP_IsTimerMuxLocked(OPAMP_TypeDef *OPAMPx)
{
return ((READ_BIT(OPAMPx->TCMR, OPAMP_TCMR_LOCK) == (OPAMP_TCMR_LOCK)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);
ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* OPAMP1 || OPAMP2 || OPAMP3 || OPAMP4 || OPAMP5 || OPAMP6 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_OPAMP_H */
| 50,560 | C | 48.183852 | 351 | 0.595392 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_ucpd.h | /**
******************************************************************************
* @file stm32g4xx_ll_ucpd.h
* @author MCD Application Team
* @brief Header file of UCPD LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_UCPD_H
#define STM32G4xx_LL_UCPD_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
#if defined (UCPD1)
/** @defgroup UCPD_LL UCPD
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure
* @{
*/
/**
* @brief UCPD Init structures definition
*/
typedef struct
{
uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock.
This parameter can be a value of @ref UCPD_LL_EC_PSC.
This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk().
*/
uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV)
to achieve a legal tTransitionWindow (set according to peripheral clock to define
an interval of between 12 and 20 us).
This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
This value can be modified afterwards using function @ref LL_UCPD_SetTransWin().
*/
uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate
tInterframeGap from the peripheral clock.
This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F
This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap().
*/
uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock
e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock :
"UCPD1_CLK".
This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F.
This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv().
*/
} LL_UCPD_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants
* @{
*/
/** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_ucpd_ReadReg function
* @{
*/
#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */
#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */
#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */
#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */
#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */
#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */
#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */
#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */
#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */
#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */
#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */
#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */
#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */
#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */
#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */
#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!<Status of DC level on CC1 pin */
#define LL_UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2 /*!<Status of DC level on CC2 pin */
#define LL_UCPD_SR_FRSEVT UCPD_SR_FRSEVT /*!<Fast Role Swap detection event */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_UCPD_ReadReg and LL_UCPD_WriteReg functions
* @{
*/
#define LL_UCPD_IMR_TXIS UCPD_IMR_TXISIE /*!< Enable transmit interrupt status */
#define LL_UCPD_IMR_TXMSGDISC UCPD_IMR_TXMSGDISCIE /*!< Enable transmit message discarded interrupt */
#define LL_UCPD_IMR_TXMSGSENT UCPD_IMR_TXMSGSENTIE /*!< Enable transmit message sent interrupt */
#define LL_UCPD_IMR_TXMSGABT UCPD_IMR_TXMSGABTIE /*!< Enable transmit message abort interrupt */
#define LL_UCPD_IMR_HRSTDISC UCPD_IMR_HRSTDISCIE /*!< Enable HRST discarded interrupt */
#define LL_UCPD_IMR_HRSTSENT UCPD_IMR_HRSTSENTIE /*!< Enable HRST sent interrupt */
#define LL_UCPD_IMR_TXUND UCPD_IMR_TXUNDIE /*!< Enable tx data underrun condition interrupt */
#define LL_UCPD_IMR_RXNE UCPD_IMR_RXNEIE /*!< Enable Receive data register not empty interrupt */
#define LL_UCPD_IMR_RXORDDET UCPD_IMR_RXORDDETIE /*!< Enable Rx ordered set (4 K-codes) detected interrupt */
#define LL_UCPD_IMR_RXHRSTDET UCPD_IMR_RXHRSTDETIE /*!< Enable Rx Hard Reset detect interrupt */
#define LL_UCPD_IMR_RXOVR UCPD_IMR_RXOVRIE /*!< Enable Rx data overflow interrupt */
#define LL_UCPD_IMR_RXMSGEND UCPD_IMR_RXMSGENDIE /*!< Enable Rx message received */
#define LL_UCPD_IMR_TYPECEVT1 UCPD_IMR_TYPECEVT1IE /*!< Enable Type C voltage level event on CC1 */
#define LL_UCPD_IMR_TYPECEVT2 UCPD_IMR_TYPECEVT2IE /*!< Enable Type C voltage level event on CC2 */
#define LL_UCPD_IMR_FRSEVT UCPD_IMR_FRSEVTIE /*!< Enable fast Role Swap detection event */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_ORDERSET Ordered sets value
* @brief definition of the usual Ordered sets
* @{
*/
#define LL_UCPD_SYNC1 0x18u /*!< K-code for Startsynch #1 */
#define LL_UCPD_SYNC2 0x11u /*!< K-code for Startsynch #2 */
#define LL_UCPD_SYNC3 0x06u /*!< K-code for Startsynch #3 */
#define LL_UCPD_RST1 0x07u /*!< K-code for Hard Reset #1 */
#define LL_UCPD_RST2 0x19u /*!< K-code for Hard Reset #2 */
#define LL_UCPD_EOP 0x0Du /*!< K-code for EOP End of Packet */
#define LL_UCPD_ORDERED_SET_SOP (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP Ordered set coding */
#define LL_UCPD_ORDERED_SET_SOP1 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Ordered set coding */
#define LL_UCPD_ORDERED_SET_SOP2 (LL_UCPD_SYNC1 | (LL_UCPD_SYNC3<<5u) | (LL_UCPD_SYNC1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP'' Ordered set coding */
#define LL_UCPD_ORDERED_SET_HARD_RESET (LL_UCPD_RST1 | (LL_UCPD_RST1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_RST2<<15u )) /*!< Hard Reset Ordered set coding */
#define LL_UCPD_ORDERED_SET_CABLE_RESET (LL_UCPD_RST1 | (LL_UCPD_SYNC1<<5u) | (LL_UCPD_RST1<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< Cable Reset Ordered set coding */
#define LL_UCPD_ORDERED_SET_SOP1_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_RST2<<10u) | (LL_UCPD_SYNC3<<15u)) /*!< SOP' Debug Ordered set coding */
#define LL_UCPD_ORDERED_SET_SOP2_DEBUG (LL_UCPD_SYNC1 | (LL_UCPD_RST2<<5u) | (LL_UCPD_SYNC3<<10u) | (LL_UCPD_SYNC2<<15u)) /*!< SOP'' Debug Ordered set coding */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_MODE Role Mode
* @{
*/
#define LL_UCPD_ROLE_SNK UCPD_CR_ANAMODE /*!< Mode SNK Rd */
#define LL_UCPD_ROLE_SRC 0x0U /*!< Mode SRC Rp */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_RESISTOR Resistor value
* @{
*/
#define LL_UCPD_RESISTOR_DEFAULT UCPD_CR_ANASUBMODE_0 /*!< Rp default */
#define LL_UCPD_RESISTOR_1_5A UCPD_CR_ANASUBMODE_1 /*!< Rp 1.5 A */
#define LL_UCPD_RESISTOR_3_0A UCPD_CR_ANASUBMODE /*!< Rp 3.0 A */
#define LL_UCPD_RESISTOR_NONE 0x0U /*!< No resistor */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_CFG1_ORDERSET ordered set configuration
* @{
*/
#define LL_UCPD_ORDERSET_SOP UCPD_CFG1_RXORDSETEN_0 /*!< SOP Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP1 UCPD_CFG1_RXORDSETEN_1 /*!< SOP' Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP2 UCPD_CFG1_RXORDSETEN_2 /*!< SOP'' Ordered set detection enabled */
#define LL_UCPD_ORDERSET_HARDRST UCPD_CFG1_RXORDSETEN_3 /*!< Hard Reset Ordered set detection enabled */
#define LL_UCPD_ORDERSET_CABLERST UCPD_CFG1_RXORDSETEN_4 /*!< Cable Reset Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP1_DEBUG UCPD_CFG1_RXORDSETEN_5 /*!< SOP' Debug Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP2_DEBUG UCPD_CFG1_RXORDSETEN_6 /*!< SOP'' Debug Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP_EXT1 UCPD_CFG1_RXORDSETEN_7 /*!< SOP extension#1 Ordered set detection enabled */
#define LL_UCPD_ORDERSET_SOP_EXT2 UCPD_CFG1_RXORDSETEN_8 /*!< SOP extension#2 Ordered set detection enabled */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_CCxEVT CCx event
* @{
*/
#define LL_UCPD_SNK_CC1_VOPEN 0x00u /*!< CC1 Sink Open state */
#define LL_UCPD_SNK_CC1_VRP UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Sink vRP default state */
#define LL_UCPD_SNK_CC1_VRP15A UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Sink vRP 1.5A state */
#define LL_UCPD_SNK_CC1_VRP30A (UCPD_SR_TYPEC_VSTATE_CC1_0 | UCPD_SR_TYPEC_VSTATE_CC1_1) /*!< CC1 Sink vRP 3.0A state */
#define LL_UCPD_SNK_CC2_VOPEN 0x00u /*!< CC2 Sink Open state */
#define LL_UCPD_SNK_CC2_VRP UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Sink vRP default state */
#define LL_UCPD_SNK_CC2_VRP15A UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Sink vRP 1.5A state */
#define LL_UCPD_SNK_CC2_VRP30A (UCPD_SR_TYPEC_VSTATE_CC2_0 | UCPD_SR_TYPEC_VSTATE_CC2_1) /*!< CC2 Sink vRP 3.0A state */
#define LL_UCPD_SRC_CC1_VRA 0x0U /*!< CC1 Source vRA state */
#define LL_UCPD_SRC_CC1_VRD UCPD_SR_TYPEC_VSTATE_CC1_0 /*!< CC1 Source vRD state */
#define LL_UCPD_SRC_CC1_OPEN UCPD_SR_TYPEC_VSTATE_CC1_1 /*!< CC1 Source Open state */
#define LL_UCPD_SRC_CC2_VRA 0x0U /*!< CC2 Source vRA state */
#define LL_UCPD_SRC_CC2_VRD UCPD_SR_TYPEC_VSTATE_CC2_0 /*!< CC2 Source vRD state */
#define LL_UCPD_SRC_CC2_OPEN UCPD_SR_TYPEC_VSTATE_CC2_1 /*!< CC2 Source Open state */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_PSC prescaler for UCPDCLK
* @{
*/
#define LL_UCPD_PSC_DIV1 0x0u /*!< Bypass pre-scaling / divide by 1 */
#define LL_UCPD_PSC_DIV2 UCPD_CFG1_PSC_UCPDCLK_0 /*!< Pre-scale clock by dividing by 2 */
#define LL_UCPD_PSC_DIV4 UCPD_CFG1_PSC_UCPDCLK_1 /*!< Pre-scale clock by dividing by 4 */
#define LL_UCPD_PSC_DIV8 (UCPD_CFG1_PSC_UCPDCLK_1 | UCPD_CFG1_PSC_UCPDCLK_0) /*!< Pre-scale clock by dividing by 8 */
#define LL_UCPD_PSC_DIV16 UCPD_CFG1_PSC_UCPDCLK_2 /*!< Pre-scale clock by dividing by 16 */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_CCENABLE CC pin enable
* @{
*/
#define LL_UCPD_CCENABLE_NONE 0x0U /*!< Neither PHY is activated (e.g. disabled state of source) */
#define LL_UCPD_CCENABLE_CC1 UCPD_CR_CCENABLE_0 /*!< Controls apply to only CC1 */
#define LL_UCPD_CCENABLE_CC2 UCPD_CR_CCENABLE_1 /*!< Controls apply to only CC1 */
#define LL_UCPD_CCENABLE_CC1CC2 (UCPD_CR_CCENABLE_0 | UCPD_CR_CCENABLE_1) /*!< Controls apply to both CC1 and CC2 (normal usage for sink/source) */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_CCPIN CC pin selection
* @{
*/
#define LL_UCPD_CCPIN_CC1 0x0U /*!< Use CC1 IO for power delivery communication */
#define LL_UCPD_CCPIN_CC2 UCPD_CR_PHYCCSEL /*!< Use CC2 IO for power delivery communication */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_RXMODE Receiver mode
* @{
*/
#define LL_UCPD_RXMODE_NORMAL 0x0U /*!< Normal receive mode */
#define LL_UCPD_RXMODE_BIST_TEST_DATA UCPD_CR_RXMODE /*!< BIST receive mode (BIST Test Data Mode) */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_TXMODE Type of Tx packet
* @{
*/
#define LL_UCPD_TXMODE_NORMAL 0x0U /*!< Initiate the transfer of a Tx message */
#define LL_UCPD_TXMODE_CABLE_RESET UCPD_CR_TXMODE_0 /*!< Trigger a the transfer of a Cable Reset sequence */
#define LL_UCPD_TXMODE_BIST_CARRIER2 UCPD_CR_TXMODE_1 /*!< Trigger a BIST test sequence send (BIST Carrier Mode 2) */
/**
* @}
*/
/** @defgroup UCPD_LL_EC_RXORDSET Rx ordered set code detected
* @{
*/
#define LL_UCPD_RXORDSET_SOP 0x0U /*!< SOP code detected in receiver */
#define LL_UCPD_RXORDSET_SOP1 UCPD_RX_ORDSET_RXORDSET_0 /*!< SOP' code detected in receiver */
#define LL_UCPD_RXORDSET_SOP2 UCPD_RX_ORDSET_RXORDSET_1 /*!< SOP'' code detected in receiver */
#define LL_UCPD_RXORDSET_SOP1_DEBUG (UCPD_RX_ORDSET_RXORDSET_0 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP' Debug code detected in receiver */
#define LL_UCPD_RXORDSET_SOP2_DEBUG UCPD_RX_ORDSET_RXORDSET_2 /*!< SOP'' Debug code detected in receiver */
#define LL_UCPD_RXORDSET_CABLE_RESET (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_0) /*!< Cable Reset code detected in receiver */
#define LL_UCPD_RXORDSET_SOPEXT1 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1) /*!< SOP extension#1 code detected in receiver */
#define LL_UCPD_RXORDSET_SOPEXT2 (UCPD_RX_ORDSET_RXORDSET_2 | UCPD_RX_ORDSET_RXORDSET_1 | UCPD_RX_ORDSET_RXORDSET_0) /*!< SOP extension#2 code detected in receiver */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup UCPD_LL_Exported_Macros UCPD Exported Macros
* @{
*/
/** @defgroup UCPD_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in UCPD register
* @param __INSTANCE__ UCPD Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_UCPD_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in UCPD register
* @param __INSTANCE__ UCPD Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions
* @{
*/
/** @defgroup UCPD_LL_EF_Configuration Configuration
* @{
*/
/** @defgroup UCPD_LL_EF_CFG1 CFG1 register
* @{
*/
/**
* @brief Enable UCPD peripheral
* @rmtoll CFG1 UCPDEN LL_UCPD_Enable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
}
/**
* @brief Disable UCPD peripheral
* @note When disabling the UCPD, follow the procedure described in the Reference Manual.
* @rmtoll CFG1 UCPDEN LL_UCPD_Disable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN);
}
/**
* @brief Check if UCPD peripheral is enabled
* @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL);
}
/**
* @brief Set the receiver ordered set detection enable
* @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet
* @param UCPDx UCPD Instance
* @param OrderSet This parameter can be combination of the following values:
* @arg @ref LL_UCPD_ORDERSET_SOP
* @arg @ref LL_UCPD_ORDERSET_SOP1
* @arg @ref LL_UCPD_ORDERSET_SOP2
* @arg @ref LL_UCPD_ORDERSET_HARDRST
* @arg @ref LL_UCPD_ORDERSET_CABLERST
* @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG
* @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG
* @arg @ref LL_UCPD_ORDERSET_SOP_EXT1
* @arg @ref LL_UCPD_ORDERSET_SOP_EXT2
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet);
}
/**
* @brief Set the prescaler for ucpd clock
* @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk
* @param UCPDx UCPD Instance
* @param Psc This parameter can be one of the following values:
* @arg @ref LL_UCPD_PSC_DIV1
* @arg @ref LL_UCPD_PSC_DIV2
* @arg @ref LL_UCPD_PSC_DIV4
* @arg @ref LL_UCPD_PSC_DIV8
* @arg @ref LL_UCPD_PSC_DIV16
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc);
}
/**
* @brief Set the number of cycles (minus 1) of the half bit clock
* @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin
* @param UCPDx UCPD Instance
* @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos);
}
/**
* @brief Set the clock divider value to generate an interframe gap
* @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap
* @param UCPDx UCPD Instance
* @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos);
}
/**
* @brief Set the clock divider value to generate an interframe gap
* @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv
* @param UCPDx UCPD Instance
* @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock)
{
MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_CFG2 CFG2 register
* @{
*/
/**
* @brief Enable the wakeup mode
* @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
}
/**
* @brief Disable the wakeup mode
* @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN);
}
/**
* @brief Force clock enable
* @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
}
/**
* @brief Force clock disable
* @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK);
}
/**
* @brief RxFilter enable
* @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
}
/**
* @brief RxFilter disable
* @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS);
}
/**
* @}
*/
/**
* @}
*/
/** @defgroup UCPD_LL_EF_CR CR register
* @{
*/
/**
* @brief Type C detector for CC2 enable
* @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
}
/**
* @brief Type C detector for CC2 disable
* @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS);
}
/**
* @brief Type C detector for CC1 enable
* @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
}
/**
* @brief Type C detector for CC1 disable
* @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS);
}
/**
* @brief Source Vconn discharge enable
* @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_RDCH);
}
/**
* @brief Source Vconn discharge disable
* @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH);
}
/**
* @brief Signal Fast Role Swap request
* @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_FRSTX);
}
/**
* @brief Fast Role swap RX detection enable
* @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
}
/**
* @brief Fast Role swap RX detection disable
* @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN);
}
/**
* @brief Set cc enable
* @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable
* @param UCPDx UCPD Instance
* @param CCEnable This parameter can be one of the following values:
* @arg @ref LL_UCPD_CCENABLE_NONE
* @arg @ref LL_UCPD_CCENABLE_CC1
* @arg @ref LL_UCPD_CCENABLE_CC2
* @arg @ref LL_UCPD_CCENABLE_CC1CC2
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable);
}
/**
* @brief Set UCPD SNK role
* @rmtoll CR ANAMODE LL_UCPD_SetSNKRole
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
}
/**
* @brief Set UCPD SRC role
* @rmtoll CR ANAMODE LL_UCPD_SetSRCRole
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE);
}
/**
* @brief Get UCPD Role
* @rmtoll CR ANAMODE LL_UCPD_GetRole
* @param UCPDx UCPD Instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_UCPD_ROLE_SNK
* @arg @ref LL_UCPD_ROLE_SRC
*/
__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx)
{
return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE));
}
/**
* @brief Set Rp resistor
* @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor
* @param UCPDx UCPD Instance
* @param Resistor This parameter can be one of the following values:
* @arg @ref LL_UCPD_RESISTOR_DEFAULT
* @arg @ref LL_UCPD_RESISTOR_1_5A
* @arg @ref LL_UCPD_RESISTOR_3_0A
* @arg @ref LL_UCPD_RESISTOR_NONE
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor);
}
/**
* @brief Set CC pin
* @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin
* @param UCPDx UCPD Instance
* @param CCPin This parameter can be one of the following values:
* @arg @ref LL_UCPD_CCPIN_CC1
* @arg @ref LL_UCPD_CCPIN_CC2
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin);
}
/**
* @brief Rx enable
* @rmtoll CR PHYRXEN LL_UCPD_RxEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
}
/**
* @brief Rx disable
* @rmtoll CR PHYRXEN LL_UCPD_RxDisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN);
}
/**
* @brief Set Rx mode
* @rmtoll CR RXMODE LL_UCPD_SetRxMode
* @param UCPDx UCPD Instance
* @param RxMode This parameter can be one of the following values:
* @arg @ref LL_UCPD_RXMODE_NORMAL
* @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode);
}
/**
* @brief Send Hard Reset
* @rmtoll CR TXHRST LL_UCPD_SendHardReset
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_TXHRST);
}
/**
* @brief Send message
* @rmtoll CR TXSEND LL_UCPD_SendMessage
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CR, UCPD_CR_TXSEND);
}
/**
* @brief Set Tx mode
* @rmtoll CR TXMODE LL_UCPD_SetTxMode
* @param UCPDx UCPD Instance
* @param TxMode This parameter can be one of the following values:
* @arg @ref LL_UCPD_TXMODE_NORMAL
* @arg @ref LL_UCPD_TXMODE_CABLE_RESET
* @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode)
{
MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_IT_Management Interrupt Management
* @{
*/
/**
* @brief Enable FRS interrupt
* @rmtoll IMR FRSEVTIE LL_UCPD_EnableIT_FRS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
}
/**
* @brief Enable type c event on CC2
* @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
}
/**
* @brief Enable type c event on CC1
* @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
}
/**
* @brief Enable Rx message end interrupt
* @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
}
/**
* @brief Enable Rx overrun interrupt
* @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
}
/**
* @brief Enable Rx hard resrt interrupt
* @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
}
/**
* @brief Enable Rx orderset interrupt
* @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
}
/**
* @brief Enable Rx non empty interrupt
* @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
}
/**
* @brief Enable TX underrun interrupt
* @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
}
/**
* @brief Enable hard reset sent interrupt
* @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
}
/**
* @brief Enable hard reset discard interrupt
* @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
}
/**
* @brief Enable Tx message abort interrupt
* @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
}
/**
* @brief Enable Tx message sent interrupt
* @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
}
/**
* @brief Enable Tx message discarded interrupt
* @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
}
/**
* @brief Enable Tx data receive interrupt
* @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
}
/**
* @brief Disable FRS interrupt
* @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE);
}
/**
* @brief Disable type c event on CC2
* @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE);
}
/**
* @brief Disable type c event on CC1
* @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE);
}
/**
* @brief Disable Rx message end interrupt
* @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE);
}
/**
* @brief Disable Rx overrun interrupt
* @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE);
}
/**
* @brief Disable Rx hard resrt interrupt
* @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE);
}
/**
* @brief Disable Rx orderset interrupt
* @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE);
}
/**
* @brief Disable Rx non empty interrupt
* @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE);
}
/**
* @brief Disable TX underrun interrupt
* @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE);
}
/**
* @brief Disable hard reset sent interrupt
* @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE);
}
/**
* @brief Disable hard reset discard interrupt
* @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE);
}
/**
* @brief Disable Tx message abort interrupt
* @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE);
}
/**
* @brief Disable Tx message sent interrupt
* @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE);
}
/**
* @brief Disable Tx message discarded interrupt
* @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE);
}
/**
* @brief Disable Tx data receive interrupt
* @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE);
}
/**
* @brief Check if FRS interrupt enabled
* @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL);
}
/**
* @brief Check if type c event on CC2 enabled
* @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL);
}
/**
* @brief Check if type c event on CC1 enabled
* @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx message end interrupt enabled
* @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx overrun interrupt enabled
* @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx hard resrt interrupt enabled
* @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx orderset interrupt enabled
* @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL);
}
/**
* @brief Check if Rx non empty interrupt enabled
* @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL);
}
/**
* @brief Check if TX underrun interrupt enabled
* @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL);
}
/**
* @brief Check if hard reset sent interrupt enabled
* @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL);
}
/**
* @brief Check if hard reset discard interrupt enabled
* @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message abort interrupt enabled
* @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message sent interrupt enabled
* @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message discarded interrupt enabled
* @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL);
}
/**
* @brief Check if Tx data receive interrupt enabled
* @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear
* @{
*/
/**
* @brief Clear FRS interrupt
* @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF);
}
/**
* @brief Clear type c event on CC2
* @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF);
}
/**
* @brief Clear type c event on CC1
* @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF);
}
/**
* @brief Clear Rx message end interrupt
* @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF);
}
/**
* @brief Clear Rx overrun interrupt
* @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF);
}
/**
* @brief Clear Rx hard resrt interrupt
* @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF);
}
/**
* @brief Clear Rx orderset interrupt
* @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF);
}
/**
* @brief Clear TX underrun interrupt
* @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF);
}
/**
* @brief Clear hard reset sent interrupt
* @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF);
}
/**
* @brief Clear hard reset discard interrupt
* @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF);
}
/**
* @brief Clear Tx message abort interrupt
* @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF);
}
/**
* @brief Clear Tx message sent interrupt
* @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF);
}
/**
* @brief Clear Tx message discarded interrupt
* @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management
* @{
*/
/**
* @brief Check if FRS interrupt
* @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL);
}
/**
* @brief Check if type c event on CC2
* @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL);
}
/**
* @brief Check if type c event on CC1
* @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL);
}
/**
* @brief Check if Rx message end interrupt
* @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL);
}
/**
* @brief Check if Rx overrun interrupt
* @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL);
}
/**
* @brief Check if Rx hard resrt interrupt
* @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL);
}
/**
* @brief Check if Rx orderset interrupt
* @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL);
}
/**
* @brief Check if Rx non empty interrupt
* @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL);
}
/**
* @brief Check if TX underrun interrupt
* @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL);
}
/**
* @brief Check if hard reset sent interrupt
* @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL);
}
/**
* @brief Check if hard reset discard interrupt
* @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message abort interrupt
* @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message sent interrupt
* @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL);
}
/**
* @brief Check if Tx message discarded interrupt
* @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL);
}
/**
* @brief Check if Tx data receive interrupt
* @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL);
}
/**
* @brief return the vstate value for CC2
* @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2
* @param UCPDx UCPD Instance
* @retval val
*/
__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx)
{
return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2;
}
/**
* @brief return the vstate value for CC1
* @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1
* @param UCPDx UCPD Instance
* @retval val
*/
__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx)
{
return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1;
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_DMA_Management DMA Management
* @{
*/
/**
* @brief Rx DMA Enable
* @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
}
/**
* @brief Rx DMA Disable
* @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN);
}
/**
* @brief Tx DMA Enable
* @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx)
{
SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
}
/**
* @brief Tx DMA Disable
* @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable
* @param UCPDx UCPD Instance
* @retval None
*/
__STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx)
{
CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN);
}
/**
* @brief Check if DMA Tx is enabled
* @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL);
}
/**
* @brief Check if DMA Rx is enabled
* @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA
* @param UCPDx UCPD Instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx)
{
return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup UCPD_LL_EF_DATA_Management DATA Management
* @{
*/
/**
* @brief write the orderset for Tx message
* @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet
* @param UCPDx UCPD Instance
* @param TxOrderSet one of the following value
* @arg @ref LL_UCPD_ORDERED_SET_SOP
* @arg @ref LL_UCPD_ORDERED_SET_SOP1
* @arg @ref LL_UCPD_ORDERED_SET_SOP2
* @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET
* @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET
* @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG
* @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG
* @retval None
*/
__STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet)
{
WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet);
}
/**
* @brief write the Tx paysize
* @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize
* @param UCPDx UCPD Instance
* @param TxPaySize
* @retval None.
*/
__STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize)
{
WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize);
}
/**
* @brief Write data
* @rmtoll TXDR DR LL_UCPD_WriteData
* @param UCPDx UCPD Instance
* @param Data Value between Min_Data=0x00 and Max_Data=0xFF
* @retval None.
*/
__STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data)
{
WRITE_REG(UCPDx->TXDR, Data);
}
/**
* @brief read RX the orderset
* @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet
* @param UCPDx UCPD Instance
* @retval RxOrderSet one of the following value
* @arg @ref LL_UCPD_RXORDSET_SOP
* @arg @ref LL_UCPD_RXORDSET_SOP1
* @arg @ref LL_UCPD_RXORDSET_SOP2
* @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG
* @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG
* @arg @ref LL_UCPD_RXORDSET_CABLE_RESET
* @arg @ref LL_UCPD_RXORDSET_SOPEXT1
* @arg @ref LL_UCPD_RXORDSET_SOPEXT2
*/
__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx)
{
return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET);
}
/**
* @brief Read the Rx paysize
* @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_ReadRxPaySize
* @param UCPDx UCPD Instance
* @retval RXPaysize.
*/
__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx)
{
return READ_BIT(UCPDx->TX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ);
}
/**
* @brief Read data
* @rmtoll TXDR RXDATA LL_UCPD_ReadData
* @param UCPDx UCPD Instance
* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
*/
__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx)
{
return READ_REG(UCPDx->RXDR);
}
/**
* @brief Set Rx OrderSet Ext1
* @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1
* @param UCPDx UCPD Instance
* @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
{
WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt);
}
/**
* @brief Set Rx OrderSet Ext2
* @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2
* @param UCPDx UCPD Instance
* @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF
* @retval None
*/
__STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt)
{
WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx);
ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct);
void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
#endif /* defined (UCPD1) */
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_UCPD_H */
| 61,904 | C | 32.210837 | 176 | 0.600785 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_smbus.h | /**
******************************************************************************
* @file stm32g4xx_hal_smbus.h
* @author MCD Application Team
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_SMBUS_H
#define STM32G4xx_HAL_SMBUS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup SMBUS
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Types SMBUS Exported Types
* @{
*/
/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
* @brief SMBUS Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value.
This parameter calculated by referring to SMBUS initialization section
in Reference manual */
uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not.
This parameter can be a value of @ref SMBUS_Analog_Filter */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
This parameter can be a value of @ref SMBUS_addressing_mode */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref SMBUS_dual_addressing_mode */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address
if dual addressing mode is selected
This parameter can be a value of @ref SMBUS_own_address2_masks. */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref SMBUS_nostretch_mode */
uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected.
This parameter can be a value of @ref SMBUS_packet_error_check_mode */
uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected.
This parameter can be a value of @ref SMBUS_peripheral_mode */
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
(Enable bits and different timeout values)
This parameter calculated by referring to SMBUS initialization section
in Reference manual */
} SMBUS_InitTypeDef;
/**
* @}
*/
/** @defgroup HAL_state_definition HAL state definition
* @brief HAL State definition
* @{
*/
#define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */
#define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */
#define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */
#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */
#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */
#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */
#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */
#define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */
/**
* @}
*/
/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
* @brief SMBUS Error Code definition
* @{
*/
#define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */
#define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */
#define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */
#define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */
#define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */
#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */
#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */
#define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */
#define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */
/**
* @}
*/
/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
* @brief SMBUS handle Structure definition
* @{
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
typedef struct __SMBUS_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
{
I2C_TypeDef *Instance; /*!< SMBUS registers base address */
SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */
uint16_t XferSize; /*!< SMBUS transfer size */
__IO uint16_t XferCount; /*!< SMBUS transfer counter */
__IO uint32_t XferOptions; /*!< SMBUS transfer options */
__IO uint32_t PreviousState; /*!< SMBUS communication Previous state */
HAL_LockTypeDef Lock; /*!< SMBUS locking object */
__IO uint32_t State; /*!< SMBUS communication state */
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Master Tx Transfer completed callback */
void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Master Rx Transfer completed callback */
void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Slave Tx Transfer completed callback */
void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Slave Rx Transfer completed callback */
void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Listen Complete callback */
void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Error callback */
void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
/*!< SMBUS Slave Address Match callback */
void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Msp Init callback */
void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
/*!< SMBUS Msp DeInit callback */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
} SMBUS_HandleTypeDef;
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
/**
* @brief HAL SMBUS Callback ID enumeration definition
*/
typedef enum
{
HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */
HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */
HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */
HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */
HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */
HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */
HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */
HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */
} HAL_SMBUS_CallbackIDTypeDef;
/**
* @brief HAL SMBUS Callback pointer definition
*/
typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
/*!< pointer to an SMBUS callback function */
typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
uint16_t AddrMatchCode);
/*!< pointer to an SMBUS Address Match callback function */
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
* @{
*/
/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
* @{
*/
#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup SMBUS_addressing_mode SMBUS addressing mode
* @{
*/
#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
* @{
*/
#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
* @{
*/
#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
* @{
*/
#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode
* @{
*/
#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
* @{
*/
#define SMBUS_PEC_DISABLE (0x00000000U)
#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
/**
* @}
*/
/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
* @{
*/
#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
/**
* @}
*/
/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
* @{
*/
#define SMBUS_SOFTEND_MODE (0x00000000U)
#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
/**
* @}
*/
/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
* @{
*/
#define SMBUS_NO_STARTSTOP (0x00000000U)
#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
* @{
*/
/* List of XferOptions in usage of :
* 1- Restart condition when direction change
* 2- No Restart condition in other use cases
*/
#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
/* List of XferOptions in usage of :
* 1- Restart condition in all use cases (direction change or not)
*/
#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
/**
* @}
*/
/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
* @brief SMBUS Interrupt definition
* Elements values convention: 0xXXXXXXXX
* - XXXXXXXX : Interrupt control mask
* @{
*/
#define SMBUS_IT_ERRI I2C_CR1_ERRIE
#define SMBUS_IT_TCI I2C_CR1_TCIE
#define SMBUS_IT_STOPI I2C_CR1_STOPIE
#define SMBUS_IT_NACKI I2C_CR1_NACKIE
#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
#define SMBUS_IT_RXI I2C_CR1_RXIE
#define SMBUS_IT_TXI I2C_CR1_TXIE
#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
SMBUS_IT_NACKI | SMBUS_IT_TXI)
#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
SMBUS_IT_RXI)
#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
/**
* @}
*/
/** @defgroup SMBUS_Flag_definition SMBUS Flag definition
* @brief Flag definition
* Elements values convention: 0xXXXXYYYY
* - XXXXXXXX : Flag mask
* @{
*/
#define SMBUS_FLAG_TXE I2C_ISR_TXE
#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
#define SMBUS_FLAG_AF I2C_ISR_NACKF
#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
#define SMBUS_FLAG_TC I2C_ISR_TC
#define SMBUS_FLAG_TCR I2C_ISR_TCR
#define SMBUS_FLAG_BERR I2C_ISR_BERR
#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
#define SMBUS_FLAG_OVR I2C_ISR_OVR
#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
#define SMBUS_FLAG_DIR I2C_ISR_DIR
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
* @{
*/
/** @brief Reset SMBUS handle state.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/** @brief Enable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified SMBUS interrupts.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified SMBUS interrupt source is enabled or not.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __INTERRUPT__ specifies the SMBUS interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref SMBUS_IT_ERRI Errors interrupt enable
* @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable
* @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
* @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
* @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
* @arg @ref SMBUS_IT_RXI RX interrupt enable
* @arg @ref SMBUS_IT_TXI TX interrupt enable
*
* @retval The new state of __IT__ (SET or RESET).
*/
#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SMBUS flag is set or not.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
* @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
* @arg @ref SMBUS_FLAG_TCR Transfer complete reload
* @arg @ref SMBUS_FLAG_BERR Bus error
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
* @arg @ref SMBUS_FLAG_BUSY Bus busy
* @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define SMBUS_FLAG_MASK (0x0001FFFFU)
#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
(((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
/** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref SMBUS_FLAG_TXE Transmit data register empty
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
* @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
* @arg @ref SMBUS_FLAG_BERR Bus error
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
* @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \
((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified SMBUS peripheral.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified SMBUS peripheral.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
* @param __HANDLE__ specifies the SMBUS Handle.
* @retval None
*/
#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SMBUS_Private_Macro SMBUS Private Macros
* @{
*/
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
((MASK) == SMBUS_OA2_MASK01) || \
((MASK) == SMBUS_OA2_MASK02) || \
((MASK) == SMBUS_OA2_MASK03) || \
((MASK) == SMBUS_OA2_MASK04) || \
((MASK) == SMBUS_OA2_MASK05) || \
((MASK) == SMBUS_OA2_MASK06) || \
((MASK) == SMBUS_OA2_MASK07))
#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
((CALL) == SMBUS_GENERALCALL_ENABLE))
#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
((PEC) == SMBUS_PEC_ENABLE))
#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
((MODE) == SMBUS_AUTOEND_MODE) || \
((MODE) == SMBUS_SOFTEND_MODE) || \
((MODE) == SMBUS_SENDPEC_MODE) || \
((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
SMBUS_RELOAD_MODE )))
#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
((REQUEST) == SMBUS_GENERATE_START_READ) || \
((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
((REQUEST) == SMBUS_NO_STARTSTOP))
#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
((REQUEST) == SMBUS_FIRST_FRAME) || \
((REQUEST) == SMBUS_NEXT_FRAME) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
(uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
I2C_CR1_PECEN)))
#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
(uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
I2C_CR2_RD_WRN)))
#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
(~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & \
(I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
(I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
/**
* @}
*/
/* Include SMBUS HAL Extended module */
#include "stm32g4xx_hal_smbus_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
* @{
*/
/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
/* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
HAL_SMBUS_CallbackIDTypeDef CallbackID,
pSMBUS_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
HAL_SMBUS_CallbackIDTypeDef CallbackID);
HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
pSMBUS_AddrCallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
* @{
*/
/* IO operation functions *****************************************************/
/** @addtogroup Blocking_mode_Polling Blocking mode Polling
* @{
*/
/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
uint32_t Timeout);
/**
* @}
*/
/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
* @{
*/
/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
uint32_t XferOptions);
HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
* @{
*/
/* Peripheral State and Errors functions **************************************************/
uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
/**
* @}
*/
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup SMBUS_Private_Functions SMBUS Private Functions
* @{
*/
/* Private functions are defined in stm32g4xx_hal_smbus.c file */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_SMBUS_H */
| 37,247 | C | 46.030303 | 117 | 0.527318 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/STM32G4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h | /**
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
* Copyright (c) 2021 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32_HAL_LEGACY
#define STM32_HAL_LEGACY
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
* @{
*/
#define AES_FLAG_RDERR CRYP_FLAG_RDERR
#define AES_FLAG_WRERR CRYP_FLAG_WRERR
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
#if defined(STM32U5)
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
* @{
*/
#define ADC_RESOLUTION12b ADC_RESOLUTION_12B
#define ADC_RESOLUTION10b ADC_RESOLUTION_10B
#define ADC_RESOLUTION8b ADC_RESOLUTION_8B
#define ADC_RESOLUTION6b ADC_RESOLUTION_6B
#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
#define REGULAR_GROUP ADC_REGULAR_GROUP
#define INJECTED_GROUP ADC_INJECTED_GROUP
#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
#define AWD_EVENT ADC_AWD_EVENT
#define AWD1_EVENT ADC_AWD1_EVENT
#define AWD2_EVENT ADC_AWD2_EVENT
#define AWD3_EVENT ADC_AWD3_EVENT
#define OVR_EVENT ADC_OVR_EVENT
#define JQOVF_EVENT ADC_JQOVF_EVENT
#define ALL_CHANNELS ADC_ALL_CHANNELS
#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
#if defined(STM32H7)
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
* @{
*/
#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
/**
* @}
*/
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
#if defined(STM32L0)
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32L0) || defined(STM32L4)
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#if defined(STM32L0)
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
/* to the second dedicated IO (only for COMP2). */
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
#else
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#endif
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
#if defined(COMP_CSR_LOCK)
#define COMP_FLAG_LOCK COMP_CSR_LOCK
#elif defined(COMP_CSR_COMP1LOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#elif defined(COMP_CSR_COMPxLOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
#endif
#if defined(STM32L4)
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
#endif
#if defined(STM32L0)
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
#else
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
#endif
#endif
/**
* @}
*/
/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
* @{
*/
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
#if defined(STM32U5)
#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE
#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE
#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup CRC_Aliases CRC API aliases
* @{
*/
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
/**
* @}
*/
/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
/**
* @}
*/
/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
* @{
*/
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
#define DAC_WAVE_NONE 0x00000000U
#define DAC_WAVE_NOISE DAC_CR_WAVE1_0
#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32U5)
#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1
#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
/**
* @}
*/
/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
#define IS_HAL_REMAPDMA IS_DMA_REMAP
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
#if defined(STM32L4)
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1
#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2
#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3
#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4
#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5
#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6
#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7
#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8
#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9
#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10
#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11
#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
#endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM
#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM
#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM
#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM
#endif
#if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
* @{
*/
#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
#define OBEX_PCROP OPTIONBYTE_PCROP
#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
#define PAGESIZE FLASH_PAGE_SIZE
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
#define OB_WDG_SW OB_IWDG_SW
#define OB_WDG_HW OB_IWDG_HW
#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
#if defined(STM32G0)
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
#else
#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE
#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE
#endif
#if defined(STM32H7)
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
#if defined(STM32U5)
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0
#define OB_USER_nBOOT0 OB_USER_NBOOT0
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
#define OB_nBOOT0_SET OB_NBOOT0_SET
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
#if defined(STM32G4)
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
/**
* @}
*/
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
#endif
/**
* @}
*/
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
* @{
*/
#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
/**
* @}
*/
/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
* @{
*/
#define GET_GPIO_SOURCE GPIO_GET_INDEX
#define GET_GPIO_INDEX GPIO_GET_INDEX
#if defined(STM32F4)
#define GPIO_AF12_SDMMC GPIO_AF12_SDIO
#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
#endif
#if defined(STM32F7)
#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif
#if defined(STM32L4)
#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
#endif
#if defined(STM32H7)
#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1
#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1
#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \
defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
#if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
#if defined(STM32U5)
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
* @{
*/
#if defined(STM32U5)
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
#if defined(STM32G4)
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A
#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
#endif /* STM32G4 */
#if defined(STM32H7)
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
#if defined(STM32F3)
/** @brief Constants defining available sources associated to external events.
*/
#define HRTIM_EVENTSRC_1 (0x00000000U)
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/**
* @}
*/
/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
* @{
*/
#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
#endif
/**
* @}
*/
/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
* @{
*/
#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
/**
* @}
*/
/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
* @{
*/
#define KR_KEY_RELOAD IWDG_KEY_RELOAD
#define KR_KEY_ENABLE IWDG_KEY_ENABLE
#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
/**
* @}
*/
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
* @{
*/
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/* The following 3 definition have also been present in a temporary version of lptim.h */
/* They need to be renamed also to the right name, just in case */
#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
/**
* @}
*/
/** @defgroup HAL_LPTIM_Aliased_Defines LL LPTIM Aliased Defines maintained for legacy purpose
* @{
*/
#define LL_LPTIM_SetCompareCH1 LL_LPTIM_OC_SetCompareCH1
#define LL_LPTIM_SetCompareCH2 LL_LPTIM_OC_SetCompareCH2
#define LL_LPTIM_GetCompareCH1 LL_LPTIM_OC_GetCompareCH1
#define LL_LPTIM_GetCompareCH2 LL_LPTIM_OC_GetCompareCH2
/**
* @}
*/
#if defined(STM32U5)
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
#define LPTIM_CHANNEL_ALL 0x00000000U
#endif /* STM32U5 */
/**
* @}
*/
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
#define NAND_AddressTypedef NAND_AddressTypeDef
#define __ARRAY_ADDRESS ARRAY_ADDRESS
#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
/**
* @}
*/
/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
* @{
*/
#define NOR_StatusTypedef HAL_NOR_StatusTypeDef
#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
#define NOR_ONGOING HAL_NOR_STATUS_ONGOING
#define NOR_ERROR HAL_NOR_STATUS_ERROR
#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
#define __NOR_WRITE NOR_WRITE
#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
/**
* @}
*/
/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
* @{
*/
#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
#if defined(STM32L4) || defined(STM32L5)
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER
#elif defined(STM32G4)
#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED
#endif
/**
* @}
*/
/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32H7)
#define I2S_IT_TXE I2S_IT_TXP
#define I2S_IT_RXNE I2S_IT_RXP
#define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP
#endif
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
*/
/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
* @{
*/
/* Compact Flash-ATA registers description */
#define CF_DATA ATA_DATA
#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
#define CF_CARD_HEAD ATA_CARD_HEAD
#define CF_STATUS_CMD ATA_STATUS_CMD
#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
/* Compact Flash-ATA commands */
#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
/**
* @}
*/
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
#define FORMAT_BIN RTC_FORMAT_BIN
#define FORMAT_BCD RTC_FORMAT_BCD
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
* @{
*/
#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
/**
* @}
*/
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{
*/
#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
/**
* @}
*/
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
* @{
*/
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
#if defined(STM32H7)
#define SPI_FLAG_TXE SPI_FLAG_TXP
#define SPI_FLAG_RXNE SPI_FLAG_RXP
#define SPI_IT_TXE SPI_IT_TXP
#define SPI_IT_RXNE SPI_IT_RXP
#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET
#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET
#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET
#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET
#endif /* STM32H7 */
/**
* @}
*/
/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
* @{
*/
#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
#define TIM_DMABase_CR1 TIM_DMABASE_CR1
#define TIM_DMABase_CR2 TIM_DMABASE_CR2
#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
#define TIM_DMABase_DIER TIM_DMABASE_DIER
#define TIM_DMABase_SR TIM_DMABASE_SR
#define TIM_DMABase_EGR TIM_DMABASE_EGR
#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
#define TIM_DMABase_CCER TIM_DMABASE_CCER
#define TIM_DMABase_CNT TIM_DMABASE_CNT
#define TIM_DMABase_PSC TIM_DMABASE_PSC
#define TIM_DMABase_ARR TIM_DMABASE_ARR
#define TIM_DMABase_RCR TIM_DMABASE_RCR
#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
#define TIM_DMABase_BDTR TIM_DMABASE_BDTR
#define TIM_DMABase_DCR TIM_DMABASE_DCR
#define TIM_DMABase_DMAR TIM_DMABASE_DMAR
#define TIM_DMABase_OR1 TIM_DMABASE_OR1
#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
#define TIM_DMABase_OR2 TIM_DMABASE_OR2
#define TIM_DMABase_OR3 TIM_DMABASE_OR3
#define TIM_DMABase_OR TIM_DMABASE_OR
#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
#define TIM_EventSource_COM TIM_EVENTSOURCE_COM
#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
#if defined(STM32L0)
#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO
#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO
#endif
#if defined(STM32F3)
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif
#if defined(STM32H7)
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
/**
* @}
*/
/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
* @{
*/
#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
/**
* @}
*/
/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
* @{
*/
#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
#define __DIV_SAMPLING16 UART_DIV_SAMPLING16
#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
#define __DIV_SAMPLING8 UART_DIV_SAMPLING8
#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
#define __DIV_LPUART UART_DIV_LPUART
#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
/**
* @}
*/
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
* @{
*/
#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
#define USARTNACK_ENABLED USART_NACK_ENABLE
#define USARTNACK_DISABLED USART_NACK_DISABLE
/**
* @}
*/
/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
* @{
*/
#define CFR_BASE WWDG_CFR_BASE
/**
* @}
*/
/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
* @{
*/
#define CAN_FilterFIFO0 CAN_FILTER_FIFO0
#define CAN_FilterFIFO1 CAN_FILTER_FIFO1
#define CAN_IT_RQCP0 CAN_IT_TME
#define CAN_IT_RQCP1 CAN_IT_TME
#define CAN_IT_RQCP2 CAN_IT_TME
#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
/**
* @}
*/
/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
* @{
*/
#define VLAN_TAG ETH_VLAN_TAG
#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
#define ETH_MMCCR 0x00000100U
#define ETH_MMCRIR 0x00000104U
#define ETH_MMCTIR 0x00000108U
#define ETH_MMCRIMR 0x0000010CU
#define ETH_MMCTIMR 0x00000110U
#define ETH_MMCTGFSCCR 0x0000014CU
#define ETH_MMCTGFMSCCR 0x00000150U
#define ETH_MMCTGFCR 0x00000168U
#define ETH_MMCRFCECR 0x00000194U
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
/**
* @}
*/
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
#define DCMI_IT_OVF DCMI_IT_OVR
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
/**
* @}
*/
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|| defined(STM32H7)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
#define CM_RGB888 DMA2D_INPUT_RGB888
#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
#define CM_L8 DMA2D_INPUT_L8
#define CM_AL44 DMA2D_INPUT_AL44
#define CM_AL88 DMA2D_INPUT_AL88
#define CM_L4 DMA2D_INPUT_L4
#define CM_A8 DMA2D_INPUT_A8
#define CM_A4 DMA2D_INPUT_A4
/**
* @}
*/
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
|| defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
|| defined(STM32H7) || defined(STM32U5)
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
for compatibility with legacy code */
/**
* @}
*/
#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
/**
* @}
*/
/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
* @{
*/
#if defined(STM32U5)
#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr
#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT
#endif /* STM32U5 */
/**
* @}
*/
#if !defined(STM32F2)
/** @defgroup HASH_alias HASH API alias
* @{
*/
#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */
/**
*
* @}
*/
#endif /* STM32F2 */
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
/*HASH Algorithm Selection*/
#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt
#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End
#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT
#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT
#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt
#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End
#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT
#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT
#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt
#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End
#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT
#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT
#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt
#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End
#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT
#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT
#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
/**
* @}
*/
/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
#else
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
/**
* @}
*/
/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
* @{
*/
#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
/**
* @}
*/
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
#if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT
#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA
#endif /* STM32F4 */
/**
* @}
*/
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{
*/
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
#define CR_OFFSET_BB PWR_CR_OFFSET_BB
#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
#define CR_PMODE_BB CR_VOS_BB
#define DBP_BitNumber DBP_BIT_NUMBER
#define PVDE_BitNumber PVDE_BIT_NUMBER
#define PMODE_BitNumber PMODE_BIT_NUMBER
#define EWUP_BitNumber EWUP_BIT_NUMBER
#define FPDS_BitNumber FPDS_BIT_NUMBER
#define ODEN_BitNumber ODEN_BIT_NUMBER
#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
#define BRE_BitNumber BRE_BIT_NUMBER
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
/**
* @}
*/
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
/**
* @}
*/
/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
/**
* @}
*/
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
#define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/**
* @}
*/
/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
/**
* @}
*/
/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
#define HAL_LTDC_Relaod HAL_LTDC_Reload
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
* @{
*/
#define AES_IT_CC CRYP_IT_CC
#define AES_IT_ERR CRYP_IT_ERR
#define AES_FLAG_CCF CRYP_FLAG_CCF
/**
* @}
*/
/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
/**
* @}
*/
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
* @{
*/
#define __ADC_ENABLE __HAL_ADC_ENABLE
#define __ADC_DISABLE __HAL_ADC_DISABLE
#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
#define __ADC_IS_ENABLED ADC_IS_ENABLE
#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
#define __HAL_ADC_JSQR_RK ADC_JSQR_RK
#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
#define __HAL_ADC_SQR1 ADC_SQR1
#define __HAL_ADC_SMPR1 ADC_SMPR1
#define __HAL_ADC_SMPR2 ADC_SMPR2
#define __HAL_ADC_SQR3_RK ADC_SQR3_RK
#define __HAL_ADC_SQR2_RK ADC_SQR2_RK
#define __HAL_ADC_SQR1_RK ADC_SQR1_RK
#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
#define __HAL_ADC_JSQR ADC_JSQR
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
/**
* @}
*/
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
/**
* @}
*/
/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
#if defined(STM32H7)
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
#else
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
#endif /* STM32H7 */
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
/**
* @}
*/
/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32F3)
#define COMP_START __HAL_COMP_ENABLE
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
__HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F302xE) || defined(STM32F302xC)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP6_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP6_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
__HAL_COMP_COMP6_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP7_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP7_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
__HAL_COMP_COMP7_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
# endif
# if defined(STM32F373xC) ||defined(STM32F378xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
# endif
#else
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
__HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
__HAL_COMP_COMP2_EXTI_ENABLE_IT())
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
__HAL_COMP_COMP2_EXTI_DISABLE_IT())
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
__HAL_COMP_COMP2_EXTI_GET_FLAG())
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
#endif
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
#if defined(STM32L0) || defined(STM32L4)
/* Note: On these STM32 families, the only argument of this macro */
/* is COMP_FLAG_LOCK. */
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
/* argument. */
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
#endif
/**
* @}
*/
#if defined(STM32L0) || defined(STM32L4)
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
/**
* @}
*/
#endif
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
* @{
*/
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
((WAVE) == DAC_WAVE_NOISE)|| \
((WAVE) == DAC_WAVE_TRIANGLE))
/**
* @}
*/
/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
* @{
*/
#define IS_WRPAREA IS_OB_WRPAREA
#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
#define IS_TYPEERASE IS_FLASH_TYPEERASE
#define IS_NBSECTORS IS_FLASH_NBSECTORS
#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
/**
* @}
*/
/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
#if defined(STM32F1)
#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
#else
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
#endif /* STM32F1 */
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
#define __HAL_I2C_SPEED I2C_SPEED
#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
#define __HAL_I2C_FREQRANGE I2C_FREQRANGE
/**
* @}
*/
/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
* @{
*/
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
#if defined(STM32H7)
#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG
#endif
/**
* @}
*/
/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
* @{
*/
#define __IRDA_DISABLE __HAL_IRDA_DISABLE
#define __IRDA_ENABLE __HAL_IRDA_ENABLE
#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
/**
* @}
*/
/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
/**
* @}
*/
/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
/**
* @}
*/
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
* @{
*/
#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
/**
* @}
*/
/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
#if defined (STM32F4)
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
#else
#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
#endif /* STM32F4 */
/**
* @}
*/
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
* @{
*/
#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
#if defined(STM32WB)
#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
#define QSPI_IRQHandler QUADSPI_IRQHandler
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
#if defined(STM32H7)
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
/* alias define maintained for legacy */
#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
#if defined(STM32L1)
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
#endif /* STM32L1 */
#if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
#define Sdmmc1ClockSelection SdioClockSelection
#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
#endif
#if defined(STM32F7) || defined(STM32L4)
#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
#define SdioClockSelection Sdmmc1ClockSelection
#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
#endif
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
#if defined(STM32H7)
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
#endif
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
#define IS_RCC_HCLK_DIV IS_RCC_PCLK
#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
#define RCC_IT_HSI14 RCC_IT_HSI14RDY
#define RCC_IT_CSSLSE RCC_IT_LSECSS
#define RCC_IT_CSSHSE RCC_IT_CSS
#define RCC_PLLMUL_3 RCC_PLL_MUL3
#define RCC_PLLMUL_4 RCC_PLL_MUL4
#define RCC_PLLMUL_6 RCC_PLL_MUL6
#define RCC_PLLMUL_8 RCC_PLL_MUL8
#define RCC_PLLMUL_12 RCC_PLL_MUL12
#define RCC_PLLMUL_16 RCC_PLL_MUL16
#define RCC_PLLMUL_24 RCC_PLL_MUL24
#define RCC_PLLMUL_32 RCC_PLL_MUL32
#define RCC_PLLMUL_48 RCC_PLL_MUL48
#define RCC_PLLDIV_2 RCC_PLL_DIV2
#define RCC_PLLDIV_3 RCC_PLL_DIV3
#define RCC_PLLDIV_4 RCC_PLL_DIV4
#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
#define RCC_MCO_NODIV RCC_MCODIV_1
#define RCC_MCO_DIV1 RCC_MCODIV_1
#define RCC_MCO_DIV2 RCC_MCODIV_2
#define RCC_MCO_DIV4 RCC_MCODIV_4
#define RCC_MCO_DIV8 RCC_MCODIV_8
#define RCC_MCO_DIV16 RCC_MCODIV_16
#define RCC_MCO_DIV32 RCC_MCODIV_32
#define RCC_MCO_DIV64 RCC_MCODIV_64
#define RCC_MCO_DIV128 RCC_MCODIV_128
#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
#define HSION_BitNumber RCC_HSION_BIT_NUMBER
#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
#define LSION_BitNumber RCC_LSION_BIT_NUMBER
#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
#define CR_HSION_BB RCC_CR_HSION_BB
#define CR_CSSON_BB RCC_CR_CSSON_BB
#define CR_PLLON_BB RCC_CR_PLLON_BB
#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
#define CR_MSION_BB RCC_CR_MSION_BB
#define CSR_LSION_BB RCC_CSR_LSION_BB
#define CSR_LSEON_BB RCC_CSR_LSEON_BB
#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
#define CR_HSEON_BB RCC_CR_HSEON_BB
#define CSR_RMVF_BB RCC_CSR_RMVF_BB
#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
#if defined(STM32U5)
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE
#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE
#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE
#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE
#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE
#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE
#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT
#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK
#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#endif
/**
* @}
*/
/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
* @{
*/
#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
/**
* @}
*/
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
#if defined (STM32F1)
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
#else
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
(((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
#endif /* STM32F1 */
#define IS_ALARM IS_RTC_ALARM
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
/**
* @}
*/
/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
* @{
*/
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE
#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV
#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV
#endif
#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
/* alias CMSIS */
#define SDMMC1_IRQn SDIO_IRQn
#define SDMMC1_IRQHandler SDIO_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32L4)
#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
/* alias CMSIS for compatibilities */
#define SDIO_IRQn SDMMC1_IRQn
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
#if defined(STM32H7) || defined(STM32L5)
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback
#endif
/**
* @}
*/
/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
* @{
*/
#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
/**
* @}
*/
/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
/**
* @}
*/
/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_SPI_1LINE_TX SPI_1LINE_TX
#define __HAL_SPI_1LINE_RX SPI_1LINE_RX
#define __HAL_SPI_RESET_CRC SPI_RESET_CRC
/**
* @}
*/
/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
/**
* @}
*/
/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
* @{
*/
#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
#define __USART_ENABLE __HAL_USART_ENABLE
#define __USART_DISABLE __HAL_USART_DISABLE
#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
#define USART_OVERSAMPLING_16 0x00000000U
#define USART_OVERSAMPLING_8 USART_CR1_OVER8
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
((__SAMPLING__) == USART_OVERSAMPLING_8))
#endif /* STM32F0 || STM32F3 || STM32F7 */
/**
* @}
*/
/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
* @{
*/
#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
/**
* @}
*/
/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
/**
* @}
*/
/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
/**
* @}
*/
/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
* @{
*/
#define __HAL_LTDC_LAYER LTDC_LAYER
#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
/**
* @}
*/
/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
* @{
*/
#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
#define SAI_STREOMODE SAI_STEREOMODE
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
/**
* @}
*/
/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
* @{
*/
#if defined(STM32H7)
#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
#endif
/**
* @}
*/
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{
*/
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
*/
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif /* STM32L4 || STM32F4 || STM32F7 */
/**
* @}
*/
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32F7)
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
#endif /* STM32F7 */
/**
* @}
*/
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32_HAL_LEGACY */
| 214,191 | C | 53.738564 | 280 | 0.664846 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Source/Templates/system_stm32g4xx.c | /**
******************************************************************************
* @file system_stm32g4xx.c
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
*
* This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32g4xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32g4xx.s" file, to
* configure the system clock before to branch to main program.
*
* This file configures the system clock as follows:
*=============================================================================
*-----------------------------------------------------------------------------
* System Clock source | HSI
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 16000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 1
*-----------------------------------------------------------------------------
* APB2 Prescaler | 1
*-----------------------------------------------------------------------------
* PLL_M | 1
*-----------------------------------------------------------------------------
* PLL_N | 16
*-----------------------------------------------------------------------------
* PLL_P | 7
*-----------------------------------------------------------------------------
* PLL_Q | 2
*-----------------------------------------------------------------------------
* PLL_R | 2
*-----------------------------------------------------------------------------
* Require 48MHz for RNG | Disabled
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g4xx_system
* @{
*/
/** @addtogroup STM32G4xx_System_Private_Includes
* @{
*/
#include "stm32g4xx.h"
#if !defined (HSE_VALUE)
#define HSE_VALUE 24000000U /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Private_Defines
* @{
*/
/************************* Miscellaneous Configuration ************************/
/* Note: Following vector table addresses must be defined in line with linker
configuration. */
/*!< Uncomment the following line if you need to relocate the vector table
anywhere in Flash or Sram, else the vector table is kept at the automatic
remap of boot address selected */
/* #define USER_VECT_TAB_ADDRESS */
#if defined(USER_VECT_TAB_ADDRESS)
/*!< Uncomment the following line if you need to relocate your vector Table
in Sram else user remap will be done in Flash. */
/* #define VECT_TAB_SRAM */
#if defined(VECT_TAB_SRAM)
#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#else
#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif /* VECT_TAB_SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
/******************************************************************************/
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Private_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
uint32_t SystemCoreClock = HSI_VALUE;
const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Private_FunctionPrototypes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
#endif
/* Configure the Vector Table location add offset address ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (**) HSI_VALUE is a constant defined in stm32g4xx_hal.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (***) HSE_VALUE is a constant defined in stm32g4xx_hal.h file (default value
* 24 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp, pllvco, pllr, pllsource, pllm;
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
{
case 0x04: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x08: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x0C: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1U ;
if (pllsource == 0x02UL) /* HSI used as PLL clock source */
{
pllvco = (HSI_VALUE / pllm);
}
else /* HSE used as PLL clock source */
{
pllvco = (HSE_VALUE / pllm);
}
pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1U) * 2U;
SystemCoreClock = pllvco/pllr;
break;
default:
break;
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
| 10,571 | C | 35.965035 | 101 | 0.4781 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Include/system_stm32g4xx.h | /**
******************************************************************************
* @file system_stm32g4xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M4 Device System Source File for STM32G4xx devices.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32g4xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32G4XX_H
#define __SYSTEM_STM32G4XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32G4xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Exported_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32G4xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32G4XX_H */
/**
* @}
*/
/**
* @}
*/
| 2,252 | C | 20.457143 | 91 | 0.569716 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g474xx.h | /**
******************************************************************************
* @file stm32g474xx.h
* @author MCD Application Team
* @brief CMSIS STM32G474xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32g474xx
* @{
*/
#ifndef __STM32G474xx_H
#define __STM32G474xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32G4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ***************************************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_IRQn = 19, /*!< USB HP Interrupt */
USB_LP_IRQn = 20, /*!< USB LP Interrupt */
FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
TIM7_DAC_IRQn = 55, /*!< TIM7 global and DAC2&4 underrun error interrupts */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
ADC5_IRQn = 62, /*!< ADC5 global Interrupt */
UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 */
COMP7_IRQn = 66, /*!< COMP7 Interrupt */
HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupt */
HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
HRTIM1_TIMF_IRQn = 74, /*!< HRTIM Timer F global Interrupt */
CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */
I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */
SPI4_IRQn = 84, /*!< SPI4 Event interrupt */
FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */
FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */
FDCAN3_IT0_IRQn = 88, /*!< FDCAN3 interrupt line 0 interrupt */
FDCAN3_IT1_IRQn = 89, /*!< FDCAN3 interrupt line 1 interrupt */
RNG_IRQn = 90, /*!< RNG global interrupt */
LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */
DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */
DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */
DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */
CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
FMAC_IRQn = 101 /*!< FMAC global Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32g4xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
__IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
} FDCAN_Config_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
__IO uint32_t RESERVED[2];
__IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
__IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
__IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
__IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
__IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
__IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
__IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
__IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */
__IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
__IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */
} FLASH_TypeDef;
/**
* @brief FMAC
*/
typedef struct
{
__IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
__IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
__IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
__IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
} FMAC_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
uint32_t RESERVED0; /*!< Reserved, 0x90 */
__IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
} FMC_Bank3_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
} OPAMP_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
__IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief QUAD Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
__IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
__IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
__IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
__IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
__IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
__IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
/*
* @brief Specific device feature definitions
*/
#define RTC_TAMP_INT_6_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 3u
#define RTC_BACKUP_NB 32u
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
} RTC_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
__IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
__IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
__IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
__IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
__IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
__IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
__IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
__IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
__IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
__IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
__IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
__IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
__IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
__IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
__IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
__IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
} TAMP_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
__IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
__IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
__IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
__IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
__IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
__IO uint16_t RESERVEDD; /*!< Reserved */
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
__IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief CORDIC
*/
typedef struct
{
__IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
__IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
__IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
} CORDIC_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @brief High resolution Timer (HRTIM)
*/
#define c7amba_hrtim1_v2_0
/* HRTIM master registers definition */
typedef struct
{
__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
__IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
__IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
__IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
uint32_t RESERVED0; /*!< Reserved, 0x20 */
__IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
__IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
__IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
}HRTIM_Master_TypeDef;
/* HRTIM Timer A to F registers definition */
typedef struct
{
__IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
__IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
__IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
__IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
__IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
__IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
__IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
__IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
__IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
__IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
__IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
__IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
__IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
__IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
__IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
__IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
__IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
__IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
__IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
__IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
__IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
__IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
__IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
__IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
__IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
__IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
__IO uint32_t TIMxCR2; /*!< HRTIM Timerx Control register 2, Address offset: 0x6C */
__IO uint32_t EEFxR3; /*!< HRTIM Timerx external event filtering 3 register, Address offset: 0x70 */
uint32_t RESERVED0[3]; /*!< Reserved, 0x74..0x7C */
}HRTIM_Timerx_TypeDef;
/* HRTIM common register definition */
typedef struct
{
__IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
__IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
__IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
__IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
__IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
__IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
__IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
__IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
__IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
__IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
__IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
__IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
__IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
__IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
__IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
__IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
__IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
__IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
__IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
__IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
__IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
__IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
__IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
__IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
__IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
__IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
__IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
__IO uint32_t BDTFUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x74 */
__IO uint32_t ADCER; /*!< HRTIM ADC Extended Trigger register, Address offset: 0x78 */
__IO uint32_t ADCUR; /*!< HRTIM ADC Trigger Update register, Address offset: 0x7C */
__IO uint32_t ADCPS1; /*!< HRTIM ADC Post Scaler Register 1, Address offset: 0x80 */
__IO uint32_t ADCPS2; /*!< HRTIM ADC Post Scaler Register 2, Address offset: 0x84 */
__IO uint32_t FLTINR3; /*!< HRTIM Fault input register3, Address offset: 0x88 */
__IO uint32_t FLTINR4; /*!< HRTIM Fault input register4, Address offset: 0x8C */
}HRTIM_Common_TypeDef;
/* HRTIM register definition */
typedef struct {
HRTIM_Master_TypeDef sMasterRegs;
HRTIM_Timerx_TypeDef sTimerxRegs[6];
HRTIM_Common_TypeDef sCommonRegs;
}HRTIM_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */
#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define FMC_BASE (0x60000000UL) /*!< FMC base address */
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */
#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
#define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
#define FMC_BANK1 FMC_BASE
#define FMC_BANK1_1 FMC_BANK1
#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
#define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
#define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL)
#define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL)
#define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL)
#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
#define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL)
#define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL)
#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
#define HRTIM1_BASE (APB2PERIPH_BASE + 0x6800UL)
#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x0080UL)
#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x0100UL)
#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x0180UL)
#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x0200UL)
#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x0280UL)
#define HRTIM1_TIMF_BASE (HRTIM1_BASE + 0x0300UL)
#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x0380UL)
/*!< AHB1 peripherals */
#define DMA1_BASE (AHB1PERIPH_BASE)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
/*!< AHB2 peripherals */
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)
#define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL)
#define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL)
#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)
#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL)
#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
#define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL)
/*!< FMC Banks registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0042000UL)
#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
#define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE)
#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
#define HRTIM1_TIMF ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMF_BASE)
#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
#define ADC5 ((ADC_TypeDef *) ADC5_BASE)
#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
#define DAC4 ((DAC_TypeDef *) DAC4_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos (15U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
#define ADC_CFGR2_GCOMP_Pos (16U)
#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
#define ADC_CFGR2_SWTRIG_Pos (25U)
#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
#define ADC_CFGR2_BULB_Pos (26U)
#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
#define ADC_CFGR2_SMPTRIG_Pos (27U)
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_AWDFILT_Pos (12U)
#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSETPOS_Pos (24U)
#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
#define ADC_OFR1_SATEN_Pos (25U)
#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSETPOS_Pos (24U)
#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
#define ADC_OFR2_SATEN_Pos (25U)
#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSETPOS_Pos (24U)
#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
#define ADC_OFR3_SATEN_Pos (25U)
#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSETPOS_Pos (24U)
#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
#define ADC_OFR4_SATEN_Pos (25U)
#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
/******************** Bit definition for ADC_GCOMP register *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos (13U)
#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
#define ADC_CCR_MDMA_Pos (14U)
#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_VSENSESEL_Pos (23U)
#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATSEL_Pos (24U)
#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_INMSEL_Pos (4U)
#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_Pos (8U)
#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
#define COMP_CSR_BLANKING_Pos (19U)
#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
/* CORDIC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CORDIC_CSR register *****************/
#define CORDIC_CSR_FUNC_Pos (0U)
#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos (4U)
#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos (8U)
#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos (16U)
#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos (17U)
#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos (18U)
#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos (19U)
#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos (20U)
#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos (21U)
#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos (22U)
#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos (31U)
#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
/******************* Bit definition for CORDIC_WDATA register ***************/
#define CORDIC_WDATA_ARG_Pos (0U)
#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
/******************* Bit definition for CORDIC_RDATA register ***************/
#define CORDIC_RDATA_RES_Pos (0U)
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_Pos (16U)
#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
#define DAC_DOR2_DACC2DORB_Pos (16U)
#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DAC1RDY_Pos (11U)
#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
#define DAC_SR_DORSTAT1_Pos (12U)
#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
#define DAC_SR_DORSTAT2_Pos (28U)
#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos (8U)
#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos (9U)
#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
#define DAC_MCR_HFSEL_Pos (14U)
#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
#define DAC_MCR_DMADOUBLE2_Pos (24U)
#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
#define DAC_MCR_SINFORMAT2_Pos (25U)
#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR2_TSAMPLE2_Pos (0U)
#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/****************** Bit definition for DAC_STR1 register ******************/
#define DAC_STR1_STRSTDATA1_Pos (0U)
#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
#define DAC_STR1_STDIR1_Pos (12U)
#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
#define DAC_STR1_STINCDATA1_Pos (16U)
#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STR2 register ******************/
#define DAC_STR2_STRSTDATA2_Pos (0U)
#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
#define DAC_STR2_STDIR2_Pos (12U)
#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
#define DAC_STR2_STINCDATA2_Pos (16U)
#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STMODR register ****************/
#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
#define DBGMCU_CR_TRACE_MODE_Pos (6U)
#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
#define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos (26U)
#define DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Pos)/*!< 0x04000000 */
#define DBGMCU_APB2FZ_DBG_HRTIM1_STOP DBGMCU_APB2FZ_DBG_HRTIM1_STOP_Msk
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos (24U)
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
#define DMA_ISR_GIF8_Pos (28U)
#define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos) /*!< 0x10000000 */
#define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk /*!< Channel 8 Global interrupt flag */
#define DMA_ISR_TCIF8_Pos (29U)
#define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos) /*!< 0x20000000 */
#define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk /*!< Channel 8 Transfer Complete flag */
#define DMA_ISR_HTIF8_Pos (30U)
#define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos) /*!< 0x40000000 */
#define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk /*!< Channel 8 Half Transfer flag */
#define DMA_ISR_TEIF8_Pos (31U)
#define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos) /*!< 0x80000000 */
#define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk /*!< Channel 8 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos (24U)
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
#define DMA_IFCR_CGIF8_Pos (28U)
#define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos) /*!< 0x10000000 */
#define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk /*!< Channel 8 Global interrupt clear */
#define DMA_IFCR_CTCIF8_Pos (29U)
#define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos) /*!< 0x20000000 */
#define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk /*!< Channel 8 Transfer Complete clear */
#define DMA_IFCR_CHTIF8_Pos (30U)
#define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos) /*!< 0x40000000 */
#define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk /*!< Channel 8 Half Transfer clear */
#define DMA_IFCR_CTEIF8_Pos (31U)
#define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos) /*!< 0x80000000 */
#define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk /*!< Channel 8 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register ****************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
#define DMAMUX_CSR_SOF12_Pos (12U)
#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
#define DMAMUX_CSR_SOF13_Pos (13U)
#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
#define DMAMUX_CSR_SOF14_Pos (14U)
#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
#define DMAMUX_CSR_SOF15_Pos (15U)
#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
/******************** Bits definition for DMAMUX_CFR register ****************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
#define DMAMUX_CFR_CSOF12_Pos (12U)
#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
#define DMAMUX_CFR_CSOF13_Pos (13U)
#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
#define DMAMUX_CFR_CSOF14_Pos (14U)
#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
#define DMAMUX_CFR_CSOF15_Pos (15U)
#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
/******************** Bits definition for DMAMUX_RGCFR register ************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos (31U)
#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos (31U)
#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/****************** Bit definition for EXTI_RTSR1 register ******************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT19_Pos (19U)
#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR1_RT22_Pos (22U)
#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR1_RT29_Pos (29U)
#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR1_RT30_Pos (30U)
#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
#define EXTI_RTSR1_RT31_Pos (31U)
#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */
#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_FT16_Pos (16U)
#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_FT17_Pos (17U)
#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_FT19_Pos (19U)
#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR1_FT22_Pos (22U)
#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR1_FT29_Pos (29U)
#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR1_FT30_Pos (30U)
#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
#define EXTI_FTSR1_FT31_Pos (31U)
#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */
#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos (16U)
#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos (17U)
#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI19_Pos (19U)
#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos (22U)
#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER1_SWI29_Pos (29U)
#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER1_SWI30_Pos (30U)
#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
#define EXTI_SWIER1_SWI31_Pos (31U)
#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */
#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */
/******************* Bit definition for EXTI_PR1 register *******************/
#define EXTI_PR1_PIF0_Pos (0U)
#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PIF1_Pos (1U)
#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PIF2_Pos (2U)
#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PIF3_Pos (3U)
#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PIF4_Pos (4U)
#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PIF5_Pos (5U)
#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PIF6_Pos (6U)
#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PIF7_Pos (7U)
#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PIF8_Pos (8U)
#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PIF9_Pos (9U)
#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PIF10_Pos (10U)
#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PIF11_Pos (11U)
#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PIF12_Pos (12U)
#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PIF13_Pos (13U)
#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PIF14_Pos (14U)
#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PIF15_Pos (15U)
#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PIF16_Pos (16U)
#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PIF17_Pos (17U)
#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR1_PIF19_Pos (19U)
#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PIF20_Pos (20U)
#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PIF21_Pos (21U)
#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR1_PIF22_Pos (22U)
#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR1_PIF29_Pos (29U)
#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR1_PIF30_Pos (30U)
#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
#define EXTI_PR1_PIF31_Pos (31U)
#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */
#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM32_Pos (0U)
#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM42_Pos (10U)
#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x7FFUL << EXTI_IMR2_IM_Pos) /*!< 0x000007FF */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM32_Pos (0U)
#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM42_Pos (10U)
#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x7FFUL << EXTI_EMR2_EM_Pos) /*!< 0x000007FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT32_Pos (0U)
#define EXTI_RTSR2_RT32_Msk (0x1UL << EXTI_RTSR2_RT32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_RT32_Msk /*!< Rising trigger event configuration bit of line 32 */
#define EXTI_RTSR2_RT33_Pos (1U)
#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */
#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */
#define EXTI_RTSR2_RT38_Pos (6U)
#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
#define EXTI_RTSR2_RT39_Pos (7U)
#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
#define EXTI_RTSR2_RT40_Pos (8U)
#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
#define EXTI_RTSR2_RT41_Pos (9U)
#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_FT32_Pos (0U)
#define EXTI_FTSR2_FT32_Msk (0x1UL << EXTI_FTSR2_FT32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_FT32_Msk /*!< Falling trigger event configuration bit of line 32 */
#define EXTI_FTSR2_FT33_Pos (1U)
#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */
#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */
#define EXTI_FTSR2_FT38_Pos (6U)
#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
#define EXTI_FTSR2_FT39_Pos (7U)
#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
#define EXTI_FTSR2_FT40_Pos (8U)
#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
#define EXTI_FTSR2_FT41_Pos (9U)
#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI32_Pos (0U)
#define EXTI_SWIER2_SWI32_Msk (0x1UL << EXTI_SWIER2_SWI32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWI32_Msk /*!< Software Interrupt on line 32 */
#define EXTI_SWIER2_SWI33_Pos (1U)
#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
#define EXTI_SWIER2_SWI38_Pos (6U)
#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
#define EXTI_SWIER2_SWI39_Pos (7U)
#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
#define EXTI_SWIER2_SWI40_Pos (8U)
#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
#define EXTI_SWIER2_SWI41_Pos (9U)
#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PIF32_Pos (0U)
#define EXTI_PR2_PIF32_Msk (0x1UL << EXTI_PR2_PIF32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PIF32 EXTI_PR2_PIF32_Msk /*!< Pending bit for line 32 */
#define EXTI_PR2_PIF33_Pos (1U)
#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */
#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */
#define EXTI_PR2_PIF38_Pos (6U)
#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
#define EXTI_PR2_PIF39_Pos (7U)
#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
#define EXTI_PR2_PIF40_Pos (8U)
#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
#define EXTI_PR2_PIF41_Pos (9U)
#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0F_Pos (1U)
#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (2U)
#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (3U)
#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1F_Pos (4U)
#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (5U)
#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (6U)
#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (7U)
#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (8U)
#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (9U)
#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (10U)
#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFF_Pos (11U)
#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (12U)
#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (13U)
#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (14U)
#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (15U)
#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_ELO_Pos (16U)
#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (17U)
#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (18U)
#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (19U)
#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (20U)
#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (21U)
#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (22U)
#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (23U)
#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0FE_Pos (1U)
#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (2U)
#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (3U)
#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1FE_Pos (4U)
#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (5U)
#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (6U)
#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (7U)
#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (8U)
#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos (9U)
#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (10U)
#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFFE_Pos (11U)
#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (12U)
#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (13U)
#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (14U)
#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (15U)
#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_ELOE_Pos (16U)
#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (17U)
#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (18U)
#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (19U)
#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (20U)
#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (21U)
#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos (22U)
#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (23U)
#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RXFIFO0_Pos (0U)
#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
Rx FIFO 0 is Full
Rx FIFO 0 Has New Message */
#define FDCAN_ILS_RXFIFO1_Pos (1U)
#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
Rx FIFO 1 is Full
Rx FIFO 1 Has New Message */
#define FDCAN_ILS_SMSG_Pos (2U)
#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
Transmission Completed
High Priority Message */
#define FDCAN_ILS_TFERR_Pos (3U)
#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
Tx Event FIFO Full
Tx Event FIFO New Entry
Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_MISC_Pos (4U)
#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
Message RAM Access Failure
Timestamp Wraparound */
#define FDCAN_ILS_BERR_Pos (5U)
#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
Error Logging Overflow */
#define FDCAN_ILS_PERR_Pos (6U)
#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
Protocol Error in Data Phase Line
Protocol Error in Arbitration Phase Line
Watchdog Interrupt Line
Bus_Off Status
Warning Status */
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_RXGFC register ********************/
#define FDCAN_RXGFC_RRFE_Pos (0U)
#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_RXGFC_RRFS_Pos (1U)
#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_RXGFC_ANFE_Pos (2U)
#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_RXGFC_ANFS_Pos (4U)
#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
#define FDCAN_RXGFC_F1OM_Pos (8U)
#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
#define FDCAN_RXGFC_F0OM_Pos (9U)
#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
#define FDCAN_RXGFC_LSS_Pos (16U)
#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
#define FDCAN_RXGFC_LSE_Pos (24U)
#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TFQM_Pos (24U)
#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CFIE_Pos (0U)
#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/*!<FDCAN config registers */
/***************** Bit definition for FDCAN_CKDIV register *********************/
#define FDCAN_CKDIV_PDIV_Pos (0U)
#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS (0x00000000U)
#define FLASH_ACR_LATENCY_1WS (0x00000001U)
#define FLASH_ACR_LATENCY_2WS (0x00000002U)
#define FLASH_ACR_LATENCY_3WS (0x00000003U)
#define FLASH_ACR_LATENCY_4WS (0x00000004U)
#define FLASH_ACR_LATENCY_5WS (0x00000005U)
#define FLASH_ACR_LATENCY_6WS (0x00000006U)
#define FLASH_ACR_LATENCY_7WS (0x00000007U)
#define FLASH_ACR_LATENCY_8WS (0x00000008U)
#define FLASH_ACR_LATENCY_9WS (0x00000009U)
#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_RUN_PD_Pos (13U)
#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
#define FLASH_ACR_SLEEP_PD_Pos (14U)
#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
#define FLASH_ACR_DBG_SWEN_Pos (18U)
#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_OPERR_Pos (1U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_PROGERR_Pos (3U)
#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_SIZERR_Pos (6U)
#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_MISERR_Pos (8U)
#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
#define FLASH_SR_FASTERR_Pos (9U)
#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
#define FLASH_SR_RDERR_Pos (14U)
#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_OPTVERR_Pos (15U)
#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PER_Pos (1U)
#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
#define FLASH_CR_PER FLASH_CR_PER_Msk
#define FLASH_CR_MER1_Pos (2U)
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_BKER_Pos (11U)
#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
#define FLASH_CR_BKER FLASH_CR_BKER_Msk
#define FLASH_CR_MER2_Pos (15U)
#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_OPTSTRT_Pos (17U)
#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
#define FLASH_CR_FSTPG_Pos (18U)
#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_RDERRIE_Pos (26U)
#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
#define FLASH_CR_SEC_PROT1_Pos (28U)
#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
#define FLASH_CR_SEC_PROT2_Pos (29U)
#define FLASH_CR_SEC_PROT2_Msk (0x1UL << FLASH_CR_SEC_PROT2_Pos) /*!< 0x20000000 */
#define FLASH_CR_SEC_PROT2 FLASH_CR_SEC_PROT2_Msk
#define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_ECCR register ***************/
#define FLASH_ECCR_ADDR_ECC_Pos (0U)
#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
#define FLASH_ECCR_BK_ECC_Pos (21U)
#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
#define FLASH_ECCR_SYSF_ECC_Pos (22U)
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
#define FLASH_ECCR_ECCIE_Pos (24U)
#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
#define FLASH_ECCR_ECCC2_Pos (28U)
#define FLASH_ECCR_ECCC2_Msk (0x1UL << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */
#define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
#define FLASH_ECCR_ECCD2_Pos (29U)
#define FLASH_ECCR_ECCD2_Msk (0x1UL << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */
#define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
#define FLASH_ECCR_ECCC_Pos (30U)
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
#define FLASH_ECCR_ECCD_Pos (31U)
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
/******************* Bits definition for FLASH_OPTR register ***************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
#define FLASH_OPTR_BOR_LEV_Pos (8U)
#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
#define FLASH_OPTR_nRST_STOP_Pos (12U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
#define FLASH_OPTR_nRST_STDBY_Pos (13U)
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
#define FLASH_OPTR_WWDG_SW_Pos (19U)
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
#define FLASH_OPTR_BFB2_Pos (20U)
#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
#define FLASH_OPTR_DBANK_Pos (22U)
#define FLASH_OPTR_DBANK_Msk (0x1UL << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */
#define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
#define FLASH_OPTR_nBOOT1_Pos (23U)
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
#define FLASH_OPTR_SRAM_PE_Pos (24U)
#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
#define FLASH_OPTR_nSWBOOT0_Pos (26U)
#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
#define FLASH_OPTR_nBOOT0_Pos (27U)
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
#define FLASH_OPTR_NRST_MODE_Pos (28U)
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
#define FLASH_OPTR_IRHEN_Pos (30U)
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
/****************** Bits definition for FLASH_PCROP1SR register **********/
#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
/****************** Bits definition for FLASH_PCROP1ER register ***********/
#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
#define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_PCROP2SR register **********/
#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
/****************** Bits definition for FLASH_PCROP2ER register ***********/
#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
#define FLASH_PCROP2ER_PCROP2_END_Msk (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
/****************** Bits definition for FLASH_WRP2AR register ***************/
#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
#define FLASH_WRP2AR_WRP2A_STRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)/*!< 0x000000FF */
#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
#define FLASH_WRP2AR_WRP2A_END_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)/*!< 0x00FF0000 */
#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
/****************** Bits definition for FLASH_WRP2BR register ***************/
#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
#define FLASH_WRP2BR_WRP2B_STRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
#define FLASH_WRP2BR_WRP2B_END_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
/****************** Bits definition for FLASH_SEC1R register **************/
#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
#define FLASH_SEC1R_SEC_SIZE1_Msk (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
/****************** Bits definition for FLASH_SEC2R register **************/
#define FLASH_SEC2R_SEC_SIZE2_Pos (0U)
#define FLASH_SEC2R_SEC_SIZE2_Msk (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)/*!< 0x000000FF */
#define FLASH_SEC2R_SEC_SIZE2 FLASH_SEC2R_SEC_SIZE2_Msk
/******************************************************************************/
/* */
/* Filter Mathematical ACcelerator unit (FMAC) */
/* */
/******************************************************************************/
/***************** Bit definition for FMAC_X1BUFCFG register ****************/
#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
/***************** Bit definition for FMAC_X2BUFCFG register ****************/
#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
/***************** Bit definition for FMAC_YBUFCFG register *****************/
#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
/****************** Bit definition for FMAC_PARAM register ******************/
#define FMAC_PARAM_P_Pos (0U)
#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
#define FMAC_PARAM_Q_Pos (8U)
#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
#define FMAC_PARAM_R_Pos (16U)
#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
#define FMAC_PARAM_FUNC_Pos (24U)
#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
#define FMAC_PARAM_START_Pos (31U)
#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
/******************** Bit definition for FMAC_CR register *******************/
#define FMAC_CR_RIEN_Pos (0U)
#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
#define FMAC_CR_WIEN_Pos (1U)
#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
#define FMAC_CR_OVFLIEN_Pos (2U)
#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
#define FMAC_CR_UNFLIEN_Pos (3U)
#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
#define FMAC_CR_SATIEN_Pos (4U)
#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
#define FMAC_CR_DMAREN_Pos (8U)
#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
#define FMAC_CR_DMAWEN_Pos (9U)
#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
#define FMAC_CR_CLIPEN_Pos (15U)
#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
#define FMAC_CR_RESET_Pos (16U)
#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
/******************* Bit definition for FMAC_SR register ********************/
#define FMAC_SR_YEMPTY_Pos (0U)
#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
#define FMAC_SR_X1FULL_Pos (1U)
#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
#define FMAC_SR_OVFL_Pos (8U)
#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
#define FMAC_SR_UNFL_Pos (9U)
#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
#define FMAC_SR_SAT_Pos (10U)
#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
/****************** Bit definition for FMAC_WDATA register ******************/
#define FMAC_WDATA_WDATA_Pos (0U)
#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
/****************** Bit definition for FMACX_RDATA register *****************/
#define FMAC_RDATA_RDATA_Pos (0U)
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
/******************************************************************************/
/* */
/* Flexible Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCRx_MUXEN_Pos (1U)
#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCRx_MTYP_Pos (2U)
#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCRx_MWID_Pos (4U)
#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCRx_FACCEN_Pos (6U)
#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCRx_BURSTEN_Pos (8U)
#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCRx_WAITPOL_Pos (9U)
#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCRx_WAITCFG_Pos (11U)
#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCRx_WREN_Pos (12U)
#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
#define FMC_BCRx_WAITEN_Pos (13U)
#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCRx_EXTMOD_Pos (14U)
#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCRx_ASYNCWAIT_Pos (15U)
#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCRx_CPSIZE_Pos (16U)
#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCRx_CBURSTRW_Pos (19U)
#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCRx_NBLSET_Pos (22U)
#define FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */
#define FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00500000 */
#define FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
#define FMC_BTRx_ADDSET_Pos (0U)
#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTRx_ADDHLD_Pos (4U)
#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTRx_DATAST_Pos (8U)
#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTRx_BUSTURN_Pos (16U)
#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTRx_CLKDIV_Pos (20U)
#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTRx_DATLAT_Pos (24U)
#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTRx_ACCMOD_Pos (28U)
#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTRx_DATAHLD_Pos (30U)
#define FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
#define FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
#define FMC_BWTRx_ADDSET_Pos (0U)
#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTRx_ADDHLD_Pos (4U)
#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTRx_DATAST_Pos (8U)
#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTRx_BUSTURN_Pos (16U)
#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTRx_ACCMOD_Pos (28U)
#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTRx_DATAHLD_Pos (30U)
#define FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
#define FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PCSCNTR register ******************/
#define FMC_PCSCNTR_CSCOUNT_Pos (0U)
#define FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos) /*!< 0x0000FFFF */
#define FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk /*!<CSCOUNT[15:0] bits (Chip select counter) */
#define FMC_PCSCNTR_CNTB1EN_Pos (16U)
#define FMC_PCSCNTR_CNTB1EN_Msk (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos) /*!< 0x00010000 */
#define FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk /*!<Counter PSRAM/NOR Bank1_1 enable */
#define FMC_PCSCNTR_CNTB2EN_Pos (17U)
#define FMC_PCSCNTR_CNTB2EN_Msk (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos) /*!< 0x00020000 */
#define FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk /*!<Counter PSRAM/NOR Bank1_2 enable */
#define FMC_PCSCNTR_CNTB3EN_Pos (18U)
#define FMC_PCSCNTR_CNTB3EN_Msk (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos) /*!< 0x00040000 */
#define FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk /*!<Counter PSRAM/NOR Bank1_3 enable */
#define FMC_PCSCNTR_CNTB4EN_Pos (19U)
#define FMC_PCSCNTR_CNTB4EN_Msk (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos) /*!< 0x00080000 */
#define FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk /*!<Counter PSRAM/NOR Bank1_4 enable */
/****************** Bit definition for FMC_PCR register ********************/
#define FMC_PCR_PWAITEN_Pos (1U)
#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
#define FMC_PCR_PBKEN_Pos (2U)
#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
#define FMC_PCR_PTYP_Pos (3U)
#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
#define FMC_PCR_PWID_Pos (4U)
#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
#define FMC_PCR_ECCEN_Pos (6U)
#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
#define FMC_PCR_TCLR_Pos (9U)
#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
#define FMC_PCR_TAR_Pos (13U)
#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
#define FMC_PCR_ECCPS_Pos (17U)
#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
/******************* Bit definition for FMC_SR register ********************/
#define FMC_SR_IRS_Pos (0U)
#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
#define FMC_SR_ILS_Pos (1U)
#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
#define FMC_SR_IFS_Pos (2U)
#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
#define FMC_SR_IREN_Pos (3U)
#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
#define FMC_SR_ILEN_Pos (4U)
#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
#define FMC_SR_IFEN_Pos (5U)
#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
#define FMC_SR_FEMPT_Pos (6U)
#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
/****************** Bit definition for FMC_PMEM register ******************/
#define FMC_PMEM_MEMSET_Pos (0U)
#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
#define FMC_PMEM_MEMWAIT_Pos (8U)
#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
#define FMC_PMEM_MEMHOLD_Pos (16U)
#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
#define FMC_PMEM_MEMHIZ_Pos (24U)
#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PATT register *******************/
#define FMC_PATT_ATTSET_Pos (0U)
#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
#define FMC_PATT_ATTWAIT_Pos (8U)
#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
#define FMC_PATT_ATTHOLD_Pos (16U)
#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
#define FMC_PATT_ATTHIZ_Pos (24U)
#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_ECCR register *******************/
#define FMC_ECCR_ECC_Pos (0U)
#define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/* Legacy defines */
#define GPIO_BRR_BR_0 GPIO_BRR_BR0
#define GPIO_BRR_BR_1 GPIO_BRR_BR1
#define GPIO_BRR_BR_2 GPIO_BRR_BR2
#define GPIO_BRR_BR_3 GPIO_BRR_BR3
#define GPIO_BRR_BR_4 GPIO_BRR_BR4
#define GPIO_BRR_BR_5 GPIO_BRR_BR5
#define GPIO_BRR_BR_6 GPIO_BRR_BR6
#define GPIO_BRR_BR_7 GPIO_BRR_BR7
#define GPIO_BRR_BR_8 GPIO_BRR_BR8
#define GPIO_BRR_BR_9 GPIO_BRR_BR9
#define GPIO_BRR_BR_10 GPIO_BRR_BR10
#define GPIO_BRR_BR_11 GPIO_BRR_BR11
#define GPIO_BRR_BR_12 GPIO_BRR_BR12
#define GPIO_BRR_BR_13 GPIO_BRR_BR13
#define GPIO_BRR_BR_14 GPIO_BRR_BR14
#define GPIO_BRR_BR_15 GPIO_BRR_BR15
/******************************************************************************/
/* */
/* High Resolution Timer (HRTIM) */
/* */
/******************************************************************************/
/******************** Master Timer control register ***************************/
#define HRTIM_MCR_CK_PSC_Pos (0U)
#define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
#define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
#define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
#define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
#define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
#define HRTIM_MCR_CONT_Pos (3U)
#define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
#define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
#define HRTIM_MCR_RETRIG_Pos (4U)
#define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
#define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
#define HRTIM_MCR_HALF_Pos (5U)
#define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
#define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
#define HRTIM_MCR_INTLVD_Pos (6U)
#define HRTIM_MCR_INTLVD_Msk (0x3UL << HRTIM_MCR_INTLVD_Pos) /*!< 0x000000C0 */
#define HRTIM_MCR_INTLVD HRTIM_MCR_INTLVD_Msk /*!< Interleaved mode */
#define HRTIM_MCR_INTLVD_0 (0x1UL << HRTIM_MCR_INTLVD_Pos) /*!< 0x00000040 */
#define HRTIM_MCR_INTLVD_1 (0x2UL << HRTIM_MCR_INTLVD_Pos) /*!< 0x00000080 */
#define HRTIM_MCR_SYNC_IN_Pos (8U)
#define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
#define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
#define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
#define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
#define HRTIM_MCR_SYNCRSTM_Pos (10U)
#define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
#define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
#define HRTIM_MCR_SYNCSTRTM_Pos (11U)
#define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
#define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
#define HRTIM_MCR_SYNC_OUT_Pos (12U)
#define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
#define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
#define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
#define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
#define HRTIM_MCR_SYNC_SRC_Pos (14U)
#define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
#define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
#define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
#define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
#define HRTIM_MCR_MCEN_Pos (16U)
#define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
#define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
#define HRTIM_MCR_TACEN_Pos (17U)
#define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
#define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
#define HRTIM_MCR_TBCEN_Pos (18U)
#define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
#define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
#define HRTIM_MCR_TCCEN_Pos (19U)
#define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
#define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
#define HRTIM_MCR_TDCEN_Pos (20U)
#define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
#define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
#define HRTIM_MCR_TECEN_Pos (21U)
#define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
#define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
#define HRTIM_MCR_TFCEN_Pos (22U)
#define HRTIM_MCR_TFCEN_Msk (0x1UL << HRTIM_MCR_TFCEN_Pos) /*!< 0x00400000 */
#define HRTIM_MCR_TFCEN HRTIM_MCR_TFCEN_Msk /*!< Timer F counter enable */
#define HRTIM_MCR_DACSYNC_Pos (25U)
#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
#define HRTIM_MCR_PREEN_Pos (27U)
#define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
#define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
#define HRTIM_MCR_MREPU_Pos (29U)
#define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
#define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
#define HRTIM_MCR_BRSTDMA_Pos (30U)
#define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
#define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
#define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
#define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
/******************** Master Timer Interrupt status register ******************/
#define HRTIM_MISR_MCMP1_Pos (0U)
#define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
#define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
#define HRTIM_MISR_MCMP2_Pos (1U)
#define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
#define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
#define HRTIM_MISR_MCMP3_Pos (2U)
#define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
#define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
#define HRTIM_MISR_MCMP4_Pos (3U)
#define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
#define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
#define HRTIM_MISR_MREP_Pos (4U)
#define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
#define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
#define HRTIM_MISR_SYNC_Pos (5U)
#define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
#define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
#define HRTIM_MISR_MUPD_Pos (6U)
#define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
#define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
/******************** Master Timer Interrupt clear register *******************/
#define HRTIM_MICR_MCMP1_Pos (0U)
#define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
#define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
#define HRTIM_MICR_MCMP2_Pos (1U)
#define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
#define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
#define HRTIM_MICR_MCMP3_Pos (2U)
#define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
#define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
#define HRTIM_MICR_MCMP4_Pos (3U)
#define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
#define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
#define HRTIM_MICR_MREP_Pos (4U)
#define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
#define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
#define HRTIM_MICR_SYNC_Pos (5U)
#define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
#define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
#define HRTIM_MICR_MUPD_Pos (6U)
#define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
#define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
/******************** Master Timer DMA/Interrupt enable register **************/
#define HRTIM_MDIER_MCMP1IE_Pos (0U)
#define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
#define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
#define HRTIM_MDIER_MCMP2IE_Pos (1U)
#define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
#define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
#define HRTIM_MDIER_MCMP3IE_Pos (2U)
#define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
#define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
#define HRTIM_MDIER_MCMP4IE_Pos (3U)
#define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
#define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
#define HRTIM_MDIER_MREPIE_Pos (4U)
#define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
#define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
#define HRTIM_MDIER_SYNCIE_Pos (5U)
#define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
#define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
#define HRTIM_MDIER_MUPDIE_Pos (6U)
#define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
#define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
#define HRTIM_MDIER_MCMP1DE_Pos (16U)
#define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
#define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
#define HRTIM_MDIER_MCMP2DE_Pos (17U)
#define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
#define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
#define HRTIM_MDIER_MCMP3DE_Pos (18U)
#define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
#define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
#define HRTIM_MDIER_MCMP4DE_Pos (19U)
#define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
#define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
#define HRTIM_MDIER_MREPDE_Pos (20U)
#define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
#define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
#define HRTIM_MDIER_SYNCDE_Pos (21U)
#define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
#define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
#define HRTIM_MDIER_MUPDDE_Pos (22U)
#define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
#define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
/******************* Bit definition for HRTIM_MCNTR register ****************/
#define HRTIM_MCNTR_MCNTR_Pos (0U)
#define HRTIM_MCNTR_MCNTR_Msk (0x0000FFFFUL << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */
#define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
/******************* Bit definition for HRTIM_MPER register *****************/
#define HRTIM_MPER_MPER_Pos (0U)
#define HRTIM_MPER_MPER_Msk (0x0000FFFFUL << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */
#define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
/******************* Bit definition for HRTIM_MREP register *****************/
#define HRTIM_MREP_MREP_Pos (0U)
#define HRTIM_MREP_MREP_Msk (0x000000FFUL << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */
#define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
/******************* Bit definition for HRTIM_MCMP1R register *****************/
#define HRTIM_MCMP1R_MCMP1R_Pos (0U)
#define HRTIM_MCMP1R_MCMP1R_Msk (0x0000FFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)/*!< 0x0000FFFF */
#define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP2R register *****************/
#define HRTIM_MCMP2R_MCMP2R_Pos (0U)
#define HRTIM_MCMP2R_MCMP2R_Msk (0x0000FFFFUL << HRTIM_MCMP2R_MCMP2R_Pos)/*!< 0x0000FFFF */
#define HRTIM_MCMP2R_MCMP2R HRTIM_MCMP2R_MCMP2R_Msk /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP3R register *****************/
#define HRTIM_MCMP3R_MCMP3R_Pos (0U)
#define HRTIM_MCMP3R_MCMP3R_Msk (0x0000FFFFUL << HRTIM_MCMP3R_MCMP3R_Pos)/*!< 0x0000FFFF */
#define HRTIM_MCMP3R_MCMP3R HRTIM_MCMP3R_MCMP3R_Msk /*!<Compare Value */
/******************* Bit definition for HRTIM_MCMP4R register *****************/
#define HRTIM_MCMP4R_MCMP4R_Pos (0U)
#define HRTIM_MCMP4R_MCMP4R_Msk (0x0000FFFFUL << HRTIM_MCMP4R_MCMP4R_Pos)/*!< 0x0000FFFF */
#define HRTIM_MCMP4R_MCMP4R HRTIM_MCMP4R_MCMP4R_Msk /*!<Compare Value */
/* Legacy defines */
#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP2R_MCMP2R
#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP3R_MCMP3R
#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP4R_MCMP4R
/******************** Slave control register **********************************/
#define HRTIM_TIMCR_CK_PSC_Pos (0U)
#define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
#define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
#define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
#define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
#define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
#define HRTIM_TIMCR_CONT_Pos (3U)
#define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
#define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
#define HRTIM_TIMCR_RETRIG_Pos (4U)
#define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
#define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
#define HRTIM_TIMCR_HALF_Pos (5U)
#define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
#define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
#define HRTIM_TIMCR_PSHPLL_Pos (6U)
#define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
#define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
#define HRTIM_TIMCR_INTLVD_Pos (7U)
#define HRTIM_TIMCR_INTLVD_Msk (0x3UL << HRTIM_TIMCR_INTLVD_Pos) /*!< 0x00000180 */
#define HRTIM_TIMCR_INTLVD HRTIM_TIMCR_INTLVD_Msk /*!< Interleaved mode */
#define HRTIM_TIMCR_INTLVD_0 (0x1UL << HRTIM_TIMCR_INTLVD_Pos) /*!< 0x00000080 */
#define HRTIM_TIMCR_INTLVD_1 (0x2UL << HRTIM_TIMCR_INTLVD_Pos) /*!< 0x00000100 */
#define HRTIM_TIMCR_RSYNCU_Pos (9U)
#define HRTIM_TIMCR_RSYNCU_Msk (0x1UL << HRTIM_TIMCR_RSYNCU_Pos) /*!< 0x00000200 */
#define HRTIM_TIMCR_RSYNCU HRTIM_TIMCR_RSYNCU_Msk /*!< Resynchronization update */
#define HRTIM_TIMCR_SYNCRST_Pos (10U)
#define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
#define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
#define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
#define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
#define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
#define HRTIM_TIMCR_DELCMP2_Pos (12U)
#define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
#define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
#define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
#define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
#define HRTIM_TIMCR_DELCMP4_Pos (14U)
#define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
#define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
#define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
#define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
#define HRTIM_TIMCR_TFU_Pos (16U)
#define HRTIM_TIMCR_TFU_Msk (0x1UL << HRTIM_TIMCR_TFU_Pos) /*!< 0x00010000 */
#define HRTIM_TIMCR_TFU HRTIM_TIMCR_TFU_Msk /*!< Slave Timer F update reserved for TIM F */
#define HRTIM_TIMCR_TREPU_Pos (17U)
#define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
#define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
#define HRTIM_TIMCR_TRSTU_Pos (18U)
#define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
#define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
#define HRTIM_TIMCR_TAU_Pos (19U)
#define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
#define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
#define HRTIM_TIMCR_TBU_Pos (20U)
#define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
#define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
#define HRTIM_TIMCR_TCU_Pos (21U)
#define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
#define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
#define HRTIM_TIMCR_TDU_Pos (22U)
#define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
#define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
#define HRTIM_TIMCR_TEU_Pos (23U)
#define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
#define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
#define HRTIM_TIMCR_MSTU_Pos (24U)
#define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) /*!< 0x02000000 */
#define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
#define HRTIM_TIMCR_DACSYNC_Pos (25U)
#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
#define HRTIM_TIMCR_PREEN_Pos (27U)
#define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
#define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
#define HRTIM_TIMCR_UPDGAT_Pos (28U)
#define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
#define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
#define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
#define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
#define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
#define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
/******************** Slave Interrupt status register **************************/
#define HRTIM_TIMISR_CMP1_Pos (0U)
#define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
#define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
#define HRTIM_TIMISR_CMP2_Pos (1U)
#define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
#define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
#define HRTIM_TIMISR_CMP3_Pos (2U)
#define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
#define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
#define HRTIM_TIMISR_CMP4_Pos (3U)
#define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
#define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
#define HRTIM_TIMISR_REP_Pos (4U)
#define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
#define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
#define HRTIM_TIMISR_UPD_Pos (6U)
#define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
#define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
#define HRTIM_TIMISR_CPT1_Pos (7U)
#define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
#define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
#define HRTIM_TIMISR_CPT2_Pos (8U)
#define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
#define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
#define HRTIM_TIMISR_SET1_Pos (9U)
#define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
#define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
#define HRTIM_TIMISR_RST1_Pos (10U)
#define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
#define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
#define HRTIM_TIMISR_SET2_Pos (11U)
#define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
#define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
#define HRTIM_TIMISR_RST2_Pos (12U)
#define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
#define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
#define HRTIM_TIMISR_RST_Pos (13U)
#define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
#define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
#define HRTIM_TIMISR_DLYPRT_Pos (14U)
#define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
#define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
#define HRTIM_TIMISR_CPPSTAT_Pos (16U)
#define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
#define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
#define HRTIM_TIMISR_IPPSTAT_Pos (17U)
#define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
#define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
#define HRTIM_TIMISR_O1STAT_Pos (18U)
#define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
#define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
#define HRTIM_TIMISR_O2STAT_Pos (19U)
#define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
#define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
#define HRTIM_TIMISR_O1CPY_Pos (20U)
#define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
#define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
#define HRTIM_TIMISR_O2CPY_Pos (21U)
#define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
#define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
/******************** Slave Interrupt clear register **************************/
#define HRTIM_TIMICR_CMP1C_Pos (0U)
#define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
#define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
#define HRTIM_TIMICR_CMP2C_Pos (1U)
#define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
#define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
#define HRTIM_TIMICR_CMP3C_Pos (2U)
#define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
#define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
#define HRTIM_TIMICR_CMP4C_Pos (3U)
#define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
#define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
#define HRTIM_TIMICR_REPC_Pos (4U)
#define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
#define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
#define HRTIM_TIMICR_UPDC_Pos (6U)
#define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
#define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
#define HRTIM_TIMICR_CPT1C_Pos (7U)
#define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
#define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
#define HRTIM_TIMICR_CPT2C_Pos (8U)
#define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
#define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
#define HRTIM_TIMICR_SET1C_Pos (9U)
#define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
#define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
#define HRTIM_TIMICR_RST1C_Pos (10U)
#define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
#define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
#define HRTIM_TIMICR_SET2C_Pos (11U)
#define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
#define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
#define HRTIM_TIMICR_RST2C_Pos (12U)
#define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
#define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
#define HRTIM_TIMICR_RSTC_Pos (13U)
#define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
#define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
#define HRTIM_TIMICR_DLYPRTC_Pos (14U)
#define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */
#define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output delay protection clear flag */
/******************** Slave DMA/Interrupt enable register *********************/
#define HRTIM_TIMDIER_CMP1IE_Pos (0U)
#define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
#define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
#define HRTIM_TIMDIER_CMP2IE_Pos (1U)
#define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
#define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
#define HRTIM_TIMDIER_CMP3IE_Pos (2U)
#define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
#define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
#define HRTIM_TIMDIER_CMP4IE_Pos (3U)
#define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
#define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
#define HRTIM_TIMDIER_REPIE_Pos (4U)
#define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
#define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
#define HRTIM_TIMDIER_UPDIE_Pos (6U)
#define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
#define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
#define HRTIM_TIMDIER_CPT1IE_Pos (7U)
#define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
#define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
#define HRTIM_TIMDIER_CPT2IE_Pos (8U)
#define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
#define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
#define HRTIM_TIMDIER_SET1IE_Pos (9U)
#define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
#define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
#define HRTIM_TIMDIER_RST1IE_Pos (10U)
#define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
#define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
#define HRTIM_TIMDIER_SET2IE_Pos (11U)
#define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
#define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
#define HRTIM_TIMDIER_RST2IE_Pos (12U)
#define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
#define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
#define HRTIM_TIMDIER_RSTIE_Pos (13U)
#define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
#define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
#define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
#define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
#define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
#define HRTIM_TIMDIER_CMP1DE_Pos (16U)
#define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
#define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
#define HRTIM_TIMDIER_CMP2DE_Pos (17U)
#define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
#define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
#define HRTIM_TIMDIER_CMP3DE_Pos (18U)
#define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
#define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
#define HRTIM_TIMDIER_CMP4DE_Pos (19U)
#define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
#define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
#define HRTIM_TIMDIER_REPDE_Pos (20U)
#define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
#define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
#define HRTIM_TIMDIER_UPDDE_Pos (22U)
#define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
#define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
#define HRTIM_TIMDIER_CPT1DE_Pos (23U)
#define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
#define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
#define HRTIM_TIMDIER_CPT2DE_Pos (24U)
#define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
#define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
#define HRTIM_TIMDIER_SET1DE_Pos (25U)
#define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
#define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
#define HRTIM_TIMDIER_RST1DE_Pos (26U)
#define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
#define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
#define HRTIM_TIMDIER_SET2DE_Pos (27U)
#define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
#define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
#define HRTIM_TIMDIER_RST2DE_Pos (28U)
#define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
#define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
#define HRTIM_TIMDIER_RSTDE_Pos (29U)
#define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
#define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
#define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
#define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
#define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
/****************** Bit definition for HRTIM_CNTR register ****************/
#define HRTIM_CNTR_CNTR_Pos (0U)
#define HRTIM_CNTR_CNTR_Msk (0x0000FFFFUL << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */
#define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
/******************* Bit definition for HRTIM_PER register *****************/
#define HRTIM_PER_PER_Pos (0U)
#define HRTIM_PER_PER_Msk (0x0000FFFFUL << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */
#define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
/******************* Bit definition for HRTIM_REP register *****************/
#define HRTIM_REP_REP_Pos (0U)
#define HRTIM_REP_REP_Msk (0x000000FFUL << HRTIM_REP_REP_Pos) /*!< 0x000000FF */
#define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
/******************* Bit definition for HRTIM_CMP1R register *****************/
#define HRTIM_CMP1R_CMP1R_Pos (0U)
#define HRTIM_CMP1R_CMP1R_Msk (0x0000FFFFUL << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CMP1CR register *****************/
#define HRTIM_CMP1CR_CMP1CR_Pos (0U)
#define HRTIM_CMP1CR_CMP1CR_Msk (0x0000FFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)/*!< 0x0000FFFF */
#define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CMP2R register *****************/
#define HRTIM_CMP2R_CMP2R_Pos (0U)
#define HRTIM_CMP2R_CMP2R_Msk (0x0000FFFFUL << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CMP3R register *****************/
#define HRTIM_CMP3R_CMP3R_Pos (0U)
#define HRTIM_CMP3R_CMP3R_Msk (0x0000FFFFUL << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CMP4R register *****************/
#define HRTIM_CMP4R_CMP4R_Pos (0U)
#define HRTIM_CMP4R_CMP4R_Msk (0x0000FFFFUL << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
/******************* Bit definition for HRTIM_CPT1R register ****************/
#define HRTIM_CPT1R_CPT1R_Pos (0U)
#define HRTIM_CPT1R_CPT1R_Msk (0x0000FFFFUL << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture 1 Value */
#define HRTIM_CPT1R_DIR_Pos (16U)
#define HRTIM_CPT1R_DIR_Msk (0x1UL << HRTIM_CPT1R_DIR_Pos) /*!< 0x00010000 */
#define HRTIM_CPT1R_DIR HRTIM_CPT1R_DIR_Msk /*!< Capture 1 direction> */
/******************* Bit definition for HRTIM_CPT2R register ****************/
#define HRTIM_CPT2R_CPT2R_Pos (0U)
#define HRTIM_CPT2R_CPT2R_Msk (0x0000FFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */
#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture 2 Value */
#define HRTIM_CPT2R_DIR_Pos (16U)
#define HRTIM_CPT2R_DIR_Msk (0x1UL << HRTIM_CPT2R_DIR_Pos) /*!< 0x00010000 */
#define HRTIM_CPT2R_DIR HRTIM_CPT2R_DIR_Msk /*!< Capture 2 direction */
/******************** Bit definition for Slave Deadtime register **************/
#define HRTIM_DTR_DTR_Pos (0U)
#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
#define HRTIM_DTR_SDTR_Pos (9U)
#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
#define HRTIM_DTR_DTPRSC_Pos (10U)
#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
#define HRTIM_DTR_DTRSLK_Pos (14U)
#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
#define HRTIM_DTR_DTRLK_Pos (15U)
#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
#define HRTIM_DTR_DTF_Pos (16U)
#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
#define HRTIM_DTR_SDTF_Pos (25U)
#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
#define HRTIM_DTR_DTFSLK_Pos (30U)
#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
#define HRTIM_DTR_DTFLK_Pos (31U)
#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
/**** Bit definition for Slave Output 1 set register **************************/
#define HRTIM_SET1R_SST_Pos (0U)
#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
#define HRTIM_SET1R_RESYNC_Pos (1U)
#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
#define HRTIM_SET1R_PER_Pos (2U)
#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
#define HRTIM_SET1R_CMP1_Pos (3U)
#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_SET1R_CMP2_Pos (4U)
#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_SET1R_CMP3_Pos (5U)
#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
#define HRTIM_SET1R_CMP4_Pos (6U)
#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_SET1R_MSTPER_Pos (7U)
#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
#define HRTIM_SET1R_MSTCMP1_Pos (8U)
#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_SET1R_MSTCMP2_Pos (9U)
#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_SET1R_MSTCMP3_Pos (10U)
#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_SET1R_MSTCMP4_Pos (11U)
#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_SET1R_TIMEVNT1_Pos (12U)
#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
#define HRTIM_SET1R_TIMEVNT2_Pos (13U)
#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
#define HRTIM_SET1R_TIMEVNT3_Pos (14U)
#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
#define HRTIM_SET1R_TIMEVNT4_Pos (15U)
#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
#define HRTIM_SET1R_TIMEVNT5_Pos (16U)
#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
#define HRTIM_SET1R_TIMEVNT6_Pos (17U)
#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
#define HRTIM_SET1R_TIMEVNT7_Pos (18U)
#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
#define HRTIM_SET1R_TIMEVNT8_Pos (19U)
#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
#define HRTIM_SET1R_TIMEVNT9_Pos (20U)
#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
#define HRTIM_SET1R_EXTVNT1_Pos (21U)
#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
#define HRTIM_SET1R_EXTVNT2_Pos (22U)
#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
#define HRTIM_SET1R_EXTVNT3_Pos (23U)
#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
#define HRTIM_SET1R_EXTVNT4_Pos (24U)
#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
#define HRTIM_SET1R_EXTVNT5_Pos (25U)
#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
#define HRTIM_SET1R_EXTVNT6_Pos (26U)
#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
#define HRTIM_SET1R_EXTVNT7_Pos (27U)
#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
#define HRTIM_SET1R_EXTVNT8_Pos (28U)
#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
#define HRTIM_SET1R_EXTVNT9_Pos (29U)
#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
#define HRTIM_SET1R_EXTVNT10_Pos (30U)
#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
#define HRTIM_SET1R_UPDATE_Pos (31U)
#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
/**** Bit definition for Slave Output 1 reset register ************************/
#define HRTIM_RST1R_SRT_Pos (0U)
#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
#define HRTIM_RST1R_RESYNC_Pos (1U)
#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
#define HRTIM_RST1R_PER_Pos (2U)
#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
#define HRTIM_RST1R_CMP1_Pos (3U)
#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RST1R_CMP2_Pos (4U)
#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RST1R_CMP3_Pos (5U)
#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
#define HRTIM_RST1R_CMP4_Pos (6U)
#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RST1R_MSTPER_Pos (7U)
#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
#define HRTIM_RST1R_MSTCMP1_Pos (8U)
#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_RST1R_MSTCMP2_Pos (9U)
#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_RST1R_MSTCMP3_Pos (10U)
#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_RST1R_MSTCMP4_Pos (11U)
#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_RST1R_TIMEVNT1_Pos (12U)
#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
#define HRTIM_RST1R_TIMEVNT2_Pos (13U)
#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
#define HRTIM_RST1R_TIMEVNT3_Pos (14U)
#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
#define HRTIM_RST1R_TIMEVNT4_Pos (15U)
#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
#define HRTIM_RST1R_TIMEVNT5_Pos (16U)
#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
#define HRTIM_RST1R_TIMEVNT6_Pos (17U)
#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
#define HRTIM_RST1R_TIMEVNT7_Pos (18U)
#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
#define HRTIM_RST1R_TIMEVNT8_Pos (19U)
#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
#define HRTIM_RST1R_TIMEVNT9_Pos (20U)
#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
#define HRTIM_RST1R_EXTVNT1_Pos (21U)
#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
#define HRTIM_RST1R_EXTVNT2_Pos (22U)
#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
#define HRTIM_RST1R_EXTVNT3_Pos (23U)
#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
#define HRTIM_RST1R_EXTVNT4_Pos (24U)
#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
#define HRTIM_RST1R_EXTVNT5_Pos (25U)
#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
#define HRTIM_RST1R_EXTVNT6_Pos (26U)
#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
#define HRTIM_RST1R_EXTVNT7_Pos (27U)
#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
#define HRTIM_RST1R_EXTVNT8_Pos (28U)
#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
#define HRTIM_RST1R_EXTVNT9_Pos (29U)
#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
#define HRTIM_RST1R_EXTVNT10_Pos (30U)
#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
#define HRTIM_RST1R_UPDATE_Pos (31U)
#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
/**** Bit definition for Slave Output 2 set register **************************/
#define HRTIM_SET2R_SST_Pos (0U)
#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
#define HRTIM_SET2R_RESYNC_Pos (1U)
#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
#define HRTIM_SET2R_PER_Pos (2U)
#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
#define HRTIM_SET2R_CMP1_Pos (3U)
#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_SET2R_CMP2_Pos (4U)
#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_SET2R_CMP3_Pos (5U)
#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
#define HRTIM_SET2R_CMP4_Pos (6U)
#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_SET2R_MSTPER_Pos (7U)
#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
#define HRTIM_SET2R_MSTCMP1_Pos (8U)
#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_SET2R_MSTCMP2_Pos (9U)
#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_SET2R_MSTCMP3_Pos (10U)
#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_SET2R_MSTCMP4_Pos (11U)
#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_SET2R_TIMEVNT1_Pos (12U)
#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
#define HRTIM_SET2R_TIMEVNT2_Pos (13U)
#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
#define HRTIM_SET2R_TIMEVNT3_Pos (14U)
#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
#define HRTIM_SET2R_TIMEVNT4_Pos (15U)
#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
#define HRTIM_SET2R_TIMEVNT5_Pos (16U)
#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
#define HRTIM_SET2R_TIMEVNT6_Pos (17U)
#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
#define HRTIM_SET2R_TIMEVNT7_Pos (18U)
#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
#define HRTIM_SET2R_TIMEVNT8_Pos (19U)
#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
#define HRTIM_SET2R_TIMEVNT9_Pos (20U)
#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
#define HRTIM_SET2R_EXTVNT1_Pos (21U)
#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
#define HRTIM_SET2R_EXTVNT2_Pos (22U)
#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
#define HRTIM_SET2R_EXTVNT3_Pos (23U)
#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
#define HRTIM_SET2R_EXTVNT4_Pos (24U)
#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
#define HRTIM_SET2R_EXTVNT5_Pos (25U)
#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
#define HRTIM_SET2R_EXTVNT6_Pos (26U)
#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
#define HRTIM_SET2R_EXTVNT7_Pos (27U)
#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
#define HRTIM_SET2R_EXTVNT8_Pos (28U)
#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
#define HRTIM_SET2R_EXTVNT9_Pos (29U)
#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
#define HRTIM_SET2R_EXTVNT10_Pos (30U)
#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
#define HRTIM_SET2R_UPDATE_Pos (31U)
#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
/**** Bit definition for Slave Output 2 reset register ************************/
#define HRTIM_RST2R_SRT_Pos (0U)
#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
#define HRTIM_RST2R_RESYNC_Pos (1U)
#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
#define HRTIM_RST2R_PER_Pos (2U)
#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
#define HRTIM_RST2R_CMP1_Pos (3U)
#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RST2R_CMP2_Pos (4U)
#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RST2R_CMP3_Pos (5U)
#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
#define HRTIM_RST2R_CMP4_Pos (6U)
#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RST2R_MSTPER_Pos (7U)
#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
#define HRTIM_RST2R_MSTCMP1_Pos (8U)
#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_RST2R_MSTCMP2_Pos (9U)
#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_RST2R_MSTCMP3_Pos (10U)
#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_RST2R_MSTCMP4_Pos (11U)
#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_RST2R_TIMEVNT1_Pos (12U)
#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
#define HRTIM_RST2R_TIMEVNT2_Pos (13U)
#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
#define HRTIM_RST2R_TIMEVNT3_Pos (14U)
#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
#define HRTIM_RST2R_TIMEVNT4_Pos (15U)
#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
#define HRTIM_RST2R_TIMEVNT5_Pos (16U)
#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
#define HRTIM_RST2R_TIMEVNT6_Pos (17U)
#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
#define HRTIM_RST2R_TIMEVNT7_Pos (18U)
#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
#define HRTIM_RST2R_TIMEVNT8_Pos (19U)
#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
#define HRTIM_RST2R_TIMEVNT9_Pos (20U)
#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
#define HRTIM_RST2R_EXTVNT1_Pos (21U)
#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
#define HRTIM_RST2R_EXTVNT2_Pos (22U)
#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
#define HRTIM_RST2R_EXTVNT3_Pos (23U)
#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
#define HRTIM_RST2R_EXTVNT4_Pos (24U)
#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
#define HRTIM_RST2R_EXTVNT5_Pos (25U)
#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
#define HRTIM_RST2R_EXTVNT6_Pos (26U)
#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
#define HRTIM_RST2R_EXTVNT7_Pos (27U)
#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
#define HRTIM_RST2R_EXTVNT8_Pos (28U)
#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
#define HRTIM_RST2R_EXTVNT9_Pos (29U)
#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
#define HRTIM_RST2R_EXTVNT10_Pos (30U)
#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
#define HRTIM_RST2R_UPDATE_Pos (31U)
#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
/**** Bit definition for Slave external event filtering register 1 ***********/
#define HRTIM_EEFR1_EE1LTCH_Pos (0U)
#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
#define HRTIM_EEFR1_EE1FLTR_Pos (1U)
#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
#define HRTIM_EEFR1_EE2LTCH_Pos (6U)
#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
#define HRTIM_EEFR1_EE2FLTR_Pos (7U)
#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
#define HRTIM_EEFR1_EE3LTCH_Pos (12U)
#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
#define HRTIM_EEFR1_EE3FLTR_Pos (13U)
#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
#define HRTIM_EEFR1_EE4LTCH_Pos (18U)
#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
#define HRTIM_EEFR1_EE4FLTR_Pos (19U)
#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
#define HRTIM_EEFR1_EE5LTCH_Pos (24U)
#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
#define HRTIM_EEFR1_EE5FLTR_Pos (25U)
#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
/**** Bit definition for Slave external event filtering register 2 ***********/
#define HRTIM_EEFR2_EE6LTCH_Pos (0U)
#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
#define HRTIM_EEFR2_EE6FLTR_Pos (1U)
#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
#define HRTIM_EEFR2_EE7LTCH_Pos (6U)
#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
#define HRTIM_EEFR2_EE7FLTR_Pos (7U)
#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
#define HRTIM_EEFR2_EE8LTCH_Pos (12U)
#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
#define HRTIM_EEFR2_EE8FLTR_Pos (13U)
#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
#define HRTIM_EEFR2_EE9LTCH_Pos (18U)
#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
#define HRTIM_EEFR2_EE9FLTR_Pos (19U)
#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
#define HRTIM_EEFR2_EE10LTCH_Pos (24U)
#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
#define HRTIM_EEFR2_EE10FLTR_Pos (25U)
#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
/**** Bit definition for Slave Timer reset register ***************************/
#define HRTIM_RSTR_TIMFCMP1_Pos (0U)
#define HRTIM_RSTR_TIMFCMP1_Msk (0x1UL << HRTIM_RSTR_TIMFCMP1_Pos) /*!< 0x00000001 */
#define HRTIM_RSTR_TIMFCMP1 HRTIM_RSTR_TIMFCMP1_Msk /*!< Timer F compare 1 */
#define HRTIM_RSTR_UPDATE_Pos (1U)
#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
#define HRTIM_RSTR_CMP2_Pos (2U)
#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
#define HRTIM_RSTR_CMP4_Pos (3U)
#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
#define HRTIM_RSTR_MSTPER_Pos (4U)
#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
#define HRTIM_RSTR_MSTCMP1_Pos (5U)
#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
#define HRTIM_RSTR_MSTCMP2_Pos (6U)
#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
#define HRTIM_RSTR_MSTCMP3_Pos (7U)
#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
#define HRTIM_RSTR_MSTCMP4_Pos (8U)
#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
#define HRTIM_RSTR_EXTEVNT1_Pos (9U)
#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
#define HRTIM_RSTR_EXTEVNT2_Pos (10U)
#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
#define HRTIM_RSTR_EXTEVNT3_Pos (11U)
#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
#define HRTIM_RSTR_EXTEVNT4_Pos (12U)
#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
#define HRTIM_RSTR_EXTEVNT5_Pos (13U)
#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
#define HRTIM_RSTR_EXTEVNT6_Pos (14U)
#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
#define HRTIM_RSTR_EXTEVNT7_Pos (15U)
#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
#define HRTIM_RSTR_EXTEVNT8_Pos (16U)
#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
#define HRTIM_RSTR_EXTEVNT9_Pos (17U)
#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
/* Slave Timer A reset enable bits upon other slave timers events */
#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTR_TIMBCMP2_Pos (20U)
#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTR_TIMCCMP2_Pos (23U)
#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTR_TIMDCMP2_Pos (26U)
#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTR_TIMECMP1_Pos (28U)
#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTR_TIMECMP2_Pos (29U)
#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTR_TIMECMP4_Pos (30U)
#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTR_TIMFCMP2 HRTIM_RSTR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer B reset enable bits upon other slave timers events */
#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTBR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTBR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTBR_TIMFCMP2 HRTIM_RSTBR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer C reset enable bits upon other slave timers events */
#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTCR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTCR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTCR_TIMFCMP2 HRTIM_RSTCR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer D reset enable bits upon other slave timers events */
#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk /*!< Timer E compare 4 */
#define HRTIM_RSTDR_TIMFCMP2_Pos (31U)
#define HRTIM_RSTDR_TIMFCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTDR_TIMFCMP2 HRTIM_RSTDR_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer E reset enable bits upon other slave timers events */
#define HRTIM_RSTER_TIMACMP1_Pos (19U)
#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTER_TIMACMP2_Pos (20U)
#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTER_TIMACMP4_Pos (21U)
#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTER_TIMFCMP2_Pos (31U)
#define HRTIM_RSTER_TIMFCMP2_Msk (0x1UL << HRTIM_RSTER_TIMFCMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTER_TIMFCMP2 HRTIM_RSTER_TIMFCMP2_Msk /*!< Timer F compare 2 */
/* Slave Timer F reset enable bits upon other slave timers events */
#define HRTIM_RSTFR_TIMACMP1_Pos (19U)
#define HRTIM_RSTFR_TIMACMP1_Msk (0x1UL << HRTIM_RSTFR_TIMACMP1_Pos) /*!< 0x00080000 */
#define HRTIM_RSTFR_TIMACMP1 HRTIM_RSTFR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_RSTFR_TIMACMP2_Pos (20U)
#define HRTIM_RSTFR_TIMACMP2_Msk (0x1UL << HRTIM_RSTFR_TIMACMP2_Pos) /*!< 0x00100000 */
#define HRTIM_RSTFR_TIMACMP2 HRTIM_RSTFR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_RSTFR_TIMACMP4_Pos (21U)
#define HRTIM_RSTFR_TIMACMP4_Msk (0x1UL << HRTIM_RSTFR_TIMACMP4_Pos) /*!< 0x00200000 */
#define HRTIM_RSTFR_TIMACMP4 HRTIM_RSTFR_TIMACMP4_Msk /*!< Timer A compare 4 */
#define HRTIM_RSTFR_TIMBCMP1_Pos (22U)
#define HRTIM_RSTFR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_RSTFR_TIMBCMP1 HRTIM_RSTFR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_RSTFR_TIMBCMP2_Pos (23U)
#define HRTIM_RSTFR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_RSTFR_TIMBCMP2 HRTIM_RSTFR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_RSTFR_TIMBCMP4_Pos (24U)
#define HRTIM_RSTFR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMBCMP4_Pos) /*!< 0x01000000 */
#define HRTIM_RSTFR_TIMBCMP4 HRTIM_RSTFR_TIMBCMP4_Msk /*!< Timer B compare 4 */
#define HRTIM_RSTFR_TIMCCMP1_Pos (25U)
#define HRTIM_RSTFR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP1_Pos) /*!< 0x02000000 */
#define HRTIM_RSTFR_TIMCCMP1 HRTIM_RSTFR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_RSTFR_TIMCCMP2_Pos (26U)
#define HRTIM_RSTFR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP2_Pos) /*!< 0x04000000 */
#define HRTIM_RSTFR_TIMCCMP2 HRTIM_RSTFR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_RSTFR_TIMCCMP4_Pos (27U)
#define HRTIM_RSTFR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMCCMP4_Pos) /*!< 0x08000000 */
#define HRTIM_RSTFR_TIMCCMP4 HRTIM_RSTFR_TIMCCMP4_Msk /*!< Timer C compare 4 */
#define HRTIM_RSTFR_TIMDCMP1_Pos (28U)
#define HRTIM_RSTFR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP1_Pos) /*!< 0x10000000 */
#define HRTIM_RSTFR_TIMDCMP1 HRTIM_RSTFR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_RSTFR_TIMDCMP2_Pos (29U)
#define HRTIM_RSTFR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP2_Pos) /*!< 0x20000000 */
#define HRTIM_RSTFR_TIMDCMP2 HRTIM_RSTFR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_RSTFR_TIMDCMP4_Pos (30U)
#define HRTIM_RSTFR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTFR_TIMDCMP4_Pos) /*!< 0x40000000 */
#define HRTIM_RSTFR_TIMDCMP4 HRTIM_RSTFR_TIMDCMP4_Msk /*!< Timer D compare 4 */
#define HRTIM_RSTFR_TIMECMP2_Pos (31U)
#define HRTIM_RSTFR_TIMECMP2_Msk (0x1UL << HRTIM_RSTFR_TIMECMP2_Pos) /*!< 0x80000000 */
#define HRTIM_RSTFR_TIMECMP2 HRTIM_RSTFR_TIMECMP2_Msk /*!< Timer E compare 2 */
/**** Bit definition for Slave Timer Chopper register *************************/
#define HRTIM_CHPR_CARFRQ_Pos (0U)
#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
#define HRTIM_CHPR_CARDTY_Pos (4U)
#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
#define HRTIM_CHPR_STRPW_Pos (7U)
#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
/**** Bit definition for Slave Timer Capture 1 control register ***************/
#define HRTIM_CPT1CR_SWCPT_Pos (0U)
#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
#define HRTIM_CPT1CR_UPDCPT_Pos (1U)
#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
#define HRTIM_CPT1CR_TF1SET_Pos (0U)
#define HRTIM_CPT1CR_TF1SET_Msk (0x1UL << HRTIM_CPT1CR_TF1SET_Pos) /*!< 0x00000001 */
#define HRTIM_CPT1CR_TF1SET HRTIM_CPT1CR_TF1SET_Msk /*!< Timer F output 1 set */
#define HRTIM_CPT1CR_TF1RST_Pos (1U)
#define HRTIM_CPT1CR_TF1RST_Msk (0x1UL << HRTIM_CPT1CR_TF1RST_Pos) /*!< 0x00000002 */
#define HRTIM_CPT1CR_TF1RST HRTIM_CPT1CR_TF1RST_Msk /*!< Timer F output 1 reset */
#define HRTIM_CPT1CR_TIMFCMP1_Pos (2U)
#define HRTIM_CPT1CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP1_Pos) /*!< 0x00000004 */
#define HRTIM_CPT1CR_TIMFCMP1 HRTIM_CPT1CR_TIMFCMP1_Msk /*!< Timer F compare 1 */
#define HRTIM_CPT1CR_TIMFCMP2_Pos (3U)
#define HRTIM_CPT1CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMFCMP2_Pos) /*!< 0x00000008 */
#define HRTIM_CPT1CR_TIMFCMP2 HRTIM_CPT1CR_TIMFCMP2_Msk /*!< Timer F compare 2 */
#define HRTIM_CPT1CR_TA1SET_Pos (12U)
#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
#define HRTIM_CPT1CR_TA1RST_Pos (13U)
#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
#define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_CPT1CR_TB1SET_Pos (16U)
#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
#define HRTIM_CPT1CR_TB1RST_Pos (17U)
#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_CPT1CR_TC1SET_Pos (20U)
#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
#define HRTIM_CPT1CR_TC1RST_Pos (21U)
#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_CPT1CR_TD1SET_Pos (24U)
#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
#define HRTIM_CPT1CR_TD1RST_Pos (25U)
#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_CPT1CR_TE1SET_Pos (28U)
#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
#define HRTIM_CPT1CR_TE1RST_Pos (29U)
#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
#define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
/**** Bit definition for Slave Timer Capture 2 control register ***************/
#define HRTIM_CPT2CR_SWCPT_Pos (0U)
#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
#define HRTIM_CPT2CR_UPDCPT_Pos (1U)
#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
#define HRTIM_CPT2CR_TF1SET_Pos (0U)
#define HRTIM_CPT2CR_TF1SET_Msk (0x1UL << HRTIM_CPT2CR_TF1SET_Pos) /*!< 0x00000001 */
#define HRTIM_CPT2CR_TF1SET HRTIM_CPT2CR_TF1SET_Msk /*!< Timer F output 1 set */
#define HRTIM_CPT2CR_TF1RST_Pos (1U)
#define HRTIM_CPT2CR_TF1RST_Msk (0x1UL << HRTIM_CPT2CR_TF1RST_Pos) /*!< 0x00000002 */
#define HRTIM_CPT2CR_TF1RST HRTIM_CPT2CR_TF1RST_Msk /*!< Timer F output 1 reset */
#define HRTIM_CPT2CR_TIMFCMP1_Pos (2U)
#define HRTIM_CPT2CR_TIMFCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP1_Pos) /*!< 0x00000004 */
#define HRTIM_CPT2CR_TIMFCMP1 HRTIM_CPT2CR_TIMFCMP1_Msk /*!< Timer F compare 1 */
#define HRTIM_CPT2CR_TIMFCMP2_Pos (3U)
#define HRTIM_CPT2CR_TIMFCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMFCMP2_Pos) /*!< 0x00000008 */
#define HRTIM_CPT2CR_TIMFCMP2 HRTIM_CPT2CR_TIMFCMP2_Msk /*!< Timer F compare 2 */
#define HRTIM_CPT2CR_TA1SET_Pos (12U)
#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
#define HRTIM_CPT2CR_TA1RST_Pos (13U)
#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
#define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_CPT2CR_TB1SET_Pos (16U)
#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
#define HRTIM_CPT2CR_TB1RST_Pos (17U)
#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_CPT2CR_TC1SET_Pos (20U)
#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
#define HRTIM_CPT2CR_TC1RST_Pos (21U)
#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
#define HRTIM_CPT2CR_TD1SET_Pos (24U)
#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
#define HRTIM_CPT2CR_TD1RST_Pos (25U)
#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_CPT2CR_TE1SET_Pos (28U)
#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
#define HRTIM_CPT2CR_TE1RST_Pos (29U)
#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
#define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
/**** Bit definition for Slave Timer Output register **************************/
#define HRTIM_OUTR_POL1_Pos (1U)
#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
#define HRTIM_OUTR_IDLM1_Pos (2U)
#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
#define HRTIM_OUTR_IDLES1_Pos (3U)
#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
#define HRTIM_OUTR_FAULT1_Pos (4U)
#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
#define HRTIM_OUTR_CHP1_Pos (6U)
#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
#define HRTIM_OUTR_DIDL1_Pos (7U)
#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
#define HRTIM_OUTR_DTEN_Pos (8U)
#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
#define HRTIM_OUTR_DLYPRTEN_Pos (9U)
#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
#define HRTIM_OUTR_DLYPRT_Pos (10U)
#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
#define HRTIM_OUTR_BIAR_Pos (14U)
#define HRTIM_OUTR_BIAR_Msk (0x1UL << HRTIM_OUTR_BIAR_Pos) /*!< 0x00004000 */
#define HRTIM_OUTR_BIAR HRTIM_OUTR_BIAR_Msk /*!< Slave output Balanced Idle Automatic resume */
#define HRTIM_OUTR_POL2_Pos (17U)
#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
#define HRTIM_OUTR_IDLM2_Pos (18U)
#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
#define HRTIM_OUTR_IDLES2_Pos (19U)
#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
#define HRTIM_OUTR_FAULT2_Pos (20U)
#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
#define HRTIM_OUTR_CHP2_Pos (22U)
#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
#define HRTIM_OUTR_DIDL2_Pos (23U)
#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
/**** Bit definition for Timerx Fault register ***************************/
#define HRTIM_FLTR_FLT1EN_Pos (0U)
#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
#define HRTIM_FLTR_FLT2EN_Pos (1U)
#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
#define HRTIM_FLTR_FLT3EN_Pos (2U)
#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
#define HRTIM_FLTR_FLT4EN_Pos (3U)
#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
#define HRTIM_FLTR_FLT5EN_Pos (4U)
#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
#define HRTIM_FLTR_FLT6EN_Pos (5U)
#define HRTIM_FLTR_FLT6EN_Msk (0x1UL << HRTIM_FLTR_FLT6EN_Pos) /*!< 0x00000020 */
#define HRTIM_FLTR_FLT6EN HRTIM_FLTR_FLT6EN_Msk /*!< Fault 6 enable */
#define HRTIM_FLTR_FLTLCK_Pos (31U)
#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
/**** Bit definition for HRTIM Timerx control register 2 ****************/
#define HRTIM_TIMCR2_DCDE_Pos (0U)
#define HRTIM_TIMCR2_DCDE_Msk (0x1UL << HRTIM_TIMCR2_DCDE_Pos) /*!< 0x00000001 */
#define HRTIM_TIMCR2_DCDE HRTIM_TIMCR2_DCDE_Msk /*!< Dual Channel DAC trigger enable */
#define HRTIM_TIMCR2_DCDS_Pos (1U)
#define HRTIM_TIMCR2_DCDS_Msk (0x1UL << HRTIM_TIMCR2_DCDS_Pos) /*!< 0x00000002 */
#define HRTIM_TIMCR2_DCDS HRTIM_TIMCR2_DCDS_Msk /*!< Dual Channel DAC step trigger */
#define HRTIM_TIMCR2_DCDR_Pos (2U)
#define HRTIM_TIMCR2_DCDR_Msk (0x1UL << HRTIM_TIMCR2_DCDR_Pos) /*!< 0x00000004 */
#define HRTIM_TIMCR2_DCDR HRTIM_TIMCR2_DCDR_Msk /*!< Dual Channel DAC reset trigger */
#define HRTIM_TIMCR2_UDM_Pos (4U)
#define HRTIM_TIMCR2_UDM_Msk (0x1UL << HRTIM_TIMCR2_UDM_Pos) /*!< 0x00000010 */
#define HRTIM_TIMCR2_UDM HRTIM_TIMCR2_UDM_Msk /*!< Up-Down Mode*/
#define HRTIM_TIMCR2_ROM_Pos (6U)
#define HRTIM_TIMCR2_ROM_Msk (0x3UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x000000C0 */
#define HRTIM_TIMCR2_ROM HRTIM_TIMCR2_ROM_Msk /*!< Roll-over Mode */
#define HRTIM_TIMCR2_ROM_0 (0x1UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x00000040 */
#define HRTIM_TIMCR2_ROM_1 (0x2UL << HRTIM_TIMCR2_ROM_Pos) /*!< 0x00000080 */
#define HRTIM_TIMCR2_OUTROM_Pos (8U)
#define HRTIM_TIMCR2_OUTROM_Msk (0x3UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000300 */
#define HRTIM_TIMCR2_OUTROM HRTIM_TIMCR2_OUTROM_Msk /*!< Output Roll-Over Mode */
#define HRTIM_TIMCR2_OUTROM_0 (0x1UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000100 */
#define HRTIM_TIMCR2_OUTROM_1 (0x2UL << HRTIM_TIMCR2_OUTROM_Pos) /*!< 0x00000200 */
#define HRTIM_TIMCR2_ADROM_Pos (10U)
#define HRTIM_TIMCR2_ADROM_Msk (0x3UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000C00 */
#define HRTIM_TIMCR2_ADROM HRTIM_TIMCR2_ADROM_Msk /*!< ADC Roll-Over Mode */
#define HRTIM_TIMCR2_ADROM_0 (0x1UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000400 */
#define HRTIM_TIMCR2_ADROM_1 (0x2UL << HRTIM_TIMCR2_ADROM_Pos) /*!< 0x00000800 */
#define HRTIM_TIMCR2_BMROM_Pos (12U)
#define HRTIM_TIMCR2_BMROM_Msk (0x3UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00003000 */
#define HRTIM_TIMCR2_BMROM HRTIM_TIMCR2_BMROM_Msk /*!< Burst Mode Rollover Mode */
#define HRTIM_TIMCR2_BMROM_0 (0x1UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00001000 */
#define HRTIM_TIMCR2_BMROM_1 (0x2UL << HRTIM_TIMCR2_BMROM_Pos) /*!< 0x00002000 */
#define HRTIM_TIMCR2_FEROM_Pos (14U)
#define HRTIM_TIMCR2_FEROM_Msk (0x3UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x0000C000 */
#define HRTIM_TIMCR2_FEROM HRTIM_TIMCR2_FEROM_Msk /*!< Fault and Event Rollover Mode */
#define HRTIM_TIMCR2_FEROM_0 (0x1UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x00004000 */
#define HRTIM_TIMCR2_FEROM_1 (0x2UL << HRTIM_TIMCR2_FEROM_Pos) /*!< 0x00008000 */
#define HRTIM_TIMCR2_GTCMP1_Pos (16U)
#define HRTIM_TIMCR2_GTCMP1_Msk (0x1UL << HRTIM_TIMCR2_GTCMP1_Pos) /*!< 0x00010000 */
#define HRTIM_TIMCR2_GTCMP1 HRTIM_TIMCR2_GTCMP1_Msk /*!< Greater than Compare 1 PWM mode */
#define HRTIM_TIMCR2_GTCMP3_Pos (17U)
#define HRTIM_TIMCR2_GTCMP3_Msk (0x1UL << HRTIM_TIMCR2_GTCMP3_Pos) /*!< 0x00020000 */
#define HRTIM_TIMCR2_GTCMP3 HRTIM_TIMCR2_GTCMP3_Msk /*!< Greater than Compare 3 PWM mode */
#define HRTIM_TIMCR2_TRGHLF_Pos (20U)
#define HRTIM_TIMCR2_TRGHLF_Msk (0x1UL << HRTIM_TIMCR2_TRGHLF_Pos) /*!< 0x00100000 */
#define HRTIM_TIMCR2_TRGHLF HRTIM_TIMCR2_TRGHLF_Msk /*!< Triggered-Half mode */
/**** Bit definition for Slave external event filtering register 3 ***********/
#define HRTIM_EEFR3_EEVACE_Pos (0U)
#define HRTIM_EEFR3_EEVACE_Msk (0x1UL << HRTIM_EEFR3_EEVACE_Pos) /*!< 0x00000001 */
#define HRTIM_EEFR3_EEVACE HRTIM_EEFR3_EEVACE_Msk /*!< External Event A Counter Enable */
#define HRTIM_EEFR3_EEVACRES_Pos (1U)
#define HRTIM_EEFR3_EEVACRES_Msk (0x1UL << HRTIM_EEFR3_EEVACRES_Pos) /*!< 0x00000002 */
#define HRTIM_EEFR3_EEVACRES HRTIM_EEFR3_EEVACRES_Msk /*!< External Event A Counter Reset */
#define HRTIM_EEFR3_EEVARSTM_Pos (2U)
#define HRTIM_EEFR3_EEVARSTM_Msk (0x1UL << HRTIM_EEFR3_EEVARSTM_Pos) /*!< 0x00000004 */
#define HRTIM_EEFR3_EEVARSTM HRTIM_EEFR3_EEVARSTM_Msk /*!< External Event A Counter Reset Mode */
#define HRTIM_EEFR3_EEVASEL_Pos (4U)
#define HRTIM_EEFR3_EEVASEL_Msk (0xFUL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x000000F0 */
#define HRTIM_EEFR3_EEVASEL HRTIM_EEFR3_EEVASEL_Msk /*!< External Event A Selection */
#define HRTIM_EEFR3_EEVASEL_0 (0x1UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000010 */
#define HRTIM_EEFR3_EEVASEL_1 (0x2UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000020 */
#define HRTIM_EEFR3_EEVASEL_2 (0x4UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000040 */
#define HRTIM_EEFR3_EEVASEL_3 (0x8UL << HRTIM_EEFR3_EEVASEL_Pos) /*!< 0x00000080 */
#define HRTIM_EEFR3_EEVACNT_Pos (8U)
#define HRTIM_EEFR3_EEVACNT_Msk (0x3FUL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00003F00 */
#define HRTIM_EEFR3_EEVACNT HRTIM_EEFR3_EEVACNT_Msk /*!< External Event A Selection */
#define HRTIM_EEFR3_EEVACNT_0 (0x1UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000100 */
#define HRTIM_EEFR3_EEVACNT_1 (0x2UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000200 */
#define HRTIM_EEFR3_EEVACNT_2 (0x4UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000400 */
#define HRTIM_EEFR3_EEVACNT_3 (0x8UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00000800 */
#define HRTIM_EEFR3_EEVACNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00001000 */
#define HRTIM_EEFR3_EEVACNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x00002000 */
#define HRTIM_EEFR3_EEVBCE_Pos (16U)
#define HRTIM_EEFR3_EEVBCE_Msk (0x1UL << HRTIM_EEFR3_EEVBCE_Pos) /*!< 0x00010000 */
#define HRTIM_EEFR3_EEVBCE HRTIM_EEFR3_EEVBCE_Msk /*!< External Event B Counter Enable */
#define HRTIM_EEFR3_EEVBCRES_Pos (17U)
#define HRTIM_EEFR3_EEVBCRES_Msk (0x1UL << HRTIM_EEFR3_EEVBCRES_Pos) /*!< 0x00020000 */
#define HRTIM_EEFR3_EEVBCRES HRTIM_EEFR3_EEVBCRES_Msk /*!< External Event B Counter Reset */
#define HRTIM_EEFR3_EEVBRSTM_Pos (18U)
#define HRTIM_EEFR3_EEVBRSTM_Msk (0x1UL << HRTIM_EEFR3_EEVBRSTM_Pos) /*!< 0x00040000 */
#define HRTIM_EEFR3_EEVBRSTM HRTIM_EEFR3_EEVBRSTM_Msk /*!< External Event B Counter Reset Mode */
#define HRTIM_EEFR3_EEVBSEL_Pos (20U)
#define HRTIM_EEFR3_EEVBSEL_Msk (0xFUL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00F00000 */
#define HRTIM_EEFR3_EEVBSEL HRTIM_EEFR3_EEVBSEL_Msk /*!< External Event B Selection */
#define HRTIM_EEFR3_EEVBSEL_0 (0x1UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00100000 */
#define HRTIM_EEFR3_EEVBSEL_1 (0x2UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00200000 */
#define HRTIM_EEFR3_EEVBSEL_2 (0x4UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00400000 */
#define HRTIM_EEFR3_EEVBSEL_3 (0x8UL << HRTIM_EEFR3_EEVBSEL_Pos) /*!< 0x00800000 */
#define HRTIM_EEFR3_EEVBCNT_Pos (24U)
#define HRTIM_EEFR3_EEVBCNT_Msk (0x3FUL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x3F000000 */
#define HRTIM_EEFR3_EEVBCNT HRTIM_EEFR3_EEVBCNT_Msk /*!< External Event B Counter */
#define HRTIM_EEFR3_EEVBCNT_0 (0x1UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x01000000 */
#define HRTIM_EEFR3_EEVBCNT_1 (0x2UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x02000000 */
#define HRTIM_EEFR3_EEVBCNT_2 (0x4UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x04000000 */
#define HRTIM_EEFR3_EEVBCNT_3 (0x8UL << HRTIM_EEFR3_EEVBCNT_Pos) /*!< 0x08000000 */
#define HRTIM_EEFR3_EEVBCNT_4 (0x10UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x10000000 */
#define HRTIM_EEFR3_EEVBCNT_5 (0x20UL << HRTIM_EEFR3_EEVACNT_Pos) /*!< 0x20000000 */
/**** Bit definition for Common HRTIM Timer control register 1 ****************/
#define HRTIM_CR1_MUDIS_Pos (0U)
#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
#define HRTIM_CR1_TAUDIS_Pos (1U)
#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
#define HRTIM_CR1_TBUDIS_Pos (2U)
#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
#define HRTIM_CR1_TCUDIS_Pos (3U)
#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
#define HRTIM_CR1_TDUDIS_Pos (4U)
#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
#define HRTIM_CR1_TEUDIS_Pos (5U)
#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
#define HRTIM_CR1_TFUDIS_Pos (6U)
#define HRTIM_CR1_TFUDIS_Msk (0x1UL << HRTIM_CR1_TFUDIS_Pos) /*!< 0x00000040 */
#define HRTIM_CR1_TFUDIS HRTIM_CR1_TFUDIS_Msk /*!< Timer F update disable*/
#define HRTIM_CR1_ADC1USRC_Pos (16U)
#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
#define HRTIM_CR1_ADC2USRC_Pos (19U)
#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
#define HRTIM_CR1_ADC3USRC_Pos (22U)
#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
#define HRTIM_CR1_ADC4USRC_Pos (25U)
#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
/**** Bit definition for Common HRTIM Timer control register 2 ****************/
#define HRTIM_CR2_MSWU_Pos (0U)
#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
#define HRTIM_CR2_TASWU_Pos (1U)
#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
#define HRTIM_CR2_TBSWU_Pos (2U)
#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
#define HRTIM_CR2_TCSWU_Pos (3U)
#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
#define HRTIM_CR2_TDSWU_Pos (4U)
#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
#define HRTIM_CR2_TESWU_Pos (5U)
#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
#define HRTIM_CR2_TFSWU_Pos (6U)
#define HRTIM_CR2_TFSWU_Msk (0x1UL << HRTIM_CR2_TFSWU_Pos) /*!< 0x00000040 */
#define HRTIM_CR2_TFSWU HRTIM_CR2_TFSWU_Msk /*!< Timer F software update */
#define HRTIM_CR2_MRST_Pos (8U)
#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
#define HRTIM_CR2_TARST_Pos (9U)
#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
#define HRTIM_CR2_TBRST_Pos (10U)
#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
#define HRTIM_CR2_TCRST_Pos (11U)
#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
#define HRTIM_CR2_TDRST_Pos (12U)
#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
#define HRTIM_CR2_TERST_Pos (13U)
#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
#define HRTIM_CR2_TFRST_Pos (14U)
#define HRTIM_CR2_TFRST_Msk (0x1UL << HRTIM_CR2_TFRST_Pos) /*!< 0x00004000 */
#define HRTIM_CR2_TFRST HRTIM_CR2_TFRST_Msk /*!< Timer F count software reset */
#define HRTIM_CR2_SWPA_Pos (16U)
#define HRTIM_CR2_SWPA_Msk (0x1UL << HRTIM_CR2_SWPA_Pos) /*!< 0x00010000 */
#define HRTIM_CR2_SWPA HRTIM_CR2_SWPA_Msk /*!< Timer A swap outputs */
#define HRTIM_CR2_SWPB_Pos (17U)
#define HRTIM_CR2_SWPB_Msk (0x1UL << HRTIM_CR2_SWPB_Pos) /*!< 0x00020000 */
#define HRTIM_CR2_SWPB HRTIM_CR2_SWPB_Msk /*!< Timer B swap outputs */
#define HRTIM_CR2_SWPC_Pos (18U)
#define HRTIM_CR2_SWPC_Msk (0x1UL << HRTIM_CR2_SWPC_Pos) /*!< 0x00040000 */
#define HRTIM_CR2_SWPC HRTIM_CR2_SWPC_Msk /*!< Timer C swap outputs */
#define HRTIM_CR2_SWPD_Pos (19U)
#define HRTIM_CR2_SWPD_Msk (0x1UL << HRTIM_CR2_SWPD_Pos) /*!< 0x00080000 */
#define HRTIM_CR2_SWPD HRTIM_CR2_SWPD_Msk /*!< Timer D swap outputs */
#define HRTIM_CR2_SWPE_Pos (20U)
#define HRTIM_CR2_SWPE_Msk (0x1UL << HRTIM_CR2_SWPE_Pos) /*!< 0x00100000 */
#define HRTIM_CR2_SWPE HRTIM_CR2_SWPE_Msk /*!< Timer E swap outputs */
#define HRTIM_CR2_SWPF_Pos (21U)
#define HRTIM_CR2_SWPF_Msk (0x1UL << HRTIM_CR2_SWPF_Pos) /*!< 0x00200000 */
#define HRTIM_CR2_SWPF HRTIM_CR2_SWPF_Msk /*!< Timer F swap outputs */
/**** Bit definition for Common HRTIM Timer interrupt status register *********/
#define HRTIM_ISR_FLT1_Pos (0U)
#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
#define HRTIM_ISR_FLT2_Pos (1U)
#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
#define HRTIM_ISR_FLT3_Pos (2U)
#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
#define HRTIM_ISR_FLT4_Pos (3U)
#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
#define HRTIM_ISR_FLT5_Pos (4U)
#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
#define HRTIM_ISR_SYSFLT_Pos (5U)
#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
#define HRTIM_ISR_FLT6_Pos (6U)
#define HRTIM_ISR_FLT6_Msk (0x1UL << HRTIM_ISR_FLT6_Pos) /*!< 0x00000040 */
#define HRTIM_ISR_FLT6 HRTIM_ISR_FLT6_Msk /*!< Fault 6 interrupt flag */
#define HRTIM_ISR_DLLRDY_Pos (16U)
#define HRTIM_ISR_DLLRDY_Msk (0x1UL << HRTIM_ISR_DLLRDY_Pos) /*!< 0x00010000 */
#define HRTIM_ISR_DLLRDY HRTIM_ISR_DLLRDY_Msk /*!< DLL ready interrupt flag */
#define HRTIM_ISR_BMPER_Pos (17U)
#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
#define HRTIM_ICR_FLT1C_Pos (0U)
#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
#define HRTIM_ICR_FLT2C_Pos (1U)
#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
#define HRTIM_ICR_FLT3C_Pos (2U)
#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
#define HRTIM_ICR_FLT4C_Pos (3U)
#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
#define HRTIM_ICR_FLT5C_Pos (4U)
#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
#define HRTIM_ICR_SYSFLTC_Pos (5U)
#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
#define HRTIM_ICR_FLT6C_Pos (6U)
#define HRTIM_ICR_FLT6C_Msk (0x1UL << HRTIM_ICR_FLT6C_Pos) /*!< 0x00000040 */
#define HRTIM_ICR_FLT6C HRTIM_ICR_FLT6C_Msk /*!< Fault 6 interrupt flag clear */
#define HRTIM_ICR_DLLRDYC_Pos (16U)
#define HRTIM_ICR_DLLRDYC_Msk (0x1UL << HRTIM_ICR_DLLRDYC_Pos) /*!< 0x00010000 */
#define HRTIM_ICR_DLLRDYC HRTIM_ICR_DLLRDYC_Msk /*!< DLL ready interrupt flag clear */
#define HRTIM_ICR_BMPERC_Pos (17U)
#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
#define HRTIM_IER_FLT1_Pos (0U)
#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
#define HRTIM_IER_FLT2_Pos (1U)
#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
#define HRTIM_IER_FLT3_Pos (2U)
#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
#define HRTIM_IER_FLT4_Pos (3U)
#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
#define HRTIM_IER_FLT5_Pos (4U)
#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
#define HRTIM_IER_SYSFLT_Pos (5U)
#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
#define HRTIM_IER_FLT6_Pos (6U)
#define HRTIM_IER_FLT6_Msk (0x1UL << HRTIM_IER_FLT6_Pos) /*!< 0x00000040 */
#define HRTIM_IER_FLT6 HRTIM_IER_FLT6_Msk /*!< Fault 6 interrupt enable */
#define HRTIM_IER_DLLRDY_Pos (16U)
#define HRTIM_IER_DLLRDY_Msk (0x1UL << HRTIM_IER_DLLRDY_Pos) /*!< 0x00010000 */
#define HRTIM_IER_DLLRDY HRTIM_IER_DLLRDY_Msk /*!< DLL ready interrupt enable */
#define HRTIM_IER_BMPER_Pos (17U)
#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
/**** Bit definition for Common HRTIM Timer output enable register ************/
#define HRTIM_OENR_TA1OEN_Pos (0U)
#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
#define HRTIM_OENR_TA2OEN_Pos (1U)
#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
#define HRTIM_OENR_TB1OEN_Pos (2U)
#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
#define HRTIM_OENR_TB2OEN_Pos (3U)
#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
#define HRTIM_OENR_TC1OEN_Pos (4U)
#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
#define HRTIM_OENR_TC2OEN_Pos (5U)
#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
#define HRTIM_OENR_TD1OEN_Pos (6U)
#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
#define HRTIM_OENR_TD2OEN_Pos (7U)
#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
#define HRTIM_OENR_TE1OEN_Pos (8U)
#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
#define HRTIM_OENR_TE2OEN_Pos (9U)
#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
#define HRTIM_OENR_TF1OEN_Pos (10U)
#define HRTIM_OENR_TF1OEN_Msk (0x1UL << HRTIM_OENR_TF1OEN_Pos) /*!< 0x00000400 */
#define HRTIM_OENR_TF1OEN HRTIM_OENR_TF1OEN_Msk /*!< Timer F Output 1 enable */
#define HRTIM_OENR_TF2OEN_Pos (11U)
#define HRTIM_OENR_TF2OEN_Msk (0x1UL << HRTIM_OENR_TF2OEN_Pos) /*!< 0x00000800 */
#define HRTIM_OENR_TF2OEN HRTIM_OENR_TF2OEN_Msk /*!< Timer F Output 2 enable */
/**** Bit definition for Common HRTIM Timer output disable register ***********/
#define HRTIM_ODISR_TA1ODIS_Pos (0U)
#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
#define HRTIM_ODISR_TA2ODIS_Pos (1U)
#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
#define HRTIM_ODISR_TB1ODIS_Pos (2U)
#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
#define HRTIM_ODISR_TB2ODIS_Pos (3U)
#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
#define HRTIM_ODISR_TC1ODIS_Pos (4U)
#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
#define HRTIM_ODISR_TC2ODIS_Pos (5U)
#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
#define HRTIM_ODISR_TD1ODIS_Pos (6U)
#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
#define HRTIM_ODISR_TD2ODIS_Pos (7U)
#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
#define HRTIM_ODISR_TE1ODIS_Pos (8U)
#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
#define HRTIM_ODISR_TE2ODIS_Pos (9U)
#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
#define HRTIM_ODISR_TF1ODIS_Pos (10U)
#define HRTIM_ODISR_TF1ODIS_Msk (0x1UL << HRTIM_ODISR_TF1ODIS_Pos) /*!< 0x00000100 */
#define HRTIM_ODISR_TF1ODIS HRTIM_ODISR_TF1ODIS_Msk /*!< Timer F Output 1 disable */
#define HRTIM_ODISR_TF2ODIS_Pos (11U)
#define HRTIM_ODISR_TF2ODIS_Msk (0x1UL << HRTIM_ODISR_TF2ODIS_Pos) /*!< 0x00000200 */
#define HRTIM_ODISR_TF2ODIS HRTIM_ODISR_TF2ODIS_Msk /*!< Timer F Output 2 disable */
/**** Bit definition for Common HRTIM Timer output disable status register *****/
#define HRTIM_ODSR_TA1ODS_Pos (0U)
#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
#define HRTIM_ODSR_TA2ODS_Pos (1U)
#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
#define HRTIM_ODSR_TB1ODS_Pos (2U)
#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
#define HRTIM_ODSR_TB2ODS_Pos (3U)
#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
#define HRTIM_ODSR_TC1ODS_Pos (4U)
#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
#define HRTIM_ODSR_TC2ODS_Pos (5U)
#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
#define HRTIM_ODSR_TD1ODS_Pos (6U)
#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
#define HRTIM_ODSR_TD2ODS_Pos (7U)
#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
#define HRTIM_ODSR_TE1ODS_Pos (8U)
#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
#define HRTIM_ODSR_TE2ODS_Pos (9U)
#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
#define HRTIM_ODSR_TF1ODS_Pos (10U)
#define HRTIM_ODSR_TF1ODS_Msk (0x1UL << HRTIM_ODSR_TF1ODS_Pos) /*!< 0x00000100 */
#define HRTIM_ODSR_TF1ODS HRTIM_ODSR_TF1ODS_Msk /*!< Timer F Output 1 disable status */
#define HRTIM_ODSR_TF2ODS_Pos (11U)
#define HRTIM_ODSR_TF2ODS_Msk (0x1UL << HRTIM_ODSR_TF2ODS_Pos) /*!< 0x00000200 */
#define HRTIM_ODSR_TF2ODS HRTIM_ODSR_TF2ODS_Msk /*!< Timer F Output 2 disable status */
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
#define HRTIM_BMCR_BME_Pos (0U)
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
#define HRTIM_BMCR_BMOM_Pos (1U)
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
#define HRTIM_BMCR_BMCLK_Pos (2U)
#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
#define HRTIM_BMCR_BMPRSC_Pos (6U)
#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
#define HRTIM_BMCR_BMPREN_Pos (10U)
#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
#define HRTIM_BMCR_MTBM_Pos (16U)
#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
#define HRTIM_BMCR_TABM_Pos (17U)
#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
#define HRTIM_BMCR_TBBM_Pos (18U)
#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
#define HRTIM_BMCR_TCBM_Pos (19U)
#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
#define HRTIM_BMCR_TDBM_Pos (20U)
#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
#define HRTIM_BMCR_TEBM_Pos (21U)
#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
#define HRTIM_BMCR_TFBM_Pos (22U)
#define HRTIM_BMCR_TFBM_Msk (0x1UL << HRTIM_BMCR_TFBM_Pos) /*!< 0x00400000 */
#define HRTIM_BMCR_TFBM HRTIM_BMCR_TFBM_Msk /*!< Timer F Burst mode */
#define HRTIM_BMCR_BMSTAT_Pos (31U)
#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
#define HRTIM_BMTRGR_SW_Pos (0U)
#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
#define HRTIM_BMTRGR_MSTRST_Pos (1U)
#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
#define HRTIM_BMTRGR_MSTREP_Pos (2U)
#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
#define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
#define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
#define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
#define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
#define HRTIM_BMTRGR_TARST_Pos (7U)
#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
#define HRTIM_BMTRGR_TAREP_Pos (8U)
#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
#define HRTIM_BMTRGR_TACMP1_Pos (9U)
#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
#define HRTIM_BMTRGR_TACMP2_Pos (10U)
#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
#define HRTIM_BMTRGR_TBRST_Pos (11U)
#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
#define HRTIM_BMTRGR_TBREP_Pos (12U)
#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
#define HRTIM_BMTRGR_TBCMP1_Pos (13U)
#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
#define HRTIM_BMTRGR_TBCMP2_Pos (14U)
#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
#define HRTIM_BMTRGR_TCRST_Pos (15U)
#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
#define HRTIM_BMTRGR_TCREP_Pos (16U)
#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
#define HRTIM_BMTRGR_TCCMP1_Pos (17U)
#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
#define HRTIM_BMTRGR_TFRST_Pos (18U)
#define HRTIM_BMTRGR_TFRST_Msk (0x1UL << HRTIM_BMTRGR_TFRST_Pos) /*!< 0x00040000 */
#define HRTIM_BMTRGR_TFRST HRTIM_BMTRGR_TFRST_Msk /*!< Timer F reset */
#define HRTIM_BMTRGR_TDRST_Pos (19U)
#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
#define HRTIM_BMTRGR_TDREP_Pos (20U)
#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
#define HRTIM_BMTRGR_TFREP_Pos (21U)
#define HRTIM_BMTRGR_TFREP_Msk (0x1UL << HRTIM_BMTRGR_TFREP_Pos) /*!< 0x00200000 */
#define HRTIM_BMTRGR_TFREP HRTIM_BMTRGR_TFREP_Msk /*!< Timer F repetition*/
#define HRTIM_BMTRGR_TDCMP2_Pos (22U)
#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
#define HRTIM_BMTRGR_TFCMP1_Pos (23U)
#define HRTIM_BMTRGR_TFCMP1_Msk (0x1UL << HRTIM_BMTRGR_TFCMP1_Pos) /*!< 0x00800000 */
#define HRTIM_BMTRGR_TFCMP1 HRTIM_BMTRGR_TFCMP1_Msk /*!< Timer F compare 1 */
#define HRTIM_BMTRGR_TEREP_Pos (24U)
#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
#define HRTIM_BMTRGR_TECMP1_Pos (25U)
#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
#define HRTIM_BMTRGR_TECMP2_Pos (26U)
#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
#define HRTIM_BMTRGR_TAEEV7_Pos (27U)
#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
#define HRTIM_BMTRGR_TDEEV8_Pos (28U)
#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
#define HRTIM_BMTRGR_EEV7_Pos (29U)
#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
#define HRTIM_BMTRGR_EEV8_Pos (30U)
#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
#define HRTIM_BMTRGR_OCHPEV_Pos (31U)
#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
/******************* Bit definition for HRTIM_BMCMPR register ***************/
#define HRTIM_BMCMPR_BMCMPR_Pos (0U)
#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
/******************* Bit definition for HRTIM_BMPER register ****************/
#define HRTIM_BMPER_BMPER_Pos (0U)
#define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
#define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
/******************* Bit definition for HRTIM_EECR1 register ****************/
#define HRTIM_EECR1_EE1SRC_Pos (0U)
#define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
#define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
#define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
#define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
#define HRTIM_EECR1_EE1POL_Pos (2U)
#define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
#define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
#define HRTIM_EECR1_EE1SNS_Pos (3U)
#define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
#define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
#define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
#define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
#define HRTIM_EECR1_EE1FAST_Pos (5U)
#define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
#define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
#define HRTIM_EECR1_EE2SRC_Pos (6U)
#define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
#define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
#define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
#define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
#define HRTIM_EECR1_EE2POL_Pos (8U)
#define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
#define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
#define HRTIM_EECR1_EE2SNS_Pos (9U)
#define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
#define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
#define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
#define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
#define HRTIM_EECR1_EE2FAST_Pos (11U)
#define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
#define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
#define HRTIM_EECR1_EE3SRC_Pos (12U)
#define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
#define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
#define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
#define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
#define HRTIM_EECR1_EE3POL_Pos (14U)
#define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
#define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
#define HRTIM_EECR1_EE3SNS_Pos (15U)
#define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
#define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
#define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
#define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
#define HRTIM_EECR1_EE3FAST_Pos (17U)
#define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
#define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
#define HRTIM_EECR1_EE4SRC_Pos (18U)
#define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
#define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
#define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
#define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
#define HRTIM_EECR1_EE4POL_Pos (20U)
#define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
#define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
#define HRTIM_EECR1_EE4SNS_Pos (21U)
#define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
#define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
#define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
#define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
#define HRTIM_EECR1_EE4FAST_Pos (23U)
#define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
#define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
#define HRTIM_EECR1_EE5SRC_Pos (24U)
#define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
#define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
#define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
#define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
#define HRTIM_EECR1_EE5POL_Pos (26U)
#define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
#define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
#define HRTIM_EECR1_EE5SNS_Pos (27U)
#define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
#define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
#define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
#define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
#define HRTIM_EECR1_EE5FAST_Pos (29U)
#define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
#define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
/******************* Bit definition for HRTIM_EECR2 register ****************/
#define HRTIM_EECR2_EE6SRC_Pos (0U)
#define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
#define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
#define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
#define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
#define HRTIM_EECR2_EE6POL_Pos (2U)
#define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
#define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
#define HRTIM_EECR2_EE6SNS_Pos (3U)
#define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
#define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
#define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
#define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
#define HRTIM_EECR2_EE7SRC_Pos (6U)
#define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
#define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
#define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
#define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
#define HRTIM_EECR2_EE7POL_Pos (8U)
#define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
#define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
#define HRTIM_EECR2_EE7SNS_Pos (9U)
#define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
#define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
#define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
#define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
#define HRTIM_EECR2_EE8SRC_Pos (12U)
#define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
#define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
#define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
#define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
#define HRTIM_EECR2_EE8POL_Pos (14U)
#define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
#define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
#define HRTIM_EECR2_EE8SNS_Pos (15U)
#define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
#define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
#define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
#define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
#define HRTIM_EECR2_EE9SRC_Pos (18U)
#define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
#define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
#define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
#define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
#define HRTIM_EECR2_EE9POL_Pos (20U)
#define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
#define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
#define HRTIM_EECR2_EE9SNS_Pos (21U)
#define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
#define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
#define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
#define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
#define HRTIM_EECR2_EE10SRC_Pos (24U)
#define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
#define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
#define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
#define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
#define HRTIM_EECR2_EE10POL_Pos (26U)
#define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
#define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
#define HRTIM_EECR2_EE10SNS_Pos (27U)
#define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
#define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
#define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
#define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
/******************* Bit definition for HRTIM_EECR3 register ****************/
#define HRTIM_EECR3_EE6F_Pos (0U)
#define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
#define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
#define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
#define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
#define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
#define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
#define HRTIM_EECR3_EE7F_Pos (6U)
#define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
#define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
#define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
#define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
#define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
#define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
#define HRTIM_EECR3_EE8F_Pos (12U)
#define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
#define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
#define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
#define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
#define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
#define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
#define HRTIM_EECR3_EE9F_Pos (18U)
#define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
#define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
#define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
#define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
#define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
#define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
#define HRTIM_EECR3_EE10F_Pos (24U)
#define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
#define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
#define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
#define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
#define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
#define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
#define HRTIM_EECR3_EEVSD_Pos (30U)
#define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
#define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
#define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
#define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
/******************* Bit definition for HRTIM_ADC1R register ****************/
#define HRTIM_ADC1R_AD1MC1_Pos (0U)
#define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
#define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
#define HRTIM_ADC1R_AD1MC2_Pos (1U)
#define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
#define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
#define HRTIM_ADC1R_AD1MC3_Pos (2U)
#define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
#define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
#define HRTIM_ADC1R_AD1MC4_Pos (3U)
#define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
#define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
#define HRTIM_ADC1R_AD1MPER_Pos (4U)
#define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
#define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
#define HRTIM_ADC1R_AD1EEV1_Pos (5U)
#define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
#define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
#define HRTIM_ADC1R_AD1EEV2_Pos (6U)
#define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
#define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
#define HRTIM_ADC1R_AD1EEV3_Pos (7U)
#define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
#define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
#define HRTIM_ADC1R_AD1EEV4_Pos (8U)
#define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
#define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
#define HRTIM_ADC1R_AD1EEV5_Pos (9U)
#define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
#define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
#define HRTIM_ADC1R_AD1TFC2_Pos (10U)
#define HRTIM_ADC1R_AD1TFC2_Msk (0x1UL << HRTIM_ADC1R_AD1TFC2_Pos) /*!< 0x00000400 */
#define HRTIM_ADC1R_AD1TFC2 HRTIM_ADC1R_AD1TFC2_Msk /*!< ADC Trigger 1 on Timer F compare 2 */
#define HRTIM_ADC1R_AD1TAC3_Pos (11U)
#define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
#define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
#define HRTIM_ADC1R_AD1TAC4_Pos (12U)
#define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
#define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
#define HRTIM_ADC1R_AD1TAPER_Pos (13U)
#define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
#define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
#define HRTIM_ADC1R_AD1TARST_Pos (14U)
#define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
#define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
#define HRTIM_ADC1R_AD1TFC3_Pos (15U)
#define HRTIM_ADC1R_AD1TFC3_Msk (0x1UL << HRTIM_ADC1R_AD1TFC3_Pos) /*!< 0x00008000 */
#define HRTIM_ADC1R_AD1TFC3 HRTIM_ADC1R_AD1TFC3_Msk /*!< ADC Trigger 1 on Timer F compare 3 */
#define HRTIM_ADC1R_AD1TBC3_Pos (16U)
#define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
#define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
#define HRTIM_ADC1R_AD1TBC4_Pos (17U)
#define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
#define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
#define HRTIM_ADC1R_AD1TBPER_Pos (18U)
#define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
#define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
#define HRTIM_ADC1R_AD1TBRST_Pos (19U)
#define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
#define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
#define HRTIM_ADC1R_AD1TFC4_Pos (20U)
#define HRTIM_ADC1R_AD1TFC4_Msk (0x1UL << HRTIM_ADC1R_AD1TFC4_Pos) /*!< 0x00100000 */
#define HRTIM_ADC1R_AD1TFC4 HRTIM_ADC1R_AD1TFC4_Msk /*!< ADC Trigger 1 on Timer F compare 4 */
#define HRTIM_ADC1R_AD1TCC3_Pos (21U)
#define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
#define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
#define HRTIM_ADC1R_AD1TCC4_Pos (22U)
#define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
#define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
#define HRTIM_ADC1R_AD1TCPER_Pos (23U)
#define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
#define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
#define HRTIM_ADC1R_AD1TFPER_Pos (24U)
#define HRTIM_ADC1R_AD1TFPER_Msk (0x1UL << HRTIM_ADC1R_AD1TFPER_Pos) /*!< 0x01000000 */
#define HRTIM_ADC1R_AD1TFPER HRTIM_ADC1R_AD1TFPER_Msk /*!< ADC Trigger 1 on Timer F period */
#define HRTIM_ADC1R_AD1TDC3_Pos (25U)
#define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
#define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
#define HRTIM_ADC1R_AD1TDC4_Pos (26U)
#define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
#define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
#define HRTIM_ADC1R_AD1TDPER_Pos (27U)
#define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
#define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
#define HRTIM_ADC1R_AD1TFRST_Pos (28U)
#define HRTIM_ADC1R_AD1TFRST_Msk (0x1UL << HRTIM_ADC1R_AD1TFRST_Pos) /*!< 0x10000000 */
#define HRTIM_ADC1R_AD1TFRST HRTIM_ADC1R_AD1TFRST_Msk /*!< ADC Trigger 1 on Timer F reset */
#define HRTIM_ADC1R_AD1TEC3_Pos (29U)
#define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
#define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
#define HRTIM_ADC1R_AD1TEC4_Pos (30U)
#define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
#define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
#define HRTIM_ADC1R_AD1TEPER_Pos (31U)
#define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
#define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E compare period */
/******************* Bit definition for HRTIM_ADC2R register ****************/
#define HRTIM_ADC2R_AD2MC1_Pos (0U)
#define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
#define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
#define HRTIM_ADC2R_AD2MC2_Pos (1U)
#define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
#define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
#define HRTIM_ADC2R_AD2MC3_Pos (2U)
#define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
#define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
#define HRTIM_ADC2R_AD2MC4_Pos (3U)
#define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
#define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
#define HRTIM_ADC2R_AD2MPER_Pos (4U)
#define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
#define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
#define HRTIM_ADC2R_AD2EEV6_Pos (5U)
#define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
#define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
#define HRTIM_ADC2R_AD2EEV7_Pos (6U)
#define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
#define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
#define HRTIM_ADC2R_AD2EEV8_Pos (7U)
#define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
#define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
#define HRTIM_ADC2R_AD2EEV9_Pos (8U)
#define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
#define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
#define HRTIM_ADC2R_AD2EEV10_Pos (9U)
#define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
#define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
#define HRTIM_ADC2R_AD2TAC2_Pos (10U)
#define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
#define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
#define HRTIM_ADC2R_AD2TFC2_Pos (11U)
#define HRTIM_ADC2R_AD2TFC2_Msk (0x1UL << HRTIM_ADC2R_AD2TFC2_Pos) /*!< 0x00000800 */
#define HRTIM_ADC2R_AD2TFC2 HRTIM_ADC2R_AD2TFC2_Msk /*!< ADC Trigger 2 on Timer F compare 2 */
#define HRTIM_ADC2R_AD2TAC4_Pos (12U)
#define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
#define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
#define HRTIM_ADC2R_AD2TAPER_Pos (13U)
#define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
#define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
#define HRTIM_ADC2R_AD2TBC2_Pos (14U)
#define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
#define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
#define HRTIM_ADC2R_AD2TFC3_Pos (15U)
#define HRTIM_ADC2R_AD2TFC3_Msk (0x1UL << HRTIM_ADC2R_AD2TFC3_Pos) /*!< 0x00008000 */
#define HRTIM_ADC2R_AD2TFC3 HRTIM_ADC2R_AD2TFC3_Msk /*!< ADC Trigger 2 on Timer F compare 3 */
#define HRTIM_ADC2R_AD2TBC4_Pos (16U)
#define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
#define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
#define HRTIM_ADC2R_AD2TBPER_Pos (17U)
#define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
#define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
#define HRTIM_ADC2R_AD2TCC2_Pos (18U)
#define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
#define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
#define HRTIM_ADC2R_AD2TFC4_Pos (19U)
#define HRTIM_ADC2R_AD2TFC4_Msk (0x1UL << HRTIM_ADC2R_AD2TFC4_Pos) /*!< 0x00080000 */
#define HRTIM_ADC2R_AD2TFC4 HRTIM_ADC2R_AD2TFC4_Msk /*!< ADC Trigger 2 on Timer F compare 4 */
#define HRTIM_ADC2R_AD2TCC4_Pos (20U)
#define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
#define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
#define HRTIM_ADC2R_AD2TCPER_Pos (21U)
#define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
#define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
#define HRTIM_ADC2R_AD2TCRST_Pos (22U)
#define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
#define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
#define HRTIM_ADC2R_AD2TDC2_Pos (23U)
#define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
#define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
#define HRTIM_ADC2R_AD2TFPER_Pos (24U)
#define HRTIM_ADC2R_AD2TFPER_Msk (0x1UL << HRTIM_ADC2R_AD2TFPER_Pos) /*!< 0x01000000 */
#define HRTIM_ADC2R_AD2TFPER HRTIM_ADC2R_AD2TFPER_Msk /*!< ADC Trigger 2 on Timer F period */
#define HRTIM_ADC2R_AD2TDC4_Pos (25U)
#define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
#define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
#define HRTIM_ADC2R_AD2TDPER_Pos (26U)
#define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
#define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
#define HRTIM_ADC2R_AD2TDRST_Pos (27U)
#define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
#define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
#define HRTIM_ADC2R_AD2TEC2_Pos (28U)
#define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
#define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
#define HRTIM_ADC2R_AD2TEC3_Pos (29U)
#define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
#define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
#define HRTIM_ADC2R_AD2TEC4_Pos (30U)
#define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
#define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
#define HRTIM_ADC2R_AD2TERST_Pos (31U)
#define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
#define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
/******************* Bit definition for HRTIM_ADC3R register ****************/
#define HRTIM_ADC3R_AD3MC1_Pos (0U)
#define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
#define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
#define HRTIM_ADC3R_AD3MC2_Pos (1U)
#define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
#define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
#define HRTIM_ADC3R_AD3MC3_Pos (2U)
#define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
#define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
#define HRTIM_ADC3R_AD3MC4_Pos (3U)
#define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
#define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
#define HRTIM_ADC3R_AD3MPER_Pos (4U)
#define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
#define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
#define HRTIM_ADC3R_AD3EEV1_Pos (5U)
#define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
#define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
#define HRTIM_ADC3R_AD3EEV2_Pos (6U)
#define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
#define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
#define HRTIM_ADC3R_AD3EEV3_Pos (7U)
#define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
#define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
#define HRTIM_ADC3R_AD3EEV4_Pos (8U)
#define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
#define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
#define HRTIM_ADC3R_AD3EEV5_Pos (9U)
#define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
#define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
#define HRTIM_ADC3R_AD3TFC2_Pos (10U)
#define HRTIM_ADC3R_AD3TFC2_Msk (0x1UL << HRTIM_ADC3R_AD3TFC2_Pos) /*!< 0x00000400 */
#define HRTIM_ADC3R_AD3TFC2 HRTIM_ADC3R_AD3TFC2_Msk /*!< ADC Trigger 3 on Timer F compare 2 */
#define HRTIM_ADC3R_AD3TAC3_Pos (11U)
#define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
#define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
#define HRTIM_ADC3R_AD3TAC4_Pos (12U)
#define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
#define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
#define HRTIM_ADC3R_AD3TAPER_Pos (13U)
#define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
#define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
#define HRTIM_ADC3R_AD3TARST_Pos (14U)
#define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
#define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
#define HRTIM_ADC3R_AD3TFC3_Pos (15U)
#define HRTIM_ADC3R_AD3TFC3_Msk (0x1UL << HRTIM_ADC3R_AD3TFC3_Pos) /*!< 0x00008000 */
#define HRTIM_ADC3R_AD3TFC3 HRTIM_ADC3R_AD3TFC3_Msk /*!< ADC Trigger 3 on Timer F compare 3 */
#define HRTIM_ADC3R_AD3TBC3_Pos (16U)
#define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
#define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
#define HRTIM_ADC3R_AD3TBC4_Pos (17U)
#define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
#define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
#define HRTIM_ADC3R_AD3TBPER_Pos (18U)
#define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
#define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
#define HRTIM_ADC3R_AD3TBRST_Pos (19U)
#define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
#define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
#define HRTIM_ADC3R_AD3TFC4_Pos (20U)
#define HRTIM_ADC3R_AD3TFC4_Msk (0x1UL << HRTIM_ADC3R_AD3TFC4_Pos) /*!< 0x00100000 */
#define HRTIM_ADC3R_AD3TFC4 HRTIM_ADC3R_AD3TFC4_Msk /*!< ADC Trigger 3 on Timer F compare 4 */
#define HRTIM_ADC3R_AD3TCC3_Pos (21U)
#define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
#define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
#define HRTIM_ADC3R_AD3TCC4_Pos (22U)
#define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
#define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
#define HRTIM_ADC3R_AD3TCPER_Pos (23U)
#define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
#define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
#define HRTIM_ADC3R_AD3TFPER_Pos (24U)
#define HRTIM_ADC3R_AD3TFPER_Msk (0x1UL << HRTIM_ADC3R_AD3TFPER_Pos) /*!< 0x01000000 */
#define HRTIM_ADC3R_AD3TFPER HRTIM_ADC3R_AD3TFPER_Msk /*!< ADC Trigger 3 on Timer F period */
#define HRTIM_ADC3R_AD3TDC3_Pos (25U)
#define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
#define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
#define HRTIM_ADC3R_AD3TDC4_Pos (26U)
#define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
#define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
#define HRTIM_ADC3R_AD3TDPER_Pos (27U)
#define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
#define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
#define HRTIM_ADC3R_AD3TFRST_Pos (28U)
#define HRTIM_ADC3R_AD3TFRST_Msk (0x1UL << HRTIM_ADC3R_AD3TFRST_Pos) /*!< 0x10000000 */
#define HRTIM_ADC3R_AD3TFRST HRTIM_ADC3R_AD3TFRST_Msk /*!< ADC Trigger 3 on Timer F reset */
#define HRTIM_ADC3R_AD3TEC3_Pos (29U)
#define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
#define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
#define HRTIM_ADC3R_AD3TEC4_Pos (30U)
#define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
#define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
#define HRTIM_ADC3R_AD3TEPER_Pos (31U)
#define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
#define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
/******************* Bit definition for HRTIM_ADC4R register ****************/
#define HRTIM_ADC4R_AD4MC1_Pos (0U)
#define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
#define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
#define HRTIM_ADC4R_AD4MC2_Pos (1U)
#define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
#define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
#define HRTIM_ADC4R_AD4MC3_Pos (2U)
#define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
#define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
#define HRTIM_ADC4R_AD4MC4_Pos (3U)
#define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
#define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
#define HRTIM_ADC4R_AD4MPER_Pos (4U)
#define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
#define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
#define HRTIM_ADC4R_AD4EEV6_Pos (5U)
#define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
#define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
#define HRTIM_ADC4R_AD4EEV7_Pos (6U)
#define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
#define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
#define HRTIM_ADC4R_AD4EEV8_Pos (7U)
#define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
#define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
#define HRTIM_ADC4R_AD4EEV9_Pos (8U)
#define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
#define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
#define HRTIM_ADC4R_AD4EEV10_Pos (9U)
#define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
#define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
#define HRTIM_ADC4R_AD4TAC2_Pos (10U)
#define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
#define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
#define HRTIM_ADC4R_AD4TFC2_Pos (11U)
#define HRTIM_ADC4R_AD4TFC2_Msk (0x1UL << HRTIM_ADC4R_AD4TFC2_Pos) /*!< 0x00000800 */
#define HRTIM_ADC4R_AD4TFC2 HRTIM_ADC4R_AD4TFC2_Msk /*!< ADC Trigger 4 on Timer F compare 2 */
#define HRTIM_ADC4R_AD4TAC4_Pos (12U)
#define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
#define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
#define HRTIM_ADC4R_AD4TAPER_Pos (13U)
#define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
#define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
#define HRTIM_ADC4R_AD4TBC2_Pos (14U)
#define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
#define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
#define HRTIM_ADC4R_AD4TFC3_Pos (15U)
#define HRTIM_ADC4R_AD4TFC3_Msk (0x1UL << HRTIM_ADC4R_AD4TFC3_Pos) /*!< 0x00008000 */
#define HRTIM_ADC4R_AD4TFC3 HRTIM_ADC4R_AD4TFC3_Msk /*!< ADC Trigger 4 on Timer F compare 3 */
#define HRTIM_ADC4R_AD4TBC4_Pos (16U)
#define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
#define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
#define HRTIM_ADC4R_AD4TBPER_Pos (17U)
#define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
#define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
#define HRTIM_ADC4R_AD4TCC2_Pos (18U)
#define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
#define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
#define HRTIM_ADC4R_AD4TFC4_Pos (19U)
#define HRTIM_ADC4R_AD4TFC4_Msk (0x1UL << HRTIM_ADC4R_AD4TFC4_Pos) /*!< 0x00080000 */
#define HRTIM_ADC4R_AD4TFC4 HRTIM_ADC4R_AD4TFC4_Msk /*!< ADC Trigger 4 on Timer F compare 4 */
#define HRTIM_ADC4R_AD4TCC4_Pos (20U)
#define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
#define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
#define HRTIM_ADC4R_AD4TCPER_Pos (21U)
#define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
#define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
#define HRTIM_ADC4R_AD4TCRST_Pos (22U)
#define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
#define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
#define HRTIM_ADC4R_AD4TDC2_Pos (23U)
#define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
#define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
#define HRTIM_ADC4R_AD4TFPER_Pos (24U)
#define HRTIM_ADC4R_AD4TFPER_Msk (0x1UL << HRTIM_ADC4R_AD4TFPER_Pos) /*!< 0x01000000 */
#define HRTIM_ADC4R_AD4TFPER HRTIM_ADC4R_AD4TFPER_Msk /*!< ADC Trigger 4 on Timer F period */
#define HRTIM_ADC4R_AD4TDC4_Pos (25U)
#define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
#define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
#define HRTIM_ADC4R_AD4TDPER_Pos (26U)
#define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
#define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
#define HRTIM_ADC4R_AD4TDRST_Pos (27U)
#define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
#define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
#define HRTIM_ADC4R_AD4TEC2_Pos (28U)
#define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
#define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
#define HRTIM_ADC4R_AD4TEC3_Pos (29U)
#define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
#define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
#define HRTIM_ADC4R_AD4TEC4_Pos (30U)
#define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
#define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
#define HRTIM_ADC4R_AD4TERST_Pos (31U)
#define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
#define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
/******************* Bit definition for HRTIM_DLLCR register ****************/
#define HRTIM_DLLCR_CAL_Pos (0U)
#define HRTIM_DLLCR_CAL_Msk (0x1UL << HRTIM_DLLCR_CAL_Pos) /*!< 0x00000001 */
#define HRTIM_DLLCR_CAL HRTIM_DLLCR_CAL_Msk /*!< DLL calibration start */
#define HRTIM_DLLCR_CALEN_Pos (1U)
#define HRTIM_DLLCR_CALEN_Msk (0x1UL << HRTIM_DLLCR_CALEN_Pos) /*!< 0x00000002 */
#define HRTIM_DLLCR_CALEN HRTIM_DLLCR_CALEN_Msk /*!< DLL calibration enable */
#define HRTIM_DLLCR_CALRTE_Pos (2U)
#define HRTIM_DLLCR_CALRTE_Msk (0x3UL << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x0000000C */
#define HRTIM_DLLCR_CALRTE HRTIM_DLLCR_CALRTE_Msk /*!< DLL calibration rate */
#define HRTIM_DLLCR_CALRTE_0 (0x1UL << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x00000004 */
#define HRTIM_DLLCR_CALRTE_1 (0x2UL << HRTIM_DLLCR_CALRTE_Pos) /*!< 0x00000008 */
/******************* Bit definition for HRTIM_FLTINR1 register ***************/
#define HRTIM_FLTINR1_FLT1E_Pos (0U)
#define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
#define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
#define HRTIM_FLTINR1_FLT1P_Pos (1U)
#define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
#define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
#define HRTIM_FLTINR1_FLT1SRC_0_Pos (2U)
#define HRTIM_FLTINR1_FLT1SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_0_Pos) /*!< 0x00000004 */
#define HRTIM_FLTINR1_FLT1SRC_0 HRTIM_FLTINR1_FLT1SRC_0_Msk /*!< Fault 1 source bit 0 */
#define HRTIM_FLTINR1_FLT1F_Pos (3U)
#define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
#define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
#define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
#define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
#define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
#define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
#define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
#define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
#define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
#define HRTIM_FLTINR1_FLT2E_Pos (8U)
#define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
#define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
#define HRTIM_FLTINR1_FLT2P_Pos (9U)
#define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
#define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
#define HRTIM_FLTINR1_FLT2SRC_0_Pos (10U)
#define HRTIM_FLTINR1_FLT2SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_0_Pos) /*!< 0x00000400 */
#define HRTIM_FLTINR1_FLT2SRC_0 HRTIM_FLTINR1_FLT2SRC_0_Msk /*!< Fault 2 source bit 0 */
#define HRTIM_FLTINR1_FLT2F_Pos (11U)
#define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
#define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
#define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
#define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
#define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
#define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
#define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
#define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
#define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
#define HRTIM_FLTINR1_FLT3E_Pos (16U)
#define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
#define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
#define HRTIM_FLTINR1_FLT3P_Pos (17U)
#define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
#define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
#define HRTIM_FLTINR1_FLT3SRC_0_Pos (18U)
#define HRTIM_FLTINR1_FLT3SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_0_Pos) /*!< 0x00040000 */
#define HRTIM_FLTINR1_FLT3SRC_0 HRTIM_FLTINR1_FLT3SRC_0_Msk /*!< Fault 3 source bit 0 */
#define HRTIM_FLTINR1_FLT3F_Pos (19U)
#define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
#define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
#define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
#define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
#define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
#define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
#define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
#define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
#define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
#define HRTIM_FLTINR1_FLT4E_Pos (24U)
#define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
#define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
#define HRTIM_FLTINR1_FLT4P_Pos (25U)
#define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
#define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
#define HRTIM_FLTINR1_FLT4SRC_0_Pos (26U)
#define HRTIM_FLTINR1_FLT4SRC_0_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_0_Pos) /*!< 0x04000000 */
#define HRTIM_FLTINR1_FLT4SRC_0 HRTIM_FLTINR1_FLT4SRC_0_Msk /*!< Fault 4 source bit 0 */
#define HRTIM_FLTINR1_FLT4F_Pos (27U)
#define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
#define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
#define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
#define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
#define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
#define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
#define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
#define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
#define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
/******************* Bit definition for HRTIM_FLTINR2 register ***************/
#define HRTIM_FLTINR2_FLT5E_Pos (0U)
#define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
#define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
#define HRTIM_FLTINR2_FLT5P_Pos (1U)
#define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
#define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
#define HRTIM_FLTINR2_FLT5SRC_0_Pos (2U)
#define HRTIM_FLTINR2_FLT5SRC_0_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_0_Pos) /*!< 0x00000004 */
#define HRTIM_FLTINR2_FLT5SRC_0 HRTIM_FLTINR2_FLT5SRC_0_Msk /*!< Fault 5 source bit 0 */
#define HRTIM_FLTINR2_FLT5F_Pos (3U)
#define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
#define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
#define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
#define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
#define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
#define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
#define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
#define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
#define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
#define HRTIM_FLTINR2_FLT6E_Pos (8U)
#define HRTIM_FLTINR2_FLT6E_Msk (0x1UL << HRTIM_FLTINR2_FLT6E_Pos) /*!< 0x00000100 */
#define HRTIM_FLTINR2_FLT6E HRTIM_FLTINR2_FLT6E_Msk /*!< Fault 6 enable */
#define HRTIM_FLTINR2_FLT6P_Pos (9U)
#define HRTIM_FLTINR2_FLT6P_Msk (0x1UL << HRTIM_FLTINR2_FLT6P_Pos) /*!< 0x00000200 */
#define HRTIM_FLTINR2_FLT6P HRTIM_FLTINR2_FLT6P_Msk /*!< Fault 6 polarity */
#define HRTIM_FLTINR2_FLT6SRC_0_Pos (10U)
#define HRTIM_FLTINR2_FLT6SRC_0_Msk (0x1UL << HRTIM_FLTINR2_FLT6SRC_0_Pos) /*!< 0x00000400 */
#define HRTIM_FLTINR2_FLT6SRC_0 HRTIM_FLTINR2_FLT6SRC_0_Msk /*!< Fault 6 source bit 0 */
#define HRTIM_FLTINR2_FLT6F_Pos (11U)
#define HRTIM_FLTINR2_FLT6F_Msk (0xFUL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00007800 */
#define HRTIM_FLTINR2_FLT6F HRTIM_FLTINR2_FLT6F_Msk /*!< Fault 6 filter */
#define HRTIM_FLTINR2_FLT6F_0 (0x1UL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00000008 */
#define HRTIM_FLTINR2_FLT6F_1 (0x2UL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00000010 */
#define HRTIM_FLTINR2_FLT6F_2 (0x4UL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00000020 */
#define HRTIM_FLTINR2_FLT6F_3 (0x8UL << HRTIM_FLTINR2_FLT6F_Pos) /*!< 0x00000040 */
#define HRTIM_FLTINR2_FLT6LCK_Pos (15U)
#define HRTIM_FLTINR2_FLT6LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT6LCK_Pos) /*!< 0x00008000 */
#define HRTIM_FLTINR2_FLT6LCK HRTIM_FLTINR2_FLT6LCK_Msk /*!< Fault 6 lock */
#define HRTIM_FLTINR2_FLT1SRC_1_Pos (16U)
#define HRTIM_FLTINR2_FLT1SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT1SRC_1_Pos) /*!< 0x00010000 */
#define HRTIM_FLTINR2_FLT1SRC_1 HRTIM_FLTINR2_FLT1SRC_1_Msk /*!< Fault 1 source bit 1 */
#define HRTIM_FLTINR2_FLT2SRC_1_Pos (17U)
#define HRTIM_FLTINR2_FLT2SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT2SRC_1_Pos) /*!< 0x00020000 */
#define HRTIM_FLTINR2_FLT2SRC_1 HRTIM_FLTINR2_FLT2SRC_1_Msk /*!< Fault 2 source bit1 */
#define HRTIM_FLTINR2_FLT3SRC_1_Pos (18U)
#define HRTIM_FLTINR2_FLT3SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT3SRC_1_Pos) /*!< 0x00040000 */
#define HRTIM_FLTINR2_FLT3SRC_1 HRTIM_FLTINR2_FLT3SRC_1_Msk /*!< Fault 3 source bit 1 */
#define HRTIM_FLTINR2_FLT4SRC_1_Pos (19U)
#define HRTIM_FLTINR2_FLT4SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT4SRC_1_Pos) /*!< 0x00080000 */
#define HRTIM_FLTINR2_FLT4SRC_1 HRTIM_FLTINR2_FLT4SRC_1_Msk /*!< Fault 4 source bit 1 */
#define HRTIM_FLTINR2_FLT5SRC_1_Pos (20U)
#define HRTIM_FLTINR2_FLT5SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_1_Pos) /*!< 0x00100000 */
#define HRTIM_FLTINR2_FLT5SRC_1 HRTIM_FLTINR2_FLT5SRC_1_Msk /*!< Fault 5 source bit 1 */
#define HRTIM_FLTINR2_FLT6SRC_1_Pos (21U)
#define HRTIM_FLTINR2_FLT6SRC_1_Msk (0x1UL << HRTIM_FLTINR2_FLT6SRC_1_Pos) /*!< 0x00200000 */
#define HRTIM_FLTINR2_FLT6SRC_1 HRTIM_FLTINR2_FLT6SRC_1_Msk /*!< Fault 6 source bit 1 */
#define HRTIM_FLTINR2_FLTSD_Pos (24U)
#define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
#define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
#define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
#define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
/******************* Bit definition for HRTIM_FLTINR3 register ***************/
#define HRTIM_FLTINR3_FLT1BLKE_Pos (0U)
#define HRTIM_FLTINR3_FLT1BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT1BLKE_Pos) /*!< 0x00000001 */
#define HRTIM_FLTINR3_FLT1BLKE HRTIM_FLTINR3_FLT1BLKE_Msk /*!< Fault 1 Blanking Enable */
#define HRTIM_FLTINR3_FLT1BLKS_Pos (1U)
#define HRTIM_FLTINR3_FLT1BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT1BLKS_Pos) /*!< 0x00000002 */
#define HRTIM_FLTINR3_FLT1BLKS HRTIM_FLTINR3_FLT1BLKS_Msk /*!< Fault 1 Blanking Source */
#define HRTIM_FLTINR3_FLT1CNT_Pos (2U)
#define HRTIM_FLTINR3_FLT1CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x0000003C */
#define HRTIM_FLTINR3_FLT1CNT HRTIM_FLTINR3_FLT1CNT_Msk /*!< Fault 1 Counter */
#define HRTIM_FLTINR3_FLT1CNT_0 (0x1UL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x00000004 */
#define HRTIM_FLTINR3_FLT1CNT_1 (0x2UL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x00000008 */
#define HRTIM_FLTINR3_FLT1CNT_2 (0x4UL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x00000010 */
#define HRTIM_FLTINR3_FLT1CNT_3 (0x8UL << HRTIM_FLTINR3_FLT1CNT_Pos) /*!< 0x00000020 */
#define HRTIM_FLTINR3_FLT1CRES_Pos (6U)
#define HRTIM_FLTINR3_FLT1CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT1CRES_Pos) /*!< 0x00000040 */
#define HRTIM_FLTINR3_FLT1CRES HRTIM_FLTINR3_FLT1CRES_Msk /*!< Fault 1 Counter Reset */
#define HRTIM_FLTINR3_FLT1RSTM_Pos (7U)
#define HRTIM_FLTINR3_FLT1RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT1RSTM_Pos) /*!< 0x00000080 */
#define HRTIM_FLTINR3_FLT1RSTM HRTIM_FLTINR3_FLT1RSTM_Msk /*!< Fault 1 Counter Reset Mode */
#define HRTIM_FLTINR3_FLT2BLKE_Pos (8U)
#define HRTIM_FLTINR3_FLT2BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT2BLKE_Pos) /*!< 0x00000100 */
#define HRTIM_FLTINR3_FLT2BLKE HRTIM_FLTINR3_FLT2BLKE_Msk /*!< Fault 2 Blanking Enable */
#define HRTIM_FLTINR3_FLT2BLKS_Pos (9U)
#define HRTIM_FLTINR3_FLT2BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT2BLKS_Pos) /*!< 0x00000200 */
#define HRTIM_FLTINR3_FLT2BLKS HRTIM_FLTINR3_FLT2BLKS_Msk /*!< Fault 2 Blanking Source */
#define HRTIM_FLTINR3_FLT2CNT_Pos (10U)
#define HRTIM_FLTINR3_FLT2CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00003C00 */
#define HRTIM_FLTINR3_FLT2CNT HRTIM_FLTINR3_FLT2CNT_Msk /*!< Fault 2 Counter */
#define HRTIM_FLTINR3_FLT2CNT_0 (0x1UL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00000400 */
#define HRTIM_FLTINR3_FLT2CNT_1 (0x2UL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00000800 */
#define HRTIM_FLTINR3_FLT2CNT_2 (0x4UL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00001000 */
#define HRTIM_FLTINR3_FLT2CNT_3 (0x8UL << HRTIM_FLTINR3_FLT2CNT_Pos) /*!< 0x00002000 */
#define HRTIM_FLTINR3_FLT2CRES_Pos (14U)
#define HRTIM_FLTINR3_FLT2CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT2CRES_Pos) /*!< 0x00004000 */
#define HRTIM_FLTINR3_FLT2CRES HRTIM_FLTINR3_FLT2CRES_Msk /*!< Fault 2 Counter Reset */
#define HRTIM_FLTINR3_FLT2RSTM_Pos (15U)
#define HRTIM_FLTINR3_FLT2RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT2RSTM_Pos) /*!< 0x00008000 */
#define HRTIM_FLTINR3_FLT2RSTM HRTIM_FLTINR3_FLT2RSTM_Msk /*!< Fault 2 Counter Reset Mode */
#define HRTIM_FLTINR3_FLT3BLKE_Pos (16U)
#define HRTIM_FLTINR3_FLT3BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT3BLKE_Pos) /*!< 0x00010000 */
#define HRTIM_FLTINR3_FLT3BLKE HRTIM_FLTINR3_FLT3BLKE_Msk /*!< Fault 3 Blanking Enable */
#define HRTIM_FLTINR3_FLT3BLKS_Pos (17U)
#define HRTIM_FLTINR3_FLT3BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT3BLKS_Pos) /*!< 0x00020000 */
#define HRTIM_FLTINR3_FLT3BLKS HRTIM_FLTINR3_FLT3BLKS_Msk /*!< Fault 3 Blanking Source */
#define HRTIM_FLTINR3_FLT3CNT_Pos (18U)
#define HRTIM_FLTINR3_FLT3CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x003C0000 */
#define HRTIM_FLTINR3_FLT3CNT HRTIM_FLTINR3_FLT3CNT_Msk /*!< Fault 3 Counter */
#define HRTIM_FLTINR3_FLT3CNT_0 (0x1UL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x00040000 */
#define HRTIM_FLTINR3_FLT3CNT_1 (0x2UL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x00080000 */
#define HRTIM_FLTINR3_FLT3CNT_2 (0x4UL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x00100000 */
#define HRTIM_FLTINR3_FLT3CNT_3 (0x8UL << HRTIM_FLTINR3_FLT3CNT_Pos) /*!< 0x00200000 */
#define HRTIM_FLTINR3_FLT3CRES_Pos (22U)
#define HRTIM_FLTINR3_FLT3CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT3CRES_Pos) /*!< 0x00400000 */
#define HRTIM_FLTINR3_FLT3CRES HRTIM_FLTINR3_FLT3CRES_Msk /*!< Fault 3 Counter Reset */
#define HRTIM_FLTINR3_FLT3RSTM_Pos (23U)
#define HRTIM_FLTINR3_FLT3RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT3RSTM_Pos) /*!< 0x00800000 */
#define HRTIM_FLTINR3_FLT3RSTM HRTIM_FLTINR3_FLT3RSTM_Msk /*!< Fault 3 Counter Reset Mode */
#define HRTIM_FLTINR3_FLT4BLKE_Pos (24U)
#define HRTIM_FLTINR3_FLT4BLKE_Msk (0x1UL << HRTIM_FLTINR3_FLT4BLKE_Pos) /*!< 0x01000000 */
#define HRTIM_FLTINR3_FLT4BLKE HRTIM_FLTINR3_FLT4BLKE_Msk /*!< Fault 4 Blanking Enable */
#define HRTIM_FLTINR3_FLT4BLKS_Pos (25U)
#define HRTIM_FLTINR3_FLT4BLKS_Msk (0x1UL << HRTIM_FLTINR3_FLT4BLKS_Pos) /*!< 0x02000000 */
#define HRTIM_FLTINR3_FLT4BLKS HRTIM_FLTINR3_FLT4BLKS_Msk /*!< Fault 4 Blanking Source */
#define HRTIM_FLTINR3_FLT4CNT_Pos (26U)
#define HRTIM_FLTINR3_FLT4CNT_Msk (0xFUL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x003C0000 */
#define HRTIM_FLTINR3_FLT4CNT HRTIM_FLTINR3_FLT4CNT_Msk /*!< Fault 4 Counter */
#define HRTIM_FLTINR3_FLT4CNT_0 (0x1UL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x00040000 */
#define HRTIM_FLTINR3_FLT4CNT_1 (0x2UL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x00080000 */
#define HRTIM_FLTINR3_FLT4CNT_2 (0x4UL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x00100000 */
#define HRTIM_FLTINR3_FLT4CNT_3 (0x8UL << HRTIM_FLTINR3_FLT4CNT_Pos) /*!< 0x00200000 */
#define HRTIM_FLTINR3_FLT4CRES_Pos (30U)
#define HRTIM_FLTINR3_FLT4CRES_Msk (0x1UL << HRTIM_FLTINR3_FLT4CRES_Pos) /*!< 0x40000000 */
#define HRTIM_FLTINR3_FLT4CRES HRTIM_FLTINR3_FLT4CRES_Msk /*!< Fault 4 Counter Reset */
#define HRTIM_FLTINR3_FLT4RSTM_Pos (31U)
#define HRTIM_FLTINR3_FLT4RSTM_Msk (0x1UL << HRTIM_FLTINR3_FLT4RSTM_Pos) /*!< 0x80000000 */
#define HRTIM_FLTINR3_FLT4RSTM HRTIM_FLTINR3_FLT4RSTM_Msk /*!< Fault 4 Counter Reset Mode */
/******************* Bit definition for HRTIM_FLTINR4 register ***************/
#define HRTIM_FLTINR4_FLT5BLKE_Pos (0U)
#define HRTIM_FLTINR4_FLT5BLKE_Msk (0x1UL << HRTIM_FLTINR4_FLT5BLKE_Pos) /*!< 0x00000001 */
#define HRTIM_FLTINR4_FLT5BLKE HRTIM_FLTINR4_FLT5BLKE_Msk /*!< Fault 5 Blanking Enable */
#define HRTIM_FLTINR4_FLT5BLKS_Pos (1U)
#define HRTIM_FLTINR4_FLT5BLKS_Msk (0x1UL << HRTIM_FLTINR4_FLT5BLKS_Pos) /*!< 0x00000002 */
#define HRTIM_FLTINR4_FLT5BLKS HRTIM_FLTINR4_FLT5BLKS_Msk /*!< Fault 5 Blanking Source */
#define HRTIM_FLTINR4_FLT5CNT_Pos (2U)
#define HRTIM_FLTINR4_FLT5CNT_Msk (0xFUL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x0000003C */
#define HRTIM_FLTINR4_FLT5CNT HRTIM_FLTINR4_FLT5CNT_Msk /*!< Fault 5 Counter */
#define HRTIM_FLTINR4_FLT5CNT_0 (0x1UL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x00000004 */
#define HRTIM_FLTINR4_FLT5CNT_1 (0x2UL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x00000008 */
#define HRTIM_FLTINR4_FLT5CNT_2 (0x4UL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x00000010 */
#define HRTIM_FLTINR4_FLT5CNT_3 (0x8UL << HRTIM_FLTINR4_FLT5CNT_Pos) /*!< 0x00000020 */
#define HRTIM_FLTINR4_FLT5CRES_Pos (6U)
#define HRTIM_FLTINR4_FLT5CRES_Msk (0x1UL << HRTIM_FLTINR4_FLT5CRES_Pos) /*!< 0x00000040 */
#define HRTIM_FLTINR4_FLT5CRES HRTIM_FLTINR4_FLT5CRES_Msk /*!< Fault 5 Counter Reset */
#define HRTIM_FLTINR4_FLT5RSTM_Pos (7U)
#define HRTIM_FLTINR4_FLT5RSTM_Msk (0x1UL << HRTIM_FLTINR4_FLT5RSTM_Pos) /*!< 0x00000080 */
#define HRTIM_FLTINR4_FLT5RSTM HRTIM_FLTINR4_FLT5RSTM_Msk /*!< Fault 5 Counter Reset Mode */
#define HRTIM_FLTINR4_FLT6BLKE_Pos (8U)
#define HRTIM_FLTINR4_FLT6BLKE_Msk (0x1UL << HRTIM_FLTINR4_FLT6BLKE_Pos) /*!< 0x00000100 */
#define HRTIM_FLTINR4_FLT6BLKE HRTIM_FLTINR4_FLT6BLKE_Msk /*!< Fault 6 Blanking Enable */
#define HRTIM_FLTINR4_FLT6BLKS_Pos (9U)
#define HRTIM_FLTINR4_FLT6BLKS_Msk (0x1UL << HRTIM_FLTINR4_FLT6BLKS_Pos) /*!< 0x00000200 */
#define HRTIM_FLTINR4_FLT6BLKS HRTIM_FLTINR4_FLT6BLKS_Msk /*!< Fault 6 Blanking Source */
#define HRTIM_FLTINR4_FLT6CNT_Pos (10U)
#define HRTIM_FLTINR4_FLT6CNT_Msk (0xFUL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00003C00 */
#define HRTIM_FLTINR4_FLT6CNT HRTIM_FLTINR4_FLT6CNT_Msk /*!< Fault 6 Counter */
#define HRTIM_FLTINR4_FLT6CNT_0 (0x1UL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00000400 */
#define HRTIM_FLTINR4_FLT6CNT_1 (0x2UL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00000800 */
#define HRTIM_FLTINR4_FLT6CNT_2 (0x4UL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00001000 */
#define HRTIM_FLTINR4_FLT6CNT_3 (0x8UL << HRTIM_FLTINR4_FLT6CNT_Pos) /*!< 0x00002000 */
#define HRTIM_FLTINR4_FLT6CRES_Pos (14U)
#define HRTIM_FLTINR4_FLT6CRES_Msk (0x1UL << HRTIM_FLTINR4_FLT6CRES_Pos) /*!< 0x00004000 */
#define HRTIM_FLTINR4_FLT6CRES HRTIM_FLTINR4_FLT6CRES_Msk /*!< Fault 6 Counter Reset */
#define HRTIM_FLTINR4_FLT6RSTM_Pos (15U)
#define HRTIM_FLTINR4_FLT6RSTM_Msk (0x1UL << HRTIM_FLTINR4_FLT6RSTM_Pos) /*!< 0x00008000 */
#define HRTIM_FLTINR4_FLT6RSTM HRTIM_FLTINR4_FLT6RSTM_Msk /*!< Fault 6 Counter Reset Mode */
/******************* Bit definition for HRTIM_BDMUPR register ***************/
#define HRTIM_BDMUPR_MCR_Pos (0U)
#define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
#define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
#define HRTIM_BDMUPR_MICR_Pos (1U)
#define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
#define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
#define HRTIM_BDMUPR_MDIER_Pos (2U)
#define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
#define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
#define HRTIM_BDMUPR_MCNT_Pos (3U)
#define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
#define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
#define HRTIM_BDMUPR_MPER_Pos (4U)
#define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
#define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
#define HRTIM_BDMUPR_MREP_Pos (5U)
#define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
#define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
#define HRTIM_BDMUPR_MCMP1_Pos (6U)
#define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
#define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
#define HRTIM_BDMUPR_MCMP2_Pos (7U)
#define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
#define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
#define HRTIM_BDMUPR_MCMP3_Pos (8U)
#define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
#define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
#define HRTIM_BDMUPR_MCMP4_Pos (9U)
#define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
#define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
/******************* Bit definition for HRTIM_BDTUPR register ***************/
#define HRTIM_BDTUPR_TIMCR_Pos (0U)
#define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
#define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
#define HRTIM_BDTUPR_TIMICR_Pos (1U)
#define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
#define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
#define HRTIM_BDTUPR_TIMDIER_Pos (2U)
#define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
#define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
#define HRTIM_BDTUPR_TIMCNT_Pos (3U)
#define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
#define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
#define HRTIM_BDTUPR_TIMPER_Pos (4U)
#define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
#define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
#define HRTIM_BDTUPR_TIMREP_Pos (5U)
#define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
#define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
#define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
#define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
#define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
#define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
#define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
#define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
#define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
#define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
#define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
#define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
#define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
#define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
#define HRTIM_BDTUPR_TIMDTR_Pos (10U)
#define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
#define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
#define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
#define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
#define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
#define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
#define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
#define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
#define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
#define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
#define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
#define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
#define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
#define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
#define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
#define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
#define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
#define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
#define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
#define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
#define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
#define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
#define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
#define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
#define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
#define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
#define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
#define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
#define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
#define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
#define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
#define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
#define HRTIM_BDTUPR_TIMCR2_Pos (21U)
#define HRTIM_BDTUPR_TIMCR2_Msk (0x1UL << HRTIM_BDTUPR_TIMCR2_Pos) /*!< 0x00200000 */
#define HRTIM_BDTUPR_TIMCR2 HRTIM_BDTUPR_TIMCR2_Msk /*!< TIMCR2 register update enable */
#define HRTIM_BDTUPR_TIMEEFR3_Pos (22U)
#define HRTIM_BDTUPR_TIMEEFR3_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR3_Pos) /*!< 0x00400000 */
#define HRTIM_BDTUPR_TIMEEFR3 HRTIM_BDTUPR_TIMEEFR3_Msk /*!< TIMEEFR3 register update enable */
/******************* Bit definition for HRTIM_BDMADR register ***************/
#define HRTIM_BDMADR_BDMADR_Pos (0U)
#define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)/*!< 0xFFFFFFFF */
#define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
/******************* Bit definition for HRTIM_ADC Extended Trigger register ***************/
#define HRTIM_ADCER_AD5TRG_Pos (0U)
#define HRTIM_ADCER_AD5TRG_Msk (0x1FUL << HRTIM_ADCER_AD5TRG_Pos) /*!< 0x0000001F */
#define HRTIM_ADCER_AD5TRG HRTIM_ADCER_AD5TRG_Msk /*!< ADC5 trigger */
#define HRTIM_ADCER_AD6TRG_Pos (5U)
#define HRTIM_ADCER_AD6TRG_Msk (0x1FUL << HRTIM_ADCER_AD6TRG_Pos) /*!< 0x000003E0 */
#define HRTIM_ADCER_AD6TRG HRTIM_ADCER_AD6TRG_Msk /*!< ADC6 trigger */
#define HRTIM_ADCER_AD7TRG_Pos (10U)
#define HRTIM_ADCER_AD7TRG_Msk (0x1FUL << HRTIM_ADCER_AD7TRG_Pos) /*!< 0x00007C00 */
#define HRTIM_ADCER_AD7TRG HRTIM_ADCER_AD7TRG_Msk /*!< ADC7 trigger */
#define HRTIM_ADCER_AD8TRG_Pos (16U)
#define HRTIM_ADCER_AD8TRG_Msk (0x1FUL << HRTIM_ADCER_AD8TRG_Pos) /*!< 0x001F0000 */
#define HRTIM_ADCER_AD8TRG HRTIM_ADCER_AD8TRG_Msk /*!< ADC8 trigger */
#define HRTIM_ADCER_AD9TRG_Pos (21U)
#define HRTIM_ADCER_AD9TRG_Msk (0x1FUL << HRTIM_ADCER_AD9TRG_Pos) /*!< 0x003E00000 */
#define HRTIM_ADCER_AD9TRG HRTIM_ADCER_AD9TRG_Msk /*!< ADC9 trigger */
#define HRTIM_ADCER_AD10TRG_Pos (26U)
#define HRTIM_ADCER_AD10TRG_Msk (0x1FUL << HRTIM_ADCER_AD10TRG_Pos) /*!< 0x7C000000 */
#define HRTIM_ADCER_AD10TRG HRTIM_ADCER_AD10TRG_Msk /*!< ADC10 trigger */
/******************* Bit definition for HRTIM_ADC Trigger Update register ***************/
#define HRTIM_ADCUR_AD5USRC_Pos (0U)
#define HRTIM_ADCUR_AD5USRC_Msk (0x7UL << HRTIM_ADCUR_AD5USRC_Pos) /*!< 0x00000007 */
#define HRTIM_ADCUR_AD5USRC HRTIM_ADCUR_AD5USRC_Msk /*!< ADC5 trigger Update Source */
#define HRTIM_ADCUR_AD6USRC_Pos (4U)
#define HRTIM_ADCUR_AD6USRC_Msk (0x7UL << HRTIM_ADCUR_AD6USRC_Pos) /*!< 0x00000070 */
#define HRTIM_ADCUR_AD6USRC HRTIM_ADCUR_AD6USRC_Msk /*!< ADC6 trigger Update Source */
#define HRTIM_ADCUR_AD7USRC_Pos (8U)
#define HRTIM_ADCUR_AD7USRC_Msk (0x7UL << HRTIM_ADCUR_AD7USRC_Pos) /*!< 0x00000700 */
#define HRTIM_ADCUR_AD7USRC HRTIM_ADCUR_AD7USRC_Msk /*!< ADC7 trigger Update Source */
#define HRTIM_ADCUR_AD8USRC_Pos (12U)
#define HRTIM_ADCUR_AD8USRC_Msk (0x7UL << HRTIM_ADCUR_AD8USRC_Pos) /*!< 0x00007000 */
#define HRTIM_ADCUR_AD8USRC HRTIM_ADCUR_AD8USRC_Msk /*!< ADC8 trigger Update Source */
#define HRTIM_ADCUR_AD9USRC_Pos (16U)
#define HRTIM_ADCUR_AD9USRC_Msk (0x7UL << HRTIM_ADCUR_AD9USRC_Pos) /*!< 0x000070000 */
#define HRTIM_ADCUR_AD9USRC HRTIM_ADCUR_AD9USRC_Msk /*!< ADC9 trigger Update Source */
#define HRTIM_ADCUR_AD10USRC_Pos (20U)
#define HRTIM_ADCUR_AD10USRC_Msk (0x7UL << HRTIM_ADCUR_AD10USRC_Pos) /*!< 0x00700000 */
#define HRTIM_ADCUR_AD10USRC HRTIM_ADCUR_AD10USRC_Msk /*!< ADC10 trigger Update Source */
/******************* Bit definition for HRTIM_ADCPS1 ADC Post Scaler register 1 ***************/
#define HRTIM_ADCPS1_AD1PSC_Pos (0U)
#define HRTIM_ADCPS1_AD1PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD1PSC_Pos) /*!< 0x0000001F */
#define HRTIM_ADCPS1_AD1PSC HRTIM_ADCPS1_AD1PSC_Msk /*!< ADC1 post scaler */
#define HRTIM_ADCPS1_AD2PSC_Pos (6U)
#define HRTIM_ADCPS1_AD2PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD2PSC_Pos) /*!< 0x000007C0 */
#define HRTIM_ADCPS1_AD2PSC HRTIM_ADCPS1_AD2PSC_Msk /*!< ADC2 post scaler */
#define HRTIM_ADCPS1_AD3PSC_Pos (12U)
#define HRTIM_ADCPS1_AD3PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD3PSC_Pos) /*!< 0x0001F000 */
#define HRTIM_ADCPS1_AD3PSC HRTIM_ADCPS1_AD3PSC_Msk /*!< ADC3 post scaler */
#define HRTIM_ADCPS1_AD4PSC_Pos (18U)
#define HRTIM_ADCPS1_AD4PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD4PSC_Pos) /*!< 0x007C0000 */
#define HRTIM_ADCPS1_AD4PSC HRTIM_ADCPS1_AD4PSC_Msk /*!< ADC4 post scaler */
#define HRTIM_ADCPS1_AD5PSC_Pos (24U)
#define HRTIM_ADCPS1_AD5PSC_Msk (0x1FUL << HRTIM_ADCPS1_AD5PSC_Pos) /*!< 0x1F000000 */
#define HRTIM_ADCPS1_AD5PSC HRTIM_ADCPS1_AD5PSC_Msk /*!< ADC5 post scaler */
/******************* Bit definition for HRTIM_ADCPS2 ADC Post Scaler register 2 ***************/
#define HRTIM_ADCPS2_AD6PSC_Pos (0U)
#define HRTIM_ADCPS2_AD6PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD6PSC_Pos) /*!< 0x0000001F */
#define HRTIM_ADCPS2_AD6PSC HRTIM_ADCPS2_AD6PSC_Msk /*!< ADC6 post scaler */
#define HRTIM_ADCPS2_AD7PSC_Pos (6U)
#define HRTIM_ADCPS2_AD7PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD7PSC_Pos) /*!< 0x000007C0 */
#define HRTIM_ADCPS2_AD7PSC HRTIM_ADCPS2_AD7PSC_Msk /*!< ADC7 post scaler */
#define HRTIM_ADCPS2_AD8PSC_Pos (12U)
#define HRTIM_ADCPS2_AD8PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD8PSC_Pos) /*!< 0x0001F000 */
#define HRTIM_ADCPS2_AD8PSC HRTIM_ADCPS2_AD8PSC_Msk /*!< ADC8 post scaler */
#define HRTIM_ADCPS2_AD9PSC_Pos (18U)
#define HRTIM_ADCPS2_AD9PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD9PSC_Pos) /*!< 0x007C0000 */
#define HRTIM_ADCPS2_AD9PSC HRTIM_ADCPS2_AD9PSC_Msk /*!< ADC9 post scaler */
#define HRTIM_ADCPS2_AD10PSC_Pos (24U)
#define HRTIM_ADCPS2_AD10PSC_Msk (0x1FUL << HRTIM_ADCPS2_AD10PSC_Pos) /*!< 0x1F000000 */
#define HRTIM_ADCPS2_AD10PSC HRTIM_ADCPS2_AD10PSC_Msk /*!< ADC10 post scaler */
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_USERTRIM_Pos (4U)
#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
#define OPAMP_CSR_OPAMPINTEN_Pos (8U)
#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
#define OPAMP_CSR_OUTCAL_Pos (30U)
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
#define OPAMP_CSR_LOCK_Pos (31U)
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
/********************* Bit definition for OPAMPx_TCMR register ***************/
#define OPAMP_TCMR_VMSSEL_Pos (0U)
#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
#define OPAMP_TCMR_VPSSEL_Pos (1U)
#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
#define OPAMP_TCMR_T1CMEN_Pos (3U)
#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
#define OPAMP_TCMR_T8CMEN_Pos (4U)
#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
#define OPAMP_TCMR_T20CMEN_Pos (5U)
#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
#define OPAMP_TCMR_LOCK_Pos (31U)
#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_LPR_Pos (14U)
#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
#define PWR_CR1_VOS_Pos (9U)
#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_LPMS_Pos (0U)
#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
#define PWR_CR1_LPMS_STOP1_Pos (0U)
#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
#define PWR_CR1_LPMS_STANDBY_Pos (0U)
#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
/******************** Bit definition for PWR_CR2 register ********************/
/*!< PVME Peripheral Voltage Monitor Enable */
#define PWR_CR2_PVME_Pos (4U)
#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
#define PWR_CR2_PVME4_Pos (7U)
#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
#define PWR_CR2_PVME3_Pos (6U)
#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
#define PWR_CR2_PVME2_Pos (5U)
#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
#define PWR_CR2_PVME1_Pos (4U)
#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
/*!< PVD level configuration */
#define PWR_CR2_PLS_Pos (1U)
#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
#define PWR_CR2_PLS_LEV1_Pos (1U)
#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR2_PLS_LEV2_Pos (2U)
#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR2_PLS_LEV3_Pos (1U)
#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR2_PLS_LEV4_Pos (3U)
#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR2_PLS_LEV5_Pos (1U)
#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR2_PLS_LEV6_Pos (2U)
#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR2_PLS_LEV7_Pos (1U)
#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
#define PWR_CR2_PVDE_Pos (0U)
#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EIWF_Pos (15U)
#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
#define PWR_CR3_UCPD_DBDIS_Pos (14U)
#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
#define PWR_CR3_UCPD_STDBY_Pos (13U)
#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
#define PWR_CR3_APC_Pos (10U)
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
#define PWR_CR3_RRS_Pos (8U)
#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
#define PWR_CR3_EWUP5_Pos (4U)
#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
#define PWR_CR3_EWUP4_Pos (3U)
#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
#define PWR_CR3_EWUP3_Pos (2U)
#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
#define PWR_CR3_EWUP2_Pos (1U)
#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
#define PWR_CR3_EWUP1_Pos (0U)
#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
#define PWR_CR3_EWUP_Pos (0U)
#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
/******************** Bit definition for PWR_CR4 register ********************/
#define PWR_CR4_VBRS_Pos (9U)
#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
#define PWR_CR4_VBE_Pos (8U)
#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
#define PWR_CR4_WP5_Pos (4U)
#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
#define PWR_CR4_WP4_Pos (3U)
#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
#define PWR_CR4_WP3_Pos (2U)
#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
#define PWR_CR4_WP2_Pos (1U)
#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
#define PWR_CR4_WP1_Pos (0U)
#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
/******************** Bit definition for PWR_SR1 register ********************/
#define PWR_SR1_WUFI_Pos (15U)
#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
#define PWR_SR1_SBF_Pos (8U)
#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
#define PWR_SR1_WUF_Pos (0U)
#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
#define PWR_SR1_WUF5_Pos (4U)
#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
#define PWR_SR1_WUF4_Pos (3U)
#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
#define PWR_SR1_WUF3_Pos (2U)
#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
#define PWR_SR1_WUF2_Pos (1U)
#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
#define PWR_SR1_WUF1_Pos (0U)
#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
/******************** Bit definition for PWR_SR2 register ********************/
#define PWR_SR2_PVMO4_Pos (15U)
#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
#define PWR_SR2_PVMO3_Pos (14U)
#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
#define PWR_SR2_PVMO2_Pos (13U)
#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
#define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
#define PWR_SR2_VOSF_Pos (10U)
#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
#define PWR_SR2_REGLPF_Pos (9U)
#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
#define PWR_SR2_REGLPS_Pos (8U)
#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CSBF_Pos (8U)
#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
#define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
#define PWR_SCR_CWUF5_Pos (4U)
#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
#define PWR_SCR_CWUF4_Pos (3U)
#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
#define PWR_SCR_CWUF3_Pos (2U)
#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
#define PWR_SCR_CWUF2_Pos (1U)
#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
#define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
/******************** Bit definition for PWR_PUCRA register ********************/
#define PWR_PUCRA_PA15_Pos (15U)
#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
#define PWR_PUCRA_PA13_Pos (13U)
#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
#define PWR_PUCRA_PA12_Pos (12U)
#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
#define PWR_PUCRA_PA11_Pos (11U)
#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
#define PWR_PUCRA_PA10_Pos (10U)
#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
#define PWR_PUCRA_PA9_Pos (9U)
#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
#define PWR_PUCRA_PA8_Pos (8U)
#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
#define PWR_PUCRA_PA7_Pos (7U)
#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
#define PWR_PUCRA_PA6_Pos (6U)
#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
#define PWR_PUCRA_PA5_Pos (5U)
#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
#define PWR_PUCRA_PA4_Pos (4U)
#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
#define PWR_PUCRA_PA3_Pos (3U)
#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
#define PWR_PUCRA_PA2_Pos (2U)
#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
#define PWR_PUCRA_PA1_Pos (1U)
#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
#define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
/******************** Bit definition for PWR_PDCRA register ********************/
#define PWR_PDCRA_PA14_Pos (14U)
#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
#define PWR_PDCRA_PA12_Pos (12U)
#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
#define PWR_PDCRA_PA11_Pos (11U)
#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
#define PWR_PDCRA_PA10_Pos (10U)
#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
#define PWR_PDCRA_PA9_Pos (9U)
#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
#define PWR_PDCRA_PA8_Pos (8U)
#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
#define PWR_PDCRA_PA7_Pos (7U)
#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
#define PWR_PDCRA_PA6_Pos (6U)
#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
#define PWR_PDCRA_PA5_Pos (5U)
#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
#define PWR_PDCRA_PA4_Pos (4U)
#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
#define PWR_PDCRA_PA3_Pos (3U)
#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
#define PWR_PDCRA_PA2_Pos (2U)
#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
#define PWR_PDCRA_PA1_Pos (1U)
#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
#define PWR_PDCRA_PA0_Pos (0U)
#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
/******************** Bit definition for PWR_PUCRB register ********************/
#define PWR_PUCRB_PB15_Pos (15U)
#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
#define PWR_PUCRB_PB14_Pos (14U)
#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
#define PWR_PUCRB_PB13_Pos (13U)
#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
#define PWR_PUCRB_PB12_Pos (12U)
#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
#define PWR_PUCRB_PB11_Pos (11U)
#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
#define PWR_PUCRB_PB10_Pos (10U)
#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
#define PWR_PUCRB_PB9_Pos (9U)
#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
#define PWR_PUCRB_PB8_Pos (8U)
#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
#define PWR_PUCRB_PB7_Pos (7U)
#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
#define PWR_PUCRB_PB6_Pos (6U)
#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
#define PWR_PUCRB_PB5_Pos (5U)
#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
#define PWR_PUCRB_PB4_Pos (4U)
#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
#define PWR_PUCRB_PB3_Pos (3U)
#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
#define PWR_PUCRB_PB2_Pos (2U)
#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
#define PWR_PUCRB_PB1_Pos (1U)
#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
#define PWR_PUCRB_PB0_Pos (0U)
#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
/******************** Bit definition for PWR_PDCRB register ********************/
#define PWR_PDCRB_PB15_Pos (15U)
#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
#define PWR_PDCRB_PB14_Pos (14U)
#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
#define PWR_PDCRB_PB13_Pos (13U)
#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
#define PWR_PDCRB_PB12_Pos (12U)
#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
#define PWR_PDCRB_PB11_Pos (11U)
#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
#define PWR_PDCRB_PB10_Pos (10U)
#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
#define PWR_PDCRB_PB9_Pos (9U)
#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
#define PWR_PDCRB_PB8_Pos (8U)
#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
#define PWR_PDCRB_PB7_Pos (7U)
#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
#define PWR_PDCRB_PB6_Pos (6U)
#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
#define PWR_PDCRB_PB5_Pos (5U)
#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
#define PWR_PDCRB_PB3_Pos (3U)
#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
#define PWR_PDCRB_PB2_Pos (2U)
#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
#define PWR_PDCRB_PB1_Pos (1U)
#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
#define PWR_PDCRB_PB0_Pos (0U)
#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
/******************** Bit definition for PWR_PUCRC register ********************/
#define PWR_PUCRC_PC15_Pos (15U)
#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
#define PWR_PUCRC_PC14_Pos (14U)
#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
#define PWR_PUCRC_PC13_Pos (13U)
#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
#define PWR_PUCRC_PC12_Pos (12U)
#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
#define PWR_PUCRC_PC11_Pos (11U)
#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
#define PWR_PUCRC_PC10_Pos (10U)
#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
#define PWR_PUCRC_PC9_Pos (9U)
#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
#define PWR_PUCRC_PC8_Pos (8U)
#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
#define PWR_PUCRC_PC7_Pos (7U)
#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
#define PWR_PUCRC_PC6_Pos (6U)
#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
#define PWR_PUCRC_PC5_Pos (5U)
#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
#define PWR_PUCRC_PC4_Pos (4U)
#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
#define PWR_PUCRC_PC3_Pos (3U)
#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
#define PWR_PUCRC_PC2_Pos (2U)
#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
#define PWR_PUCRC_PC1_Pos (1U)
#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
#define PWR_PUCRC_PC0_Pos (0U)
#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
/******************** Bit definition for PWR_PDCRC register ********************/
#define PWR_PDCRC_PC15_Pos (15U)
#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
#define PWR_PDCRC_PC14_Pos (14U)
#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
#define PWR_PDCRC_PC13_Pos (13U)
#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
#define PWR_PDCRC_PC12_Pos (12U)
#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
#define PWR_PDCRC_PC11_Pos (11U)
#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
#define PWR_PDCRC_PC10_Pos (10U)
#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
#define PWR_PDCRC_PC9_Pos (9U)
#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
#define PWR_PDCRC_PC8_Pos (8U)
#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
#define PWR_PDCRC_PC7_Pos (7U)
#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
#define PWR_PDCRC_PC6_Pos (6U)
#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
#define PWR_PDCRC_PC5_Pos (5U)
#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
#define PWR_PDCRC_PC4_Pos (4U)
#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
#define PWR_PDCRC_PC3_Pos (3U)
#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
#define PWR_PDCRC_PC2_Pos (2U)
#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
#define PWR_PDCRC_PC1_Pos (1U)
#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
#define PWR_PDCRC_PC0_Pos (0U)
#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
/******************** Bit definition for PWR_PUCRD register ********************/
#define PWR_PUCRD_PD15_Pos (15U)
#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
#define PWR_PUCRD_PD14_Pos (14U)
#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
#define PWR_PUCRD_PD13_Pos (13U)
#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
#define PWR_PUCRD_PD12_Pos (12U)
#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
#define PWR_PUCRD_PD11_Pos (11U)
#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
#define PWR_PUCRD_PD10_Pos (10U)
#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
#define PWR_PUCRD_PD9_Pos (9U)
#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
#define PWR_PUCRD_PD8_Pos (8U)
#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
#define PWR_PUCRD_PD7_Pos (7U)
#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
#define PWR_PUCRD_PD6_Pos (6U)
#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
#define PWR_PUCRD_PD5_Pos (5U)
#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
#define PWR_PUCRD_PD4_Pos (4U)
#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
#define PWR_PUCRD_PD3_Pos (3U)
#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
#define PWR_PUCRD_PD2_Pos (2U)
#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
#define PWR_PUCRD_PD1_Pos (1U)
#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
#define PWR_PUCRD_PD0_Pos (0U)
#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register ********************/
#define PWR_PDCRD_PD15_Pos (15U)
#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
#define PWR_PDCRD_PD14_Pos (14U)
#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
#define PWR_PDCRD_PD13_Pos (13U)
#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
#define PWR_PDCRD_PD12_Pos (12U)
#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
#define PWR_PDCRD_PD11_Pos (11U)
#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
#define PWR_PDCRD_PD10_Pos (10U)
#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
#define PWR_PDCRD_PD9_Pos (9U)
#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
#define PWR_PDCRD_PD8_Pos (8U)
#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
#define PWR_PDCRD_PD7_Pos (7U)
#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
#define PWR_PDCRD_PD6_Pos (6U)
#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
#define PWR_PDCRD_PD5_Pos (5U)
#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
#define PWR_PDCRD_PD4_Pos (4U)
#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
#define PWR_PDCRD_PD3_Pos (3U)
#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
#define PWR_PDCRD_PD2_Pos (2U)
#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
#define PWR_PDCRD_PD1_Pos (1U)
#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
/******************** Bit definition for PWR_PUCRE register ********************/
#define PWR_PUCRE_PE15_Pos (15U)
#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
#define PWR_PUCRE_PE14_Pos (14U)
#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
#define PWR_PUCRE_PE13_Pos (13U)
#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
#define PWR_PUCRE_PE12_Pos (12U)
#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
#define PWR_PUCRE_PE11_Pos (11U)
#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
#define PWR_PUCRE_PE10_Pos (10U)
#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
#define PWR_PUCRE_PE9_Pos (9U)
#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
#define PWR_PUCRE_PE8_Pos (8U)
#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
#define PWR_PUCRE_PE7_Pos (7U)
#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
#define PWR_PUCRE_PE6_Pos (6U)
#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
#define PWR_PUCRE_PE5_Pos (5U)
#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
#define PWR_PUCRE_PE4_Pos (4U)
#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
#define PWR_PUCRE_PE3_Pos (3U)
#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
#define PWR_PUCRE_PE2_Pos (2U)
#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
#define PWR_PUCRE_PE1_Pos (1U)
#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
#define PWR_PUCRE_PE0_Pos (0U)
#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
/******************** Bit definition for PWR_PDCRE register ********************/
#define PWR_PDCRE_PE15_Pos (15U)
#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
#define PWR_PDCRE_PE14_Pos (14U)
#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
#define PWR_PDCRE_PE13_Pos (13U)
#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
#define PWR_PDCRE_PE12_Pos (12U)
#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
#define PWR_PDCRE_PE11_Pos (11U)
#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
#define PWR_PDCRE_PE10_Pos (10U)
#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
#define PWR_PDCRE_PE9_Pos (9U)
#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
#define PWR_PDCRE_PE8_Pos (8U)
#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
#define PWR_PDCRE_PE7_Pos (7U)
#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
#define PWR_PDCRE_PE6_Pos (6U)
#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
#define PWR_PDCRE_PE5_Pos (5U)
#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
#define PWR_PDCRE_PE4_Pos (4U)
#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
#define PWR_PDCRE_PE3_Pos (3U)
#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
#define PWR_PDCRE_PE2_Pos (2U)
#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
#define PWR_PDCRE_PE1_Pos (1U)
#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
#define PWR_PDCRE_PE0_Pos (0U)
#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
/******************** Bit definition for PWR_PUCRF register ********************/
#define PWR_PUCRF_PF15_Pos (15U)
#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
#define PWR_PUCRF_PF14_Pos (14U)
#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
#define PWR_PUCRF_PF13_Pos (13U)
#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
#define PWR_PUCRF_PF12_Pos (12U)
#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
#define PWR_PUCRF_PF11_Pos (11U)
#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
#define PWR_PUCRF_PF10_Pos (10U)
#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
#define PWR_PUCRF_PF9_Pos (9U)
#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
#define PWR_PUCRF_PF8_Pos (8U)
#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
#define PWR_PUCRF_PF7_Pos (7U)
#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
#define PWR_PUCRF_PF6_Pos (6U)
#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
#define PWR_PUCRF_PF5_Pos (5U)
#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
#define PWR_PUCRF_PF4_Pos (4U)
#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
#define PWR_PUCRF_PF3_Pos (3U)
#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
#define PWR_PUCRF_PF2_Pos (2U)
#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
#define PWR_PUCRF_PF1_Pos (1U)
#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
#define PWR_PUCRF_PF0_Pos (0U)
#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
/******************** Bit definition for PWR_PDCRF register ********************/
#define PWR_PDCRF_PF15_Pos (15U)
#define PWR_PDCRF_PF15_Msk (0x1UL << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
#define PWR_PDCRF_PF14_Pos (14U)
#define PWR_PDCRF_PF14_Msk (0x1UL << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
#define PWR_PDCRF_PF13_Pos (13U)
#define PWR_PDCRF_PF13_Msk (0x1UL << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
#define PWR_PDCRF_PF12_Pos (12U)
#define PWR_PDCRF_PF12_Msk (0x1UL << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
#define PWR_PDCRF_PF11_Pos (11U)
#define PWR_PDCRF_PF11_Msk (0x1UL << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
#define PWR_PDCRF_PF10_Pos (10U)
#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
#define PWR_PDCRF_PF9_Pos (9U)
#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
#define PWR_PDCRF_PF8_Pos (8U)
#define PWR_PDCRF_PF8_Msk (0x1UL << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
#define PWR_PDCRF_PF7_Pos (7U)
#define PWR_PDCRF_PF7_Msk (0x1UL << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
#define PWR_PDCRF_PF6_Pos (6U)
#define PWR_PDCRF_PF6_Msk (0x1UL << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
#define PWR_PDCRF_PF5_Pos (5U)
#define PWR_PDCRF_PF5_Msk (0x1UL << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
#define PWR_PDCRF_PF4_Pos (4U)
#define PWR_PDCRF_PF4_Msk (0x1UL << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
#define PWR_PDCRF_PF3_Pos (3U)
#define PWR_PDCRF_PF3_Msk (0x1UL << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
#define PWR_PDCRF_PF2_Pos (2U)
#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
#define PWR_PDCRF_PF1_Pos (1U)
#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
#define PWR_PDCRF_PF0_Pos (0U)
#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
/******************** Bit definition for PWR_PUCRG register ********************/
#define PWR_PUCRG_PG15_Pos (15U)
#define PWR_PUCRG_PG15_Msk (0x1UL << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
#define PWR_PUCRG_PG14_Pos (14U)
#define PWR_PUCRG_PG14_Msk (0x1UL << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
#define PWR_PUCRG_PG13_Pos (13U)
#define PWR_PUCRG_PG13_Msk (0x1UL << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
#define PWR_PUCRG_PG12_Pos (12U)
#define PWR_PUCRG_PG12_Msk (0x1UL << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
#define PWR_PUCRG_PG11_Pos (11U)
#define PWR_PUCRG_PG11_Msk (0x1UL << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
#define PWR_PUCRG_PG10_Pos (10U)
#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
#define PWR_PUCRG_PG9_Pos (9U)
#define PWR_PUCRG_PG9_Msk (0x1UL << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
#define PWR_PUCRG_PG8_Pos (8U)
#define PWR_PUCRG_PG8_Msk (0x1UL << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
#define PWR_PUCRG_PG7_Pos (7U)
#define PWR_PUCRG_PG7_Msk (0x1UL << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
#define PWR_PUCRG_PG6_Pos (6U)
#define PWR_PUCRG_PG6_Msk (0x1UL << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
#define PWR_PUCRG_PG5_Pos (5U)
#define PWR_PUCRG_PG5_Msk (0x1UL << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
#define PWR_PUCRG_PG4_Pos (4U)
#define PWR_PUCRG_PG4_Msk (0x1UL << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
#define PWR_PUCRG_PG3_Pos (3U)
#define PWR_PUCRG_PG3_Msk (0x1UL << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
#define PWR_PUCRG_PG2_Pos (2U)
#define PWR_PUCRG_PG2_Msk (0x1UL << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
#define PWR_PUCRG_PG1_Pos (1U)
#define PWR_PUCRG_PG1_Msk (0x1UL << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
#define PWR_PUCRG_PG0_Pos (0U)
#define PWR_PUCRG_PG0_Msk (0x1UL << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
/******************** Bit definition for PWR_PDCRG register ********************/
#define PWR_PDCRG_PG10_Pos (10U)
#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
#define PWR_PDCRG_PG9_Pos (9U)
#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
#define PWR_PDCRG_PG8_Pos (8U)
#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
#define PWR_PDCRG_PG7_Pos (7U)
#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
#define PWR_PDCRG_PG6_Pos (6U)
#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
#define PWR_PDCRG_PG5_Pos (5U)
#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
#define PWR_PDCRG_PG4_Pos (4U)
#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
#define PWR_PDCRG_PG3_Pos (3U)
#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
#define PWR_PDCRG_PG2_Pos (2U)
#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
#define PWR_PDCRG_PG1_Pos (1U)
#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
#define PWR_PDCRG_PG0_Pos (0U)
#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
/******************** Bit definition for PWR_CR5 register ********************/
#define PWR_CR5_R1MODE_Pos (8U)
#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
/******************************************************************************/
/* */
/* QUADSPI */
/* */
/******************************************************************************/
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
#define QUADSPI_CR_ABORT_Pos (1U)
#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
#define QUADSPI_CR_SSHIFT_Pos (4U)
#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
#define QUADSPI_CR_DFM_Pos (6U)
#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
#define QUADSPI_CR_FSEL_Pos (7U)
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
#define QUADSPI_CR_FTHRES_Pos (8U)
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
#define QUADSPI_CR_TEIE_Pos (16U)
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define QUADSPI_CR_TCIE_Pos (17U)
#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define QUADSPI_CR_FTIE_Pos (18U)
#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
#define QUADSPI_CR_SMIE_Pos (19U)
#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
#define QUADSPI_CR_TOIE_Pos (20U)
#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
#define QUADSPI_CR_APMS_Pos (22U)
#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
#define QUADSPI_CR_PMM_Pos (23U)
#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
#define QUADSPI_CR_PRESCALER_Pos (24U)
#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
/***************** Bit definition for QUADSPI_DCR register ******************/
#define QUADSPI_DCR_CKMODE_Pos (0U)
#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
#define QUADSPI_DCR_CSHT_Pos (8U)
#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_FSIZE_Pos (16U)
#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
/****************** Bit definition for QUADSPI_SR register *******************/
#define QUADSPI_SR_TEF_Pos (0U)
#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
#define QUADSPI_SR_TCF_Pos (1U)
#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
#define QUADSPI_SR_FTF_Pos (2U)
#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_SMF_Pos (3U)
#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
#define QUADSPI_SR_TOF_Pos (4U)
#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
#define QUADSPI_SR_BUSY_Pos (5U)
#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
#define QUADSPI_SR_FLEVEL_Pos (8U)
#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
/****************** Bit definition for QUADSPI_FCR register ******************/
#define QUADSPI_FCR_CTEF_Pos (0U)
#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
#define QUADSPI_FCR_CTCF_Pos (1U)
#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
#define QUADSPI_FCR_CSMF_Pos (3U)
#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
#define QUADSPI_FCR_CTOF_Pos (4U)
#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
/****************** Bit definition for QUADSPI_DLR register ******************/
#define QUADSPI_DLR_DL_Pos (0U)
#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
/****************** Bit definition for QUADSPI_CCR register ******************/
#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_IMODE_Pos (8U)
#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_ADMODE_Pos (10U)
#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADSIZE_Pos (12U)
#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ABMODE_Pos (14U)
#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABSIZE_Pos (16U)
#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_DCYC_Pos (18U)
#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DMODE_Pos (24U)
#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_FMODE_Pos (26U)
#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_SIOO_Pos (28U)
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_DHHC_Pos (30U)
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
#define QUADSPI_CCR_DDRM_Pos (31U)
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
/****************** Bit definition for QUADSPI_AR register *******************/
#define QUADSPI_AR_ADDRESS_Pos (0U)
#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
/****************** Bit definition for QUADSPI_ABR register ******************/
#define QUADSPI_ABR_ALTERNATE_Pos (0U)
#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
/****************** Bit definition for QUADSPI_DR register *******************/
#define QUADSPI_DR_DATA_Pos (0U)
#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
/****************** Bit definition for QUADSPI_PSMKR register ****************/
#define QUADSPI_PSMKR_MASK_Pos (0U)
#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
/****************** Bit definition for QUADSPI_PSMAR register ****************/
#define QUADSPI_PSMAR_MATCH_Pos (0U)
#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
/****************** Bit definition for QUADSPI_PIR register *****************/
#define QUADSPI_PIR_INTERVAL_Pos (0U)
#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
/****************** Bit definition for QUADSPI_LPTR register *****************/
#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (8U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
#define RCC_CR_HSIKERON_Pos (9U)
#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
#define RCC_CR_HSIRDY_Pos (10U)
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
#define RCC_CR_HSEON_Pos (16U)
#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
#define RCC_CR_PLLON_Pos (24U)
#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (16U)
#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
/*!< MCOSEL configuration */
#define RCC_CFGR_MCOSEL_Pos (24U)
#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
#define RCC_CFGR_MCOPRE_Pos (28U)
#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
/* Legacy aliases */
#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLSRC_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
#define RCC_PLLCFGR_PLLM_Pos (4U)
#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
#define RCC_PLLCFGR_PLLN_Pos (8U)
#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
#define RCC_PLLCFGR_PLLPEN_Pos (16U)
#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
#define RCC_PLLCFGR_PLLP_Pos (17U)
#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
#define RCC_PLLCFGR_PLLQEN_Pos (20U)
#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
#define RCC_PLLCFGR_PLLQ_Pos (21U)
#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
#define RCC_PLLCFGR_PLLREN_Pos (24U)
#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
#define RCC_PLLCFGR_PLLR_Pos (25U)
#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos (3U)
#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos (4U)
#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_PLLRDYIE_Pos (5U)
#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos (9U)
#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos (10U)
#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
/******************** Bit definition for RCC_CIFR register ******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos (3U)
#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos (4U)
#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_PLLRDYF_Pos (5U)
#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
#define RCC_CIFR_CSSF_Pos (8U)
#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
#define RCC_CIFR_LSECSSF_Pos (9U)
#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSI48RDYF_Pos (10U)
#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
/******************** Bit definition for RCC_CICR register ******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos (3U)
#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos (4U)
#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
#define RCC_CICR_PLLRDYC_Pos (5U)
#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
#define RCC_CICR_CSSC_Pos (8U)
#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
#define RCC_CICR_LSECSSC_Pos (9U)
#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSI48RDYC_Pos (10U)
#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
#define RCC_AHB1RSTR_CORDICRST_Pos (3U)
#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
#define RCC_AHB1RSTR_FMACRST_Pos (4U)
#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
#define RCC_AHB1RSTR_CRCRST_Pos (12U)
#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
#define RCC_AHB2RSTR_ADC12RST_Pos (13U)
#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
#define RCC_AHB2RSTR_ADC345RST_Pos (14U)
#define RCC_AHB2RSTR_ADC345RST_Msk (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
#define RCC_AHB2RSTR_ADC345RST RCC_AHB2RSTR_ADC345RST_Msk
#define RCC_AHB2RSTR_DAC1RST_Pos (16U)
#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
#define RCC_AHB2RSTR_DAC2RST_Pos (17U)
#define RCC_AHB2RSTR_DAC2RST_Msk (0x1UL << RCC_AHB2RSTR_DAC2RST_Pos)/*!< 0x00020000 */
#define RCC_AHB2RSTR_DAC2RST RCC_AHB2RSTR_DAC2RST_Msk
#define RCC_AHB2RSTR_DAC3RST_Pos (18U)
#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
#define RCC_AHB2RSTR_DAC4RST_Pos (19U)
#define RCC_AHB2RSTR_DAC4RST_Msk (0x1UL << RCC_AHB2RSTR_DAC4RST_Pos)/*!< 0x00080000 */
#define RCC_AHB2RSTR_DAC4RST RCC_AHB2RSTR_DAC4RST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (26U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
/******************** Bit definition for RCC_AHB3RSTR register **************/
#define RCC_AHB3RSTR_FMCRST_Pos (0U)
#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)/*!< 0x00000001 */
#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
/******************** Bit definition for RCC_APB1RSTR1 register **************/
#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
#define RCC_APB1RSTR1_CRSRST_Pos (8U)
#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
#define RCC_APB1RSTR1_USART2RST_Pos (17U)
#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
#define RCC_APB1RSTR1_USART3RST_Pos (18U)
#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
#define RCC_APB1RSTR1_UART4RST_Pos (19U)
#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
#define RCC_APB1RSTR1_UART5RST_Pos (20U)
#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
#define RCC_APB1RSTR1_USBRST_Pos (23U)
#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
#define RCC_APB1RSTR1_FDCANRST_Pos (25U)
#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
#define RCC_APB1RSTR1_PWRRST_Pos (28U)
#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
#define RCC_APB1RSTR1_I2C3RST_Pos (30U)
#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
#define RCC_APB1RSTR2_I2C4RST_Pos (1U)
#define RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
#define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_TIM8RST_Pos (13U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_SPI4RST_Pos (15U)
#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)/*!< 0x00008000 */
#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_TIM20RST_Pos (20U)
#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
#define RCC_APB2RSTR_HRTIM1RST_Pos (26U)
#define RCC_APB2RSTR_HRTIM1RST_Msk (0x1UL << RCC_APB2RSTR_HRTIM1RST_Pos)/*!< 0x04000000 */
#define RCC_APB2RSTR_HRTIM1RST RCC_APB2RSTR_HRTIM1RST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define RCC_AHB1ENR_DMA2EN_Pos (1U)
#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
#define RCC_AHB1ENR_CORDICEN_Pos (3U)
#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
#define RCC_AHB1ENR_FMACEN_Pos (4U)
#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
#define RCC_AHB1ENR_FLASHEN_Pos (8U)
#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
#define RCC_AHB1ENR_CRCEN_Pos (12U)
#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
#define RCC_AHB2ENR_GPIODEN_Pos (3U)
#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
#define RCC_AHB2ENR_ADC12EN_Pos (13U)
#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
#define RCC_AHB2ENR_ADC345EN_Pos (14U)
#define RCC_AHB2ENR_ADC345EN_Msk (0x1UL << RCC_AHB2ENR_ADC345EN_Pos) /*!< 0x00004000 */
#define RCC_AHB2ENR_ADC345EN RCC_AHB2ENR_ADC345EN_Msk
#define RCC_AHB2ENR_DAC1EN_Pos (16U)
#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
#define RCC_AHB2ENR_DAC2EN_Pos (17U)
#define RCC_AHB2ENR_DAC2EN_Msk (0x1UL << RCC_AHB2ENR_DAC2EN_Pos) /*!< 0x00020000 */
#define RCC_AHB2ENR_DAC2EN RCC_AHB2ENR_DAC2EN_Msk
#define RCC_AHB2ENR_DAC3EN_Pos (18U)
#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
#define RCC_AHB2ENR_DAC4EN_Pos (19U)
#define RCC_AHB2ENR_DAC4EN_Msk (0x1UL << RCC_AHB2ENR_DAC4EN_Pos) /*!< 0x00080000 */
#define RCC_AHB2ENR_DAC4EN RCC_AHB2ENR_DAC4EN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (26U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
/******************** Bit definition for RCC_AHB3ENR register ***************/
#define RCC_AHB3ENR_FMCEN_Pos (0U)
#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
#define RCC_AHB3ENR_QSPIEN_Pos (8U)
#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
/******************** Bit definition for RCC_APB1ENR1 register ***************/
#define RCC_APB1ENR1_TIM2EN_Pos (0U)
#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
#define RCC_APB1ENR1_TIM3EN_Pos (1U)
#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM5EN_Pos (3U)
#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
#define RCC_APB1ENR1_TIM7EN_Pos (5U)
#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
#define RCC_APB1ENR1_CRSEN_Pos (8U)
#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
#define RCC_APB1ENR1_WWDGEN_Pos (11U)
#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
#define RCC_APB1ENR1_SPI2EN_Pos (14U)
#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
#define RCC_APB1ENR1_SPI3EN_Pos (15U)
#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
#define RCC_APB1ENR1_USART2EN_Pos (17U)
#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
#define RCC_APB1ENR1_USART3EN_Pos (18U)
#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
#define RCC_APB1ENR1_UART4EN_Pos (19U)
#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
#define RCC_APB1ENR1_UART5EN_Pos (20U)
#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
#define RCC_APB1ENR1_I2C1EN_Pos (21U)
#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
#define RCC_APB1ENR1_I2C2EN_Pos (22U)
#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
#define RCC_APB1ENR1_USBEN_Pos (23U)
#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
#define RCC_APB1ENR1_FDCANEN_Pos (25U)
#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
#define RCC_APB1ENR1_PWREN_Pos (28U)
#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
#define RCC_APB1ENR1_I2C3EN_Pos (30U)
#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
#define RCC_APB1ENR2_I2C4EN_Pos (1U)
#define RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
#define RCC_APB1ENR2_UCPD1EN_Pos (8U)
#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
#define RCC_APB2ENR_TIM1EN_Pos (11U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_TIM8EN_Pos (13U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define RCC_APB2ENR_USART1EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_SPI4EN_Pos (15U)
#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_TIM20EN_Pos (20U)
#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
#define RCC_APB2ENR_HRTIM1EN_Pos (26U)
#define RCC_APB2ENR_HRTIM1EN_Msk (0x1UL << RCC_APB2ENR_HRTIM1EN_Pos)/*!< 0x04000000 */
#define RCC_APB2ENR_HRTIM1EN RCC_APB2ENR_HRTIM1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
/******************** Bit definition for RCC_AHB2SMENR register *************/
#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
#define RCC_AHB2SMENR_ADC345SMEN_Pos (14U)
#define RCC_AHB2SMENR_ADC345SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
#define RCC_AHB2SMENR_ADC345SMEN RCC_AHB2SMENR_ADC345SMEN_Msk
#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
#define RCC_AHB2SMENR_DAC2SMEN_Pos (17U)
#define RCC_AHB2SMENR_DAC2SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC2SMEN_Pos)/*!< 0x00020000 */
#define RCC_AHB2SMENR_DAC2SMEN RCC_AHB2SMENR_DAC2SMEN_Msk
#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
#define RCC_AHB2SMENR_DAC4SMEN_Pos (19U)
#define RCC_AHB2SMENR_DAC4SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC4SMEN_Pos)/*!< 0x00080000 */
#define RCC_AHB2SMENR_DAC4SMEN RCC_AHB2SMENR_DAC4SMEN_Msk
#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register *************/
#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
/******************** Bit definition for RCC_APB1SMENR1 register *************/
#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
#define RCC_APB1SMENR1_USBSMEN_Pos (23U)
#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
/******************** Bit definition for RCC_APB1SMENR2 register *************/
#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
/******************** Bit definition for RCC_APB2SMENR register *************/
#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
#define RCC_APB2SMENR_SPI4SMEN_Pos (15U)
#define RCC_APB2SMENR_SPI4SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI4SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB2SMENR_SPI4SMEN RCC_APB2SMENR_SPI4SMEN_Msk
#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
#define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
#define RCC_APB2SMENR_HRTIM1SMEN_Pos (26U)
#define RCC_APB2SMENR_HRTIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_HRTIM1SMEN_Pos)/*!< 0x04000000 */
#define RCC_APB2SMENR_HRTIM1SMEN RCC_APB2SMENR_HRTIM1SMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
#define RCC_CCIPR_USART2SEL_Pos (2U)
#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
#define RCC_CCIPR_USART3SEL_Pos (4U)
#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
#define RCC_CCIPR_UART4SEL_Pos (6U)
#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR_UART5SEL_Pos (8U)
#define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
#define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR_LPUART1SEL_Pos (10U)
#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
#define RCC_CCIPR_I2C1SEL_Pos (12U)
#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR_I2C2SEL_Pos (14U)
#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR_I2C3SEL_Pos (16U)
#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
#define RCC_CCIPR_SAI1SEL_Pos (20U)
#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
#define RCC_CCIPR_I2S23SEL_Pos (22U)
#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
#define RCC_CCIPR_FDCANSEL_Pos (24U)
#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR_CLK48SEL_Pos (26U)
#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
#define RCC_CCIPR_ADC12SEL_Pos (28U)
#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
#define RCC_CCIPR_ADC345SEL_Pos (30U)
#define RCC_CCIPR_ADC345SEL_Msk (0x3UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
#define RCC_CCIPR_ADC345SEL RCC_CCIPR_ADC345SEL_Msk
#define RCC_CCIPR_ADC345SEL_0 (0x1UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x40000000 */
#define RCC_CCIPR_ADC345SEL_1 (0x2UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos (3U)
#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos (5U)
#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos (6U)
#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
#define RCC_BDCR_LSCOEN_Pos (24U)
#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
#define RCC_BDCR_LSCOSEL_Pos (25U)
#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION_Pos (0U)
#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos (1U)
#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
#define RCC_CSR_RMVF_Pos (23U)
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
#define RCC_CSR_OBLRSTF_Pos (25U)
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_BORRSTF_Pos (27U)
#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/******************** Bit definition for RCC_CRRCR register *****************/
#define RCC_CRRCR_HSI48ON_Pos (0U)
#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
#define RCC_CRRCR_HSI48RDY_Pos (1U)
#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos (7U)
#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
/******************** Bit definition for RCC_CCIPR2 register ******************/
#define RCC_CCIPR2_I2C4SEL_Pos (0U)
#define RCC_CCIPR2_I2C4SEL_Msk (0x3UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
#define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
#define RCC_CCIPR2_I2C4SEL_0 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR2_I2C4SEL_1 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR2_QSPISEL_Pos (20U)
#define RCC_CCIPR2_QSPISEL_Msk (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR2_QSPISEL RCC_CCIPR2_QSPISEL_Msk
#define RCC_CCIPR2_QSPISEL_0 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR2_QSPISEL_1 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_ICSR register ******************/
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_ALRBWF_Pos (1U)
#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
#define RTC_ICSR_ALRAWF_Pos (0U)
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_SR register *******************/
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
/******************** Bits definition for RTC_MISR register *****************/
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
/******************** Bits definition for RTC_SCR register ******************/
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register *****************/
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos (21U)
#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
/******************** Bits definition for TAMP_CR2 register *****************/
#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
#define TAMP_CR2_TAMP1MF_Pos (16U)
#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
#define TAMP_CR2_TAMP2MF_Pos (17U)
#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
#define TAMP_CR2_TAMP3MF_Pos (18U)
#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_IER register *****************/
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos (21U)
#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
/******************** Bits definition for TAMP_SR register ******************/
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos (21U)
#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
/******************** Bits definition for TAMP_MISR register ****************/
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos (21U)
#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
/******************** Bits definition for TAMP_SCR register *****************/
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos (21U)
#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
/******************** Bits definition for TAMP_BKP1R register ***************/
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
/******************** Bits definition for TAMP_BKP2R register ***************/
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
/******************** Bits definition for TAMP_BKP3R register ***************/
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
/******************** Bits definition for TAMP_BKP4R register ***************/
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************** Bits definition for TAMP_BKP5R register ***************/
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
/******************** Bits definition for TAMP_BKP6R register ***************/
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
/******************** Bits definition for TAMP_BKP7R register ***************/
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
/******************** Bits definition for TAMP_BKP8R register ***************/
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
/******************** Bits definition for TAMP_BKP9R register ***************/
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
/******************** Bits definition for TAMP_BKP10R register ***************/
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
/******************** Bits definition for TAMP_BKP11R register ***************/
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
/******************** Bits definition for TAMP_BKP12R register ***************/
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
/******************** Bits definition for TAMP_BKP13R register ***************/
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
/******************** Bits definition for TAMP_BKP14R register ***************/
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
/******************** Bits definition for TAMP_BKP15R register ***************/
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
/******************** Bits definition for TAMP_BKP16R register ***************/
#define TAMP_BKP16R_Pos (0U)
#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP16R TAMP_BKP16R_Msk
/******************** Bits definition for TAMP_BKP17R register ***************/
#define TAMP_BKP17R_Pos (0U)
#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP17R TAMP_BKP17R_Msk
/******************** Bits definition for TAMP_BKP18R register ***************/
#define TAMP_BKP18R_Pos (0U)
#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP18R TAMP_BKP18R_Msk
/******************** Bits definition for TAMP_BKP19R register ***************/
#define TAMP_BKP19R_Pos (0U)
#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP19R TAMP_BKP19R_Msk
/******************** Bits definition for TAMP_BKP20R register ***************/
#define TAMP_BKP20R_Pos (0U)
#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP20R TAMP_BKP20R_Msk
/******************** Bits definition for TAMP_BKP21R register ***************/
#define TAMP_BKP21R_Pos (0U)
#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP21R TAMP_BKP21R_Msk
/******************** Bits definition for TAMP_BKP22R register ***************/
#define TAMP_BKP22R_Pos (0U)
#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP22R TAMP_BKP22R_Msk
/******************** Bits definition for TAMP_BKP23R register ***************/
#define TAMP_BKP23R_Pos (0U)
#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP23R TAMP_BKP23R_Msk
/******************** Bits definition for TAMP_BKP24R register ***************/
#define TAMP_BKP24R_Pos (0U)
#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP24R TAMP_BKP24R_Msk
/******************** Bits definition for TAMP_BKP25R register ***************/
#define TAMP_BKP25R_Pos (0U)
#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP25R TAMP_BKP25R_Msk
/******************** Bits definition for TAMP_BKP26R register ***************/
#define TAMP_BKP26R_Pos (0U)
#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP26R TAMP_BKP26R_Msk
/******************** Bits definition for TAMP_BKP27R register ***************/
#define TAMP_BKP27R_Pos (0U)
#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP27R TAMP_BKP27R_Msk
/******************** Bits definition for TAMP_BKP28R register ***************/
#define TAMP_BKP28R_Pos (0U)
#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP28R TAMP_BKP28R_Msk
/******************** Bits definition for TAMP_BKP29R register ***************/
#define TAMP_BKP29R_Pos (0U)
#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP29R TAMP_BKP29R_Msk
/******************** Bits definition for TAMP_BKP30R register ***************/
#define TAMP_BKP30R_Pos (0U)
#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP30R TAMP_BKP30R_Msk
/******************** Bits definition for TAMP_BKP31R register ***************/
#define TAMP_BKP31R_Pos (0U)
#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP31R TAMP_BKP31R_Msk
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/****************** Bit definition for SAI_PDMCR register *******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
#define SPI_CR1_CPOL_Pos (1U)
#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
#define SPI_CR1_MSTR_Pos (2U)
#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
#define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
#define SPI_CR1_LSBFIRST_Pos (7U)
#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
#define SPI_CR1_SSI_Pos (8U)
#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
#define SPI_CR1_SSM_Pos (9U)
#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
#define SPI_CR1_RXONLY_Pos (10U)
#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
#define SPI_CR1_CRCL_Pos (11U)
#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
#define SPI_CR1_CRCNEXT_Pos (12U)
#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
#define SPI_CR1_CRCEN_Pos (13U)
#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE_Pos (14U)
#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos (15U)
#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN_Pos (0U)
#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN_Pos (1U)
#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
#define SPI_CR2_SSOE_Pos (2U)
#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
#define SPI_CR2_NSSP_Pos (3U)
#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
#define SPI_CR2_FRF_Pos (4U)
#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
#define SPI_CR2_ERRIE_Pos (5U)
#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE_Pos (6U)
#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE_Pos (7U)
#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
#define SPI_CR2_LDMARX_Pos (13U)
#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
#define SPI_CR2_LDMATX_Pos (14U)
#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE_Pos (0U)
#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
#define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
#define SPI_SR_MODF_Pos (5U)
#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
#define SPI_SR_BSY_Pos (7U)
#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
#define SPI_SR_FRE_Pos (8U)
#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
#define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U)
#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY_Pos (0U)
#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC_Pos (0U)
#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC_Pos (0U)
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN_Pos (0U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN_Pos (1U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_CKPOL_Pos (3U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_I2SE_Pos (10U)
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD_Pos (8U)
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE_Pos (9U)
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
/****************** Bit definition for SYSCFG_CFGR1 register ******************/
#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
#define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */
#define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
/****************** Bit definition for SYSCFG_SCSR register ****************/
#define SYSCFG_SCSR_CCMER_Pos (0U)
#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
#define SYSCFG_SCSR_CCMBSY_Pos (1U)
#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
/****************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_CLL_Pos (0U)
#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
#define SYSCFG_CFGR2_SPL_Pos (1U)
#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
#define SYSCFG_CFGR2_PVDL_Pos (2U)
#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
#define SYSCFG_CFGR2_ECCL_Pos (3U)
#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
#define SYSCFG_CFGR2_SPF_Pos (8U)
#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
#define SYSCFG_SWPR_PAGE16_Pos (16U)
#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
#define SYSCFG_SWPR_PAGE17_Pos (17U)
#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
#define SYSCFG_SWPR_PAGE18_Pos (18U)
#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
#define SYSCFG_SWPR_PAGE19_Pos (19U)
#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
#define SYSCFG_SWPR_PAGE20_Pos (20U)
#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
#define SYSCFG_SWPR_PAGE21_Pos (21U)
#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
#define SYSCFG_SWPR_PAGE22_Pos (22U)
#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
#define SYSCFG_SWPR_PAGE23_Pos (23U)
#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
#define SYSCFG_SWPR_PAGE24_Pos (24U)
#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
#define SYSCFG_SWPR_PAGE25_Pos (25U)
#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
#define SYSCFG_SWPR_PAGE26_Pos (26U)
#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
#define SYSCFG_SWPR_PAGE27_Pos (27U)
#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
#define SYSCFG_SWPR_PAGE28_Pos (28U)
#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
#define SYSCFG_SWPR_PAGE29_Pos (29U)
#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
#define SYSCFG_SWPR_PAGE30_Pos (30U)
#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
#define SYSCFG_SWPR_PAGE31_Pos (31U)
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
#define TIM_CR1_CMS_Pos (5U)
#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos (7U)
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos (8U)
#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos (12U)
#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos (15U)
#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos (3U)
#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE_Pos (0U)
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos (1U)
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos (2U)
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos (3U)
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos (4U)
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos (5U)
#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos (6U)
#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos (7U)
#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos (8U)
#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos (9U)
#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos (10U)
#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos (11U)
#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos (12U)
#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos (13U)
#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos (14U)
#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos (20U)
#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos (21U)
#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos (20U)
#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
#define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos (21U)
#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
#define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos (22U)
#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
#define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos (23U)
#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
#define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG_Pos (0U)
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos (6U)
#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
#define TIM_EGR_BG_Pos (7U)
#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
#define TIM_EGR_B2G_Pos (8U)
#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos (4U)
#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos (12U)
#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA_Pos (0U)
#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos (8U)
#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
/******************* Bit definition for TIM1_AF1 register *******************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
#define TIM1_AF1_BKCMP1E_Pos (1U)
#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
#define TIM1_AF1_BKCMP2E_Pos (2U)
#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
#define TIM1_AF1_BKCMP3E_Pos (3U)
#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
#define TIM1_AF1_BKCMP4E_Pos (4U)
#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
#define TIM1_AF1_BKCMP5E_Pos (5U)
#define TIM1_AF1_BKCMP5E_Msk (0x1UL << TIM1_AF1_BKCMP5E_Pos) /*!< 0x00000020 */
#define TIM1_AF1_BKCMP5E TIM1_AF1_BKCMP5E_Msk /*!<BRK COMP5 enable */
#define TIM1_AF1_BKCMP6E_Pos (6U)
#define TIM1_AF1_BKCMP6E_Msk (0x1UL << TIM1_AF1_BKCMP6E_Pos) /*!< 0x00000040 */
#define TIM1_AF1_BKCMP6E TIM1_AF1_BKCMP6E_Msk /*!<BRK COMP6 enable */
#define TIM1_AF1_BKCMP7E_Pos (7U)
#define TIM1_AF1_BKCMP7E_Msk (0x1UL << TIM1_AF1_BKCMP7E_Pos) /*!< 0x00000080 */
#define TIM1_AF1_BKCMP7E TIM1_AF1_BKCMP7E_Msk /*!<BRK COMP7 enable */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
#define TIM1_AF1_BKCMP1P_Pos (10U)
#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
#define TIM1_AF1_BKCMP2P_Pos (11U)
#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
#define TIM1_AF1_BKCMP3P_Pos (12U)
#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
#define TIM1_AF1_BKCMP4P_Pos (13U)
#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
#define TIM1_AF1_ETRSEL_Pos (14U)
#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
#define TIM1_AF2_BK2CMP1E_Pos (1U)
#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
#define TIM1_AF2_BK2CMP2E_Pos (2U)
#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
#define TIM1_AF2_BK2CMP3E_Pos (3U)
#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
#define TIM1_AF2_BK2CMP4E_Pos (4U)
#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
#define TIM1_AF2_BK2CMP5E_Pos (5U)
#define TIM1_AF2_BK2CMP5E_Msk (0x1UL << TIM1_AF2_BK2CMP5E_Pos) /*!< 0x00000020 */
#define TIM1_AF2_BK2CMP5E TIM1_AF2_BK2CMP5E_Msk /*!<BRK2 COMP5 enable */
#define TIM1_AF2_BK2CMP6E_Pos (6U)
#define TIM1_AF2_BK2CMP6E_Msk (0x1UL << TIM1_AF2_BK2CMP6E_Pos) /*!< 0x00000040 */
#define TIM1_AF2_BK2CMP6E TIM1_AF2_BK2CMP6E_Msk /*!<BRK2 COMP6 enable */
#define TIM1_AF2_BK2CMP7E_Pos (7U)
#define TIM1_AF2_BK2CMP7E_Msk (0x1UL << TIM1_AF2_BK2CMP7E_Pos) /*!< 0x00000080 */
#define TIM1_AF2_BK2CMP7E TIM1_AF2_BK2CMP7E_Msk /*!<BRK2 COMP7 enable */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
#define TIM1_AF2_BK2CMP1P_Pos (10U)
#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
#define TIM1_AF2_BK2CMP2P_Pos (11U)
#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_BK2CMP3P_Pos (12U)
#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
#define TIM1_AF2_BK2CMP4P_Pos (13U)
#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
#define TIM1_AF2_OCRSEL_Pos (16U)
#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_HSE32EN_Pos (0U)
#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM_DTR2 register *********************/
#define TIM_DTR2_DTGF_Pos (0U)
#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos (16U)
#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos (17U)
#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
/******************* Bit definition for TIM_ECR register *********************/
#define TIM_ECR_IE_Pos (0U)
#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
#define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
#define TIM_ECR_IDIR_Pos (1U)
#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_FIDX_Pos (5U)
#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
#define TIM_ECR_IPOS_Pos (6U)
#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
#define TIM_ECR_PW_Pos (16U)
#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
#define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos (24U)
#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB_Pos (0U)
#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_OR register *******************/
#define LPTIM_OR_IN1_Pos (0U)
#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
#define LPTIM_OR_IN2_Pos (1U)
#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART_Pos (0U)
#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR_Pos (0U)
#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */
#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
/******************* Bit definition for VREFBUF_CCR register ******************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* USB Device FS Endpoint registers */
/* */
/******************************************************************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
/* bit positions */
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
/* */
/* USB Device FS General registers */
/* */
/******************************************************************************/
#define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
#define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
#define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
#define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
#define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
#define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
/****************** Bits definition for USB_CNTR register *******************/
#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/****************** Bits definition for USB_ISTR register *******************/
#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
/****************** Bits definition for USB_FNR register ********************/
#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
/****************** Bits definition for USB_DADDR register ****************/
#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
#define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
#define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
#define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
#define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
#define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
#define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
#define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
#define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
/****************** Bit definition for USB_BTABLE register ******************/
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
/****************** Bits definition for USB_BCDR register *******************/
#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
/******************* Bit definition for LPMCSR register *********************/
#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
/*!< Buffer descriptor table */
/***************** Bit definition for USB_ADDR0_TX register *****************/
#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_TX register *****************/
#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_TX register *****************/
#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_TX register *****************/
#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_TX register *****************/
#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_TX register *****************/
#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_TX register *****************/
#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_TX register *****************/
#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_TX register ****************/
#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
/***************** Bit definition for USB_COUNT1_TX register ****************/
#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
/***************** Bit definition for USB_COUNT2_TX register ****************/
#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
/***************** Bit definition for USB_COUNT3_TX register ****************/
#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
/***************** Bit definition for USB_COUNT4_TX register ****************/
#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
/***************** Bit definition for USB_COUNT5_TX register ****************/
#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
/***************** Bit definition for USB_COUNT6_TX register ****************/
#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
/***************** Bit definition for USB_COUNT7_TX register ****************/
#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_ADDR0_RX register *****************/
#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_RX register *****************/
#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_RX register *****************/
#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_RX register *****************/
#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_RX register *****************/
#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_RX register *****************/
#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_RX register *****************/
#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_RX register *****************/
#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_RX register ****************/
#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT0_RX_BLSIZE_Pos (15U)
#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT1_RX register ****************/
#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT1_RX_BLSIZE_Pos (15U)
#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT2_RX register ****************/
#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT2_RX_BLSIZE_Pos (15U)
#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT3_RX register ****************/
#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT3_RX_BLSIZE_Pos (15U)
#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT4_RX register ****************/
#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT4_RX_BLSIZE_Pos (15U)
#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT5_RX register ****************/
#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT5_RX_BLSIZE_Pos (15U)
#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT6_RX register ****************/
#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT6_RX_BLSIZE_Pos (15U)
#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT7_RX register ****************/
#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT7_RX_BLSIZE_Pos (15U)
#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
/* UCPD */
/* */
/******************************************************************************/
/******************** Bits definition for UCPD_CFG1 register *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos (6U)
#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos (11U)
#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos (20U)
#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos (29U)
#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define UCPD_CFG1_RXDMAEN_Pos (30U)
#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define UCPD_CFG1_UCPDEN_Pos (31U)
#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
/******************** Bits definition for UCPD_CFG2 register *******************/
#define UCPD_CFG2_RXFILTDIS_Pos (0U)
#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos (1U)
#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos (2U)
#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos (3U)
#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
/******************** Bits definition for UCPD_CR register ********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos (2U)
#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXHRST_Pos (3U)
#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
#define UCPD_CR_RXMODE_Pos (4U)
#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
#define UCPD_CR_PHYRXEN_Pos (5U)
#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
#define UCPD_CR_PHYCCSEL_Pos (6U)
#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
#define UCPD_CR_ANASUBMODE_Pos (7U)
#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos (9U)
#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
#define UCPD_CR_CCENABLE_Pos (10U)
#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
#define UCPD_CR_FRSRXEN_Pos (16U)
#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
#define UCPD_CR_FRSTX_Pos (17U)
#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos (18U)
#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
#define UCPD_CR_CC1TCDIS_Pos (20U)
#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos (21U)
#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
/******************** Bits definition for UCPD_IMR register *******************/
#define UCPD_IMR_TXISIE_Pos (0U)
#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
#define UCPD_IMR_TXMSGABTIE_Pos (3U)
#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
#define UCPD_IMR_HRSTDISCIE_Pos (4U)
#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
#define UCPD_IMR_HRSTSENTIE_Pos (5U)
#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
#define UCPD_IMR_TXUNDIE_Pos (6U)
#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
#define UCPD_IMR_RXNEIE_Pos (8U)
#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
#define UCPD_IMR_RXORDDETIE_Pos (9U)
#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
#define UCPD_IMR_RXOVRIE_Pos (11U)
#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
#define UCPD_IMR_RXMSGENDIE_Pos (12U)
#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
#define UCPD_IMR_FRSEVTIE_Pos (20U)
#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
/******************** Bits definition for UCPD_SR register ********************/
#define UCPD_SR_TXIS_Pos (0U)
#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
#define UCPD_SR_TXMSGDISC_Pos (1U)
#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
#define UCPD_SR_TXMSGSENT_Pos (2U)
#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
#define UCPD_SR_TXMSGABT_Pos (3U)
#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
#define UCPD_SR_HRSTDISC_Pos (4U)
#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
#define UCPD_SR_HRSTSENT_Pos (5U)
#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
#define UCPD_SR_TXUND_Pos (6U)
#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
#define UCPD_SR_RXNE_Pos (8U)
#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
#define UCPD_SR_RXORDDET_Pos (9U)
#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
#define UCPD_SR_RXHRSTDET_Pos (10U)
#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
#define UCPD_SR_RXOVR_Pos (11U)
#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
#define UCPD_SR_RXMSGEND_Pos (12U)
#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
#define UCPD_SR_RXERR_Pos (13U)
#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos (14U)
#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
#define UCPD_SR_TYPECEVT2_Pos (15U)
#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
#define UCPD_SR_FRSEVT_Pos (20U)
#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
/******************** Bits definition for UCPD_ICR register *******************/
#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
#define UCPD_ICR_TXMSGABTCF_Pos (3U)
#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
#define UCPD_ICR_HRSTDISCCF_Pos (4U)
#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
#define UCPD_ICR_HRSTSENTCF_Pos (5U)
#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
#define UCPD_ICR_TXUNDCF_Pos (6U)
#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
#define UCPD_ICR_RXORDDETCF_Pos (9U)
#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
#define UCPD_ICR_RXOVRCF_Pos (11U)
#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
#define UCPD_ICR_RXMSGENDCF_Pos (12U)
#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
#define UCPD_ICR_FRSEVTCF_Pos (20U)
#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
/******************** Bits definition for UCPD_TXORDSET register **************/
#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
/******************** Bits definition for UCPD_TXPAYSZ register ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
/******************** Bits definition for UCPD_TXDR register *******************/
#define UCPD_TXDR_TXDATA_Pos (0U)
#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
/******************** Bits definition for UCPD_RXORDSET register **************/
#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
/******************** Bits definition for UCPD_RXPAYSZ register ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
/******************** Bits definition for UCPD_RXDR register *******************/
#define UCPD_RXDR_RXDATA_Pos (0U)
#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/******************** Bits definition for UCPD_RXORDEXT1 register **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
/******************** Bits definition for UCPD_RXORDEXT2 register **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2) || \
((INSTANCE) == ADC3) || \
((INSTANCE) == ADC4) || \
((INSTANCE) == ADC5))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC3))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
((INSTANCE) == ADC345_COMMON) )
/******************************** FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
((INSTANCE) == FDCAN2) || \
((INSTANCE) == FDCAN3))
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2) || \
((INSTANCE) == COMP3) || \
((INSTANCE) == COMP4) || \
((INSTANCE) == COMP5) || \
((INSTANCE) == COMP6) || \
((INSTANCE) == COMP7))
/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC2) || \
((INSTANCE) == DAC3) || \
((INSTANCE) == DAC4))
/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7) || \
((INSTANCE) == DMA1_Channel8) || \
((INSTANCE) == DMA2_Channel1) || \
((INSTANCE) == DMA2_Channel2) || \
((INSTANCE) == DMA2_Channel3) || \
((INSTANCE) == DMA2_Channel4) || \
((INSTANCE) == DMA2_Channel5) || \
((INSTANCE) == DMA2_Channel6) || \
((INSTANCE) == DMA2_Channel7) || \
((INSTANCE) == DMA2_Channel8))
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
/******************************* FMAC Instances *******************************/
#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances *****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4))
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3) || \
((INSTANCE) == OPAMP4) || \
((INSTANCE) == OPAMP5) || \
((INSTANCE) == OPAMP6))
/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/******************************* QSPI Instances *******************************/
#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4))
/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
((__INSTANCE__) == SPI3))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM5) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************************** HRTIM Instances *******************************/
#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** UCPD Instances ********************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
/******************************* USB Instances *******************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/**
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32G4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32G4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
/* Aliases for __IRQHandler */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32G474xx_H */
/**
* @}
*/
/**
* @}
*/
| 1,392,535 | C | 75.804148 | 180 | 0.526245 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g483xx.h | /**
******************************************************************************
* @file stm32g483xx.h
* @author MCD Application Team
* @brief CMSIS STM32G483xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32g483xx
* @{
*/
#ifndef __STM32G483xx_H
#define __STM32G483xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32G4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ***************************************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_IRQn = 19, /*!< USB HP Interrupt */
USB_LP_IRQn = 20, /*!< USB LP Interrupt */
FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
TIM7_DAC_IRQn = 55, /*!< TIM7 global and DAC2&4 underrun error interrupts */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
ADC5_IRQn = 62, /*!< ADC5 global Interrupt */
UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 */
COMP7_IRQn = 66, /*!< COMP7 Interrupt */
CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */
I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */
SPI4_IRQn = 84, /*!< SPI4 Event interrupt */
AES_IRQn = 85, /*!< AES global interrupt */
FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */
FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */
FDCAN3_IT0_IRQn = 88, /*!< FDCAN3 interrupt line 0 interrupt */
FDCAN3_IT1_IRQn = 89, /*!< FDCAN3 interrupt line 1 interrupt */
RNG_IRQn = 90, /*!< RNG global interrupt */
LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */
DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */
DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */
DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */
CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
FMAC_IRQn = 101 /*!< FMAC global Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32g4xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
__IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
} FDCAN_Config_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
__IO uint32_t RESERVED[2];
__IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
__IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
__IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
__IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
__IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
__IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
__IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
__IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */
__IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
__IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */
} FLASH_TypeDef;
/**
* @brief FMAC
*/
typedef struct
{
__IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
__IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
__IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
__IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
} FMAC_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
uint32_t RESERVED0; /*!< Reserved, 0x90 */
__IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
} FMC_Bank3_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
} OPAMP_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
__IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief QUAD Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
__IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
__IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
__IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
__IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
__IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
__IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
/*
* @brief Specific device feature definitions
*/
#define RTC_TAMP_INT_6_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 3u
#define RTC_BACKUP_NB 32u
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
} RTC_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
__IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
__IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
__IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
__IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
__IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
__IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
__IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
__IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
__IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
__IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
__IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
__IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
__IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
__IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
__IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
__IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
} TAMP_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
__IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
__IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
__IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
__IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
__IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
__IO uint16_t RESERVEDD; /*!< Reserved */
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
__IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief AES hardware accelerator
*/
typedef struct
{
__IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
__IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
__IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
__IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
__IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
__IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
__IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
__IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
__IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
__IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
__IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
__IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
__IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
__IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
__IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
__IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
__IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
__IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
__IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
__IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
__IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
__IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
__IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
} AES_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief CORDIC
*/
typedef struct
{
__IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
__IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
__IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
} CORDIC_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */
#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define FMC_BASE (0x60000000UL) /*!< FMC base address */
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */
#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
#define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
#define FMC_BANK1 FMC_BASE
#define FMC_BANK1_1 FMC_BANK1
#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
#define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
#define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL)
#define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL)
#define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL)
#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
#define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL)
#define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL)
#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
/*!< AHB1 peripherals */
#define DMA1_BASE (AHB1PERIPH_BASE)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
/*!< AHB2 peripherals */
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)
#define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL)
#define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL)
#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)
#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL)
#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
#define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL)
#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL)
/*!< FMC Banks registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0042000UL)
#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
#define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE)
#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
#define ADC5 ((ADC_TypeDef *) ADC5_BASE)
#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
#define DAC4 ((DAC_TypeDef *) DAC4_BASE)
#define AES ((AES_TypeDef *) AES_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos (15U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
#define ADC_CFGR2_GCOMP_Pos (16U)
#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
#define ADC_CFGR2_SWTRIG_Pos (25U)
#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
#define ADC_CFGR2_BULB_Pos (26U)
#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
#define ADC_CFGR2_SMPTRIG_Pos (27U)
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_AWDFILT_Pos (12U)
#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSETPOS_Pos (24U)
#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
#define ADC_OFR1_SATEN_Pos (25U)
#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSETPOS_Pos (24U)
#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
#define ADC_OFR2_SATEN_Pos (25U)
#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSETPOS_Pos (24U)
#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
#define ADC_OFR3_SATEN_Pos (25U)
#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSETPOS_Pos (24U)
#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
#define ADC_OFR4_SATEN_Pos (25U)
#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
/******************** Bit definition for ADC_GCOMP register *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos (13U)
#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
#define ADC_CCR_MDMA_Pos (14U)
#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_VSENSESEL_Pos (23U)
#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATSEL_Pos (24U)
#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
/******************************************************************************/
/* */
/* Advanced Encryption Standard (AES) */
/* */
/******************************************************************************/
/******************* Bit definition for AES_CR register *********************/
#define AES_CR_EN_Pos (0U)
#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
#define AES_CR_DATATYPE_Pos (1U)
#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
#define AES_CR_MODE_Pos (3U)
#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
#define AES_CR_CHMOD_Pos (5U)
#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
#define AES_CR_CCFC_Pos (7U)
#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
#define AES_CR_ERRC_Pos (8U)
#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
#define AES_CR_CCFIE_Pos (9U)
#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
#define AES_CR_ERRIE_Pos (10U)
#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
#define AES_CR_DMAINEN_Pos (11U)
#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
#define AES_CR_DMAOUTEN_Pos (12U)
#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
#define AES_CR_GCMPH_Pos (13U)
#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
#define AES_CR_KEYSIZE_Pos (18U)
#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
#define AES_CR_NPBLB_Pos (20U)
#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */
#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */
#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */
#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */
#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */
#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */
/******************* Bit definition for AES_SR register *********************/
#define AES_SR_CCF_Pos (0U)
#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
#define AES_SR_RDERR_Pos (1U)
#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
#define AES_SR_WRERR_Pos (2U)
#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
#define AES_SR_BUSY_Pos (3U)
#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */
#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
/******************* Bit definition for AES_DINR register *******************/
#define AES_DINR_Pos (0U)
#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */
#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
/******************* Bit definition for AES_DOUTR register ******************/
#define AES_DOUTR_Pos (0U)
#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
/******************* Bit definition for AES_KEYR0 register ******************/
#define AES_KEYR0_Pos (0U)
#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
/******************* Bit definition for AES_KEYR1 register ******************/
#define AES_KEYR1_Pos (0U)
#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
/******************* Bit definition for AES_KEYR2 register ******************/
#define AES_KEYR2_Pos (0U)
#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
/******************* Bit definition for AES_KEYR3 register ******************/
#define AES_KEYR3_Pos (0U)
#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
/******************* Bit definition for AES_KEYR4 register ******************/
#define AES_KEYR4_Pos (0U)
#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
/******************* Bit definition for AES_KEYR5 register ******************/
#define AES_KEYR5_Pos (0U)
#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
/******************* Bit definition for AES_KEYR6 register ******************/
#define AES_KEYR6_Pos (0U)
#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
/******************* Bit definition for AES_KEYR7 register ******************/
#define AES_KEYR7_Pos (0U)
#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
/******************* Bit definition for AES_IVR0 register ******************/
#define AES_IVR0_Pos (0U)
#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
/******************* Bit definition for AES_IVR1 register ******************/
#define AES_IVR1_Pos (0U)
#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
/******************* Bit definition for AES_IVR2 register ******************/
#define AES_IVR2_Pos (0U)
#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
/******************* Bit definition for AES_IVR3 register ******************/
#define AES_IVR3_Pos (0U)
#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
/******************* Bit definition for AES_SUSP0R register ******************/
#define AES_SUSP0R_Pos (0U)
#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
/******************* Bit definition for AES_SUSP1R register ******************/
#define AES_SUSP1R_Pos (0U)
#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
/******************* Bit definition for AES_SUSP2R register ******************/
#define AES_SUSP2R_Pos (0U)
#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
/******************* Bit definition for AES_SUSP3R register ******************/
#define AES_SUSP3R_Pos (0U)
#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
/******************* Bit definition for AES_SUSP4R register ******************/
#define AES_SUSP4R_Pos (0U)
#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
/******************* Bit definition for AES_SUSP5R register ******************/
#define AES_SUSP5R_Pos (0U)
#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
/******************* Bit definition for AES_SUSP6R register ******************/
#define AES_SUSP6R_Pos (0U)
#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
/******************* Bit definition for AES_SUSP7R register ******************/
#define AES_SUSP7R_Pos (0U)
#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_INMSEL_Pos (4U)
#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_Pos (8U)
#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
#define COMP_CSR_BLANKING_Pos (19U)
#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
/* CORDIC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CORDIC_CSR register *****************/
#define CORDIC_CSR_FUNC_Pos (0U)
#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos (4U)
#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos (8U)
#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos (16U)
#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos (17U)
#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos (18U)
#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos (19U)
#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos (20U)
#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos (21U)
#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos (22U)
#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos (31U)
#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
/******************* Bit definition for CORDIC_WDATA register ***************/
#define CORDIC_WDATA_ARG_Pos (0U)
#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
/******************* Bit definition for CORDIC_RDATA register ***************/
#define CORDIC_RDATA_RES_Pos (0U)
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_Pos (16U)
#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
#define DAC_DOR2_DACC2DORB_Pos (16U)
#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DAC1RDY_Pos (11U)
#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
#define DAC_SR_DORSTAT1_Pos (12U)
#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
#define DAC_SR_DORSTAT2_Pos (28U)
#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos (8U)
#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos (9U)
#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
#define DAC_MCR_HFSEL_Pos (14U)
#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
#define DAC_MCR_DMADOUBLE2_Pos (24U)
#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
#define DAC_MCR_SINFORMAT2_Pos (25U)
#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR2_TSAMPLE2_Pos (0U)
#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/****************** Bit definition for DAC_STR1 register ******************/
#define DAC_STR1_STRSTDATA1_Pos (0U)
#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
#define DAC_STR1_STDIR1_Pos (12U)
#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
#define DAC_STR1_STINCDATA1_Pos (16U)
#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STR2 register ******************/
#define DAC_STR2_STRSTDATA2_Pos (0U)
#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
#define DAC_STR2_STDIR2_Pos (12U)
#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
#define DAC_STR2_STINCDATA2_Pos (16U)
#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STMODR register ****************/
#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
#define DBGMCU_CR_TRACE_MODE_Pos (6U)
#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos (24U)
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
#define DMA_ISR_GIF8_Pos (28U)
#define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos) /*!< 0x10000000 */
#define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk /*!< Channel 8 Global interrupt flag */
#define DMA_ISR_TCIF8_Pos (29U)
#define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos) /*!< 0x20000000 */
#define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk /*!< Channel 8 Transfer Complete flag */
#define DMA_ISR_HTIF8_Pos (30U)
#define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos) /*!< 0x40000000 */
#define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk /*!< Channel 8 Half Transfer flag */
#define DMA_ISR_TEIF8_Pos (31U)
#define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos) /*!< 0x80000000 */
#define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk /*!< Channel 8 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos (24U)
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
#define DMA_IFCR_CGIF8_Pos (28U)
#define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos) /*!< 0x10000000 */
#define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk /*!< Channel 8 Global interrupt clear */
#define DMA_IFCR_CTCIF8_Pos (29U)
#define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos) /*!< 0x20000000 */
#define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk /*!< Channel 8 Transfer Complete clear */
#define DMA_IFCR_CHTIF8_Pos (30U)
#define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos) /*!< 0x40000000 */
#define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk /*!< Channel 8 Half Transfer clear */
#define DMA_IFCR_CTEIF8_Pos (31U)
#define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos) /*!< 0x80000000 */
#define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk /*!< Channel 8 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register ****************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
#define DMAMUX_CSR_SOF12_Pos (12U)
#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
#define DMAMUX_CSR_SOF13_Pos (13U)
#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
#define DMAMUX_CSR_SOF14_Pos (14U)
#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
#define DMAMUX_CSR_SOF15_Pos (15U)
#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
/******************** Bits definition for DMAMUX_CFR register ****************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
#define DMAMUX_CFR_CSOF12_Pos (12U)
#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
#define DMAMUX_CFR_CSOF13_Pos (13U)
#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
#define DMAMUX_CFR_CSOF14_Pos (14U)
#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
#define DMAMUX_CFR_CSOF15_Pos (15U)
#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
/******************** Bits definition for DMAMUX_RGCFR register ************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos (31U)
#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos (31U)
#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/****************** Bit definition for EXTI_RTSR1 register ******************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT19_Pos (19U)
#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR1_RT22_Pos (22U)
#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR1_RT29_Pos (29U)
#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR1_RT30_Pos (30U)
#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
#define EXTI_RTSR1_RT31_Pos (31U)
#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */
#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_FT16_Pos (16U)
#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_FT17_Pos (17U)
#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_FT19_Pos (19U)
#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR1_FT22_Pos (22U)
#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR1_FT29_Pos (29U)
#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR1_FT30_Pos (30U)
#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
#define EXTI_FTSR1_FT31_Pos (31U)
#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */
#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos (16U)
#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos (17U)
#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI19_Pos (19U)
#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos (22U)
#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER1_SWI29_Pos (29U)
#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER1_SWI30_Pos (30U)
#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
#define EXTI_SWIER1_SWI31_Pos (31U)
#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */
#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */
/******************* Bit definition for EXTI_PR1 register *******************/
#define EXTI_PR1_PIF0_Pos (0U)
#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PIF1_Pos (1U)
#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PIF2_Pos (2U)
#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PIF3_Pos (3U)
#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PIF4_Pos (4U)
#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PIF5_Pos (5U)
#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PIF6_Pos (6U)
#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PIF7_Pos (7U)
#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PIF8_Pos (8U)
#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PIF9_Pos (9U)
#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PIF10_Pos (10U)
#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PIF11_Pos (11U)
#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PIF12_Pos (12U)
#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PIF13_Pos (13U)
#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PIF14_Pos (14U)
#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PIF15_Pos (15U)
#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PIF16_Pos (16U)
#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PIF17_Pos (17U)
#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR1_PIF19_Pos (19U)
#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PIF20_Pos (20U)
#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PIF21_Pos (21U)
#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR1_PIF22_Pos (22U)
#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR1_PIF29_Pos (29U)
#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR1_PIF30_Pos (30U)
#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
#define EXTI_PR1_PIF31_Pos (31U)
#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */
#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM32_Pos (0U)
#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM42_Pos (10U)
#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x7FFUL << EXTI_IMR2_IM_Pos) /*!< 0x000007FF */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM32_Pos (0U)
#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM42_Pos (10U)
#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x7FFUL << EXTI_EMR2_EM_Pos) /*!< 0x000007FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT32_Pos (0U)
#define EXTI_RTSR2_RT32_Msk (0x1UL << EXTI_RTSR2_RT32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_RT32_Msk /*!< Rising trigger event configuration bit of line 32 */
#define EXTI_RTSR2_RT33_Pos (1U)
#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */
#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */
#define EXTI_RTSR2_RT38_Pos (6U)
#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
#define EXTI_RTSR2_RT39_Pos (7U)
#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
#define EXTI_RTSR2_RT40_Pos (8U)
#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
#define EXTI_RTSR2_RT41_Pos (9U)
#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_FT32_Pos (0U)
#define EXTI_FTSR2_FT32_Msk (0x1UL << EXTI_FTSR2_FT32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_FT32_Msk /*!< Falling trigger event configuration bit of line 32 */
#define EXTI_FTSR2_FT33_Pos (1U)
#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */
#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */
#define EXTI_FTSR2_FT38_Pos (6U)
#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
#define EXTI_FTSR2_FT39_Pos (7U)
#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
#define EXTI_FTSR2_FT40_Pos (8U)
#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
#define EXTI_FTSR2_FT41_Pos (9U)
#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI32_Pos (0U)
#define EXTI_SWIER2_SWI32_Msk (0x1UL << EXTI_SWIER2_SWI32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWI32_Msk /*!< Software Interrupt on line 32 */
#define EXTI_SWIER2_SWI33_Pos (1U)
#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
#define EXTI_SWIER2_SWI38_Pos (6U)
#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
#define EXTI_SWIER2_SWI39_Pos (7U)
#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
#define EXTI_SWIER2_SWI40_Pos (8U)
#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
#define EXTI_SWIER2_SWI41_Pos (9U)
#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PIF32_Pos (0U)
#define EXTI_PR2_PIF32_Msk (0x1UL << EXTI_PR2_PIF32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PIF32 EXTI_PR2_PIF32_Msk /*!< Pending bit for line 32 */
#define EXTI_PR2_PIF33_Pos (1U)
#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */
#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */
#define EXTI_PR2_PIF38_Pos (6U)
#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
#define EXTI_PR2_PIF39_Pos (7U)
#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
#define EXTI_PR2_PIF40_Pos (8U)
#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
#define EXTI_PR2_PIF41_Pos (9U)
#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0F_Pos (1U)
#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (2U)
#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (3U)
#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1F_Pos (4U)
#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (5U)
#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (6U)
#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (7U)
#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (8U)
#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (9U)
#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (10U)
#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFF_Pos (11U)
#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (12U)
#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (13U)
#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (14U)
#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (15U)
#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_ELO_Pos (16U)
#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (17U)
#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (18U)
#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (19U)
#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (20U)
#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (21U)
#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (22U)
#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (23U)
#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0FE_Pos (1U)
#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (2U)
#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (3U)
#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1FE_Pos (4U)
#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (5U)
#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (6U)
#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (7U)
#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (8U)
#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos (9U)
#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (10U)
#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFFE_Pos (11U)
#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (12U)
#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (13U)
#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (14U)
#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (15U)
#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_ELOE_Pos (16U)
#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (17U)
#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (18U)
#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (19U)
#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (20U)
#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (21U)
#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos (22U)
#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (23U)
#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RXFIFO0_Pos (0U)
#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
Rx FIFO 0 is Full
Rx FIFO 0 Has New Message */
#define FDCAN_ILS_RXFIFO1_Pos (1U)
#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
Rx FIFO 1 is Full
Rx FIFO 1 Has New Message */
#define FDCAN_ILS_SMSG_Pos (2U)
#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
Transmission Completed
High Priority Message */
#define FDCAN_ILS_TFERR_Pos (3U)
#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
Tx Event FIFO Full
Tx Event FIFO New Entry
Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_MISC_Pos (4U)
#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
Message RAM Access Failure
Timestamp Wraparound */
#define FDCAN_ILS_BERR_Pos (5U)
#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
Error Logging Overflow */
#define FDCAN_ILS_PERR_Pos (6U)
#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
Protocol Error in Data Phase Line
Protocol Error in Arbitration Phase Line
Watchdog Interrupt Line
Bus_Off Status
Warning Status */
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_RXGFC register ********************/
#define FDCAN_RXGFC_RRFE_Pos (0U)
#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_RXGFC_RRFS_Pos (1U)
#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_RXGFC_ANFE_Pos (2U)
#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_RXGFC_ANFS_Pos (4U)
#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
#define FDCAN_RXGFC_F1OM_Pos (8U)
#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
#define FDCAN_RXGFC_F0OM_Pos (9U)
#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
#define FDCAN_RXGFC_LSS_Pos (16U)
#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
#define FDCAN_RXGFC_LSE_Pos (24U)
#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TFQM_Pos (24U)
#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CFIE_Pos (0U)
#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/*!<FDCAN config registers */
/***************** Bit definition for FDCAN_CKDIV register *********************/
#define FDCAN_CKDIV_PDIV_Pos (0U)
#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS (0x00000000U)
#define FLASH_ACR_LATENCY_1WS (0x00000001U)
#define FLASH_ACR_LATENCY_2WS (0x00000002U)
#define FLASH_ACR_LATENCY_3WS (0x00000003U)
#define FLASH_ACR_LATENCY_4WS (0x00000004U)
#define FLASH_ACR_LATENCY_5WS (0x00000005U)
#define FLASH_ACR_LATENCY_6WS (0x00000006U)
#define FLASH_ACR_LATENCY_7WS (0x00000007U)
#define FLASH_ACR_LATENCY_8WS (0x00000008U)
#define FLASH_ACR_LATENCY_9WS (0x00000009U)
#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_RUN_PD_Pos (13U)
#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
#define FLASH_ACR_SLEEP_PD_Pos (14U)
#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
#define FLASH_ACR_DBG_SWEN_Pos (18U)
#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_OPERR_Pos (1U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_PROGERR_Pos (3U)
#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_SIZERR_Pos (6U)
#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_MISERR_Pos (8U)
#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
#define FLASH_SR_FASTERR_Pos (9U)
#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
#define FLASH_SR_RDERR_Pos (14U)
#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_OPTVERR_Pos (15U)
#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PER_Pos (1U)
#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
#define FLASH_CR_PER FLASH_CR_PER_Msk
#define FLASH_CR_MER1_Pos (2U)
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_BKER_Pos (11U)
#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
#define FLASH_CR_BKER FLASH_CR_BKER_Msk
#define FLASH_CR_MER2_Pos (15U)
#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_OPTSTRT_Pos (17U)
#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
#define FLASH_CR_FSTPG_Pos (18U)
#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_RDERRIE_Pos (26U)
#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
#define FLASH_CR_SEC_PROT1_Pos (28U)
#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
#define FLASH_CR_SEC_PROT2_Pos (29U)
#define FLASH_CR_SEC_PROT2_Msk (0x1UL << FLASH_CR_SEC_PROT2_Pos) /*!< 0x20000000 */
#define FLASH_CR_SEC_PROT2 FLASH_CR_SEC_PROT2_Msk
#define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_ECCR register ***************/
#define FLASH_ECCR_ADDR_ECC_Pos (0U)
#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
#define FLASH_ECCR_BK_ECC_Pos (21U)
#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
#define FLASH_ECCR_SYSF_ECC_Pos (22U)
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
#define FLASH_ECCR_ECCIE_Pos (24U)
#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
#define FLASH_ECCR_ECCC2_Pos (28U)
#define FLASH_ECCR_ECCC2_Msk (0x1UL << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */
#define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
#define FLASH_ECCR_ECCD2_Pos (29U)
#define FLASH_ECCR_ECCD2_Msk (0x1UL << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */
#define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
#define FLASH_ECCR_ECCC_Pos (30U)
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
#define FLASH_ECCR_ECCD_Pos (31U)
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
/******************* Bits definition for FLASH_OPTR register ***************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
#define FLASH_OPTR_BOR_LEV_Pos (8U)
#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
#define FLASH_OPTR_nRST_STOP_Pos (12U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
#define FLASH_OPTR_nRST_STDBY_Pos (13U)
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
#define FLASH_OPTR_WWDG_SW_Pos (19U)
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
#define FLASH_OPTR_BFB2_Pos (20U)
#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
#define FLASH_OPTR_DBANK_Pos (22U)
#define FLASH_OPTR_DBANK_Msk (0x1UL << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */
#define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
#define FLASH_OPTR_nBOOT1_Pos (23U)
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
#define FLASH_OPTR_SRAM_PE_Pos (24U)
#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
#define FLASH_OPTR_nSWBOOT0_Pos (26U)
#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
#define FLASH_OPTR_nBOOT0_Pos (27U)
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
#define FLASH_OPTR_NRST_MODE_Pos (28U)
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
#define FLASH_OPTR_IRHEN_Pos (30U)
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
/****************** Bits definition for FLASH_PCROP1SR register **********/
#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
/****************** Bits definition for FLASH_PCROP1ER register ***********/
#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
#define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_PCROP2SR register **********/
#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
/****************** Bits definition for FLASH_PCROP2ER register ***********/
#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
#define FLASH_PCROP2ER_PCROP2_END_Msk (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
/****************** Bits definition for FLASH_WRP2AR register ***************/
#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
#define FLASH_WRP2AR_WRP2A_STRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)/*!< 0x000000FF */
#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
#define FLASH_WRP2AR_WRP2A_END_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)/*!< 0x00FF0000 */
#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
/****************** Bits definition for FLASH_WRP2BR register ***************/
#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
#define FLASH_WRP2BR_WRP2B_STRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
#define FLASH_WRP2BR_WRP2B_END_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
/****************** Bits definition for FLASH_SEC1R register **************/
#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
#define FLASH_SEC1R_SEC_SIZE1_Msk (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
/****************** Bits definition for FLASH_SEC2R register **************/
#define FLASH_SEC2R_SEC_SIZE2_Pos (0U)
#define FLASH_SEC2R_SEC_SIZE2_Msk (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)/*!< 0x000000FF */
#define FLASH_SEC2R_SEC_SIZE2 FLASH_SEC2R_SEC_SIZE2_Msk
/******************************************************************************/
/* */
/* Filter Mathematical ACcelerator unit (FMAC) */
/* */
/******************************************************************************/
/***************** Bit definition for FMAC_X1BUFCFG register ****************/
#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
/***************** Bit definition for FMAC_X2BUFCFG register ****************/
#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
/***************** Bit definition for FMAC_YBUFCFG register *****************/
#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
/****************** Bit definition for FMAC_PARAM register ******************/
#define FMAC_PARAM_P_Pos (0U)
#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
#define FMAC_PARAM_Q_Pos (8U)
#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
#define FMAC_PARAM_R_Pos (16U)
#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
#define FMAC_PARAM_FUNC_Pos (24U)
#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
#define FMAC_PARAM_START_Pos (31U)
#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
/******************** Bit definition for FMAC_CR register *******************/
#define FMAC_CR_RIEN_Pos (0U)
#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
#define FMAC_CR_WIEN_Pos (1U)
#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
#define FMAC_CR_OVFLIEN_Pos (2U)
#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
#define FMAC_CR_UNFLIEN_Pos (3U)
#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
#define FMAC_CR_SATIEN_Pos (4U)
#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
#define FMAC_CR_DMAREN_Pos (8U)
#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
#define FMAC_CR_DMAWEN_Pos (9U)
#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
#define FMAC_CR_CLIPEN_Pos (15U)
#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
#define FMAC_CR_RESET_Pos (16U)
#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
/******************* Bit definition for FMAC_SR register ********************/
#define FMAC_SR_YEMPTY_Pos (0U)
#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
#define FMAC_SR_X1FULL_Pos (1U)
#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
#define FMAC_SR_OVFL_Pos (8U)
#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
#define FMAC_SR_UNFL_Pos (9U)
#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
#define FMAC_SR_SAT_Pos (10U)
#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
/****************** Bit definition for FMAC_WDATA register ******************/
#define FMAC_WDATA_WDATA_Pos (0U)
#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
/****************** Bit definition for FMACX_RDATA register *****************/
#define FMAC_RDATA_RDATA_Pos (0U)
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
/******************************************************************************/
/* */
/* Flexible Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCRx_MUXEN_Pos (1U)
#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCRx_MTYP_Pos (2U)
#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCRx_MWID_Pos (4U)
#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCRx_FACCEN_Pos (6U)
#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCRx_BURSTEN_Pos (8U)
#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCRx_WAITPOL_Pos (9U)
#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCRx_WAITCFG_Pos (11U)
#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCRx_WREN_Pos (12U)
#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
#define FMC_BCRx_WAITEN_Pos (13U)
#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCRx_EXTMOD_Pos (14U)
#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCRx_ASYNCWAIT_Pos (15U)
#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCRx_CPSIZE_Pos (16U)
#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCRx_CBURSTRW_Pos (19U)
#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCRx_NBLSET_Pos (22U)
#define FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */
#define FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00500000 */
#define FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
#define FMC_BTRx_ADDSET_Pos (0U)
#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTRx_ADDHLD_Pos (4U)
#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTRx_DATAST_Pos (8U)
#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTRx_BUSTURN_Pos (16U)
#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTRx_CLKDIV_Pos (20U)
#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTRx_DATLAT_Pos (24U)
#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTRx_ACCMOD_Pos (28U)
#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTRx_DATAHLD_Pos (30U)
#define FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
#define FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
#define FMC_BWTRx_ADDSET_Pos (0U)
#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTRx_ADDHLD_Pos (4U)
#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTRx_DATAST_Pos (8U)
#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTRx_BUSTURN_Pos (16U)
#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTRx_ACCMOD_Pos (28U)
#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTRx_DATAHLD_Pos (30U)
#define FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
#define FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PCSCNTR register ******************/
#define FMC_PCSCNTR_CSCOUNT_Pos (0U)
#define FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos) /*!< 0x0000FFFF */
#define FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk /*!<CSCOUNT[15:0] bits (Chip select counter) */
#define FMC_PCSCNTR_CNTB1EN_Pos (16U)
#define FMC_PCSCNTR_CNTB1EN_Msk (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos) /*!< 0x00010000 */
#define FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk /*!<Counter PSRAM/NOR Bank1_1 enable */
#define FMC_PCSCNTR_CNTB2EN_Pos (17U)
#define FMC_PCSCNTR_CNTB2EN_Msk (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos) /*!< 0x00020000 */
#define FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk /*!<Counter PSRAM/NOR Bank1_2 enable */
#define FMC_PCSCNTR_CNTB3EN_Pos (18U)
#define FMC_PCSCNTR_CNTB3EN_Msk (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos) /*!< 0x00040000 */
#define FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk /*!<Counter PSRAM/NOR Bank1_3 enable */
#define FMC_PCSCNTR_CNTB4EN_Pos (19U)
#define FMC_PCSCNTR_CNTB4EN_Msk (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos) /*!< 0x00080000 */
#define FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk /*!<Counter PSRAM/NOR Bank1_4 enable */
/****************** Bit definition for FMC_PCR register ********************/
#define FMC_PCR_PWAITEN_Pos (1U)
#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
#define FMC_PCR_PBKEN_Pos (2U)
#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
#define FMC_PCR_PTYP_Pos (3U)
#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
#define FMC_PCR_PWID_Pos (4U)
#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
#define FMC_PCR_ECCEN_Pos (6U)
#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
#define FMC_PCR_TCLR_Pos (9U)
#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
#define FMC_PCR_TAR_Pos (13U)
#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
#define FMC_PCR_ECCPS_Pos (17U)
#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
/******************* Bit definition for FMC_SR register ********************/
#define FMC_SR_IRS_Pos (0U)
#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
#define FMC_SR_ILS_Pos (1U)
#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
#define FMC_SR_IFS_Pos (2U)
#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
#define FMC_SR_IREN_Pos (3U)
#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
#define FMC_SR_ILEN_Pos (4U)
#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
#define FMC_SR_IFEN_Pos (5U)
#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
#define FMC_SR_FEMPT_Pos (6U)
#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
/****************** Bit definition for FMC_PMEM register ******************/
#define FMC_PMEM_MEMSET_Pos (0U)
#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
#define FMC_PMEM_MEMWAIT_Pos (8U)
#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
#define FMC_PMEM_MEMHOLD_Pos (16U)
#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
#define FMC_PMEM_MEMHIZ_Pos (24U)
#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PATT register *******************/
#define FMC_PATT_ATTSET_Pos (0U)
#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
#define FMC_PATT_ATTWAIT_Pos (8U)
#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
#define FMC_PATT_ATTHOLD_Pos (16U)
#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
#define FMC_PATT_ATTHIZ_Pos (24U)
#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_ECCR register *******************/
#define FMC_ECCR_ECC_Pos (0U)
#define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/* Legacy defines */
#define GPIO_BRR_BR_0 GPIO_BRR_BR0
#define GPIO_BRR_BR_1 GPIO_BRR_BR1
#define GPIO_BRR_BR_2 GPIO_BRR_BR2
#define GPIO_BRR_BR_3 GPIO_BRR_BR3
#define GPIO_BRR_BR_4 GPIO_BRR_BR4
#define GPIO_BRR_BR_5 GPIO_BRR_BR5
#define GPIO_BRR_BR_6 GPIO_BRR_BR6
#define GPIO_BRR_BR_7 GPIO_BRR_BR7
#define GPIO_BRR_BR_8 GPIO_BRR_BR8
#define GPIO_BRR_BR_9 GPIO_BRR_BR9
#define GPIO_BRR_BR_10 GPIO_BRR_BR10
#define GPIO_BRR_BR_11 GPIO_BRR_BR11
#define GPIO_BRR_BR_12 GPIO_BRR_BR12
#define GPIO_BRR_BR_13 GPIO_BRR_BR13
#define GPIO_BRR_BR_14 GPIO_BRR_BR14
#define GPIO_BRR_BR_15 GPIO_BRR_BR15
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_USERTRIM_Pos (4U)
#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
#define OPAMP_CSR_OPAMPINTEN_Pos (8U)
#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
#define OPAMP_CSR_OUTCAL_Pos (30U)
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
#define OPAMP_CSR_LOCK_Pos (31U)
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
/********************* Bit definition for OPAMPx_TCMR register ***************/
#define OPAMP_TCMR_VMSSEL_Pos (0U)
#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
#define OPAMP_TCMR_VPSSEL_Pos (1U)
#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
#define OPAMP_TCMR_T1CMEN_Pos (3U)
#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
#define OPAMP_TCMR_T8CMEN_Pos (4U)
#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
#define OPAMP_TCMR_T20CMEN_Pos (5U)
#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
#define OPAMP_TCMR_LOCK_Pos (31U)
#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_LPR_Pos (14U)
#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
#define PWR_CR1_VOS_Pos (9U)
#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_LPMS_Pos (0U)
#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
#define PWR_CR1_LPMS_STOP1_Pos (0U)
#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
#define PWR_CR1_LPMS_STANDBY_Pos (0U)
#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
/******************** Bit definition for PWR_CR2 register ********************/
/*!< PVME Peripheral Voltage Monitor Enable */
#define PWR_CR2_PVME_Pos (4U)
#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
#define PWR_CR2_PVME4_Pos (7U)
#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
#define PWR_CR2_PVME3_Pos (6U)
#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
#define PWR_CR2_PVME2_Pos (5U)
#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
#define PWR_CR2_PVME1_Pos (4U)
#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
/*!< PVD level configuration */
#define PWR_CR2_PLS_Pos (1U)
#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
#define PWR_CR2_PLS_LEV1_Pos (1U)
#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR2_PLS_LEV2_Pos (2U)
#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR2_PLS_LEV3_Pos (1U)
#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR2_PLS_LEV4_Pos (3U)
#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR2_PLS_LEV5_Pos (1U)
#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR2_PLS_LEV6_Pos (2U)
#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR2_PLS_LEV7_Pos (1U)
#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
#define PWR_CR2_PVDE_Pos (0U)
#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EIWF_Pos (15U)
#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
#define PWR_CR3_UCPD_DBDIS_Pos (14U)
#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
#define PWR_CR3_UCPD_STDBY_Pos (13U)
#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
#define PWR_CR3_APC_Pos (10U)
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
#define PWR_CR3_RRS_Pos (8U)
#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
#define PWR_CR3_EWUP5_Pos (4U)
#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
#define PWR_CR3_EWUP4_Pos (3U)
#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
#define PWR_CR3_EWUP3_Pos (2U)
#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
#define PWR_CR3_EWUP2_Pos (1U)
#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
#define PWR_CR3_EWUP1_Pos (0U)
#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
#define PWR_CR3_EWUP_Pos (0U)
#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
/******************** Bit definition for PWR_CR4 register ********************/
#define PWR_CR4_VBRS_Pos (9U)
#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
#define PWR_CR4_VBE_Pos (8U)
#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
#define PWR_CR4_WP5_Pos (4U)
#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
#define PWR_CR4_WP4_Pos (3U)
#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
#define PWR_CR4_WP3_Pos (2U)
#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
#define PWR_CR4_WP2_Pos (1U)
#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
#define PWR_CR4_WP1_Pos (0U)
#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
/******************** Bit definition for PWR_SR1 register ********************/
#define PWR_SR1_WUFI_Pos (15U)
#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
#define PWR_SR1_SBF_Pos (8U)
#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
#define PWR_SR1_WUF_Pos (0U)
#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
#define PWR_SR1_WUF5_Pos (4U)
#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
#define PWR_SR1_WUF4_Pos (3U)
#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
#define PWR_SR1_WUF3_Pos (2U)
#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
#define PWR_SR1_WUF2_Pos (1U)
#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
#define PWR_SR1_WUF1_Pos (0U)
#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
/******************** Bit definition for PWR_SR2 register ********************/
#define PWR_SR2_PVMO4_Pos (15U)
#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
#define PWR_SR2_PVMO3_Pos (14U)
#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
#define PWR_SR2_PVMO2_Pos (13U)
#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
#define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
#define PWR_SR2_VOSF_Pos (10U)
#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
#define PWR_SR2_REGLPF_Pos (9U)
#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
#define PWR_SR2_REGLPS_Pos (8U)
#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CSBF_Pos (8U)
#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
#define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
#define PWR_SCR_CWUF5_Pos (4U)
#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
#define PWR_SCR_CWUF4_Pos (3U)
#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
#define PWR_SCR_CWUF3_Pos (2U)
#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
#define PWR_SCR_CWUF2_Pos (1U)
#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
#define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
/******************** Bit definition for PWR_PUCRA register ********************/
#define PWR_PUCRA_PA15_Pos (15U)
#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
#define PWR_PUCRA_PA13_Pos (13U)
#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
#define PWR_PUCRA_PA12_Pos (12U)
#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
#define PWR_PUCRA_PA11_Pos (11U)
#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
#define PWR_PUCRA_PA10_Pos (10U)
#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
#define PWR_PUCRA_PA9_Pos (9U)
#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
#define PWR_PUCRA_PA8_Pos (8U)
#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
#define PWR_PUCRA_PA7_Pos (7U)
#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
#define PWR_PUCRA_PA6_Pos (6U)
#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
#define PWR_PUCRA_PA5_Pos (5U)
#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
#define PWR_PUCRA_PA4_Pos (4U)
#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
#define PWR_PUCRA_PA3_Pos (3U)
#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
#define PWR_PUCRA_PA2_Pos (2U)
#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
#define PWR_PUCRA_PA1_Pos (1U)
#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
#define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
/******************** Bit definition for PWR_PDCRA register ********************/
#define PWR_PDCRA_PA14_Pos (14U)
#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
#define PWR_PDCRA_PA12_Pos (12U)
#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
#define PWR_PDCRA_PA11_Pos (11U)
#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
#define PWR_PDCRA_PA10_Pos (10U)
#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
#define PWR_PDCRA_PA9_Pos (9U)
#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
#define PWR_PDCRA_PA8_Pos (8U)
#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
#define PWR_PDCRA_PA7_Pos (7U)
#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
#define PWR_PDCRA_PA6_Pos (6U)
#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
#define PWR_PDCRA_PA5_Pos (5U)
#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
#define PWR_PDCRA_PA4_Pos (4U)
#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
#define PWR_PDCRA_PA3_Pos (3U)
#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
#define PWR_PDCRA_PA2_Pos (2U)
#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
#define PWR_PDCRA_PA1_Pos (1U)
#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
#define PWR_PDCRA_PA0_Pos (0U)
#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
/******************** Bit definition for PWR_PUCRB register ********************/
#define PWR_PUCRB_PB15_Pos (15U)
#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
#define PWR_PUCRB_PB14_Pos (14U)
#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
#define PWR_PUCRB_PB13_Pos (13U)
#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
#define PWR_PUCRB_PB12_Pos (12U)
#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
#define PWR_PUCRB_PB11_Pos (11U)
#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
#define PWR_PUCRB_PB10_Pos (10U)
#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
#define PWR_PUCRB_PB9_Pos (9U)
#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
#define PWR_PUCRB_PB8_Pos (8U)
#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
#define PWR_PUCRB_PB7_Pos (7U)
#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
#define PWR_PUCRB_PB6_Pos (6U)
#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
#define PWR_PUCRB_PB5_Pos (5U)
#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
#define PWR_PUCRB_PB4_Pos (4U)
#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
#define PWR_PUCRB_PB3_Pos (3U)
#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
#define PWR_PUCRB_PB2_Pos (2U)
#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
#define PWR_PUCRB_PB1_Pos (1U)
#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
#define PWR_PUCRB_PB0_Pos (0U)
#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
/******************** Bit definition for PWR_PDCRB register ********************/
#define PWR_PDCRB_PB15_Pos (15U)
#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
#define PWR_PDCRB_PB14_Pos (14U)
#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
#define PWR_PDCRB_PB13_Pos (13U)
#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
#define PWR_PDCRB_PB12_Pos (12U)
#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
#define PWR_PDCRB_PB11_Pos (11U)
#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
#define PWR_PDCRB_PB10_Pos (10U)
#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
#define PWR_PDCRB_PB9_Pos (9U)
#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
#define PWR_PDCRB_PB8_Pos (8U)
#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
#define PWR_PDCRB_PB7_Pos (7U)
#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
#define PWR_PDCRB_PB6_Pos (6U)
#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
#define PWR_PDCRB_PB5_Pos (5U)
#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
#define PWR_PDCRB_PB3_Pos (3U)
#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
#define PWR_PDCRB_PB2_Pos (2U)
#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
#define PWR_PDCRB_PB1_Pos (1U)
#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
#define PWR_PDCRB_PB0_Pos (0U)
#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
/******************** Bit definition for PWR_PUCRC register ********************/
#define PWR_PUCRC_PC15_Pos (15U)
#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
#define PWR_PUCRC_PC14_Pos (14U)
#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
#define PWR_PUCRC_PC13_Pos (13U)
#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
#define PWR_PUCRC_PC12_Pos (12U)
#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
#define PWR_PUCRC_PC11_Pos (11U)
#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
#define PWR_PUCRC_PC10_Pos (10U)
#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
#define PWR_PUCRC_PC9_Pos (9U)
#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
#define PWR_PUCRC_PC8_Pos (8U)
#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
#define PWR_PUCRC_PC7_Pos (7U)
#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
#define PWR_PUCRC_PC6_Pos (6U)
#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
#define PWR_PUCRC_PC5_Pos (5U)
#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
#define PWR_PUCRC_PC4_Pos (4U)
#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
#define PWR_PUCRC_PC3_Pos (3U)
#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
#define PWR_PUCRC_PC2_Pos (2U)
#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
#define PWR_PUCRC_PC1_Pos (1U)
#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
#define PWR_PUCRC_PC0_Pos (0U)
#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
/******************** Bit definition for PWR_PDCRC register ********************/
#define PWR_PDCRC_PC15_Pos (15U)
#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
#define PWR_PDCRC_PC14_Pos (14U)
#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
#define PWR_PDCRC_PC13_Pos (13U)
#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
#define PWR_PDCRC_PC12_Pos (12U)
#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
#define PWR_PDCRC_PC11_Pos (11U)
#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
#define PWR_PDCRC_PC10_Pos (10U)
#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
#define PWR_PDCRC_PC9_Pos (9U)
#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
#define PWR_PDCRC_PC8_Pos (8U)
#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
#define PWR_PDCRC_PC7_Pos (7U)
#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
#define PWR_PDCRC_PC6_Pos (6U)
#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
#define PWR_PDCRC_PC5_Pos (5U)
#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
#define PWR_PDCRC_PC4_Pos (4U)
#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
#define PWR_PDCRC_PC3_Pos (3U)
#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
#define PWR_PDCRC_PC2_Pos (2U)
#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
#define PWR_PDCRC_PC1_Pos (1U)
#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
#define PWR_PDCRC_PC0_Pos (0U)
#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
/******************** Bit definition for PWR_PUCRD register ********************/
#define PWR_PUCRD_PD15_Pos (15U)
#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
#define PWR_PUCRD_PD14_Pos (14U)
#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
#define PWR_PUCRD_PD13_Pos (13U)
#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
#define PWR_PUCRD_PD12_Pos (12U)
#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
#define PWR_PUCRD_PD11_Pos (11U)
#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
#define PWR_PUCRD_PD10_Pos (10U)
#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
#define PWR_PUCRD_PD9_Pos (9U)
#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
#define PWR_PUCRD_PD8_Pos (8U)
#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
#define PWR_PUCRD_PD7_Pos (7U)
#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
#define PWR_PUCRD_PD6_Pos (6U)
#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
#define PWR_PUCRD_PD5_Pos (5U)
#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
#define PWR_PUCRD_PD4_Pos (4U)
#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
#define PWR_PUCRD_PD3_Pos (3U)
#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
#define PWR_PUCRD_PD2_Pos (2U)
#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
#define PWR_PUCRD_PD1_Pos (1U)
#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
#define PWR_PUCRD_PD0_Pos (0U)
#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register ********************/
#define PWR_PDCRD_PD15_Pos (15U)
#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
#define PWR_PDCRD_PD14_Pos (14U)
#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
#define PWR_PDCRD_PD13_Pos (13U)
#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
#define PWR_PDCRD_PD12_Pos (12U)
#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
#define PWR_PDCRD_PD11_Pos (11U)
#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
#define PWR_PDCRD_PD10_Pos (10U)
#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
#define PWR_PDCRD_PD9_Pos (9U)
#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
#define PWR_PDCRD_PD8_Pos (8U)
#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
#define PWR_PDCRD_PD7_Pos (7U)
#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
#define PWR_PDCRD_PD6_Pos (6U)
#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
#define PWR_PDCRD_PD5_Pos (5U)
#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
#define PWR_PDCRD_PD4_Pos (4U)
#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
#define PWR_PDCRD_PD3_Pos (3U)
#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
#define PWR_PDCRD_PD2_Pos (2U)
#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
#define PWR_PDCRD_PD1_Pos (1U)
#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
/******************** Bit definition for PWR_PUCRE register ********************/
#define PWR_PUCRE_PE15_Pos (15U)
#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
#define PWR_PUCRE_PE14_Pos (14U)
#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
#define PWR_PUCRE_PE13_Pos (13U)
#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
#define PWR_PUCRE_PE12_Pos (12U)
#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
#define PWR_PUCRE_PE11_Pos (11U)
#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
#define PWR_PUCRE_PE10_Pos (10U)
#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
#define PWR_PUCRE_PE9_Pos (9U)
#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
#define PWR_PUCRE_PE8_Pos (8U)
#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
#define PWR_PUCRE_PE7_Pos (7U)
#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
#define PWR_PUCRE_PE6_Pos (6U)
#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
#define PWR_PUCRE_PE5_Pos (5U)
#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
#define PWR_PUCRE_PE4_Pos (4U)
#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
#define PWR_PUCRE_PE3_Pos (3U)
#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
#define PWR_PUCRE_PE2_Pos (2U)
#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
#define PWR_PUCRE_PE1_Pos (1U)
#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
#define PWR_PUCRE_PE0_Pos (0U)
#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
/******************** Bit definition for PWR_PDCRE register ********************/
#define PWR_PDCRE_PE15_Pos (15U)
#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
#define PWR_PDCRE_PE14_Pos (14U)
#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
#define PWR_PDCRE_PE13_Pos (13U)
#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
#define PWR_PDCRE_PE12_Pos (12U)
#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
#define PWR_PDCRE_PE11_Pos (11U)
#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
#define PWR_PDCRE_PE10_Pos (10U)
#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
#define PWR_PDCRE_PE9_Pos (9U)
#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
#define PWR_PDCRE_PE8_Pos (8U)
#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
#define PWR_PDCRE_PE7_Pos (7U)
#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
#define PWR_PDCRE_PE6_Pos (6U)
#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
#define PWR_PDCRE_PE5_Pos (5U)
#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
#define PWR_PDCRE_PE4_Pos (4U)
#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
#define PWR_PDCRE_PE3_Pos (3U)
#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
#define PWR_PDCRE_PE2_Pos (2U)
#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
#define PWR_PDCRE_PE1_Pos (1U)
#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
#define PWR_PDCRE_PE0_Pos (0U)
#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
/******************** Bit definition for PWR_PUCRF register ********************/
#define PWR_PUCRF_PF15_Pos (15U)
#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
#define PWR_PUCRF_PF14_Pos (14U)
#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
#define PWR_PUCRF_PF13_Pos (13U)
#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
#define PWR_PUCRF_PF12_Pos (12U)
#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
#define PWR_PUCRF_PF11_Pos (11U)
#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
#define PWR_PUCRF_PF10_Pos (10U)
#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
#define PWR_PUCRF_PF9_Pos (9U)
#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
#define PWR_PUCRF_PF8_Pos (8U)
#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
#define PWR_PUCRF_PF7_Pos (7U)
#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
#define PWR_PUCRF_PF6_Pos (6U)
#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
#define PWR_PUCRF_PF5_Pos (5U)
#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
#define PWR_PUCRF_PF4_Pos (4U)
#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
#define PWR_PUCRF_PF3_Pos (3U)
#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
#define PWR_PUCRF_PF2_Pos (2U)
#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
#define PWR_PUCRF_PF1_Pos (1U)
#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
#define PWR_PUCRF_PF0_Pos (0U)
#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
/******************** Bit definition for PWR_PDCRF register ********************/
#define PWR_PDCRF_PF15_Pos (15U)
#define PWR_PDCRF_PF15_Msk (0x1UL << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
#define PWR_PDCRF_PF14_Pos (14U)
#define PWR_PDCRF_PF14_Msk (0x1UL << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
#define PWR_PDCRF_PF13_Pos (13U)
#define PWR_PDCRF_PF13_Msk (0x1UL << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
#define PWR_PDCRF_PF12_Pos (12U)
#define PWR_PDCRF_PF12_Msk (0x1UL << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
#define PWR_PDCRF_PF11_Pos (11U)
#define PWR_PDCRF_PF11_Msk (0x1UL << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
#define PWR_PDCRF_PF10_Pos (10U)
#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
#define PWR_PDCRF_PF9_Pos (9U)
#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
#define PWR_PDCRF_PF8_Pos (8U)
#define PWR_PDCRF_PF8_Msk (0x1UL << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
#define PWR_PDCRF_PF7_Pos (7U)
#define PWR_PDCRF_PF7_Msk (0x1UL << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
#define PWR_PDCRF_PF6_Pos (6U)
#define PWR_PDCRF_PF6_Msk (0x1UL << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
#define PWR_PDCRF_PF5_Pos (5U)
#define PWR_PDCRF_PF5_Msk (0x1UL << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
#define PWR_PDCRF_PF4_Pos (4U)
#define PWR_PDCRF_PF4_Msk (0x1UL << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
#define PWR_PDCRF_PF3_Pos (3U)
#define PWR_PDCRF_PF3_Msk (0x1UL << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
#define PWR_PDCRF_PF2_Pos (2U)
#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
#define PWR_PDCRF_PF1_Pos (1U)
#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
#define PWR_PDCRF_PF0_Pos (0U)
#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
/******************** Bit definition for PWR_PUCRG register ********************/
#define PWR_PUCRG_PG15_Pos (15U)
#define PWR_PUCRG_PG15_Msk (0x1UL << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
#define PWR_PUCRG_PG14_Pos (14U)
#define PWR_PUCRG_PG14_Msk (0x1UL << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
#define PWR_PUCRG_PG13_Pos (13U)
#define PWR_PUCRG_PG13_Msk (0x1UL << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
#define PWR_PUCRG_PG12_Pos (12U)
#define PWR_PUCRG_PG12_Msk (0x1UL << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
#define PWR_PUCRG_PG11_Pos (11U)
#define PWR_PUCRG_PG11_Msk (0x1UL << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
#define PWR_PUCRG_PG10_Pos (10U)
#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
#define PWR_PUCRG_PG9_Pos (9U)
#define PWR_PUCRG_PG9_Msk (0x1UL << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
#define PWR_PUCRG_PG8_Pos (8U)
#define PWR_PUCRG_PG8_Msk (0x1UL << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
#define PWR_PUCRG_PG7_Pos (7U)
#define PWR_PUCRG_PG7_Msk (0x1UL << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
#define PWR_PUCRG_PG6_Pos (6U)
#define PWR_PUCRG_PG6_Msk (0x1UL << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
#define PWR_PUCRG_PG5_Pos (5U)
#define PWR_PUCRG_PG5_Msk (0x1UL << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
#define PWR_PUCRG_PG4_Pos (4U)
#define PWR_PUCRG_PG4_Msk (0x1UL << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
#define PWR_PUCRG_PG3_Pos (3U)
#define PWR_PUCRG_PG3_Msk (0x1UL << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
#define PWR_PUCRG_PG2_Pos (2U)
#define PWR_PUCRG_PG2_Msk (0x1UL << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
#define PWR_PUCRG_PG1_Pos (1U)
#define PWR_PUCRG_PG1_Msk (0x1UL << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
#define PWR_PUCRG_PG0_Pos (0U)
#define PWR_PUCRG_PG0_Msk (0x1UL << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
/******************** Bit definition for PWR_PDCRG register ********************/
#define PWR_PDCRG_PG10_Pos (10U)
#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
#define PWR_PDCRG_PG9_Pos (9U)
#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
#define PWR_PDCRG_PG8_Pos (8U)
#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
#define PWR_PDCRG_PG7_Pos (7U)
#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
#define PWR_PDCRG_PG6_Pos (6U)
#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
#define PWR_PDCRG_PG5_Pos (5U)
#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
#define PWR_PDCRG_PG4_Pos (4U)
#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
#define PWR_PDCRG_PG3_Pos (3U)
#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
#define PWR_PDCRG_PG2_Pos (2U)
#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
#define PWR_PDCRG_PG1_Pos (1U)
#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
#define PWR_PDCRG_PG0_Pos (0U)
#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
/******************** Bit definition for PWR_CR5 register ********************/
#define PWR_CR5_R1MODE_Pos (8U)
#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
/******************************************************************************/
/* */
/* QUADSPI */
/* */
/******************************************************************************/
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
#define QUADSPI_CR_ABORT_Pos (1U)
#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
#define QUADSPI_CR_SSHIFT_Pos (4U)
#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
#define QUADSPI_CR_DFM_Pos (6U)
#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
#define QUADSPI_CR_FSEL_Pos (7U)
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
#define QUADSPI_CR_FTHRES_Pos (8U)
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
#define QUADSPI_CR_TEIE_Pos (16U)
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define QUADSPI_CR_TCIE_Pos (17U)
#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define QUADSPI_CR_FTIE_Pos (18U)
#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
#define QUADSPI_CR_SMIE_Pos (19U)
#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
#define QUADSPI_CR_TOIE_Pos (20U)
#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
#define QUADSPI_CR_APMS_Pos (22U)
#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
#define QUADSPI_CR_PMM_Pos (23U)
#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
#define QUADSPI_CR_PRESCALER_Pos (24U)
#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
/***************** Bit definition for QUADSPI_DCR register ******************/
#define QUADSPI_DCR_CKMODE_Pos (0U)
#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
#define QUADSPI_DCR_CSHT_Pos (8U)
#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_FSIZE_Pos (16U)
#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
/****************** Bit definition for QUADSPI_SR register *******************/
#define QUADSPI_SR_TEF_Pos (0U)
#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
#define QUADSPI_SR_TCF_Pos (1U)
#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
#define QUADSPI_SR_FTF_Pos (2U)
#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_SMF_Pos (3U)
#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
#define QUADSPI_SR_TOF_Pos (4U)
#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
#define QUADSPI_SR_BUSY_Pos (5U)
#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
#define QUADSPI_SR_FLEVEL_Pos (8U)
#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
/****************** Bit definition for QUADSPI_FCR register ******************/
#define QUADSPI_FCR_CTEF_Pos (0U)
#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
#define QUADSPI_FCR_CTCF_Pos (1U)
#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
#define QUADSPI_FCR_CSMF_Pos (3U)
#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
#define QUADSPI_FCR_CTOF_Pos (4U)
#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
/****************** Bit definition for QUADSPI_DLR register ******************/
#define QUADSPI_DLR_DL_Pos (0U)
#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
/****************** Bit definition for QUADSPI_CCR register ******************/
#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_IMODE_Pos (8U)
#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_ADMODE_Pos (10U)
#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADSIZE_Pos (12U)
#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ABMODE_Pos (14U)
#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABSIZE_Pos (16U)
#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_DCYC_Pos (18U)
#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DMODE_Pos (24U)
#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_FMODE_Pos (26U)
#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_SIOO_Pos (28U)
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_DHHC_Pos (30U)
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
#define QUADSPI_CCR_DDRM_Pos (31U)
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
/****************** Bit definition for QUADSPI_AR register *******************/
#define QUADSPI_AR_ADDRESS_Pos (0U)
#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
/****************** Bit definition for QUADSPI_ABR register ******************/
#define QUADSPI_ABR_ALTERNATE_Pos (0U)
#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
/****************** Bit definition for QUADSPI_DR register *******************/
#define QUADSPI_DR_DATA_Pos (0U)
#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
/****************** Bit definition for QUADSPI_PSMKR register ****************/
#define QUADSPI_PSMKR_MASK_Pos (0U)
#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
/****************** Bit definition for QUADSPI_PSMAR register ****************/
#define QUADSPI_PSMAR_MATCH_Pos (0U)
#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
/****************** Bit definition for QUADSPI_PIR register *****************/
#define QUADSPI_PIR_INTERVAL_Pos (0U)
#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
/****************** Bit definition for QUADSPI_LPTR register *****************/
#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (8U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
#define RCC_CR_HSIKERON_Pos (9U)
#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
#define RCC_CR_HSIRDY_Pos (10U)
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
#define RCC_CR_HSEON_Pos (16U)
#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
#define RCC_CR_PLLON_Pos (24U)
#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (16U)
#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
/*!< MCOSEL configuration */
#define RCC_CFGR_MCOSEL_Pos (24U)
#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
#define RCC_CFGR_MCOPRE_Pos (28U)
#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
/* Legacy aliases */
#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLSRC_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
#define RCC_PLLCFGR_PLLM_Pos (4U)
#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
#define RCC_PLLCFGR_PLLN_Pos (8U)
#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
#define RCC_PLLCFGR_PLLPEN_Pos (16U)
#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
#define RCC_PLLCFGR_PLLP_Pos (17U)
#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
#define RCC_PLLCFGR_PLLQEN_Pos (20U)
#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
#define RCC_PLLCFGR_PLLQ_Pos (21U)
#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
#define RCC_PLLCFGR_PLLREN_Pos (24U)
#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
#define RCC_PLLCFGR_PLLR_Pos (25U)
#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos (3U)
#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos (4U)
#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_PLLRDYIE_Pos (5U)
#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos (9U)
#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos (10U)
#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
/******************** Bit definition for RCC_CIFR register ******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos (3U)
#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos (4U)
#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_PLLRDYF_Pos (5U)
#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
#define RCC_CIFR_CSSF_Pos (8U)
#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
#define RCC_CIFR_LSECSSF_Pos (9U)
#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSI48RDYF_Pos (10U)
#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
/******************** Bit definition for RCC_CICR register ******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos (3U)
#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos (4U)
#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
#define RCC_CICR_PLLRDYC_Pos (5U)
#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
#define RCC_CICR_CSSC_Pos (8U)
#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
#define RCC_CICR_LSECSSC_Pos (9U)
#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSI48RDYC_Pos (10U)
#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
#define RCC_AHB1RSTR_CORDICRST_Pos (3U)
#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
#define RCC_AHB1RSTR_FMACRST_Pos (4U)
#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
#define RCC_AHB1RSTR_CRCRST_Pos (12U)
#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
#define RCC_AHB2RSTR_ADC12RST_Pos (13U)
#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
#define RCC_AHB2RSTR_ADC345RST_Pos (14U)
#define RCC_AHB2RSTR_ADC345RST_Msk (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
#define RCC_AHB2RSTR_ADC345RST RCC_AHB2RSTR_ADC345RST_Msk
#define RCC_AHB2RSTR_DAC1RST_Pos (16U)
#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
#define RCC_AHB2RSTR_DAC2RST_Pos (17U)
#define RCC_AHB2RSTR_DAC2RST_Msk (0x1UL << RCC_AHB2RSTR_DAC2RST_Pos)/*!< 0x00020000 */
#define RCC_AHB2RSTR_DAC2RST RCC_AHB2RSTR_DAC2RST_Msk
#define RCC_AHB2RSTR_DAC3RST_Pos (18U)
#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
#define RCC_AHB2RSTR_DAC4RST_Pos (19U)
#define RCC_AHB2RSTR_DAC4RST_Msk (0x1UL << RCC_AHB2RSTR_DAC4RST_Pos)/*!< 0x00080000 */
#define RCC_AHB2RSTR_DAC4RST RCC_AHB2RSTR_DAC4RST_Msk
#define RCC_AHB2RSTR_AESRST_Pos (24U)
#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos)/*!< 0x01000000 */
#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (26U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
/******************** Bit definition for RCC_AHB3RSTR register **************/
#define RCC_AHB3RSTR_FMCRST_Pos (0U)
#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)/*!< 0x00000001 */
#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
/******************** Bit definition for RCC_APB1RSTR1 register **************/
#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
#define RCC_APB1RSTR1_CRSRST_Pos (8U)
#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
#define RCC_APB1RSTR1_USART2RST_Pos (17U)
#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
#define RCC_APB1RSTR1_USART3RST_Pos (18U)
#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
#define RCC_APB1RSTR1_UART4RST_Pos (19U)
#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
#define RCC_APB1RSTR1_UART5RST_Pos (20U)
#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
#define RCC_APB1RSTR1_USBRST_Pos (23U)
#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
#define RCC_APB1RSTR1_FDCANRST_Pos (25U)
#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
#define RCC_APB1RSTR1_PWRRST_Pos (28U)
#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
#define RCC_APB1RSTR1_I2C3RST_Pos (30U)
#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
#define RCC_APB1RSTR2_I2C4RST_Pos (1U)
#define RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
#define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_TIM8RST_Pos (13U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_SPI4RST_Pos (15U)
#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)/*!< 0x00008000 */
#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_TIM20RST_Pos (20U)
#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define RCC_AHB1ENR_DMA2EN_Pos (1U)
#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
#define RCC_AHB1ENR_CORDICEN_Pos (3U)
#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
#define RCC_AHB1ENR_FMACEN_Pos (4U)
#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
#define RCC_AHB1ENR_FLASHEN_Pos (8U)
#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
#define RCC_AHB1ENR_CRCEN_Pos (12U)
#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
#define RCC_AHB2ENR_GPIODEN_Pos (3U)
#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
#define RCC_AHB2ENR_ADC12EN_Pos (13U)
#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
#define RCC_AHB2ENR_ADC345EN_Pos (14U)
#define RCC_AHB2ENR_ADC345EN_Msk (0x1UL << RCC_AHB2ENR_ADC345EN_Pos) /*!< 0x00004000 */
#define RCC_AHB2ENR_ADC345EN RCC_AHB2ENR_ADC345EN_Msk
#define RCC_AHB2ENR_DAC1EN_Pos (16U)
#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
#define RCC_AHB2ENR_DAC2EN_Pos (17U)
#define RCC_AHB2ENR_DAC2EN_Msk (0x1UL << RCC_AHB2ENR_DAC2EN_Pos) /*!< 0x00020000 */
#define RCC_AHB2ENR_DAC2EN RCC_AHB2ENR_DAC2EN_Msk
#define RCC_AHB2ENR_DAC3EN_Pos (18U)
#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
#define RCC_AHB2ENR_DAC4EN_Pos (19U)
#define RCC_AHB2ENR_DAC4EN_Msk (0x1UL << RCC_AHB2ENR_DAC4EN_Pos) /*!< 0x00080000 */
#define RCC_AHB2ENR_DAC4EN RCC_AHB2ENR_DAC4EN_Msk
#define RCC_AHB2ENR_AESEN_Pos (24U)
#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x01000000 */
#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (26U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
/******************** Bit definition for RCC_AHB3ENR register ***************/
#define RCC_AHB3ENR_FMCEN_Pos (0U)
#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
#define RCC_AHB3ENR_QSPIEN_Pos (8U)
#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
/******************** Bit definition for RCC_APB1ENR1 register ***************/
#define RCC_APB1ENR1_TIM2EN_Pos (0U)
#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
#define RCC_APB1ENR1_TIM3EN_Pos (1U)
#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM5EN_Pos (3U)
#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
#define RCC_APB1ENR1_TIM7EN_Pos (5U)
#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
#define RCC_APB1ENR1_CRSEN_Pos (8U)
#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
#define RCC_APB1ENR1_WWDGEN_Pos (11U)
#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
#define RCC_APB1ENR1_SPI2EN_Pos (14U)
#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
#define RCC_APB1ENR1_SPI3EN_Pos (15U)
#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
#define RCC_APB1ENR1_USART2EN_Pos (17U)
#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
#define RCC_APB1ENR1_USART3EN_Pos (18U)
#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
#define RCC_APB1ENR1_UART4EN_Pos (19U)
#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
#define RCC_APB1ENR1_UART5EN_Pos (20U)
#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
#define RCC_APB1ENR1_I2C1EN_Pos (21U)
#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
#define RCC_APB1ENR1_I2C2EN_Pos (22U)
#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
#define RCC_APB1ENR1_USBEN_Pos (23U)
#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
#define RCC_APB1ENR1_FDCANEN_Pos (25U)
#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
#define RCC_APB1ENR1_PWREN_Pos (28U)
#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
#define RCC_APB1ENR1_I2C3EN_Pos (30U)
#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
#define RCC_APB1ENR2_I2C4EN_Pos (1U)
#define RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
#define RCC_APB1ENR2_UCPD1EN_Pos (8U)
#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
#define RCC_APB2ENR_TIM1EN_Pos (11U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_TIM8EN_Pos (13U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define RCC_APB2ENR_USART1EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_SPI4EN_Pos (15U)
#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_TIM20EN_Pos (20U)
#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
/******************** Bit definition for RCC_AHB2SMENR register *************/
#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
#define RCC_AHB2SMENR_ADC345SMEN_Pos (14U)
#define RCC_AHB2SMENR_ADC345SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
#define RCC_AHB2SMENR_ADC345SMEN RCC_AHB2SMENR_ADC345SMEN_Msk
#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
#define RCC_AHB2SMENR_DAC2SMEN_Pos (17U)
#define RCC_AHB2SMENR_DAC2SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC2SMEN_Pos)/*!< 0x00020000 */
#define RCC_AHB2SMENR_DAC2SMEN RCC_AHB2SMENR_DAC2SMEN_Msk
#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
#define RCC_AHB2SMENR_DAC4SMEN_Pos (19U)
#define RCC_AHB2SMENR_DAC4SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC4SMEN_Pos)/*!< 0x00080000 */
#define RCC_AHB2SMENR_DAC4SMEN RCC_AHB2SMENR_DAC4SMEN_Msk
#define RCC_AHB2SMENR_AESSMEN_Pos (24U)
#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos)/*!< 0x01000000 */
#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk
#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register *************/
#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
/******************** Bit definition for RCC_APB1SMENR1 register *************/
#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
#define RCC_APB1SMENR1_USBSMEN_Pos (23U)
#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
/******************** Bit definition for RCC_APB1SMENR2 register *************/
#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
/******************** Bit definition for RCC_APB2SMENR register *************/
#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
#define RCC_APB2SMENR_SPI4SMEN_Pos (15U)
#define RCC_APB2SMENR_SPI4SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI4SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB2SMENR_SPI4SMEN RCC_APB2SMENR_SPI4SMEN_Msk
#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
#define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
#define RCC_CCIPR_USART2SEL_Pos (2U)
#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
#define RCC_CCIPR_USART3SEL_Pos (4U)
#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
#define RCC_CCIPR_UART4SEL_Pos (6U)
#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR_UART5SEL_Pos (8U)
#define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
#define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR_LPUART1SEL_Pos (10U)
#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
#define RCC_CCIPR_I2C1SEL_Pos (12U)
#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR_I2C2SEL_Pos (14U)
#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR_I2C3SEL_Pos (16U)
#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
#define RCC_CCIPR_SAI1SEL_Pos (20U)
#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
#define RCC_CCIPR_I2S23SEL_Pos (22U)
#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
#define RCC_CCIPR_FDCANSEL_Pos (24U)
#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR_CLK48SEL_Pos (26U)
#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
#define RCC_CCIPR_ADC12SEL_Pos (28U)
#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
#define RCC_CCIPR_ADC345SEL_Pos (30U)
#define RCC_CCIPR_ADC345SEL_Msk (0x3UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
#define RCC_CCIPR_ADC345SEL RCC_CCIPR_ADC345SEL_Msk
#define RCC_CCIPR_ADC345SEL_0 (0x1UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x40000000 */
#define RCC_CCIPR_ADC345SEL_1 (0x2UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos (3U)
#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos (5U)
#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos (6U)
#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
#define RCC_BDCR_LSCOEN_Pos (24U)
#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
#define RCC_BDCR_LSCOSEL_Pos (25U)
#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION_Pos (0U)
#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos (1U)
#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
#define RCC_CSR_RMVF_Pos (23U)
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
#define RCC_CSR_OBLRSTF_Pos (25U)
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_BORRSTF_Pos (27U)
#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/******************** Bit definition for RCC_CRRCR register *****************/
#define RCC_CRRCR_HSI48ON_Pos (0U)
#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
#define RCC_CRRCR_HSI48RDY_Pos (1U)
#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos (7U)
#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
/******************** Bit definition for RCC_CCIPR2 register ******************/
#define RCC_CCIPR2_I2C4SEL_Pos (0U)
#define RCC_CCIPR2_I2C4SEL_Msk (0x3UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
#define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
#define RCC_CCIPR2_I2C4SEL_0 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR2_I2C4SEL_1 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR2_QSPISEL_Pos (20U)
#define RCC_CCIPR2_QSPISEL_Msk (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR2_QSPISEL RCC_CCIPR2_QSPISEL_Msk
#define RCC_CCIPR2_QSPISEL_0 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR2_QSPISEL_1 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_ICSR register ******************/
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_ALRBWF_Pos (1U)
#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
#define RTC_ICSR_ALRAWF_Pos (0U)
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_SR register *******************/
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
/******************** Bits definition for RTC_MISR register *****************/
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
/******************** Bits definition for RTC_SCR register ******************/
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register *****************/
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos (21U)
#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
/******************** Bits definition for TAMP_CR2 register *****************/
#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
#define TAMP_CR2_TAMP1MF_Pos (16U)
#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
#define TAMP_CR2_TAMP2MF_Pos (17U)
#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
#define TAMP_CR2_TAMP3MF_Pos (18U)
#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_IER register *****************/
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos (21U)
#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
/******************** Bits definition for TAMP_SR register ******************/
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos (21U)
#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
/******************** Bits definition for TAMP_MISR register ****************/
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos (21U)
#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
/******************** Bits definition for TAMP_SCR register *****************/
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos (21U)
#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
/******************** Bits definition for TAMP_BKP1R register ***************/
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
/******************** Bits definition for TAMP_BKP2R register ***************/
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
/******************** Bits definition for TAMP_BKP3R register ***************/
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
/******************** Bits definition for TAMP_BKP4R register ***************/
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************** Bits definition for TAMP_BKP5R register ***************/
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
/******************** Bits definition for TAMP_BKP6R register ***************/
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
/******************** Bits definition for TAMP_BKP7R register ***************/
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
/******************** Bits definition for TAMP_BKP8R register ***************/
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
/******************** Bits definition for TAMP_BKP9R register ***************/
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
/******************** Bits definition for TAMP_BKP10R register ***************/
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
/******************** Bits definition for TAMP_BKP11R register ***************/
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
/******************** Bits definition for TAMP_BKP12R register ***************/
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
/******************** Bits definition for TAMP_BKP13R register ***************/
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
/******************** Bits definition for TAMP_BKP14R register ***************/
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
/******************** Bits definition for TAMP_BKP15R register ***************/
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
/******************** Bits definition for TAMP_BKP16R register ***************/
#define TAMP_BKP16R_Pos (0U)
#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP16R TAMP_BKP16R_Msk
/******************** Bits definition for TAMP_BKP17R register ***************/
#define TAMP_BKP17R_Pos (0U)
#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP17R TAMP_BKP17R_Msk
/******************** Bits definition for TAMP_BKP18R register ***************/
#define TAMP_BKP18R_Pos (0U)
#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP18R TAMP_BKP18R_Msk
/******************** Bits definition for TAMP_BKP19R register ***************/
#define TAMP_BKP19R_Pos (0U)
#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP19R TAMP_BKP19R_Msk
/******************** Bits definition for TAMP_BKP20R register ***************/
#define TAMP_BKP20R_Pos (0U)
#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP20R TAMP_BKP20R_Msk
/******************** Bits definition for TAMP_BKP21R register ***************/
#define TAMP_BKP21R_Pos (0U)
#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP21R TAMP_BKP21R_Msk
/******************** Bits definition for TAMP_BKP22R register ***************/
#define TAMP_BKP22R_Pos (0U)
#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP22R TAMP_BKP22R_Msk
/******************** Bits definition for TAMP_BKP23R register ***************/
#define TAMP_BKP23R_Pos (0U)
#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP23R TAMP_BKP23R_Msk
/******************** Bits definition for TAMP_BKP24R register ***************/
#define TAMP_BKP24R_Pos (0U)
#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP24R TAMP_BKP24R_Msk
/******************** Bits definition for TAMP_BKP25R register ***************/
#define TAMP_BKP25R_Pos (0U)
#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP25R TAMP_BKP25R_Msk
/******************** Bits definition for TAMP_BKP26R register ***************/
#define TAMP_BKP26R_Pos (0U)
#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP26R TAMP_BKP26R_Msk
/******************** Bits definition for TAMP_BKP27R register ***************/
#define TAMP_BKP27R_Pos (0U)
#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP27R TAMP_BKP27R_Msk
/******************** Bits definition for TAMP_BKP28R register ***************/
#define TAMP_BKP28R_Pos (0U)
#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP28R TAMP_BKP28R_Msk
/******************** Bits definition for TAMP_BKP29R register ***************/
#define TAMP_BKP29R_Pos (0U)
#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP29R TAMP_BKP29R_Msk
/******************** Bits definition for TAMP_BKP30R register ***************/
#define TAMP_BKP30R_Pos (0U)
#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP30R TAMP_BKP30R_Msk
/******************** Bits definition for TAMP_BKP31R register ***************/
#define TAMP_BKP31R_Pos (0U)
#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP31R TAMP_BKP31R_Msk
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/****************** Bit definition for SAI_PDMCR register *******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
#define SPI_CR1_CPOL_Pos (1U)
#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
#define SPI_CR1_MSTR_Pos (2U)
#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
#define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
#define SPI_CR1_LSBFIRST_Pos (7U)
#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
#define SPI_CR1_SSI_Pos (8U)
#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
#define SPI_CR1_SSM_Pos (9U)
#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
#define SPI_CR1_RXONLY_Pos (10U)
#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
#define SPI_CR1_CRCL_Pos (11U)
#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
#define SPI_CR1_CRCNEXT_Pos (12U)
#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
#define SPI_CR1_CRCEN_Pos (13U)
#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE_Pos (14U)
#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos (15U)
#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN_Pos (0U)
#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN_Pos (1U)
#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
#define SPI_CR2_SSOE_Pos (2U)
#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
#define SPI_CR2_NSSP_Pos (3U)
#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
#define SPI_CR2_FRF_Pos (4U)
#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
#define SPI_CR2_ERRIE_Pos (5U)
#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE_Pos (6U)
#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE_Pos (7U)
#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
#define SPI_CR2_LDMARX_Pos (13U)
#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
#define SPI_CR2_LDMATX_Pos (14U)
#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE_Pos (0U)
#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
#define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
#define SPI_SR_MODF_Pos (5U)
#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
#define SPI_SR_BSY_Pos (7U)
#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
#define SPI_SR_FRE_Pos (8U)
#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
#define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U)
#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY_Pos (0U)
#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC_Pos (0U)
#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC_Pos (0U)
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN_Pos (0U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN_Pos (1U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_CKPOL_Pos (3U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_I2SE_Pos (10U)
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD_Pos (8U)
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE_Pos (9U)
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
/****************** Bit definition for SYSCFG_CFGR1 register ******************/
#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
#define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */
#define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
/****************** Bit definition for SYSCFG_SCSR register ****************/
#define SYSCFG_SCSR_CCMER_Pos (0U)
#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
#define SYSCFG_SCSR_CCMBSY_Pos (1U)
#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
/****************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_CLL_Pos (0U)
#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
#define SYSCFG_CFGR2_SPL_Pos (1U)
#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
#define SYSCFG_CFGR2_PVDL_Pos (2U)
#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
#define SYSCFG_CFGR2_ECCL_Pos (3U)
#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
#define SYSCFG_CFGR2_SPF_Pos (8U)
#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
#define SYSCFG_SWPR_PAGE16_Pos (16U)
#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
#define SYSCFG_SWPR_PAGE17_Pos (17U)
#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
#define SYSCFG_SWPR_PAGE18_Pos (18U)
#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
#define SYSCFG_SWPR_PAGE19_Pos (19U)
#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
#define SYSCFG_SWPR_PAGE20_Pos (20U)
#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
#define SYSCFG_SWPR_PAGE21_Pos (21U)
#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
#define SYSCFG_SWPR_PAGE22_Pos (22U)
#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
#define SYSCFG_SWPR_PAGE23_Pos (23U)
#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
#define SYSCFG_SWPR_PAGE24_Pos (24U)
#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
#define SYSCFG_SWPR_PAGE25_Pos (25U)
#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
#define SYSCFG_SWPR_PAGE26_Pos (26U)
#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
#define SYSCFG_SWPR_PAGE27_Pos (27U)
#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
#define SYSCFG_SWPR_PAGE28_Pos (28U)
#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
#define SYSCFG_SWPR_PAGE29_Pos (29U)
#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
#define SYSCFG_SWPR_PAGE30_Pos (30U)
#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
#define SYSCFG_SWPR_PAGE31_Pos (31U)
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
#define TIM_CR1_CMS_Pos (5U)
#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos (7U)
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos (8U)
#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos (12U)
#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos (15U)
#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos (3U)
#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE_Pos (0U)
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos (1U)
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos (2U)
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos (3U)
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos (4U)
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos (5U)
#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos (6U)
#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos (7U)
#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos (8U)
#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos (9U)
#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos (10U)
#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos (11U)
#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos (12U)
#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos (13U)
#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos (14U)
#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos (20U)
#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos (21U)
#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos (20U)
#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
#define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos (21U)
#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
#define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos (22U)
#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
#define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos (23U)
#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
#define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG_Pos (0U)
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos (6U)
#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
#define TIM_EGR_BG_Pos (7U)
#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
#define TIM_EGR_B2G_Pos (8U)
#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos (4U)
#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos (12U)
#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA_Pos (0U)
#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos (8U)
#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
/******************* Bit definition for TIM1_AF1 register *******************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
#define TIM1_AF1_BKCMP1E_Pos (1U)
#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
#define TIM1_AF1_BKCMP2E_Pos (2U)
#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
#define TIM1_AF1_BKCMP3E_Pos (3U)
#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
#define TIM1_AF1_BKCMP4E_Pos (4U)
#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
#define TIM1_AF1_BKCMP5E_Pos (5U)
#define TIM1_AF1_BKCMP5E_Msk (0x1UL << TIM1_AF1_BKCMP5E_Pos) /*!< 0x00000020 */
#define TIM1_AF1_BKCMP5E TIM1_AF1_BKCMP5E_Msk /*!<BRK COMP5 enable */
#define TIM1_AF1_BKCMP6E_Pos (6U)
#define TIM1_AF1_BKCMP6E_Msk (0x1UL << TIM1_AF1_BKCMP6E_Pos) /*!< 0x00000040 */
#define TIM1_AF1_BKCMP6E TIM1_AF1_BKCMP6E_Msk /*!<BRK COMP6 enable */
#define TIM1_AF1_BKCMP7E_Pos (7U)
#define TIM1_AF1_BKCMP7E_Msk (0x1UL << TIM1_AF1_BKCMP7E_Pos) /*!< 0x00000080 */
#define TIM1_AF1_BKCMP7E TIM1_AF1_BKCMP7E_Msk /*!<BRK COMP7 enable */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
#define TIM1_AF1_BKCMP1P_Pos (10U)
#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
#define TIM1_AF1_BKCMP2P_Pos (11U)
#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
#define TIM1_AF1_BKCMP3P_Pos (12U)
#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
#define TIM1_AF1_BKCMP4P_Pos (13U)
#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
#define TIM1_AF1_ETRSEL_Pos (14U)
#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
#define TIM1_AF2_BK2CMP1E_Pos (1U)
#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
#define TIM1_AF2_BK2CMP2E_Pos (2U)
#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
#define TIM1_AF2_BK2CMP3E_Pos (3U)
#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
#define TIM1_AF2_BK2CMP4E_Pos (4U)
#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
#define TIM1_AF2_BK2CMP5E_Pos (5U)
#define TIM1_AF2_BK2CMP5E_Msk (0x1UL << TIM1_AF2_BK2CMP5E_Pos) /*!< 0x00000020 */
#define TIM1_AF2_BK2CMP5E TIM1_AF2_BK2CMP5E_Msk /*!<BRK2 COMP5 enable */
#define TIM1_AF2_BK2CMP6E_Pos (6U)
#define TIM1_AF2_BK2CMP6E_Msk (0x1UL << TIM1_AF2_BK2CMP6E_Pos) /*!< 0x00000040 */
#define TIM1_AF2_BK2CMP6E TIM1_AF2_BK2CMP6E_Msk /*!<BRK2 COMP6 enable */
#define TIM1_AF2_BK2CMP7E_Pos (7U)
#define TIM1_AF2_BK2CMP7E_Msk (0x1UL << TIM1_AF2_BK2CMP7E_Pos) /*!< 0x00000080 */
#define TIM1_AF2_BK2CMP7E TIM1_AF2_BK2CMP7E_Msk /*!<BRK2 COMP7 enable */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
#define TIM1_AF2_BK2CMP1P_Pos (10U)
#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
#define TIM1_AF2_BK2CMP2P_Pos (11U)
#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_BK2CMP3P_Pos (12U)
#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
#define TIM1_AF2_BK2CMP4P_Pos (13U)
#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
#define TIM1_AF2_OCRSEL_Pos (16U)
#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_HSE32EN_Pos (0U)
#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM_DTR2 register *********************/
#define TIM_DTR2_DTGF_Pos (0U)
#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos (16U)
#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos (17U)
#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
/******************* Bit definition for TIM_ECR register *********************/
#define TIM_ECR_IE_Pos (0U)
#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
#define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
#define TIM_ECR_IDIR_Pos (1U)
#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_FIDX_Pos (5U)
#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
#define TIM_ECR_IPOS_Pos (6U)
#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
#define TIM_ECR_PW_Pos (16U)
#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
#define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos (24U)
#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB_Pos (0U)
#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_OR register *******************/
#define LPTIM_OR_IN1_Pos (0U)
#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
#define LPTIM_OR_IN2_Pos (1U)
#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART_Pos (0U)
#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR_Pos (0U)
#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */
#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
/******************* Bit definition for VREFBUF_CCR register ******************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* USB Device FS Endpoint registers */
/* */
/******************************************************************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
/* bit positions */
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
/* */
/* USB Device FS General registers */
/* */
/******************************************************************************/
#define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
#define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
#define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
#define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
#define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
#define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
/****************** Bits definition for USB_CNTR register *******************/
#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/****************** Bits definition for USB_ISTR register *******************/
#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
/****************** Bits definition for USB_FNR register ********************/
#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
/****************** Bits definition for USB_DADDR register ****************/
#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
#define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
#define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
#define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
#define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
#define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
#define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
#define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
#define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
/****************** Bit definition for USB_BTABLE register ******************/
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
/****************** Bits definition for USB_BCDR register *******************/
#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
/******************* Bit definition for LPMCSR register *********************/
#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
/*!< Buffer descriptor table */
/***************** Bit definition for USB_ADDR0_TX register *****************/
#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_TX register *****************/
#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_TX register *****************/
#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_TX register *****************/
#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_TX register *****************/
#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_TX register *****************/
#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_TX register *****************/
#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_TX register *****************/
#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_TX register ****************/
#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
/***************** Bit definition for USB_COUNT1_TX register ****************/
#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
/***************** Bit definition for USB_COUNT2_TX register ****************/
#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
/***************** Bit definition for USB_COUNT3_TX register ****************/
#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
/***************** Bit definition for USB_COUNT4_TX register ****************/
#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
/***************** Bit definition for USB_COUNT5_TX register ****************/
#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
/***************** Bit definition for USB_COUNT6_TX register ****************/
#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
/***************** Bit definition for USB_COUNT7_TX register ****************/
#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_ADDR0_RX register *****************/
#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_RX register *****************/
#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_RX register *****************/
#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_RX register *****************/
#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_RX register *****************/
#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_RX register *****************/
#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_RX register *****************/
#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_RX register *****************/
#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_RX register ****************/
#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT0_RX_BLSIZE_Pos (15U)
#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT1_RX register ****************/
#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT1_RX_BLSIZE_Pos (15U)
#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT2_RX register ****************/
#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT2_RX_BLSIZE_Pos (15U)
#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT3_RX register ****************/
#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT3_RX_BLSIZE_Pos (15U)
#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT4_RX register ****************/
#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT4_RX_BLSIZE_Pos (15U)
#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT5_RX register ****************/
#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT5_RX_BLSIZE_Pos (15U)
#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT6_RX register ****************/
#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT6_RX_BLSIZE_Pos (15U)
#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT7_RX register ****************/
#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT7_RX_BLSIZE_Pos (15U)
#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
/* UCPD */
/* */
/******************************************************************************/
/******************** Bits definition for UCPD_CFG1 register *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos (6U)
#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos (11U)
#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos (20U)
#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos (29U)
#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define UCPD_CFG1_RXDMAEN_Pos (30U)
#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define UCPD_CFG1_UCPDEN_Pos (31U)
#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
/******************** Bits definition for UCPD_CFG2 register *******************/
#define UCPD_CFG2_RXFILTDIS_Pos (0U)
#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos (1U)
#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos (2U)
#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos (3U)
#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
/******************** Bits definition for UCPD_CR register ********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos (2U)
#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXHRST_Pos (3U)
#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
#define UCPD_CR_RXMODE_Pos (4U)
#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
#define UCPD_CR_PHYRXEN_Pos (5U)
#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
#define UCPD_CR_PHYCCSEL_Pos (6U)
#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
#define UCPD_CR_ANASUBMODE_Pos (7U)
#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos (9U)
#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
#define UCPD_CR_CCENABLE_Pos (10U)
#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
#define UCPD_CR_FRSRXEN_Pos (16U)
#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
#define UCPD_CR_FRSTX_Pos (17U)
#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos (18U)
#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
#define UCPD_CR_CC1TCDIS_Pos (20U)
#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos (21U)
#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
/******************** Bits definition for UCPD_IMR register *******************/
#define UCPD_IMR_TXISIE_Pos (0U)
#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
#define UCPD_IMR_TXMSGABTIE_Pos (3U)
#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
#define UCPD_IMR_HRSTDISCIE_Pos (4U)
#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
#define UCPD_IMR_HRSTSENTIE_Pos (5U)
#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
#define UCPD_IMR_TXUNDIE_Pos (6U)
#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
#define UCPD_IMR_RXNEIE_Pos (8U)
#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
#define UCPD_IMR_RXORDDETIE_Pos (9U)
#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
#define UCPD_IMR_RXOVRIE_Pos (11U)
#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
#define UCPD_IMR_RXMSGENDIE_Pos (12U)
#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
#define UCPD_IMR_FRSEVTIE_Pos (20U)
#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
/******************** Bits definition for UCPD_SR register ********************/
#define UCPD_SR_TXIS_Pos (0U)
#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
#define UCPD_SR_TXMSGDISC_Pos (1U)
#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
#define UCPD_SR_TXMSGSENT_Pos (2U)
#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
#define UCPD_SR_TXMSGABT_Pos (3U)
#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
#define UCPD_SR_HRSTDISC_Pos (4U)
#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
#define UCPD_SR_HRSTSENT_Pos (5U)
#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
#define UCPD_SR_TXUND_Pos (6U)
#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
#define UCPD_SR_RXNE_Pos (8U)
#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
#define UCPD_SR_RXORDDET_Pos (9U)
#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
#define UCPD_SR_RXHRSTDET_Pos (10U)
#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
#define UCPD_SR_RXOVR_Pos (11U)
#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
#define UCPD_SR_RXMSGEND_Pos (12U)
#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
#define UCPD_SR_RXERR_Pos (13U)
#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos (14U)
#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
#define UCPD_SR_TYPECEVT2_Pos (15U)
#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
#define UCPD_SR_FRSEVT_Pos (20U)
#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
/******************** Bits definition for UCPD_ICR register *******************/
#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
#define UCPD_ICR_TXMSGABTCF_Pos (3U)
#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
#define UCPD_ICR_HRSTDISCCF_Pos (4U)
#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
#define UCPD_ICR_HRSTSENTCF_Pos (5U)
#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
#define UCPD_ICR_TXUNDCF_Pos (6U)
#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
#define UCPD_ICR_RXORDDETCF_Pos (9U)
#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
#define UCPD_ICR_RXOVRCF_Pos (11U)
#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
#define UCPD_ICR_RXMSGENDCF_Pos (12U)
#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
#define UCPD_ICR_FRSEVTCF_Pos (20U)
#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
/******************** Bits definition for UCPD_TXORDSET register **************/
#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
/******************** Bits definition for UCPD_TXPAYSZ register ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
/******************** Bits definition for UCPD_TXDR register *******************/
#define UCPD_TXDR_TXDATA_Pos (0U)
#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
/******************** Bits definition for UCPD_RXORDSET register **************/
#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
/******************** Bits definition for UCPD_RXPAYSZ register ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
/******************** Bits definition for UCPD_RXDR register *******************/
#define UCPD_RXDR_RXDATA_Pos (0U)
#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/******************** Bits definition for UCPD_RXORDEXT1 register **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
/******************** Bits definition for UCPD_RXORDEXT2 register **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2) || \
((INSTANCE) == ADC3) || \
((INSTANCE) == ADC4) || \
((INSTANCE) == ADC5))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC3))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
((INSTANCE) == ADC345_COMMON) )
/******************************* AES Instances ********************************/
#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
/******************************** FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
((INSTANCE) == FDCAN2) || \
((INSTANCE) == FDCAN3))
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2) || \
((INSTANCE) == COMP3) || \
((INSTANCE) == COMP4) || \
((INSTANCE) == COMP5) || \
((INSTANCE) == COMP6) || \
((INSTANCE) == COMP7))
/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC2) || \
((INSTANCE) == DAC3) || \
((INSTANCE) == DAC4))
/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7) || \
((INSTANCE) == DMA1_Channel8) || \
((INSTANCE) == DMA2_Channel1) || \
((INSTANCE) == DMA2_Channel2) || \
((INSTANCE) == DMA2_Channel3) || \
((INSTANCE) == DMA2_Channel4) || \
((INSTANCE) == DMA2_Channel5) || \
((INSTANCE) == DMA2_Channel6) || \
((INSTANCE) == DMA2_Channel7) || \
((INSTANCE) == DMA2_Channel8))
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
/******************************* FMAC Instances *******************************/
#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances *****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4))
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3) || \
((INSTANCE) == OPAMP4) || \
((INSTANCE) == OPAMP5) || \
((INSTANCE) == OPAMP6))
/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/******************************* QSPI Instances *******************************/
#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4))
/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
((__INSTANCE__) == SPI3))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM5) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** UCPD Instances ********************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
/******************************* USB Instances *******************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/**
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32G4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32G4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
/* Aliases for __IRQHandler */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32G483xx_H */
/**
* @}
*/
/**
* @}
*/
| 1,116,767 | C | 74.549181 | 180 | 0.510811 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g491xx.h | /**
******************************************************************************
* @file stm32g491xx.h
* @author MCD Application Team
* @brief CMSIS STM32G491xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32g491xx
* @{
*/
#ifndef __STM32G491xx_H
#define __STM32G491xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32G4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ***************************************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_IRQn = 19, /*!< USB HP Interrupt */
USB_LP_IRQn = 20, /*!< USB LP Interrupt */
FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupts */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
COMP4_IRQn = 65, /*!< COMP4 */
CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */
FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */
RNG_IRQn = 90, /*!< RNG global interrupt */
LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */
DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */
DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */
DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */
CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
FMAC_IRQn = 101 /*!< FMAC global Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32g4xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
__IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
} FDCAN_Config_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
__IO uint32_t RESERVED[2];
__IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
__IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
__IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
__IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
__IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
__IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
__IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */
__IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
} FLASH_TypeDef;
/**
* @brief FMAC
*/
typedef struct
{
__IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
__IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
__IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
__IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
} FMAC_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
} OPAMP_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
__IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief QUAD Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
__IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
__IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
__IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
__IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
__IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
__IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
/*
* @brief Specific device feature definitions
*/
#define RTC_TAMP_INT_6_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 3u
#define RTC_BACKUP_NB 32u
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
} RTC_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
__IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
__IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
__IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
__IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
__IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
__IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
__IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
__IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
__IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
__IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
__IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
__IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
__IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
__IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
__IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
__IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
} TAMP_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
__IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
__IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
__IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
__IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
__IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
__IO uint16_t RESERVEDD; /*!< Reserved */
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
__IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief CORDIC
*/
typedef struct
{
__IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
__IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
__IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
} CORDIC_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */
#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
/*!< AHB1 peripherals */
#define DMA1_BASE (AHB1PERIPH_BASE)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
/*!< AHB2 peripherals */
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)
#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)
#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0042000UL)
#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos (15U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
#define ADC_CFGR2_GCOMP_Pos (16U)
#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
#define ADC_CFGR2_SWTRIG_Pos (25U)
#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
#define ADC_CFGR2_BULB_Pos (26U)
#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
#define ADC_CFGR2_SMPTRIG_Pos (27U)
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_AWDFILT_Pos (12U)
#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSETPOS_Pos (24U)
#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
#define ADC_OFR1_SATEN_Pos (25U)
#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSETPOS_Pos (24U)
#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
#define ADC_OFR2_SATEN_Pos (25U)
#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSETPOS_Pos (24U)
#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
#define ADC_OFR3_SATEN_Pos (25U)
#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSETPOS_Pos (24U)
#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
#define ADC_OFR4_SATEN_Pos (25U)
#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
/******************** Bit definition for ADC_GCOMP register *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos (13U)
#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
#define ADC_CCR_MDMA_Pos (14U)
#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_VSENSESEL_Pos (23U)
#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATSEL_Pos (24U)
#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_INMSEL_Pos (4U)
#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_Pos (8U)
#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
#define COMP_CSR_BLANKING_Pos (19U)
#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
/* CORDIC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CORDIC_CSR register *****************/
#define CORDIC_CSR_FUNC_Pos (0U)
#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos (4U)
#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos (8U)
#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos (16U)
#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos (17U)
#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos (18U)
#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos (19U)
#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos (20U)
#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos (21U)
#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos (22U)
#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos (31U)
#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
/******************* Bit definition for CORDIC_WDATA register ***************/
#define CORDIC_WDATA_ARG_Pos (0U)
#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
/******************* Bit definition for CORDIC_RDATA register ***************/
#define CORDIC_RDATA_RES_Pos (0U)
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_Pos (16U)
#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
#define DAC_DOR2_DACC2DORB_Pos (16U)
#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DAC1RDY_Pos (11U)
#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
#define DAC_SR_DORSTAT1_Pos (12U)
#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
#define DAC_SR_DORSTAT2_Pos (28U)
#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos (8U)
#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos (9U)
#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
#define DAC_MCR_HFSEL_Pos (14U)
#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
#define DAC_MCR_DMADOUBLE2_Pos (24U)
#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
#define DAC_MCR_SINFORMAT2_Pos (25U)
#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR2_TSAMPLE2_Pos (0U)
#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/****************** Bit definition for DAC_STR1 register ******************/
#define DAC_STR1_STRSTDATA1_Pos (0U)
#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
#define DAC_STR1_STDIR1_Pos (12U)
#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
#define DAC_STR1_STINCDATA1_Pos (16U)
#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STR2 register ******************/
#define DAC_STR2_STRSTDATA2_Pos (0U)
#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
#define DAC_STR2_STDIR2_Pos (12U)
#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
#define DAC_STR2_STINCDATA2_Pos (16U)
#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STMODR register ****************/
#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
#define DBGMCU_CR_TRACE_MODE_Pos (6U)
#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos (24U)
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
#define DMA_ISR_GIF8_Pos (28U)
#define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos) /*!< 0x10000000 */
#define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk /*!< Channel 8 Global interrupt flag */
#define DMA_ISR_TCIF8_Pos (29U)
#define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos) /*!< 0x20000000 */
#define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk /*!< Channel 8 Transfer Complete flag */
#define DMA_ISR_HTIF8_Pos (30U)
#define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos) /*!< 0x40000000 */
#define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk /*!< Channel 8 Half Transfer flag */
#define DMA_ISR_TEIF8_Pos (31U)
#define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos) /*!< 0x80000000 */
#define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk /*!< Channel 8 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos (24U)
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
#define DMA_IFCR_CGIF8_Pos (28U)
#define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos) /*!< 0x10000000 */
#define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk /*!< Channel 8 Global interrupt clear */
#define DMA_IFCR_CTCIF8_Pos (29U)
#define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos) /*!< 0x20000000 */
#define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk /*!< Channel 8 Transfer Complete clear */
#define DMA_IFCR_CHTIF8_Pos (30U)
#define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos) /*!< 0x40000000 */
#define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk /*!< Channel 8 Half Transfer clear */
#define DMA_IFCR_CTEIF8_Pos (31U)
#define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos) /*!< 0x80000000 */
#define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk /*!< Channel 8 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register ****************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
#define DMAMUX_CSR_SOF12_Pos (12U)
#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
#define DMAMUX_CSR_SOF13_Pos (13U)
#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
#define DMAMUX_CSR_SOF14_Pos (14U)
#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
#define DMAMUX_CSR_SOF15_Pos (15U)
#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
/******************** Bits definition for DMAMUX_CFR register ****************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
#define DMAMUX_CFR_CSOF12_Pos (12U)
#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
#define DMAMUX_CFR_CSOF13_Pos (13U)
#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
#define DMAMUX_CFR_CSOF14_Pos (14U)
#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
#define DMAMUX_CFR_CSOF15_Pos (15U)
#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
/******************** Bits definition for DMAMUX_RGCFR register ************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x7FFFFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
/****************** Bit definition for EXTI_RTSR1 register ******************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT19_Pos (19U)
#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR1_RT22_Pos (22U)
#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR1_RT29_Pos (29U)
#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR1_RT30_Pos (30U)
#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_FT16_Pos (16U)
#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_FT17_Pos (17U)
#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_FT19_Pos (19U)
#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR1_FT22_Pos (22U)
#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR1_FT29_Pos (29U)
#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR1_FT30_Pos (30U)
#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos (16U)
#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos (17U)
#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI19_Pos (19U)
#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos (22U)
#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER1_SWI29_Pos (29U)
#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER1_SWI30_Pos (30U)
#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
/******************* Bit definition for EXTI_PR1 register *******************/
#define EXTI_PR1_PIF0_Pos (0U)
#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PIF1_Pos (1U)
#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PIF2_Pos (2U)
#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PIF3_Pos (3U)
#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PIF4_Pos (4U)
#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PIF5_Pos (5U)
#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PIF6_Pos (6U)
#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PIF7_Pos (7U)
#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PIF8_Pos (8U)
#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PIF9_Pos (9U)
#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PIF10_Pos (10U)
#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PIF11_Pos (11U)
#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PIF12_Pos (12U)
#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PIF13_Pos (13U)
#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PIF14_Pos (14U)
#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PIF15_Pos (15U)
#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PIF16_Pos (16U)
#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PIF17_Pos (17U)
#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR1_PIF19_Pos (19U)
#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PIF20_Pos (20U)
#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PIF21_Pos (21U)
#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR1_PIF22_Pos (22U)
#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR1_PIF29_Pos (29U)
#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR1_PIF30_Pos (30U)
#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x2FCUL << EXTI_IMR2_IM_Pos) /*!< 0x000002FC */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x2FCUL << EXTI_EMR2_EM_Pos) /*!< 0x000002FC */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT38_Pos (6U)
#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
#define EXTI_RTSR2_RT39_Pos (7U)
#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
#define EXTI_RTSR2_RT40_Pos (8U)
#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
#define EXTI_RTSR2_RT41_Pos (9U)
#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_FT38_Pos (6U)
#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
#define EXTI_FTSR2_FT39_Pos (7U)
#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
#define EXTI_FTSR2_FT40_Pos (8U)
#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
#define EXTI_FTSR2_FT41_Pos (9U)
#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI38_Pos (6U)
#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
#define EXTI_SWIER2_SWI39_Pos (7U)
#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
#define EXTI_SWIER2_SWI40_Pos (8U)
#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
#define EXTI_SWIER2_SWI41_Pos (9U)
#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PIF38_Pos (6U)
#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
#define EXTI_PR2_PIF39_Pos (7U)
#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
#define EXTI_PR2_PIF40_Pos (8U)
#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
#define EXTI_PR2_PIF41_Pos (9U)
#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0F_Pos (1U)
#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (2U)
#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (3U)
#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1F_Pos (4U)
#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (5U)
#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (6U)
#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (7U)
#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (8U)
#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (9U)
#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (10U)
#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFF_Pos (11U)
#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (12U)
#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (13U)
#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (14U)
#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (15U)
#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_ELO_Pos (16U)
#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (17U)
#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (18U)
#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (19U)
#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (20U)
#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (21U)
#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (22U)
#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (23U)
#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0FE_Pos (1U)
#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (2U)
#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (3U)
#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1FE_Pos (4U)
#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (5U)
#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (6U)
#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (7U)
#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (8U)
#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos (9U)
#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (10U)
#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFFE_Pos (11U)
#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (12U)
#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (13U)
#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (14U)
#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (15U)
#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_ELOE_Pos (16U)
#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (17U)
#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (18U)
#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (19U)
#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (20U)
#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (21U)
#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos (22U)
#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (23U)
#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RXFIFO0_Pos (0U)
#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
Rx FIFO 0 is Full
Rx FIFO 0 Has New Message */
#define FDCAN_ILS_RXFIFO1_Pos (1U)
#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
Rx FIFO 1 is Full
Rx FIFO 1 Has New Message */
#define FDCAN_ILS_SMSG_Pos (2U)
#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
Transmission Completed
High Priority Message */
#define FDCAN_ILS_TFERR_Pos (3U)
#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
Tx Event FIFO Full
Tx Event FIFO New Entry
Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_MISC_Pos (4U)
#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
Message RAM Access Failure
Timestamp Wraparound */
#define FDCAN_ILS_BERR_Pos (5U)
#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
Error Logging Overflow */
#define FDCAN_ILS_PERR_Pos (6U)
#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
Protocol Error in Data Phase Line
Protocol Error in Arbitration Phase Line
Watchdog Interrupt Line
Bus_Off Status
Warning Status */
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_RXGFC register ********************/
#define FDCAN_RXGFC_RRFE_Pos (0U)
#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_RXGFC_RRFS_Pos (1U)
#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_RXGFC_ANFE_Pos (2U)
#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_RXGFC_ANFS_Pos (4U)
#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
#define FDCAN_RXGFC_F1OM_Pos (8U)
#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
#define FDCAN_RXGFC_F0OM_Pos (9U)
#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
#define FDCAN_RXGFC_LSS_Pos (16U)
#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
#define FDCAN_RXGFC_LSE_Pos (24U)
#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TFQM_Pos (24U)
#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CFIE_Pos (0U)
#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/*!<FDCAN config registers */
/***************** Bit definition for FDCAN_CKDIV register *********************/
#define FDCAN_CKDIV_PDIV_Pos (0U)
#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS (0x00000000U)
#define FLASH_ACR_LATENCY_1WS (0x00000001U)
#define FLASH_ACR_LATENCY_2WS (0x00000002U)
#define FLASH_ACR_LATENCY_3WS (0x00000003U)
#define FLASH_ACR_LATENCY_4WS (0x00000004U)
#define FLASH_ACR_LATENCY_5WS (0x00000005U)
#define FLASH_ACR_LATENCY_6WS (0x00000006U)
#define FLASH_ACR_LATENCY_7WS (0x00000007U)
#define FLASH_ACR_LATENCY_8WS (0x00000008U)
#define FLASH_ACR_LATENCY_9WS (0x00000009U)
#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_RUN_PD_Pos (13U)
#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
#define FLASH_ACR_SLEEP_PD_Pos (14U)
#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
#define FLASH_ACR_DBG_SWEN_Pos (18U)
#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_OPERR_Pos (1U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_PROGERR_Pos (3U)
#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_SIZERR_Pos (6U)
#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_MISERR_Pos (8U)
#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
#define FLASH_SR_FASTERR_Pos (9U)
#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
#define FLASH_SR_RDERR_Pos (14U)
#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_OPTVERR_Pos (15U)
#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PER_Pos (1U)
#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
#define FLASH_CR_PER FLASH_CR_PER_Msk
#define FLASH_CR_MER1_Pos (2U)
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_OPTSTRT_Pos (17U)
#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
#define FLASH_CR_FSTPG_Pos (18U)
#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_RDERRIE_Pos (26U)
#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
#define FLASH_CR_SEC_PROT1_Pos (28U)
#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
#define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_ECCR register ***************/
#define FLASH_ECCR_ADDR_ECC_Pos (0U)
#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
#define FLASH_ECCR_BK_ECC_Pos (21U)
#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
#define FLASH_ECCR_SYSF_ECC_Pos (22U)
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
#define FLASH_ECCR_ECCIE_Pos (24U)
#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
#define FLASH_ECCR_ECCC_Pos (30U)
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
#define FLASH_ECCR_ECCD_Pos (31U)
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
/******************* Bits definition for FLASH_OPTR register ***************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
#define FLASH_OPTR_BOR_LEV_Pos (8U)
#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
#define FLASH_OPTR_nRST_STOP_Pos (12U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
#define FLASH_OPTR_nRST_STDBY_Pos (13U)
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
#define FLASH_OPTR_WWDG_SW_Pos (19U)
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
#define FLASH_OPTR_PB4_PUPEN_Pos (22U)
#define FLASH_OPTR_PB4_PUPEN_Msk (0x1UL << FLASH_OPTR_PB4_PUPEN_Pos) /*!< 0x00400000 */
#define FLASH_OPTR_PB4_PUPEN FLASH_OPTR_PB4_PUPEN_Msk
#define FLASH_OPTR_nBOOT1_Pos (23U)
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
#define FLASH_OPTR_SRAM_PE_Pos (24U)
#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
#define FLASH_OPTR_nSWBOOT0_Pos (26U)
#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
#define FLASH_OPTR_nBOOT0_Pos (27U)
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
#define FLASH_OPTR_NRST_MODE_Pos (28U)
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
#define FLASH_OPTR_IRHEN_Pos (30U)
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
/****************** Bits definition for FLASH_PCROP1SR register **********/
#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
/****************** Bits definition for FLASH_PCROP1ER register ***********/
#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
#define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_SEC1R register **************/
#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
#define FLASH_SEC1R_SEC_SIZE1_Msk (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
/******************************************************************************/
/* */
/* Filter Mathematical ACcelerator unit (FMAC) */
/* */
/******************************************************************************/
/***************** Bit definition for FMAC_X1BUFCFG register ****************/
#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
/***************** Bit definition for FMAC_X2BUFCFG register ****************/
#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
/***************** Bit definition for FMAC_YBUFCFG register *****************/
#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
/****************** Bit definition for FMAC_PARAM register ******************/
#define FMAC_PARAM_P_Pos (0U)
#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
#define FMAC_PARAM_Q_Pos (8U)
#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
#define FMAC_PARAM_R_Pos (16U)
#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
#define FMAC_PARAM_FUNC_Pos (24U)
#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
#define FMAC_PARAM_START_Pos (31U)
#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
/******************** Bit definition for FMAC_CR register *******************/
#define FMAC_CR_RIEN_Pos (0U)
#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
#define FMAC_CR_WIEN_Pos (1U)
#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
#define FMAC_CR_OVFLIEN_Pos (2U)
#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
#define FMAC_CR_UNFLIEN_Pos (3U)
#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
#define FMAC_CR_SATIEN_Pos (4U)
#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
#define FMAC_CR_DMAREN_Pos (8U)
#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
#define FMAC_CR_DMAWEN_Pos (9U)
#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
#define FMAC_CR_CLIPEN_Pos (15U)
#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
#define FMAC_CR_RESET_Pos (16U)
#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
/******************* Bit definition for FMAC_SR register ********************/
#define FMAC_SR_YEMPTY_Pos (0U)
#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
#define FMAC_SR_X1FULL_Pos (1U)
#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
#define FMAC_SR_OVFL_Pos (8U)
#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
#define FMAC_SR_UNFL_Pos (9U)
#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
#define FMAC_SR_SAT_Pos (10U)
#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
/****************** Bit definition for FMAC_WDATA register ******************/
#define FMAC_WDATA_WDATA_Pos (0U)
#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
/****************** Bit definition for FMACX_RDATA register *****************/
#define FMAC_RDATA_RDATA_Pos (0U)
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/* Legacy defines */
#define GPIO_BRR_BR_0 GPIO_BRR_BR0
#define GPIO_BRR_BR_1 GPIO_BRR_BR1
#define GPIO_BRR_BR_2 GPIO_BRR_BR2
#define GPIO_BRR_BR_3 GPIO_BRR_BR3
#define GPIO_BRR_BR_4 GPIO_BRR_BR4
#define GPIO_BRR_BR_5 GPIO_BRR_BR5
#define GPIO_BRR_BR_6 GPIO_BRR_BR6
#define GPIO_BRR_BR_7 GPIO_BRR_BR7
#define GPIO_BRR_BR_8 GPIO_BRR_BR8
#define GPIO_BRR_BR_9 GPIO_BRR_BR9
#define GPIO_BRR_BR_10 GPIO_BRR_BR10
#define GPIO_BRR_BR_11 GPIO_BRR_BR11
#define GPIO_BRR_BR_12 GPIO_BRR_BR12
#define GPIO_BRR_BR_13 GPIO_BRR_BR13
#define GPIO_BRR_BR_14 GPIO_BRR_BR14
#define GPIO_BRR_BR_15 GPIO_BRR_BR15
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_USERTRIM_Pos (4U)
#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
#define OPAMP_CSR_OPAMPINTEN_Pos (8U)
#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
#define OPAMP_CSR_OUTCAL_Pos (30U)
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
#define OPAMP_CSR_LOCK_Pos (31U)
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
/********************* Bit definition for OPAMPx_TCMR register ***************/
#define OPAMP_TCMR_VMSSEL_Pos (0U)
#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
#define OPAMP_TCMR_VPSSEL_Pos (1U)
#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
#define OPAMP_TCMR_T1CMEN_Pos (3U)
#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
#define OPAMP_TCMR_T8CMEN_Pos (4U)
#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
#define OPAMP_TCMR_T20CMEN_Pos (5U)
#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
#define OPAMP_TCMR_LOCK_Pos (31U)
#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_LPR_Pos (14U)
#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
#define PWR_CR1_VOS_Pos (9U)
#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_LPMS_Pos (0U)
#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
#define PWR_CR1_LPMS_STOP1_Pos (0U)
#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
#define PWR_CR1_LPMS_STANDBY_Pos (0U)
#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
/******************** Bit definition for PWR_CR2 register ********************/
/*!< PVME Peripheral Voltage Monitor Enable */
#define PWR_CR2_PVME_Pos (4U)
#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
#define PWR_CR2_PVME4_Pos (7U)
#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
#define PWR_CR2_PVME3_Pos (6U)
#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
#define PWR_CR2_PVME2_Pos (5U)
#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
#define PWR_CR2_PVME1_Pos (4U)
#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
/*!< PVD level configuration */
#define PWR_CR2_PLS_Pos (1U)
#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
#define PWR_CR2_PLS_LEV1_Pos (1U)
#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR2_PLS_LEV2_Pos (2U)
#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR2_PLS_LEV3_Pos (1U)
#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR2_PLS_LEV4_Pos (3U)
#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR2_PLS_LEV5_Pos (1U)
#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR2_PLS_LEV6_Pos (2U)
#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR2_PLS_LEV7_Pos (1U)
#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
#define PWR_CR2_PVDE_Pos (0U)
#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EIWF_Pos (15U)
#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
#define PWR_CR3_UCPD_DBDIS_Pos (14U)
#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
#define PWR_CR3_UCPD_STDBY_Pos (13U)
#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
#define PWR_CR3_APC_Pos (10U)
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
#define PWR_CR3_RRS_Pos (8U)
#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
#define PWR_CR3_EWUP5_Pos (4U)
#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
#define PWR_CR3_EWUP4_Pos (3U)
#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
#define PWR_CR3_EWUP3_Pos (2U)
#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
#define PWR_CR3_EWUP2_Pos (1U)
#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
#define PWR_CR3_EWUP1_Pos (0U)
#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
#define PWR_CR3_EWUP_Pos (0U)
#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
/******************** Bit definition for PWR_CR4 register ********************/
#define PWR_CR4_VBRS_Pos (9U)
#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
#define PWR_CR4_VBE_Pos (8U)
#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
#define PWR_CR4_WP5_Pos (4U)
#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
#define PWR_CR4_WP4_Pos (3U)
#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
#define PWR_CR4_WP3_Pos (2U)
#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
#define PWR_CR4_WP2_Pos (1U)
#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
#define PWR_CR4_WP1_Pos (0U)
#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
/******************** Bit definition for PWR_SR1 register ********************/
#define PWR_SR1_WUFI_Pos (15U)
#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
#define PWR_SR1_SBF_Pos (8U)
#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
#define PWR_SR1_WUF_Pos (0U)
#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
#define PWR_SR1_WUF5_Pos (4U)
#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
#define PWR_SR1_WUF4_Pos (3U)
#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
#define PWR_SR1_WUF3_Pos (2U)
#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
#define PWR_SR1_WUF2_Pos (1U)
#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
#define PWR_SR1_WUF1_Pos (0U)
#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
/******************** Bit definition for PWR_SR2 register ********************/
#define PWR_SR2_PVMO4_Pos (15U)
#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
#define PWR_SR2_PVMO3_Pos (14U)
#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
#define PWR_SR2_PVMO2_Pos (13U)
#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
#define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
#define PWR_SR2_VOSF_Pos (10U)
#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
#define PWR_SR2_REGLPF_Pos (9U)
#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
#define PWR_SR2_REGLPS_Pos (8U)
#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CSBF_Pos (8U)
#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
#define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
#define PWR_SCR_CWUF5_Pos (4U)
#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
#define PWR_SCR_CWUF4_Pos (3U)
#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
#define PWR_SCR_CWUF3_Pos (2U)
#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
#define PWR_SCR_CWUF2_Pos (1U)
#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
#define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
/******************** Bit definition for PWR_PUCRA register ********************/
#define PWR_PUCRA_PA15_Pos (15U)
#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
#define PWR_PUCRA_PA13_Pos (13U)
#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
#define PWR_PUCRA_PA12_Pos (12U)
#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
#define PWR_PUCRA_PA11_Pos (11U)
#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
#define PWR_PUCRA_PA10_Pos (10U)
#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
#define PWR_PUCRA_PA9_Pos (9U)
#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
#define PWR_PUCRA_PA8_Pos (8U)
#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
#define PWR_PUCRA_PA7_Pos (7U)
#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
#define PWR_PUCRA_PA6_Pos (6U)
#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
#define PWR_PUCRA_PA5_Pos (5U)
#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
#define PWR_PUCRA_PA4_Pos (4U)
#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
#define PWR_PUCRA_PA3_Pos (3U)
#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
#define PWR_PUCRA_PA2_Pos (2U)
#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
#define PWR_PUCRA_PA1_Pos (1U)
#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
#define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
/******************** Bit definition for PWR_PDCRA register ********************/
#define PWR_PDCRA_PA14_Pos (14U)
#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
#define PWR_PDCRA_PA12_Pos (12U)
#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
#define PWR_PDCRA_PA11_Pos (11U)
#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
#define PWR_PDCRA_PA10_Pos (10U)
#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
#define PWR_PDCRA_PA9_Pos (9U)
#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
#define PWR_PDCRA_PA8_Pos (8U)
#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
#define PWR_PDCRA_PA7_Pos (7U)
#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
#define PWR_PDCRA_PA6_Pos (6U)
#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
#define PWR_PDCRA_PA5_Pos (5U)
#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
#define PWR_PDCRA_PA4_Pos (4U)
#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
#define PWR_PDCRA_PA3_Pos (3U)
#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
#define PWR_PDCRA_PA2_Pos (2U)
#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
#define PWR_PDCRA_PA1_Pos (1U)
#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
#define PWR_PDCRA_PA0_Pos (0U)
#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
/******************** Bit definition for PWR_PUCRB register ********************/
#define PWR_PUCRB_PB15_Pos (15U)
#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
#define PWR_PUCRB_PB14_Pos (14U)
#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
#define PWR_PUCRB_PB13_Pos (13U)
#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
#define PWR_PUCRB_PB12_Pos (12U)
#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
#define PWR_PUCRB_PB11_Pos (11U)
#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
#define PWR_PUCRB_PB10_Pos (10U)
#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
#define PWR_PUCRB_PB9_Pos (9U)
#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
#define PWR_PUCRB_PB8_Pos (8U)
#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
#define PWR_PUCRB_PB7_Pos (7U)
#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
#define PWR_PUCRB_PB6_Pos (6U)
#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
#define PWR_PUCRB_PB5_Pos (5U)
#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
#define PWR_PUCRB_PB4_Pos (4U)
#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
#define PWR_PUCRB_PB3_Pos (3U)
#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
#define PWR_PUCRB_PB2_Pos (2U)
#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
#define PWR_PUCRB_PB1_Pos (1U)
#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
#define PWR_PUCRB_PB0_Pos (0U)
#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
/******************** Bit definition for PWR_PDCRB register ********************/
#define PWR_PDCRB_PB15_Pos (15U)
#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
#define PWR_PDCRB_PB14_Pos (14U)
#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
#define PWR_PDCRB_PB13_Pos (13U)
#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
#define PWR_PDCRB_PB12_Pos (12U)
#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
#define PWR_PDCRB_PB11_Pos (11U)
#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
#define PWR_PDCRB_PB10_Pos (10U)
#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
#define PWR_PDCRB_PB9_Pos (9U)
#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
#define PWR_PDCRB_PB8_Pos (8U)
#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
#define PWR_PDCRB_PB7_Pos (7U)
#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
#define PWR_PDCRB_PB6_Pos (6U)
#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
#define PWR_PDCRB_PB5_Pos (5U)
#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
#define PWR_PDCRB_PB3_Pos (3U)
#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
#define PWR_PDCRB_PB2_Pos (2U)
#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
#define PWR_PDCRB_PB1_Pos (1U)
#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
#define PWR_PDCRB_PB0_Pos (0U)
#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
/******************** Bit definition for PWR_PUCRC register ********************/
#define PWR_PUCRC_PC15_Pos (15U)
#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
#define PWR_PUCRC_PC14_Pos (14U)
#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
#define PWR_PUCRC_PC13_Pos (13U)
#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
#define PWR_PUCRC_PC12_Pos (12U)
#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
#define PWR_PUCRC_PC11_Pos (11U)
#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
#define PWR_PUCRC_PC10_Pos (10U)
#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
#define PWR_PUCRC_PC9_Pos (9U)
#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
#define PWR_PUCRC_PC8_Pos (8U)
#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
#define PWR_PUCRC_PC7_Pos (7U)
#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
#define PWR_PUCRC_PC6_Pos (6U)
#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
#define PWR_PUCRC_PC5_Pos (5U)
#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
#define PWR_PUCRC_PC4_Pos (4U)
#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
#define PWR_PUCRC_PC3_Pos (3U)
#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
#define PWR_PUCRC_PC2_Pos (2U)
#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
#define PWR_PUCRC_PC1_Pos (1U)
#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
#define PWR_PUCRC_PC0_Pos (0U)
#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
/******************** Bit definition for PWR_PDCRC register ********************/
#define PWR_PDCRC_PC15_Pos (15U)
#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
#define PWR_PDCRC_PC14_Pos (14U)
#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
#define PWR_PDCRC_PC13_Pos (13U)
#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
#define PWR_PDCRC_PC12_Pos (12U)
#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
#define PWR_PDCRC_PC11_Pos (11U)
#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
#define PWR_PDCRC_PC10_Pos (10U)
#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
#define PWR_PDCRC_PC9_Pos (9U)
#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
#define PWR_PDCRC_PC8_Pos (8U)
#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
#define PWR_PDCRC_PC7_Pos (7U)
#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
#define PWR_PDCRC_PC6_Pos (6U)
#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
#define PWR_PDCRC_PC5_Pos (5U)
#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
#define PWR_PDCRC_PC4_Pos (4U)
#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
#define PWR_PDCRC_PC3_Pos (3U)
#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
#define PWR_PDCRC_PC2_Pos (2U)
#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
#define PWR_PDCRC_PC1_Pos (1U)
#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
#define PWR_PDCRC_PC0_Pos (0U)
#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
/******************** Bit definition for PWR_PUCRD register ********************/
#define PWR_PUCRD_PD15_Pos (15U)
#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
#define PWR_PUCRD_PD14_Pos (14U)
#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
#define PWR_PUCRD_PD13_Pos (13U)
#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
#define PWR_PUCRD_PD12_Pos (12U)
#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
#define PWR_PUCRD_PD11_Pos (11U)
#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
#define PWR_PUCRD_PD10_Pos (10U)
#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
#define PWR_PUCRD_PD9_Pos (9U)
#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
#define PWR_PUCRD_PD8_Pos (8U)
#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
#define PWR_PUCRD_PD7_Pos (7U)
#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
#define PWR_PUCRD_PD6_Pos (6U)
#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
#define PWR_PUCRD_PD5_Pos (5U)
#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
#define PWR_PUCRD_PD4_Pos (4U)
#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
#define PWR_PUCRD_PD3_Pos (3U)
#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
#define PWR_PUCRD_PD2_Pos (2U)
#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
#define PWR_PUCRD_PD1_Pos (1U)
#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
#define PWR_PUCRD_PD0_Pos (0U)
#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register ********************/
#define PWR_PDCRD_PD15_Pos (15U)
#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
#define PWR_PDCRD_PD14_Pos (14U)
#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
#define PWR_PDCRD_PD13_Pos (13U)
#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
#define PWR_PDCRD_PD12_Pos (12U)
#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
#define PWR_PDCRD_PD11_Pos (11U)
#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
#define PWR_PDCRD_PD10_Pos (10U)
#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
#define PWR_PDCRD_PD9_Pos (9U)
#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
#define PWR_PDCRD_PD8_Pos (8U)
#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
#define PWR_PDCRD_PD7_Pos (7U)
#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
#define PWR_PDCRD_PD6_Pos (6U)
#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
#define PWR_PDCRD_PD5_Pos (5U)
#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
#define PWR_PDCRD_PD4_Pos (4U)
#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
#define PWR_PDCRD_PD3_Pos (3U)
#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
#define PWR_PDCRD_PD2_Pos (2U)
#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
#define PWR_PDCRD_PD1_Pos (1U)
#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
/******************** Bit definition for PWR_PUCRE register ********************/
#define PWR_PUCRE_PE15_Pos (15U)
#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
#define PWR_PUCRE_PE14_Pos (14U)
#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
#define PWR_PUCRE_PE13_Pos (13U)
#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
#define PWR_PUCRE_PE12_Pos (12U)
#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
#define PWR_PUCRE_PE11_Pos (11U)
#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
#define PWR_PUCRE_PE10_Pos (10U)
#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
#define PWR_PUCRE_PE9_Pos (9U)
#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
#define PWR_PUCRE_PE8_Pos (8U)
#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
#define PWR_PUCRE_PE7_Pos (7U)
#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
#define PWR_PUCRE_PE6_Pos (6U)
#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
#define PWR_PUCRE_PE5_Pos (5U)
#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
#define PWR_PUCRE_PE4_Pos (4U)
#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
#define PWR_PUCRE_PE3_Pos (3U)
#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
#define PWR_PUCRE_PE2_Pos (2U)
#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
#define PWR_PUCRE_PE1_Pos (1U)
#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
#define PWR_PUCRE_PE0_Pos (0U)
#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
/******************** Bit definition for PWR_PDCRE register ********************/
#define PWR_PDCRE_PE15_Pos (15U)
#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
#define PWR_PDCRE_PE14_Pos (14U)
#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
#define PWR_PDCRE_PE13_Pos (13U)
#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
#define PWR_PDCRE_PE12_Pos (12U)
#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
#define PWR_PDCRE_PE11_Pos (11U)
#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
#define PWR_PDCRE_PE10_Pos (10U)
#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
#define PWR_PDCRE_PE9_Pos (9U)
#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
#define PWR_PDCRE_PE8_Pos (8U)
#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
#define PWR_PDCRE_PE7_Pos (7U)
#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
#define PWR_PDCRE_PE6_Pos (6U)
#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
#define PWR_PDCRE_PE5_Pos (5U)
#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
#define PWR_PDCRE_PE4_Pos (4U)
#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
#define PWR_PDCRE_PE3_Pos (3U)
#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
#define PWR_PDCRE_PE2_Pos (2U)
#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
#define PWR_PDCRE_PE1_Pos (1U)
#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
#define PWR_PDCRE_PE0_Pos (0U)
#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
/******************** Bit definition for PWR_PUCRF register ********************/
#define PWR_PUCRF_PF15_Pos (15U)
#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
#define PWR_PUCRF_PF14_Pos (14U)
#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
#define PWR_PUCRF_PF13_Pos (13U)
#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
#define PWR_PUCRF_PF12_Pos (12U)
#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
#define PWR_PUCRF_PF11_Pos (11U)
#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
#define PWR_PUCRF_PF10_Pos (10U)
#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
#define PWR_PUCRF_PF9_Pos (9U)
#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
#define PWR_PUCRF_PF8_Pos (8U)
#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
#define PWR_PUCRF_PF7_Pos (7U)
#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
#define PWR_PUCRF_PF6_Pos (6U)
#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
#define PWR_PUCRF_PF5_Pos (5U)
#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
#define PWR_PUCRF_PF4_Pos (4U)
#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
#define PWR_PUCRF_PF3_Pos (3U)
#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
#define PWR_PUCRF_PF2_Pos (2U)
#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
#define PWR_PUCRF_PF1_Pos (1U)
#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
#define PWR_PUCRF_PF0_Pos (0U)
#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
/******************** Bit definition for PWR_PDCRF register ********************/
#define PWR_PDCRF_PF10_Pos (10U)
#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
#define PWR_PDCRF_PF9_Pos (9U)
#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
#define PWR_PDCRF_PF2_Pos (2U)
#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
#define PWR_PDCRF_PF1_Pos (1U)
#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
#define PWR_PDCRF_PF0_Pos (0U)
#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
/******************** Bit definition for PWR_PUCRG register ********************/
#define PWR_PUCRG_PG10_Pos (10U)
#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
/******************** Bit definition for PWR_PDCRG register ********************/
#define PWR_PDCRG_PG10_Pos (10U)
#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
#define PWR_PDCRG_PG9_Pos (9U)
#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
#define PWR_PDCRG_PG8_Pos (8U)
#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
#define PWR_PDCRG_PG7_Pos (7U)
#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
#define PWR_PDCRG_PG6_Pos (6U)
#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
#define PWR_PDCRG_PG5_Pos (5U)
#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
#define PWR_PDCRG_PG4_Pos (4U)
#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
#define PWR_PDCRG_PG3_Pos (3U)
#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
#define PWR_PDCRG_PG2_Pos (2U)
#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
#define PWR_PDCRG_PG1_Pos (1U)
#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
#define PWR_PDCRG_PG0_Pos (0U)
#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
/******************** Bit definition for PWR_CR5 register ********************/
#define PWR_CR5_R1MODE_Pos (8U)
#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
/******************************************************************************/
/* */
/* QUADSPI */
/* */
/******************************************************************************/
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
#define QUADSPI_CR_ABORT_Pos (1U)
#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
#define QUADSPI_CR_SSHIFT_Pos (4U)
#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
#define QUADSPI_CR_DFM_Pos (6U)
#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
#define QUADSPI_CR_FSEL_Pos (7U)
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
#define QUADSPI_CR_FTHRES_Pos (8U)
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
#define QUADSPI_CR_TEIE_Pos (16U)
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define QUADSPI_CR_TCIE_Pos (17U)
#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define QUADSPI_CR_FTIE_Pos (18U)
#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
#define QUADSPI_CR_SMIE_Pos (19U)
#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
#define QUADSPI_CR_TOIE_Pos (20U)
#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
#define QUADSPI_CR_APMS_Pos (22U)
#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
#define QUADSPI_CR_PMM_Pos (23U)
#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
#define QUADSPI_CR_PRESCALER_Pos (24U)
#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
/***************** Bit definition for QUADSPI_DCR register ******************/
#define QUADSPI_DCR_CKMODE_Pos (0U)
#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
#define QUADSPI_DCR_CSHT_Pos (8U)
#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_FSIZE_Pos (16U)
#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
/****************** Bit definition for QUADSPI_SR register *******************/
#define QUADSPI_SR_TEF_Pos (0U)
#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
#define QUADSPI_SR_TCF_Pos (1U)
#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
#define QUADSPI_SR_FTF_Pos (2U)
#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_SMF_Pos (3U)
#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
#define QUADSPI_SR_TOF_Pos (4U)
#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
#define QUADSPI_SR_BUSY_Pos (5U)
#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
#define QUADSPI_SR_FLEVEL_Pos (8U)
#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
/****************** Bit definition for QUADSPI_FCR register ******************/
#define QUADSPI_FCR_CTEF_Pos (0U)
#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
#define QUADSPI_FCR_CTCF_Pos (1U)
#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
#define QUADSPI_FCR_CSMF_Pos (3U)
#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
#define QUADSPI_FCR_CTOF_Pos (4U)
#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
/****************** Bit definition for QUADSPI_DLR register ******************/
#define QUADSPI_DLR_DL_Pos (0U)
#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
/****************** Bit definition for QUADSPI_CCR register ******************/
#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_IMODE_Pos (8U)
#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_ADMODE_Pos (10U)
#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADSIZE_Pos (12U)
#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ABMODE_Pos (14U)
#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABSIZE_Pos (16U)
#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_DCYC_Pos (18U)
#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DMODE_Pos (24U)
#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_FMODE_Pos (26U)
#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_SIOO_Pos (28U)
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_DHHC_Pos (30U)
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
#define QUADSPI_CCR_DDRM_Pos (31U)
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
/****************** Bit definition for QUADSPI_AR register *******************/
#define QUADSPI_AR_ADDRESS_Pos (0U)
#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
/****************** Bit definition for QUADSPI_ABR register ******************/
#define QUADSPI_ABR_ALTERNATE_Pos (0U)
#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
/****************** Bit definition for QUADSPI_DR register *******************/
#define QUADSPI_DR_DATA_Pos (0U)
#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
/****************** Bit definition for QUADSPI_PSMKR register ****************/
#define QUADSPI_PSMKR_MASK_Pos (0U)
#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
/****************** Bit definition for QUADSPI_PSMAR register ****************/
#define QUADSPI_PSMAR_MATCH_Pos (0U)
#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
/****************** Bit definition for QUADSPI_PIR register *****************/
#define QUADSPI_PIR_INTERVAL_Pos (0U)
#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
/****************** Bit definition for QUADSPI_LPTR register *****************/
#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (8U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
#define RCC_CR_HSIKERON_Pos (9U)
#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
#define RCC_CR_HSIRDY_Pos (10U)
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
#define RCC_CR_HSEON_Pos (16U)
#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
#define RCC_CR_PLLON_Pos (24U)
#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (16U)
#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
/*!< MCOSEL configuration */
#define RCC_CFGR_MCOSEL_Pos (24U)
#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
#define RCC_CFGR_MCOPRE_Pos (28U)
#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
/* Legacy aliases */
#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLSRC_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
#define RCC_PLLCFGR_PLLM_Pos (4U)
#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
#define RCC_PLLCFGR_PLLN_Pos (8U)
#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
#define RCC_PLLCFGR_PLLPEN_Pos (16U)
#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
#define RCC_PLLCFGR_PLLP_Pos (17U)
#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
#define RCC_PLLCFGR_PLLQEN_Pos (20U)
#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
#define RCC_PLLCFGR_PLLQ_Pos (21U)
#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
#define RCC_PLLCFGR_PLLREN_Pos (24U)
#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
#define RCC_PLLCFGR_PLLR_Pos (25U)
#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos (3U)
#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos (4U)
#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_PLLRDYIE_Pos (5U)
#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos (9U)
#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos (10U)
#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
/******************** Bit definition for RCC_CIFR register ******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos (3U)
#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos (4U)
#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_PLLRDYF_Pos (5U)
#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
#define RCC_CIFR_CSSF_Pos (8U)
#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
#define RCC_CIFR_LSECSSF_Pos (9U)
#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSI48RDYF_Pos (10U)
#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
/******************** Bit definition for RCC_CICR register ******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos (3U)
#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos (4U)
#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
#define RCC_CICR_PLLRDYC_Pos (5U)
#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
#define RCC_CICR_CSSC_Pos (8U)
#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
#define RCC_CICR_LSECSSC_Pos (9U)
#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSI48RDYC_Pos (10U)
#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
#define RCC_AHB1RSTR_CORDICRST_Pos (3U)
#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
#define RCC_AHB1RSTR_FMACRST_Pos (4U)
#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
#define RCC_AHB1RSTR_CRCRST_Pos (12U)
#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
#define RCC_AHB2RSTR_ADC12RST_Pos (13U)
#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
#define RCC_AHB2RSTR_ADC345RST_Pos (14U)
#define RCC_AHB2RSTR_ADC345RST_Msk (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
#define RCC_AHB2RSTR_ADC345RST RCC_AHB2RSTR_ADC345RST_Msk
#define RCC_AHB2RSTR_DAC1RST_Pos (16U)
#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
#define RCC_AHB2RSTR_DAC3RST_Pos (18U)
#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (26U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
/******************** Bit definition for RCC_AHB3RSTR register **************/
#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
/******************** Bit definition for RCC_APB1RSTR1 register **************/
#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
#define RCC_APB1RSTR1_CRSRST_Pos (8U)
#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
#define RCC_APB1RSTR1_USART2RST_Pos (17U)
#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
#define RCC_APB1RSTR1_USART3RST_Pos (18U)
#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
#define RCC_APB1RSTR1_UART4RST_Pos (19U)
#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
#define RCC_APB1RSTR1_UART5RST_Pos (20U)
#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
#define RCC_APB1RSTR1_USBRST_Pos (23U)
#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
#define RCC_APB1RSTR1_FDCANRST_Pos (25U)
#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
#define RCC_APB1RSTR1_PWRRST_Pos (28U)
#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
#define RCC_APB1RSTR1_I2C3RST_Pos (30U)
#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
#define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_TIM8RST_Pos (13U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_TIM20RST_Pos (20U)
#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define RCC_AHB1ENR_DMA2EN_Pos (1U)
#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
#define RCC_AHB1ENR_CORDICEN_Pos (3U)
#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
#define RCC_AHB1ENR_FMACEN_Pos (4U)
#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
#define RCC_AHB1ENR_FLASHEN_Pos (8U)
#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
#define RCC_AHB1ENR_CRCEN_Pos (12U)
#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
#define RCC_AHB2ENR_GPIODEN_Pos (3U)
#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
#define RCC_AHB2ENR_ADC12EN_Pos (13U)
#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
#define RCC_AHB2ENR_ADC345EN_Pos (14U)
#define RCC_AHB2ENR_ADC345EN_Msk (0x1UL << RCC_AHB2ENR_ADC345EN_Pos) /*!< 0x00004000 */
#define RCC_AHB2ENR_ADC345EN RCC_AHB2ENR_ADC345EN_Msk
#define RCC_AHB2ENR_DAC1EN_Pos (16U)
#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
#define RCC_AHB2ENR_DAC3EN_Pos (18U)
#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (26U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
/******************** Bit definition for RCC_AHB3ENR register ***************/
#define RCC_AHB3ENR_QSPIEN_Pos (8U)
#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
/******************** Bit definition for RCC_APB1ENR1 register ***************/
#define RCC_APB1ENR1_TIM2EN_Pos (0U)
#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
#define RCC_APB1ENR1_TIM3EN_Pos (1U)
#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
#define RCC_APB1ENR1_TIM7EN_Pos (5U)
#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
#define RCC_APB1ENR1_CRSEN_Pos (8U)
#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
#define RCC_APB1ENR1_WWDGEN_Pos (11U)
#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
#define RCC_APB1ENR1_SPI2EN_Pos (14U)
#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
#define RCC_APB1ENR1_SPI3EN_Pos (15U)
#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
#define RCC_APB1ENR1_USART2EN_Pos (17U)
#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
#define RCC_APB1ENR1_USART3EN_Pos (18U)
#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
#define RCC_APB1ENR1_UART4EN_Pos (19U)
#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
#define RCC_APB1ENR1_UART5EN_Pos (20U)
#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
#define RCC_APB1ENR1_I2C1EN_Pos (21U)
#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
#define RCC_APB1ENR1_I2C2EN_Pos (22U)
#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
#define RCC_APB1ENR1_USBEN_Pos (23U)
#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
#define RCC_APB1ENR1_FDCANEN_Pos (25U)
#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
#define RCC_APB1ENR1_PWREN_Pos (28U)
#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
#define RCC_APB1ENR1_I2C3EN_Pos (30U)
#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
#define RCC_APB1ENR2_UCPD1EN_Pos (8U)
#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
#define RCC_APB2ENR_TIM1EN_Pos (11U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_TIM8EN_Pos (13U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define RCC_APB2ENR_USART1EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_TIM20EN_Pos (20U)
#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
/******************** Bit definition for RCC_AHB2SMENR register *************/
#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
#define RCC_AHB2SMENR_ADC345SMEN_Pos (14U)
#define RCC_AHB2SMENR_ADC345SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
#define RCC_AHB2SMENR_ADC345SMEN RCC_AHB2SMENR_ADC345SMEN_Msk
#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register *************/
#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
/******************** Bit definition for RCC_APB1SMENR1 register *************/
#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
#define RCC_APB1SMENR1_USBSMEN_Pos (23U)
#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
/******************** Bit definition for RCC_APB1SMENR2 register *************/
#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
/******************** Bit definition for RCC_APB2SMENR register *************/
#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
#define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
#define RCC_CCIPR_USART2SEL_Pos (2U)
#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
#define RCC_CCIPR_USART3SEL_Pos (4U)
#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
#define RCC_CCIPR_UART4SEL_Pos (6U)
#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR_UART5SEL_Pos (8U)
#define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
#define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR_LPUART1SEL_Pos (10U)
#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
#define RCC_CCIPR_I2C1SEL_Pos (12U)
#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR_I2C2SEL_Pos (14U)
#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR_I2C3SEL_Pos (16U)
#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
#define RCC_CCIPR_SAI1SEL_Pos (20U)
#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
#define RCC_CCIPR_I2S23SEL_Pos (22U)
#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
#define RCC_CCIPR_FDCANSEL_Pos (24U)
#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR_CLK48SEL_Pos (26U)
#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
#define RCC_CCIPR_ADC12SEL_Pos (28U)
#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
#define RCC_CCIPR_ADC345SEL_Pos (30U)
#define RCC_CCIPR_ADC345SEL_Msk (0x3UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
#define RCC_CCIPR_ADC345SEL RCC_CCIPR_ADC345SEL_Msk
#define RCC_CCIPR_ADC345SEL_0 (0x1UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x40000000 */
#define RCC_CCIPR_ADC345SEL_1 (0x2UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos (3U)
#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos (5U)
#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos (6U)
#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
#define RCC_BDCR_LSCOEN_Pos (24U)
#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
#define RCC_BDCR_LSCOSEL_Pos (25U)
#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION_Pos (0U)
#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos (1U)
#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
#define RCC_CSR_RMVF_Pos (23U)
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
#define RCC_CSR_OBLRSTF_Pos (25U)
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_BORRSTF_Pos (27U)
#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/******************** Bit definition for RCC_CRRCR register *****************/
#define RCC_CRRCR_HSI48ON_Pos (0U)
#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
#define RCC_CRRCR_HSI48RDY_Pos (1U)
#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos (7U)
#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
/******************** Bit definition for RCC_CCIPR2 register ******************/
#define RCC_CCIPR2_QSPISEL_Pos (20U)
#define RCC_CCIPR2_QSPISEL_Msk (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR2_QSPISEL RCC_CCIPR2_QSPISEL_Msk
#define RCC_CCIPR2_QSPISEL_0 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR2_QSPISEL_1 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_ICSR register ******************/
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_ALRBWF_Pos (1U)
#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
#define RTC_ICSR_ALRAWF_Pos (0U)
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_SR register *******************/
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
/******************** Bits definition for RTC_MISR register *****************/
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
/******************** Bits definition for RTC_SCR register ******************/
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register *****************/
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos (21U)
#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
/******************** Bits definition for TAMP_CR2 register *****************/
#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
#define TAMP_CR2_TAMP1MF_Pos (16U)
#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
#define TAMP_CR2_TAMP2MF_Pos (17U)
#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
#define TAMP_CR2_TAMP3MF_Pos (18U)
#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_IER register *****************/
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos (21U)
#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
/******************** Bits definition for TAMP_SR register ******************/
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos (21U)
#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
/******************** Bits definition for TAMP_MISR register ****************/
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos (21U)
#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
/******************** Bits definition for TAMP_SCR register *****************/
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos (21U)
#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
/******************** Bits definition for TAMP_BKP1R register ***************/
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
/******************** Bits definition for TAMP_BKP2R register ***************/
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
/******************** Bits definition for TAMP_BKP3R register ***************/
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
/******************** Bits definition for TAMP_BKP4R register ***************/
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************** Bits definition for TAMP_BKP5R register ***************/
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
/******************** Bits definition for TAMP_BKP6R register ***************/
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
/******************** Bits definition for TAMP_BKP7R register ***************/
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
/******************** Bits definition for TAMP_BKP8R register ***************/
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
/******************** Bits definition for TAMP_BKP9R register ***************/
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
/******************** Bits definition for TAMP_BKP10R register ***************/
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
/******************** Bits definition for TAMP_BKP11R register ***************/
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
/******************** Bits definition for TAMP_BKP12R register ***************/
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
/******************** Bits definition for TAMP_BKP13R register ***************/
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
/******************** Bits definition for TAMP_BKP14R register ***************/
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
/******************** Bits definition for TAMP_BKP15R register ***************/
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
/******************** Bits definition for TAMP_BKP16R register ***************/
#define TAMP_BKP16R_Pos (0U)
#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP16R TAMP_BKP16R_Msk
/******************** Bits definition for TAMP_BKP17R register ***************/
#define TAMP_BKP17R_Pos (0U)
#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP17R TAMP_BKP17R_Msk
/******************** Bits definition for TAMP_BKP18R register ***************/
#define TAMP_BKP18R_Pos (0U)
#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP18R TAMP_BKP18R_Msk
/******************** Bits definition for TAMP_BKP19R register ***************/
#define TAMP_BKP19R_Pos (0U)
#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP19R TAMP_BKP19R_Msk
/******************** Bits definition for TAMP_BKP20R register ***************/
#define TAMP_BKP20R_Pos (0U)
#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP20R TAMP_BKP20R_Msk
/******************** Bits definition for TAMP_BKP21R register ***************/
#define TAMP_BKP21R_Pos (0U)
#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP21R TAMP_BKP21R_Msk
/******************** Bits definition for TAMP_BKP22R register ***************/
#define TAMP_BKP22R_Pos (0U)
#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP22R TAMP_BKP22R_Msk
/******************** Bits definition for TAMP_BKP23R register ***************/
#define TAMP_BKP23R_Pos (0U)
#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP23R TAMP_BKP23R_Msk
/******************** Bits definition for TAMP_BKP24R register ***************/
#define TAMP_BKP24R_Pos (0U)
#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP24R TAMP_BKP24R_Msk
/******************** Bits definition for TAMP_BKP25R register ***************/
#define TAMP_BKP25R_Pos (0U)
#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP25R TAMP_BKP25R_Msk
/******************** Bits definition for TAMP_BKP26R register ***************/
#define TAMP_BKP26R_Pos (0U)
#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP26R TAMP_BKP26R_Msk
/******************** Bits definition for TAMP_BKP27R register ***************/
#define TAMP_BKP27R_Pos (0U)
#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP27R TAMP_BKP27R_Msk
/******************** Bits definition for TAMP_BKP28R register ***************/
#define TAMP_BKP28R_Pos (0U)
#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP28R TAMP_BKP28R_Msk
/******************** Bits definition for TAMP_BKP29R register ***************/
#define TAMP_BKP29R_Pos (0U)
#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP29R TAMP_BKP29R_Msk
/******************** Bits definition for TAMP_BKP30R register ***************/
#define TAMP_BKP30R_Pos (0U)
#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP30R TAMP_BKP30R_Msk
/******************** Bits definition for TAMP_BKP31R register ***************/
#define TAMP_BKP31R_Pos (0U)
#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP31R TAMP_BKP31R_Msk
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/****************** Bit definition for SAI_PDMCR register *******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
#define SPI_CR1_CPOL_Pos (1U)
#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
#define SPI_CR1_MSTR_Pos (2U)
#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
#define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
#define SPI_CR1_LSBFIRST_Pos (7U)
#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
#define SPI_CR1_SSI_Pos (8U)
#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
#define SPI_CR1_SSM_Pos (9U)
#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
#define SPI_CR1_RXONLY_Pos (10U)
#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
#define SPI_CR1_CRCL_Pos (11U)
#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
#define SPI_CR1_CRCNEXT_Pos (12U)
#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
#define SPI_CR1_CRCEN_Pos (13U)
#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE_Pos (14U)
#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos (15U)
#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN_Pos (0U)
#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN_Pos (1U)
#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
#define SPI_CR2_SSOE_Pos (2U)
#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
#define SPI_CR2_NSSP_Pos (3U)
#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
#define SPI_CR2_FRF_Pos (4U)
#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
#define SPI_CR2_ERRIE_Pos (5U)
#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE_Pos (6U)
#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE_Pos (7U)
#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
#define SPI_CR2_LDMARX_Pos (13U)
#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
#define SPI_CR2_LDMATX_Pos (14U)
#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE_Pos (0U)
#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
#define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
#define SPI_SR_MODF_Pos (5U)
#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
#define SPI_SR_BSY_Pos (7U)
#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
#define SPI_SR_FRE_Pos (8U)
#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
#define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U)
#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY_Pos (0U)
#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC_Pos (0U)
#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC_Pos (0U)
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN_Pos (0U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN_Pos (1U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_CKPOL_Pos (3U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_I2SE_Pos (10U)
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD_Pos (8U)
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE_Pos (9U)
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
/****************** Bit definition for SYSCFG_CFGR1 register ******************/
#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
/****************** Bit definition for SYSCFG_SCSR register ****************/
#define SYSCFG_SCSR_CCMER_Pos (0U)
#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
#define SYSCFG_SCSR_CCMBSY_Pos (1U)
#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
/****************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_CLL_Pos (0U)
#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
#define SYSCFG_CFGR2_SPL_Pos (1U)
#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
#define SYSCFG_CFGR2_PVDL_Pos (2U)
#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
#define SYSCFG_CFGR2_ECCL_Pos (3U)
#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
#define SYSCFG_CFGR2_SPF_Pos (8U)
#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
#define TIM_CR1_CMS_Pos (5U)
#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos (7U)
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos (8U)
#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos (12U)
#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos (15U)
#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos (3U)
#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE_Pos (0U)
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos (1U)
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos (2U)
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos (3U)
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos (4U)
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos (5U)
#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos (6U)
#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos (7U)
#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos (8U)
#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos (9U)
#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos (10U)
#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos (11U)
#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos (12U)
#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos (13U)
#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos (14U)
#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos (20U)
#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos (21U)
#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos (20U)
#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
#define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos (21U)
#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
#define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos (22U)
#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
#define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos (23U)
#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
#define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG_Pos (0U)
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos (6U)
#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
#define TIM_EGR_BG_Pos (7U)
#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
#define TIM_EGR_B2G_Pos (8U)
#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos (4U)
#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos (12U)
#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA_Pos (0U)
#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos (8U)
#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
/******************* Bit definition for TIM1_AF1 register *******************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
#define TIM1_AF1_BKCMP1E_Pos (1U)
#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
#define TIM1_AF1_BKCMP2E_Pos (2U)
#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
#define TIM1_AF1_BKCMP3E_Pos (3U)
#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
#define TIM1_AF1_BKCMP4E_Pos (4U)
#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
#define TIM1_AF1_BKCMP1P_Pos (10U)
#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
#define TIM1_AF1_BKCMP2P_Pos (11U)
#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
#define TIM1_AF1_BKCMP3P_Pos (12U)
#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
#define TIM1_AF1_BKCMP4P_Pos (13U)
#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
#define TIM1_AF1_ETRSEL_Pos (14U)
#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
#define TIM1_AF2_BK2CMP1E_Pos (1U)
#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
#define TIM1_AF2_BK2CMP2E_Pos (2U)
#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
#define TIM1_AF2_BK2CMP3E_Pos (3U)
#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
#define TIM1_AF2_BK2CMP4E_Pos (4U)
#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
#define TIM1_AF2_BK2CMP1P_Pos (10U)
#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
#define TIM1_AF2_BK2CMP2P_Pos (11U)
#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_BK2CMP3P_Pos (12U)
#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
#define TIM1_AF2_BK2CMP4P_Pos (13U)
#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
#define TIM1_AF2_OCRSEL_Pos (16U)
#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_HSE32EN_Pos (0U)
#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM_DTR2 register *********************/
#define TIM_DTR2_DTGF_Pos (0U)
#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos (16U)
#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos (17U)
#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
/******************* Bit definition for TIM_ECR register *********************/
#define TIM_ECR_IE_Pos (0U)
#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
#define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
#define TIM_ECR_IDIR_Pos (1U)
#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_FIDX_Pos (5U)
#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
#define TIM_ECR_IPOS_Pos (6U)
#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
#define TIM_ECR_PW_Pos (16U)
#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
#define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos (24U)
#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB_Pos (0U)
#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_OR register *******************/
#define LPTIM_OR_IN1_Pos (0U)
#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
#define LPTIM_OR_IN2_Pos (1U)
#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART_Pos (0U)
#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR_Pos (0U)
#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */
#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
/******************* Bit definition for VREFBUF_CCR register ******************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* USB Device FS Endpoint registers */
/* */
/******************************************************************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
/* bit positions */
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
/* */
/* USB Device FS General registers */
/* */
/******************************************************************************/
#define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
#define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
#define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
#define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
#define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
#define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
/****************** Bits definition for USB_CNTR register *******************/
#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/****************** Bits definition for USB_ISTR register *******************/
#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
/****************** Bits definition for USB_FNR register ********************/
#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
/****************** Bits definition for USB_DADDR register ****************/
#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
#define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
#define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
#define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
#define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
#define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
#define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
#define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
#define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
/****************** Bit definition for USB_BTABLE register ******************/
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
/****************** Bits definition for USB_BCDR register *******************/
#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
/******************* Bit definition for LPMCSR register *********************/
#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
/*!< Buffer descriptor table */
/***************** Bit definition for USB_ADDR0_TX register *****************/
#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_TX register *****************/
#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_TX register *****************/
#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_TX register *****************/
#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_TX register *****************/
#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_TX register *****************/
#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_TX register *****************/
#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_TX register *****************/
#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_TX register ****************/
#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
/***************** Bit definition for USB_COUNT1_TX register ****************/
#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
/***************** Bit definition for USB_COUNT2_TX register ****************/
#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
/***************** Bit definition for USB_COUNT3_TX register ****************/
#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
/***************** Bit definition for USB_COUNT4_TX register ****************/
#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
/***************** Bit definition for USB_COUNT5_TX register ****************/
#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
/***************** Bit definition for USB_COUNT6_TX register ****************/
#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
/***************** Bit definition for USB_COUNT7_TX register ****************/
#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_ADDR0_RX register *****************/
#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_RX register *****************/
#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_RX register *****************/
#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_RX register *****************/
#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_RX register *****************/
#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_RX register *****************/
#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_RX register *****************/
#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_RX register *****************/
#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_RX register ****************/
#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT0_RX_BLSIZE_Pos (15U)
#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT1_RX register ****************/
#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT1_RX_BLSIZE_Pos (15U)
#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT2_RX register ****************/
#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT2_RX_BLSIZE_Pos (15U)
#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT3_RX register ****************/
#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT3_RX_BLSIZE_Pos (15U)
#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT4_RX register ****************/
#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT4_RX_BLSIZE_Pos (15U)
#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT5_RX register ****************/
#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT5_RX_BLSIZE_Pos (15U)
#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT6_RX register ****************/
#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT6_RX_BLSIZE_Pos (15U)
#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT7_RX register ****************/
#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT7_RX_BLSIZE_Pos (15U)
#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
/* UCPD */
/* */
/******************************************************************************/
/******************** Bits definition for UCPD_CFG1 register *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos (6U)
#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos (11U)
#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos (20U)
#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos (29U)
#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define UCPD_CFG1_RXDMAEN_Pos (30U)
#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define UCPD_CFG1_UCPDEN_Pos (31U)
#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
/******************** Bits definition for UCPD_CFG2 register *******************/
#define UCPD_CFG2_RXFILTDIS_Pos (0U)
#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos (1U)
#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos (2U)
#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos (3U)
#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
/******************** Bits definition for UCPD_CR register ********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos (2U)
#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXHRST_Pos (3U)
#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
#define UCPD_CR_RXMODE_Pos (4U)
#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
#define UCPD_CR_PHYRXEN_Pos (5U)
#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
#define UCPD_CR_PHYCCSEL_Pos (6U)
#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
#define UCPD_CR_ANASUBMODE_Pos (7U)
#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos (9U)
#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
#define UCPD_CR_CCENABLE_Pos (10U)
#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
#define UCPD_CR_FRSRXEN_Pos (16U)
#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
#define UCPD_CR_FRSTX_Pos (17U)
#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos (18U)
#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
#define UCPD_CR_CC1TCDIS_Pos (20U)
#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos (21U)
#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
/******************** Bits definition for UCPD_IMR register *******************/
#define UCPD_IMR_TXISIE_Pos (0U)
#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
#define UCPD_IMR_TXMSGABTIE_Pos (3U)
#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
#define UCPD_IMR_HRSTDISCIE_Pos (4U)
#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
#define UCPD_IMR_HRSTSENTIE_Pos (5U)
#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
#define UCPD_IMR_TXUNDIE_Pos (6U)
#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
#define UCPD_IMR_RXNEIE_Pos (8U)
#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
#define UCPD_IMR_RXORDDETIE_Pos (9U)
#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
#define UCPD_IMR_RXOVRIE_Pos (11U)
#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
#define UCPD_IMR_RXMSGENDIE_Pos (12U)
#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
#define UCPD_IMR_FRSEVTIE_Pos (20U)
#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
/******************** Bits definition for UCPD_SR register ********************/
#define UCPD_SR_TXIS_Pos (0U)
#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
#define UCPD_SR_TXMSGDISC_Pos (1U)
#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
#define UCPD_SR_TXMSGSENT_Pos (2U)
#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
#define UCPD_SR_TXMSGABT_Pos (3U)
#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
#define UCPD_SR_HRSTDISC_Pos (4U)
#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
#define UCPD_SR_HRSTSENT_Pos (5U)
#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
#define UCPD_SR_TXUND_Pos (6U)
#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
#define UCPD_SR_RXNE_Pos (8U)
#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
#define UCPD_SR_RXORDDET_Pos (9U)
#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
#define UCPD_SR_RXHRSTDET_Pos (10U)
#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
#define UCPD_SR_RXOVR_Pos (11U)
#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
#define UCPD_SR_RXMSGEND_Pos (12U)
#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
#define UCPD_SR_RXERR_Pos (13U)
#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos (14U)
#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
#define UCPD_SR_TYPECEVT2_Pos (15U)
#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
#define UCPD_SR_FRSEVT_Pos (20U)
#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
/******************** Bits definition for UCPD_ICR register *******************/
#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
#define UCPD_ICR_TXMSGABTCF_Pos (3U)
#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
#define UCPD_ICR_HRSTDISCCF_Pos (4U)
#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
#define UCPD_ICR_HRSTSENTCF_Pos (5U)
#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
#define UCPD_ICR_TXUNDCF_Pos (6U)
#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
#define UCPD_ICR_RXORDDETCF_Pos (9U)
#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
#define UCPD_ICR_RXOVRCF_Pos (11U)
#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
#define UCPD_ICR_RXMSGENDCF_Pos (12U)
#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
#define UCPD_ICR_FRSEVTCF_Pos (20U)
#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
/******************** Bits definition for UCPD_TXORDSET register **************/
#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
/******************** Bits definition for UCPD_TXPAYSZ register ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
/******************** Bits definition for UCPD_TXDR register *******************/
#define UCPD_TXDR_TXDATA_Pos (0U)
#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
/******************** Bits definition for UCPD_RXORDSET register **************/
#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
/******************** Bits definition for UCPD_RXPAYSZ register ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
/******************** Bits definition for UCPD_RXDR register *******************/
#define UCPD_RXDR_RXDATA_Pos (0U)
#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/******************** Bits definition for UCPD_RXORDEXT1 register **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
/******************** Bits definition for UCPD_RXORDEXT2 register **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2) || \
((INSTANCE) == ADC3))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
((INSTANCE) == ADC345_COMMON) )
/******************************** FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
((INSTANCE) == FDCAN2))
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2) || \
((INSTANCE) == COMP3) || \
((INSTANCE) == COMP4))
/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC3))
/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7) || \
((INSTANCE) == DMA1_Channel8) || \
((INSTANCE) == DMA2_Channel1) || \
((INSTANCE) == DMA2_Channel2) || \
((INSTANCE) == DMA2_Channel3) || \
((INSTANCE) == DMA2_Channel4) || \
((INSTANCE) == DMA2_Channel5) || \
((INSTANCE) == DMA2_Channel6) || \
((INSTANCE) == DMA2_Channel7) || \
((INSTANCE) == DMA2_Channel8))
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
/******************************* FMAC Instances *******************************/
#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances *****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3))
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3) || \
((INSTANCE) == OPAMP6))
/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/******************************* QSPI Instances *******************************/
#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3))
/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
((__INSTANCE__) == SPI3))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** UCPD Instances ********************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
/******************************* USB Instances *******************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/**
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32G4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32G4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
/* Aliases for __IRQHandler */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32G491xx_H */
/**
* @}
*/
/**
* @}
*/
| 1,034,283 | C | 74.418113 | 180 | 0.511259 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g473xx.h | /**
******************************************************************************
* @file stm32g473xx.h
* @author MCD Application Team
* @brief CMSIS STM32G473xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32g473xx
* @{
*/
#ifndef __STM32G473xx_H
#define __STM32G473xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32G4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ***************************************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_IRQn = 19, /*!< USB HP Interrupt */
USB_LP_IRQn = 20, /*!< USB LP Interrupt */
FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
FMC_IRQn = 48, /*!< FMC global Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
TIM7_DAC_IRQn = 55, /*!< TIM7 global and DAC2&4 underrun error interrupts */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
ADC5_IRQn = 62, /*!< ADC5 global Interrupt */
UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 */
COMP7_IRQn = 66, /*!< COMP7 Interrupt */
CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
I2C4_EV_IRQn = 82, /*!< I2C4 Event interrupt */
I2C4_ER_IRQn = 83, /*!< I2C4 Error interrupt */
SPI4_IRQn = 84, /*!< SPI4 Event interrupt */
FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */
FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */
FDCAN3_IT0_IRQn = 88, /*!< FDCAN3 interrupt line 0 interrupt */
FDCAN3_IT1_IRQn = 89, /*!< FDCAN3 interrupt line 1 interrupt */
RNG_IRQn = 90, /*!< RNG global interrupt */
LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */
DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */
DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */
DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */
CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
FMAC_IRQn = 101 /*!< FMAC global Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32g4xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
__IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
} FDCAN_Config_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
__IO uint32_t RESERVED[2];
__IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
__IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
__IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
__IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
__IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
__IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
__IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
uint32_t RESERVED2[4]; /*!< Reserved2, Address offset: 0x34 */
__IO uint32_t PCROP2SR; /*!< FLASH bank2 PCROP start address register, Address offset: 0x44 */
__IO uint32_t PCROP2ER; /*!< FLASH bank2 PCROP end address register, Address offset: 0x48 */
__IO uint32_t WRP2AR; /*!< FLASH bank2 WRP area A address register, Address offset: 0x4C */
__IO uint32_t WRP2BR; /*!< FLASH bank2 WRP area B address register, Address offset: 0x50 */
uint32_t RESERVED3[7]; /*!< Reserved3, Address offset: 0x54 */
__IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
__IO uint32_t SEC2R; /*!< FLASH Securable memory register bank2, Address offset: 0x74 */
} FLASH_TypeDef;
/**
* @brief FMAC
*/
typedef struct
{
__IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
__IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
__IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
__IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
} FMAC_TypeDef;
/**
* @brief Flexible Memory Controller
*/
typedef struct
{
__IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */
} FMC_Bank1_TypeDef;
/**
* @brief Flexible Memory Controller Bank1E
*/
typedef struct
{
__IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} FMC_Bank1E_TypeDef;
/**
* @brief Flexible Memory Controller Bank3
*/
typedef struct
{
__IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */
__IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */
__IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */
__IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */
uint32_t RESERVED0; /*!< Reserved, 0x90 */
__IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */
} FMC_Bank3_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
} OPAMP_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
__IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief QUAD Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
__IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
__IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
__IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
__IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
__IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
__IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
/*
* @brief Specific device feature definitions
*/
#define RTC_TAMP_INT_6_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 3u
#define RTC_BACKUP_NB 32u
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
} RTC_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
__IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
__IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
__IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
__IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
__IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
__IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
__IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
__IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
__IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
__IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
__IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
__IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
__IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
__IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
__IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
__IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
} TAMP_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
__IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
__IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
__IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
__IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
__IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
__IO uint16_t RESERVEDD; /*!< Reserved */
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
__IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief CORDIC
*/
typedef struct
{
__IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
__IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
__IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
} CORDIC_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */
#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(32 KB) base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define FMC_BASE (0x60000000UL) /*!< FMC base address */
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
#define FMC_R_BASE (0xA0000000UL) /*!< FMC control registers base address */
#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(32 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
#define CCMSRAM_SIZE (0x00008000UL) /*!< CCMSRAM size (32 KBytes) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
#define FMC_BANK1 FMC_BASE
#define FMC_BANK1_1 FMC_BANK1
#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL)
#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL)
#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL)
#define FMC_BANK3 (FMC_BASE + 0x20000000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
#define FDCAN3_BASE (APB1PERIPH_BASE + 0x6C00UL)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
#define I2C4_BASE (APB1PERIPH_BASE + 0x8400UL)
#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
#define COMP5_BASE (APB2PERIPH_BASE + 0x0210UL)
#define COMP6_BASE (APB2PERIPH_BASE + 0x0214UL)
#define COMP7_BASE (APB2PERIPH_BASE + 0x0218UL)
#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
#define OPAMP4_BASE (APB2PERIPH_BASE + 0x030CUL)
#define OPAMP5_BASE (APB2PERIPH_BASE + 0x0310UL)
#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
#define SPI4_BASE (APB2PERIPH_BASE + 0x3C00UL)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
/*!< AHB1 peripherals */
#define DMA1_BASE (AHB1PERIPH_BASE)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
/*!< AHB2 peripherals */
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)
#define ADC4_BASE (AHB2PERIPH_BASE + 0x08000500UL)
#define ADC5_BASE (AHB2PERIPH_BASE + 0x08000600UL)
#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)
#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC2_BASE (AHB2PERIPH_BASE + 0x08000C00UL)
#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
#define DAC4_BASE (AHB2PERIPH_BASE + 0x08001400UL)
/*!< FMC Banks registers base address */
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0042000UL)
#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
#define OPAMP5 ((OPAMP_TypeDef *) OPAMP5_BASE)
#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
#define ADC5 ((ADC_TypeDef *) ADC5_BASE)
#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
#define DAC4 ((DAC_TypeDef *) DAC4_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos (15U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
#define ADC_CFGR2_GCOMP_Pos (16U)
#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
#define ADC_CFGR2_SWTRIG_Pos (25U)
#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
#define ADC_CFGR2_BULB_Pos (26U)
#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
#define ADC_CFGR2_SMPTRIG_Pos (27U)
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_AWDFILT_Pos (12U)
#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSETPOS_Pos (24U)
#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
#define ADC_OFR1_SATEN_Pos (25U)
#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSETPOS_Pos (24U)
#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
#define ADC_OFR2_SATEN_Pos (25U)
#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSETPOS_Pos (24U)
#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
#define ADC_OFR3_SATEN_Pos (25U)
#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSETPOS_Pos (24U)
#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
#define ADC_OFR4_SATEN_Pos (25U)
#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
/******************** Bit definition for ADC_GCOMP register *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos (13U)
#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
#define ADC_CCR_MDMA_Pos (14U)
#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_VSENSESEL_Pos (23U)
#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATSEL_Pos (24U)
#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_INMSEL_Pos (4U)
#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_Pos (8U)
#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
#define COMP_CSR_BLANKING_Pos (19U)
#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
/* CORDIC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CORDIC_CSR register *****************/
#define CORDIC_CSR_FUNC_Pos (0U)
#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos (4U)
#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos (8U)
#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos (16U)
#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos (17U)
#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos (18U)
#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos (19U)
#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos (20U)
#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos (21U)
#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos (22U)
#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos (31U)
#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
/******************* Bit definition for CORDIC_WDATA register ***************/
#define CORDIC_WDATA_ARG_Pos (0U)
#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
/******************* Bit definition for CORDIC_RDATA register ***************/
#define CORDIC_RDATA_RES_Pos (0U)
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_Pos (16U)
#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
#define DAC_DOR2_DACC2DORB_Pos (16U)
#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DAC1RDY_Pos (11U)
#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
#define DAC_SR_DORSTAT1_Pos (12U)
#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
#define DAC_SR_DORSTAT2_Pos (28U)
#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos (8U)
#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos (9U)
#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
#define DAC_MCR_HFSEL_Pos (14U)
#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
#define DAC_MCR_DMADOUBLE2_Pos (24U)
#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
#define DAC_MCR_SINFORMAT2_Pos (25U)
#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR2_TSAMPLE2_Pos (0U)
#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/****************** Bit definition for DAC_STR1 register ******************/
#define DAC_STR1_STRSTDATA1_Pos (0U)
#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
#define DAC_STR1_STDIR1_Pos (12U)
#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
#define DAC_STR1_STINCDATA1_Pos (16U)
#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STR2 register ******************/
#define DAC_STR2_STRSTDATA2_Pos (0U)
#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
#define DAC_STR2_STDIR2_Pos (12U)
#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
#define DAC_STR2_STINCDATA2_Pos (16U)
#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STMODR register ****************/
#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
#define DBGMCU_CR_TRACE_MODE_Pos (6U)
#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U)
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos)/*!< 0x00000008 */
#define DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
/******************** Bit definition for DBGMCU_APB1FZR2 register **********/
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U)
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos (24U)
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
#define DMA_ISR_GIF8_Pos (28U)
#define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos) /*!< 0x10000000 */
#define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk /*!< Channel 8 Global interrupt flag */
#define DMA_ISR_TCIF8_Pos (29U)
#define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos) /*!< 0x20000000 */
#define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk /*!< Channel 8 Transfer Complete flag */
#define DMA_ISR_HTIF8_Pos (30U)
#define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos) /*!< 0x40000000 */
#define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk /*!< Channel 8 Half Transfer flag */
#define DMA_ISR_TEIF8_Pos (31U)
#define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos) /*!< 0x80000000 */
#define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk /*!< Channel 8 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos (24U)
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
#define DMA_IFCR_CGIF8_Pos (28U)
#define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos) /*!< 0x10000000 */
#define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk /*!< Channel 8 Global interrupt clear */
#define DMA_IFCR_CTCIF8_Pos (29U)
#define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos) /*!< 0x20000000 */
#define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk /*!< Channel 8 Transfer Complete clear */
#define DMA_IFCR_CHTIF8_Pos (30U)
#define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos) /*!< 0x40000000 */
#define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk /*!< Channel 8 Half Transfer clear */
#define DMA_IFCR_CTEIF8_Pos (31U)
#define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos) /*!< 0x80000000 */
#define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk /*!< Channel 8 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register ****************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
#define DMAMUX_CSR_SOF12_Pos (12U)
#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
#define DMAMUX_CSR_SOF13_Pos (13U)
#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
#define DMAMUX_CSR_SOF14_Pos (14U)
#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
#define DMAMUX_CSR_SOF15_Pos (15U)
#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
/******************** Bits definition for DMAMUX_CFR register ****************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
#define DMAMUX_CFR_CSOF12_Pos (12U)
#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
#define DMAMUX_CFR_CSOF13_Pos (13U)
#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
#define DMAMUX_CFR_CSOF14_Pos (14U)
#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
#define DMAMUX_CFR_CSOF15_Pos (15U)
#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
/******************** Bits definition for DMAMUX_RGCFR register ************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM31_Pos (31U)
#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
#define EXTI_EMR1_EM31_Pos (31U)
#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
/****************** Bit definition for EXTI_RTSR1 register ******************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT19_Pos (19U)
#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR1_RT22_Pos (22U)
#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR1_RT29_Pos (29U)
#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR1_RT30_Pos (30U)
#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
#define EXTI_RTSR1_RT31_Pos (31U)
#define EXTI_RTSR1_RT31_Msk (0x1UL << EXTI_RTSR1_RT31_Pos) /*!< 0x80000000 */
#define EXTI_RTSR1_RT31 EXTI_RTSR1_RT31_Msk /*!< Rising trigger event configuration bit of line 31 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_FT16_Pos (16U)
#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_FT17_Pos (17U)
#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_FT19_Pos (19U)
#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR1_FT22_Pos (22U)
#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR1_FT29_Pos (29U)
#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR1_FT30_Pos (30U)
#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
#define EXTI_FTSR1_FT31_Pos (31U)
#define EXTI_FTSR1_FT31_Msk (0x1UL << EXTI_FTSR1_FT31_Pos) /*!< 0x80000000 */
#define EXTI_FTSR1_FT31 EXTI_FTSR1_FT31_Msk /*!< Falling trigger event configuration bit of line 31 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos (16U)
#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos (17U)
#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI19_Pos (19U)
#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos (22U)
#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER1_SWI29_Pos (29U)
#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER1_SWI30_Pos (30U)
#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
#define EXTI_SWIER1_SWI31_Pos (31U)
#define EXTI_SWIER1_SWI31_Msk (0x1UL << EXTI_SWIER1_SWI31_Pos) /*!< 0x80000000 */
#define EXTI_SWIER1_SWI31 EXTI_SWIER1_SWI31_Msk /*!< Software Interrupt on line 31 */
/******************* Bit definition for EXTI_PR1 register *******************/
#define EXTI_PR1_PIF0_Pos (0U)
#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PIF1_Pos (1U)
#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PIF2_Pos (2U)
#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PIF3_Pos (3U)
#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PIF4_Pos (4U)
#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PIF5_Pos (5U)
#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PIF6_Pos (6U)
#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PIF7_Pos (7U)
#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PIF8_Pos (8U)
#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PIF9_Pos (9U)
#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PIF10_Pos (10U)
#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PIF11_Pos (11U)
#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PIF12_Pos (12U)
#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PIF13_Pos (13U)
#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PIF14_Pos (14U)
#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PIF15_Pos (15U)
#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PIF16_Pos (16U)
#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PIF17_Pos (17U)
#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR1_PIF19_Pos (19U)
#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PIF20_Pos (20U)
#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PIF21_Pos (21U)
#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR1_PIF22_Pos (22U)
#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR1_PIF29_Pos (29U)
#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR1_PIF30_Pos (30U)
#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
#define EXTI_PR1_PIF31_Pos (31U)
#define EXTI_PR1_PIF31_Msk (0x1UL << EXTI_PR1_PIF31_Pos) /*!< 0x80000000 */
#define EXTI_PR1_PIF31 EXTI_PR1_PIF31_Msk /*!< Pending bit for line 31 */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM32_Pos (0U)
#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM42_Pos (10U)
#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x7FFUL << EXTI_IMR2_IM_Pos) /*!< 0x000007FF */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM32_Pos (0U)
#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32 */
#define EXTI_EMR2_EM33_Pos (1U)
#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33 */
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM35_Pos (3U)
#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM42_Pos (10U)
#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x7FFUL << EXTI_EMR2_EM_Pos) /*!< 0x000007FF */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT32_Pos (0U)
#define EXTI_RTSR2_RT32_Msk (0x1UL << EXTI_RTSR2_RT32_Pos) /*!< 0x00000001 */
#define EXTI_RTSR2_RT32 EXTI_RTSR2_RT32_Msk /*!< Rising trigger event configuration bit of line 32 */
#define EXTI_RTSR2_RT33_Pos (1U)
#define EXTI_RTSR2_RT33_Msk (0x1UL << EXTI_RTSR2_RT33_Pos) /*!< 0x00000002 */
#define EXTI_RTSR2_RT33 EXTI_RTSR2_RT33_Msk /*!< Rising trigger event configuration bit of line 33 */
#define EXTI_RTSR2_RT38_Pos (6U)
#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
#define EXTI_RTSR2_RT39_Pos (7U)
#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
#define EXTI_RTSR2_RT40_Pos (8U)
#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
#define EXTI_RTSR2_RT41_Pos (9U)
#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_FT32_Pos (0U)
#define EXTI_FTSR2_FT32_Msk (0x1UL << EXTI_FTSR2_FT32_Pos) /*!< 0x00000001 */
#define EXTI_FTSR2_FT32 EXTI_FTSR2_FT32_Msk /*!< Falling trigger event configuration bit of line 32 */
#define EXTI_FTSR2_FT33_Pos (1U)
#define EXTI_FTSR2_FT33_Msk (0x1UL << EXTI_FTSR2_FT33_Pos) /*!< 0x00000002 */
#define EXTI_FTSR2_FT33 EXTI_FTSR2_FT33_Msk /*!< Falling trigger event configuration bit of line 33 */
#define EXTI_FTSR2_FT38_Pos (6U)
#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
#define EXTI_FTSR2_FT39_Pos (7U)
#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
#define EXTI_FTSR2_FT40_Pos (8U)
#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
#define EXTI_FTSR2_FT41_Pos (9U)
#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI32_Pos (0U)
#define EXTI_SWIER2_SWI32_Msk (0x1UL << EXTI_SWIER2_SWI32_Pos) /*!< 0x00000001 */
#define EXTI_SWIER2_SWI32 EXTI_SWIER2_SWI32_Msk /*!< Software Interrupt on line 32 */
#define EXTI_SWIER2_SWI33_Pos (1U)
#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
#define EXTI_SWIER2_SWI38_Pos (6U)
#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
#define EXTI_SWIER2_SWI39_Pos (7U)
#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
#define EXTI_SWIER2_SWI40_Pos (8U)
#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
#define EXTI_SWIER2_SWI41_Pos (9U)
#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PIF32_Pos (0U)
#define EXTI_PR2_PIF32_Msk (0x1UL << EXTI_PR2_PIF32_Pos) /*!< 0x00000001 */
#define EXTI_PR2_PIF32 EXTI_PR2_PIF32_Msk /*!< Pending bit for line 32 */
#define EXTI_PR2_PIF33_Pos (1U)
#define EXTI_PR2_PIF33_Msk (0x1UL << EXTI_PR2_PIF33_Pos) /*!< 0x00000002 */
#define EXTI_PR2_PIF33 EXTI_PR2_PIF33_Msk /*!< Pending bit for line 33 */
#define EXTI_PR2_PIF38_Pos (6U)
#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
#define EXTI_PR2_PIF39_Pos (7U)
#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
#define EXTI_PR2_PIF40_Pos (8U)
#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
#define EXTI_PR2_PIF41_Pos (9U)
#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0F_Pos (1U)
#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (2U)
#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (3U)
#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1F_Pos (4U)
#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (5U)
#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (6U)
#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (7U)
#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (8U)
#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (9U)
#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (10U)
#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFF_Pos (11U)
#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (12U)
#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (13U)
#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (14U)
#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (15U)
#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_ELO_Pos (16U)
#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (17U)
#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (18U)
#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (19U)
#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (20U)
#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (21U)
#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (22U)
#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (23U)
#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0FE_Pos (1U)
#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (2U)
#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (3U)
#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1FE_Pos (4U)
#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (5U)
#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (6U)
#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (7U)
#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (8U)
#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos (9U)
#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (10U)
#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFFE_Pos (11U)
#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (12U)
#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (13U)
#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (14U)
#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (15U)
#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_ELOE_Pos (16U)
#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (17U)
#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (18U)
#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (19U)
#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (20U)
#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (21U)
#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos (22U)
#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (23U)
#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RXFIFO0_Pos (0U)
#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
Rx FIFO 0 is Full
Rx FIFO 0 Has New Message */
#define FDCAN_ILS_RXFIFO1_Pos (1U)
#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
Rx FIFO 1 is Full
Rx FIFO 1 Has New Message */
#define FDCAN_ILS_SMSG_Pos (2U)
#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
Transmission Completed
High Priority Message */
#define FDCAN_ILS_TFERR_Pos (3U)
#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
Tx Event FIFO Full
Tx Event FIFO New Entry
Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_MISC_Pos (4U)
#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
Message RAM Access Failure
Timestamp Wraparound */
#define FDCAN_ILS_BERR_Pos (5U)
#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
Error Logging Overflow */
#define FDCAN_ILS_PERR_Pos (6U)
#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
Protocol Error in Data Phase Line
Protocol Error in Arbitration Phase Line
Watchdog Interrupt Line
Bus_Off Status
Warning Status */
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_RXGFC register ********************/
#define FDCAN_RXGFC_RRFE_Pos (0U)
#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_RXGFC_RRFS_Pos (1U)
#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_RXGFC_ANFE_Pos (2U)
#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_RXGFC_ANFS_Pos (4U)
#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
#define FDCAN_RXGFC_F1OM_Pos (8U)
#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
#define FDCAN_RXGFC_F0OM_Pos (9U)
#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
#define FDCAN_RXGFC_LSS_Pos (16U)
#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
#define FDCAN_RXGFC_LSE_Pos (24U)
#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TFQM_Pos (24U)
#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CFIE_Pos (0U)
#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/*!<FDCAN config registers */
/***************** Bit definition for FDCAN_CKDIV register *********************/
#define FDCAN_CKDIV_PDIV_Pos (0U)
#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS (0x00000000U)
#define FLASH_ACR_LATENCY_1WS (0x00000001U)
#define FLASH_ACR_LATENCY_2WS (0x00000002U)
#define FLASH_ACR_LATENCY_3WS (0x00000003U)
#define FLASH_ACR_LATENCY_4WS (0x00000004U)
#define FLASH_ACR_LATENCY_5WS (0x00000005U)
#define FLASH_ACR_LATENCY_6WS (0x00000006U)
#define FLASH_ACR_LATENCY_7WS (0x00000007U)
#define FLASH_ACR_LATENCY_8WS (0x00000008U)
#define FLASH_ACR_LATENCY_9WS (0x00000009U)
#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_RUN_PD_Pos (13U)
#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
#define FLASH_ACR_SLEEP_PD_Pos (14U)
#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
#define FLASH_ACR_DBG_SWEN_Pos (18U)
#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_OPERR_Pos (1U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_PROGERR_Pos (3U)
#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_SIZERR_Pos (6U)
#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_MISERR_Pos (8U)
#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
#define FLASH_SR_FASTERR_Pos (9U)
#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
#define FLASH_SR_RDERR_Pos (14U)
#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_OPTVERR_Pos (15U)
#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PER_Pos (1U)
#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
#define FLASH_CR_PER FLASH_CR_PER_Msk
#define FLASH_CR_MER1_Pos (2U)
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
#define FLASH_CR_PNB_Msk (0x7FUL << FLASH_CR_PNB_Pos) /*!< 0x000003F8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_BKER_Pos (11U)
#define FLASH_CR_BKER_Msk (0x1UL << FLASH_CR_BKER_Pos) /*!< 0x00000800 */
#define FLASH_CR_BKER FLASH_CR_BKER_Msk
#define FLASH_CR_MER2_Pos (15U)
#define FLASH_CR_MER2_Msk (0x1UL << FLASH_CR_MER2_Pos) /*!< 0x00008000 */
#define FLASH_CR_MER2 FLASH_CR_MER2_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_OPTSTRT_Pos (17U)
#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
#define FLASH_CR_FSTPG_Pos (18U)
#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_RDERRIE_Pos (26U)
#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
#define FLASH_CR_SEC_PROT1_Pos (28U)
#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
#define FLASH_CR_SEC_PROT2_Pos (29U)
#define FLASH_CR_SEC_PROT2_Msk (0x1UL << FLASH_CR_SEC_PROT2_Pos) /*!< 0x20000000 */
#define FLASH_CR_SEC_PROT2 FLASH_CR_SEC_PROT2_Msk
#define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_ECCR register ***************/
#define FLASH_ECCR_ADDR_ECC_Pos (0U)
#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
#define FLASH_ECCR_BK_ECC_Pos (21U)
#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
#define FLASH_ECCR_SYSF_ECC_Pos (22U)
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
#define FLASH_ECCR_ECCIE_Pos (24U)
#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
#define FLASH_ECCR_ECCC2_Pos (28U)
#define FLASH_ECCR_ECCC2_Msk (0x1UL << FLASH_ECCR_ECCC2_Pos) /*!< 0x10000000 */
#define FLASH_ECCR_ECCC2 FLASH_ECCR_ECCC2_Msk
#define FLASH_ECCR_ECCD2_Pos (29U)
#define FLASH_ECCR_ECCD2_Msk (0x1UL << FLASH_ECCR_ECCD2_Pos) /*!< 0x20000000 */
#define FLASH_ECCR_ECCD2 FLASH_ECCR_ECCD2_Msk
#define FLASH_ECCR_ECCC_Pos (30U)
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
#define FLASH_ECCR_ECCD_Pos (31U)
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
/******************* Bits definition for FLASH_OPTR register ***************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
#define FLASH_OPTR_BOR_LEV_Pos (8U)
#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
#define FLASH_OPTR_nRST_STOP_Pos (12U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
#define FLASH_OPTR_nRST_STDBY_Pos (13U)
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
#define FLASH_OPTR_WWDG_SW_Pos (19U)
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
#define FLASH_OPTR_BFB2_Pos (20U)
#define FLASH_OPTR_BFB2_Msk (0x1UL << FLASH_OPTR_BFB2_Pos) /*!< 0x00100000 */
#define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk
#define FLASH_OPTR_DBANK_Pos (22U)
#define FLASH_OPTR_DBANK_Msk (0x1UL << FLASH_OPTR_DBANK_Pos) /*!< 0x00400000 */
#define FLASH_OPTR_DBANK FLASH_OPTR_DBANK_Msk
#define FLASH_OPTR_nBOOT1_Pos (23U)
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
#define FLASH_OPTR_SRAM_PE_Pos (24U)
#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
#define FLASH_OPTR_nSWBOOT0_Pos (26U)
#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
#define FLASH_OPTR_nBOOT0_Pos (27U)
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
#define FLASH_OPTR_NRST_MODE_Pos (28U)
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
#define FLASH_OPTR_IRHEN_Pos (30U)
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
/****************** Bits definition for FLASH_PCROP1SR register **********/
#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
/****************** Bits definition for FLASH_PCROP1ER register ***********/
#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
#define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_PCROP2SR register **********/
#define FLASH_PCROP2SR_PCROP2_STRT_Pos (0U)
#define FLASH_PCROP2SR_PCROP2_STRT_Msk (0x07FFFUL << FLASH_PCROP2SR_PCROP2_STRT_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP2SR_PCROP2_STRT FLASH_PCROP2SR_PCROP2_STRT_Msk
/****************** Bits definition for FLASH_PCROP2ER register ***********/
#define FLASH_PCROP2ER_PCROP2_END_Pos (0U)
#define FLASH_PCROP2ER_PCROP2_END_Msk (0x07FFFUL << FLASH_PCROP2ER_PCROP2_END_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP2ER_PCROP2_END FLASH_PCROP2ER_PCROP2_END_Msk
/****************** Bits definition for FLASH_WRP2AR register ***************/
#define FLASH_WRP2AR_WRP2A_STRT_Pos (0U)
#define FLASH_WRP2AR_WRP2A_STRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_STRT_Pos)/*!< 0x000000FF */
#define FLASH_WRP2AR_WRP2A_STRT FLASH_WRP2AR_WRP2A_STRT_Msk
#define FLASH_WRP2AR_WRP2A_END_Pos (16U)
#define FLASH_WRP2AR_WRP2A_END_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_END_Pos)/*!< 0x00FF0000 */
#define FLASH_WRP2AR_WRP2A_END FLASH_WRP2AR_WRP2A_END_Msk
/****************** Bits definition for FLASH_WRP2BR register ***************/
#define FLASH_WRP2BR_WRP2B_STRT_Pos (0U)
#define FLASH_WRP2BR_WRP2B_STRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP2BR_WRP2B_STRT FLASH_WRP2BR_WRP2B_STRT_Msk
#define FLASH_WRP2BR_WRP2B_END_Pos (16U)
#define FLASH_WRP2BR_WRP2B_END_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP2BR_WRP2B_END FLASH_WRP2BR_WRP2B_END_Msk
/****************** Bits definition for FLASH_SEC1R register **************/
#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
#define FLASH_SEC1R_SEC_SIZE1_Msk (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
/****************** Bits definition for FLASH_SEC2R register **************/
#define FLASH_SEC2R_SEC_SIZE2_Pos (0U)
#define FLASH_SEC2R_SEC_SIZE2_Msk (0xFFUL << FLASH_SEC2R_SEC_SIZE2_Pos)/*!< 0x000000FF */
#define FLASH_SEC2R_SEC_SIZE2 FLASH_SEC2R_SEC_SIZE2_Msk
/******************************************************************************/
/* */
/* Filter Mathematical ACcelerator unit (FMAC) */
/* */
/******************************************************************************/
/***************** Bit definition for FMAC_X1BUFCFG register ****************/
#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
/***************** Bit definition for FMAC_X2BUFCFG register ****************/
#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
/***************** Bit definition for FMAC_YBUFCFG register *****************/
#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
/****************** Bit definition for FMAC_PARAM register ******************/
#define FMAC_PARAM_P_Pos (0U)
#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
#define FMAC_PARAM_Q_Pos (8U)
#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
#define FMAC_PARAM_R_Pos (16U)
#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
#define FMAC_PARAM_FUNC_Pos (24U)
#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
#define FMAC_PARAM_START_Pos (31U)
#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
/******************** Bit definition for FMAC_CR register *******************/
#define FMAC_CR_RIEN_Pos (0U)
#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
#define FMAC_CR_WIEN_Pos (1U)
#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
#define FMAC_CR_OVFLIEN_Pos (2U)
#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
#define FMAC_CR_UNFLIEN_Pos (3U)
#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
#define FMAC_CR_SATIEN_Pos (4U)
#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
#define FMAC_CR_DMAREN_Pos (8U)
#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
#define FMAC_CR_DMAWEN_Pos (9U)
#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
#define FMAC_CR_CLIPEN_Pos (15U)
#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
#define FMAC_CR_RESET_Pos (16U)
#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
/******************* Bit definition for FMAC_SR register ********************/
#define FMAC_SR_YEMPTY_Pos (0U)
#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
#define FMAC_SR_X1FULL_Pos (1U)
#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
#define FMAC_SR_OVFL_Pos (8U)
#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
#define FMAC_SR_UNFL_Pos (9U)
#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
#define FMAC_SR_SAT_Pos (10U)
#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
/****************** Bit definition for FMAC_WDATA register ******************/
#define FMAC_WDATA_WDATA_Pos (0U)
#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
/****************** Bit definition for FMACX_RDATA register *****************/
#define FMAC_RDATA_RDATA_Pos (0U)
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
/******************************************************************************/
/* */
/* Flexible Memory Controller */
/* */
/******************************************************************************/
/****************** Bit definition for FMC_BCR1 register *******************/
#define FMC_BCR1_CCLKEN_Pos (20U)
#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
#define FMC_BCR1_WFDIS_Pos (21U)
#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
#define FMC_BCRx_MBKEN_Pos (0U)
#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
#define FMC_BCRx_MUXEN_Pos (1U)
#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
#define FMC_BCRx_MTYP_Pos (2U)
#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
#define FMC_BCRx_MWID_Pos (4U)
#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
#define FMC_BCRx_FACCEN_Pos (6U)
#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
#define FMC_BCRx_BURSTEN_Pos (8U)
#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
#define FMC_BCRx_WAITPOL_Pos (9U)
#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
#define FMC_BCRx_WAITCFG_Pos (11U)
#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
#define FMC_BCRx_WREN_Pos (12U)
#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
#define FMC_BCRx_WAITEN_Pos (13U)
#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
#define FMC_BCRx_EXTMOD_Pos (14U)
#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
#define FMC_BCRx_ASYNCWAIT_Pos (15U)
#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
#define FMC_BCRx_CPSIZE_Pos (16U)
#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<CRAM page size */
#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
#define FMC_BCRx_CBURSTRW_Pos (19U)
#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
#define FMC_BCRx_NBLSET_Pos (22U)
#define FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00C00000 */
#define FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk /*!<Byte lane (NBL) setup */
#define FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00500000 */
#define FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos) /*!< 0x00800000 */
/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
#define FMC_BTRx_ADDSET_Pos (0U)
#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BTRx_ADDHLD_Pos (4U)
#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BTRx_DATAST_Pos (8U)
#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BTRx_BUSTURN_Pos (16U)
#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BTRx_CLKDIV_Pos (20U)
#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
#define FMC_BTRx_DATLAT_Pos (24U)
#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLAT[3:0] bits (Data latency) */
#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
#define FMC_BTRx_ACCMOD_Pos (28U)
#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BTRx_DATAHLD_Pos (30U)
#define FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
#define FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
#define FMC_BWTRx_ADDSET_Pos (0U)
#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
#define FMC_BWTRx_ADDHLD_Pos (4U)
#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
#define FMC_BWTRx_DATAST_Pos (8U)
#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
#define FMC_BWTRx_BUSTURN_Pos (16U)
#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
#define FMC_BWTRx_ACCMOD_Pos (28U)
#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
#define FMC_BWTRx_DATAHLD_Pos (30U)
#define FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0xC0000000 */
#define FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk /*!<DATAHLD[1:0] bits (Data hold phase duration) */
#define FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x40000000 */
#define FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PCSCNTR register ******************/
#define FMC_PCSCNTR_CSCOUNT_Pos (0U)
#define FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos) /*!< 0x0000FFFF */
#define FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk /*!<CSCOUNT[15:0] bits (Chip select counter) */
#define FMC_PCSCNTR_CNTB1EN_Pos (16U)
#define FMC_PCSCNTR_CNTB1EN_Msk (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos) /*!< 0x00010000 */
#define FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk /*!<Counter PSRAM/NOR Bank1_1 enable */
#define FMC_PCSCNTR_CNTB2EN_Pos (17U)
#define FMC_PCSCNTR_CNTB2EN_Msk (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos) /*!< 0x00020000 */
#define FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk /*!<Counter PSRAM/NOR Bank1_2 enable */
#define FMC_PCSCNTR_CNTB3EN_Pos (18U)
#define FMC_PCSCNTR_CNTB3EN_Msk (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos) /*!< 0x00040000 */
#define FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk /*!<Counter PSRAM/NOR Bank1_3 enable */
#define FMC_PCSCNTR_CNTB4EN_Pos (19U)
#define FMC_PCSCNTR_CNTB4EN_Msk (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos) /*!< 0x00080000 */
#define FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk /*!<Counter PSRAM/NOR Bank1_4 enable */
/****************** Bit definition for FMC_PCR register ********************/
#define FMC_PCR_PWAITEN_Pos (1U)
#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
#define FMC_PCR_PBKEN_Pos (2U)
#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
#define FMC_PCR_PTYP_Pos (3U)
#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */
#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */
#define FMC_PCR_PWID_Pos (4U)
#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
#define FMC_PCR_ECCEN_Pos (6U)
#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
#define FMC_PCR_TCLR_Pos (9U)
#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
#define FMC_PCR_TAR_Pos (13U)
#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
#define FMC_PCR_ECCPS_Pos (17U)
#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
/******************* Bit definition for FMC_SR register ********************/
#define FMC_SR_IRS_Pos (0U)
#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
#define FMC_SR_ILS_Pos (1U)
#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
#define FMC_SR_IFS_Pos (2U)
#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
#define FMC_SR_IREN_Pos (3U)
#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
#define FMC_SR_ILEN_Pos (4U)
#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
#define FMC_SR_IFEN_Pos (5U)
#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
#define FMC_SR_FEMPT_Pos (6U)
#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
/****************** Bit definition for FMC_PMEM register ******************/
#define FMC_PMEM_MEMSET_Pos (0U)
#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
#define FMC_PMEM_MEMWAIT_Pos (8U)
#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
#define FMC_PMEM_MEMHOLD_Pos (16U)
#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
#define FMC_PMEM_MEMHIZ_Pos (24U)
#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_PATT register *******************/
#define FMC_PATT_ATTSET_Pos (0U)
#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
#define FMC_PATT_ATTWAIT_Pos (8U)
#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
#define FMC_PATT_ATTHOLD_Pos (16U)
#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
#define FMC_PATT_ATTHIZ_Pos (24U)
#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
/****************** Bit definition for FMC_ECCR register *******************/
#define FMC_ECCR_ECC_Pos (0U)
#define FMC_ECCR_ECC_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC_Pos) /*!< 0xFFFFFFFF */
#define FMC_ECCR_ECC FMC_ECCR_ECC_Msk /*!<ECC result */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/* Legacy defines */
#define GPIO_BRR_BR_0 GPIO_BRR_BR0
#define GPIO_BRR_BR_1 GPIO_BRR_BR1
#define GPIO_BRR_BR_2 GPIO_BRR_BR2
#define GPIO_BRR_BR_3 GPIO_BRR_BR3
#define GPIO_BRR_BR_4 GPIO_BRR_BR4
#define GPIO_BRR_BR_5 GPIO_BRR_BR5
#define GPIO_BRR_BR_6 GPIO_BRR_BR6
#define GPIO_BRR_BR_7 GPIO_BRR_BR7
#define GPIO_BRR_BR_8 GPIO_BRR_BR8
#define GPIO_BRR_BR_9 GPIO_BRR_BR9
#define GPIO_BRR_BR_10 GPIO_BRR_BR10
#define GPIO_BRR_BR_11 GPIO_BRR_BR11
#define GPIO_BRR_BR_12 GPIO_BRR_BR12
#define GPIO_BRR_BR_13 GPIO_BRR_BR13
#define GPIO_BRR_BR_14 GPIO_BRR_BR14
#define GPIO_BRR_BR_15 GPIO_BRR_BR15
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_USERTRIM_Pos (4U)
#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
#define OPAMP_CSR_OPAMPINTEN_Pos (8U)
#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
#define OPAMP_CSR_OUTCAL_Pos (30U)
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
#define OPAMP_CSR_LOCK_Pos (31U)
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
/********************* Bit definition for OPAMPx_TCMR register ***************/
#define OPAMP_TCMR_VMSSEL_Pos (0U)
#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
#define OPAMP_TCMR_VPSSEL_Pos (1U)
#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
#define OPAMP_TCMR_T1CMEN_Pos (3U)
#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
#define OPAMP_TCMR_T8CMEN_Pos (4U)
#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
#define OPAMP_TCMR_T20CMEN_Pos (5U)
#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
#define OPAMP_TCMR_LOCK_Pos (31U)
#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_LPR_Pos (14U)
#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
#define PWR_CR1_VOS_Pos (9U)
#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_LPMS_Pos (0U)
#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
#define PWR_CR1_LPMS_STOP1_Pos (0U)
#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
#define PWR_CR1_LPMS_STANDBY_Pos (0U)
#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
/******************** Bit definition for PWR_CR2 register ********************/
/*!< PVME Peripheral Voltage Monitor Enable */
#define PWR_CR2_PVME_Pos (4U)
#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
#define PWR_CR2_PVME4_Pos (7U)
#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
#define PWR_CR2_PVME3_Pos (6U)
#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
#define PWR_CR2_PVME2_Pos (5U)
#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
#define PWR_CR2_PVME1_Pos (4U)
#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
/*!< PVD level configuration */
#define PWR_CR2_PLS_Pos (1U)
#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
#define PWR_CR2_PLS_LEV1_Pos (1U)
#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR2_PLS_LEV2_Pos (2U)
#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR2_PLS_LEV3_Pos (1U)
#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR2_PLS_LEV4_Pos (3U)
#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR2_PLS_LEV5_Pos (1U)
#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR2_PLS_LEV6_Pos (2U)
#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR2_PLS_LEV7_Pos (1U)
#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
#define PWR_CR2_PVDE_Pos (0U)
#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EIWF_Pos (15U)
#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
#define PWR_CR3_UCPD_DBDIS_Pos (14U)
#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
#define PWR_CR3_UCPD_STDBY_Pos (13U)
#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
#define PWR_CR3_APC_Pos (10U)
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
#define PWR_CR3_RRS_Pos (8U)
#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
#define PWR_CR3_EWUP5_Pos (4U)
#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
#define PWR_CR3_EWUP4_Pos (3U)
#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
#define PWR_CR3_EWUP3_Pos (2U)
#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
#define PWR_CR3_EWUP2_Pos (1U)
#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
#define PWR_CR3_EWUP1_Pos (0U)
#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
#define PWR_CR3_EWUP_Pos (0U)
#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
/******************** Bit definition for PWR_CR4 register ********************/
#define PWR_CR4_VBRS_Pos (9U)
#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
#define PWR_CR4_VBE_Pos (8U)
#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
#define PWR_CR4_WP5_Pos (4U)
#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
#define PWR_CR4_WP4_Pos (3U)
#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
#define PWR_CR4_WP3_Pos (2U)
#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
#define PWR_CR4_WP2_Pos (1U)
#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
#define PWR_CR4_WP1_Pos (0U)
#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
/******************** Bit definition for PWR_SR1 register ********************/
#define PWR_SR1_WUFI_Pos (15U)
#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
#define PWR_SR1_SBF_Pos (8U)
#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
#define PWR_SR1_WUF_Pos (0U)
#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
#define PWR_SR1_WUF5_Pos (4U)
#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
#define PWR_SR1_WUF4_Pos (3U)
#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
#define PWR_SR1_WUF3_Pos (2U)
#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
#define PWR_SR1_WUF2_Pos (1U)
#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
#define PWR_SR1_WUF1_Pos (0U)
#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
/******************** Bit definition for PWR_SR2 register ********************/
#define PWR_SR2_PVMO4_Pos (15U)
#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
#define PWR_SR2_PVMO3_Pos (14U)
#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
#define PWR_SR2_PVMO2_Pos (13U)
#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
#define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
#define PWR_SR2_VOSF_Pos (10U)
#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
#define PWR_SR2_REGLPF_Pos (9U)
#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
#define PWR_SR2_REGLPS_Pos (8U)
#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CSBF_Pos (8U)
#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
#define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
#define PWR_SCR_CWUF5_Pos (4U)
#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
#define PWR_SCR_CWUF4_Pos (3U)
#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
#define PWR_SCR_CWUF3_Pos (2U)
#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
#define PWR_SCR_CWUF2_Pos (1U)
#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
#define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
/******************** Bit definition for PWR_PUCRA register ********************/
#define PWR_PUCRA_PA15_Pos (15U)
#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
#define PWR_PUCRA_PA13_Pos (13U)
#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
#define PWR_PUCRA_PA12_Pos (12U)
#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
#define PWR_PUCRA_PA11_Pos (11U)
#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
#define PWR_PUCRA_PA10_Pos (10U)
#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
#define PWR_PUCRA_PA9_Pos (9U)
#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
#define PWR_PUCRA_PA8_Pos (8U)
#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
#define PWR_PUCRA_PA7_Pos (7U)
#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
#define PWR_PUCRA_PA6_Pos (6U)
#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
#define PWR_PUCRA_PA5_Pos (5U)
#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
#define PWR_PUCRA_PA4_Pos (4U)
#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
#define PWR_PUCRA_PA3_Pos (3U)
#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
#define PWR_PUCRA_PA2_Pos (2U)
#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
#define PWR_PUCRA_PA1_Pos (1U)
#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
#define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
/******************** Bit definition for PWR_PDCRA register ********************/
#define PWR_PDCRA_PA14_Pos (14U)
#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
#define PWR_PDCRA_PA12_Pos (12U)
#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
#define PWR_PDCRA_PA11_Pos (11U)
#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
#define PWR_PDCRA_PA10_Pos (10U)
#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
#define PWR_PDCRA_PA9_Pos (9U)
#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
#define PWR_PDCRA_PA8_Pos (8U)
#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
#define PWR_PDCRA_PA7_Pos (7U)
#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
#define PWR_PDCRA_PA6_Pos (6U)
#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
#define PWR_PDCRA_PA5_Pos (5U)
#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
#define PWR_PDCRA_PA4_Pos (4U)
#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
#define PWR_PDCRA_PA3_Pos (3U)
#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
#define PWR_PDCRA_PA2_Pos (2U)
#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
#define PWR_PDCRA_PA1_Pos (1U)
#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
#define PWR_PDCRA_PA0_Pos (0U)
#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
/******************** Bit definition for PWR_PUCRB register ********************/
#define PWR_PUCRB_PB15_Pos (15U)
#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
#define PWR_PUCRB_PB14_Pos (14U)
#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
#define PWR_PUCRB_PB13_Pos (13U)
#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
#define PWR_PUCRB_PB12_Pos (12U)
#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
#define PWR_PUCRB_PB11_Pos (11U)
#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
#define PWR_PUCRB_PB10_Pos (10U)
#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
#define PWR_PUCRB_PB9_Pos (9U)
#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
#define PWR_PUCRB_PB8_Pos (8U)
#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
#define PWR_PUCRB_PB7_Pos (7U)
#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
#define PWR_PUCRB_PB6_Pos (6U)
#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
#define PWR_PUCRB_PB5_Pos (5U)
#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
#define PWR_PUCRB_PB4_Pos (4U)
#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
#define PWR_PUCRB_PB3_Pos (3U)
#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
#define PWR_PUCRB_PB2_Pos (2U)
#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
#define PWR_PUCRB_PB1_Pos (1U)
#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
#define PWR_PUCRB_PB0_Pos (0U)
#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
/******************** Bit definition for PWR_PDCRB register ********************/
#define PWR_PDCRB_PB15_Pos (15U)
#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
#define PWR_PDCRB_PB14_Pos (14U)
#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
#define PWR_PDCRB_PB13_Pos (13U)
#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
#define PWR_PDCRB_PB12_Pos (12U)
#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
#define PWR_PDCRB_PB11_Pos (11U)
#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
#define PWR_PDCRB_PB10_Pos (10U)
#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
#define PWR_PDCRB_PB9_Pos (9U)
#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
#define PWR_PDCRB_PB8_Pos (8U)
#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
#define PWR_PDCRB_PB7_Pos (7U)
#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
#define PWR_PDCRB_PB6_Pos (6U)
#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
#define PWR_PDCRB_PB5_Pos (5U)
#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
#define PWR_PDCRB_PB3_Pos (3U)
#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
#define PWR_PDCRB_PB2_Pos (2U)
#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
#define PWR_PDCRB_PB1_Pos (1U)
#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
#define PWR_PDCRB_PB0_Pos (0U)
#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
/******************** Bit definition for PWR_PUCRC register ********************/
#define PWR_PUCRC_PC15_Pos (15U)
#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
#define PWR_PUCRC_PC14_Pos (14U)
#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
#define PWR_PUCRC_PC13_Pos (13U)
#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
#define PWR_PUCRC_PC12_Pos (12U)
#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
#define PWR_PUCRC_PC11_Pos (11U)
#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
#define PWR_PUCRC_PC10_Pos (10U)
#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
#define PWR_PUCRC_PC9_Pos (9U)
#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
#define PWR_PUCRC_PC8_Pos (8U)
#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
#define PWR_PUCRC_PC7_Pos (7U)
#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
#define PWR_PUCRC_PC6_Pos (6U)
#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
#define PWR_PUCRC_PC5_Pos (5U)
#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
#define PWR_PUCRC_PC4_Pos (4U)
#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
#define PWR_PUCRC_PC3_Pos (3U)
#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
#define PWR_PUCRC_PC2_Pos (2U)
#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
#define PWR_PUCRC_PC1_Pos (1U)
#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
#define PWR_PUCRC_PC0_Pos (0U)
#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
/******************** Bit definition for PWR_PDCRC register ********************/
#define PWR_PDCRC_PC15_Pos (15U)
#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
#define PWR_PDCRC_PC14_Pos (14U)
#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
#define PWR_PDCRC_PC13_Pos (13U)
#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
#define PWR_PDCRC_PC12_Pos (12U)
#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
#define PWR_PDCRC_PC11_Pos (11U)
#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
#define PWR_PDCRC_PC10_Pos (10U)
#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
#define PWR_PDCRC_PC9_Pos (9U)
#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
#define PWR_PDCRC_PC8_Pos (8U)
#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
#define PWR_PDCRC_PC7_Pos (7U)
#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
#define PWR_PDCRC_PC6_Pos (6U)
#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
#define PWR_PDCRC_PC5_Pos (5U)
#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
#define PWR_PDCRC_PC4_Pos (4U)
#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
#define PWR_PDCRC_PC3_Pos (3U)
#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
#define PWR_PDCRC_PC2_Pos (2U)
#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
#define PWR_PDCRC_PC1_Pos (1U)
#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
#define PWR_PDCRC_PC0_Pos (0U)
#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
/******************** Bit definition for PWR_PUCRD register ********************/
#define PWR_PUCRD_PD15_Pos (15U)
#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
#define PWR_PUCRD_PD14_Pos (14U)
#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
#define PWR_PUCRD_PD13_Pos (13U)
#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
#define PWR_PUCRD_PD12_Pos (12U)
#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
#define PWR_PUCRD_PD11_Pos (11U)
#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
#define PWR_PUCRD_PD10_Pos (10U)
#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
#define PWR_PUCRD_PD9_Pos (9U)
#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
#define PWR_PUCRD_PD8_Pos (8U)
#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
#define PWR_PUCRD_PD7_Pos (7U)
#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
#define PWR_PUCRD_PD6_Pos (6U)
#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
#define PWR_PUCRD_PD5_Pos (5U)
#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
#define PWR_PUCRD_PD4_Pos (4U)
#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
#define PWR_PUCRD_PD3_Pos (3U)
#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
#define PWR_PUCRD_PD2_Pos (2U)
#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
#define PWR_PUCRD_PD1_Pos (1U)
#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
#define PWR_PUCRD_PD0_Pos (0U)
#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register ********************/
#define PWR_PDCRD_PD15_Pos (15U)
#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
#define PWR_PDCRD_PD14_Pos (14U)
#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
#define PWR_PDCRD_PD13_Pos (13U)
#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
#define PWR_PDCRD_PD12_Pos (12U)
#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
#define PWR_PDCRD_PD11_Pos (11U)
#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
#define PWR_PDCRD_PD10_Pos (10U)
#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
#define PWR_PDCRD_PD9_Pos (9U)
#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
#define PWR_PDCRD_PD8_Pos (8U)
#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
#define PWR_PDCRD_PD7_Pos (7U)
#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
#define PWR_PDCRD_PD6_Pos (6U)
#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
#define PWR_PDCRD_PD5_Pos (5U)
#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
#define PWR_PDCRD_PD4_Pos (4U)
#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
#define PWR_PDCRD_PD3_Pos (3U)
#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
#define PWR_PDCRD_PD2_Pos (2U)
#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
#define PWR_PDCRD_PD1_Pos (1U)
#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
/******************** Bit definition for PWR_PUCRE register ********************/
#define PWR_PUCRE_PE15_Pos (15U)
#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
#define PWR_PUCRE_PE14_Pos (14U)
#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
#define PWR_PUCRE_PE13_Pos (13U)
#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
#define PWR_PUCRE_PE12_Pos (12U)
#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
#define PWR_PUCRE_PE11_Pos (11U)
#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
#define PWR_PUCRE_PE10_Pos (10U)
#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
#define PWR_PUCRE_PE9_Pos (9U)
#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
#define PWR_PUCRE_PE8_Pos (8U)
#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
#define PWR_PUCRE_PE7_Pos (7U)
#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
#define PWR_PUCRE_PE6_Pos (6U)
#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
#define PWR_PUCRE_PE5_Pos (5U)
#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
#define PWR_PUCRE_PE4_Pos (4U)
#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
#define PWR_PUCRE_PE3_Pos (3U)
#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
#define PWR_PUCRE_PE2_Pos (2U)
#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
#define PWR_PUCRE_PE1_Pos (1U)
#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
#define PWR_PUCRE_PE0_Pos (0U)
#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
/******************** Bit definition for PWR_PDCRE register ********************/
#define PWR_PDCRE_PE15_Pos (15U)
#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
#define PWR_PDCRE_PE14_Pos (14U)
#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
#define PWR_PDCRE_PE13_Pos (13U)
#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
#define PWR_PDCRE_PE12_Pos (12U)
#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
#define PWR_PDCRE_PE11_Pos (11U)
#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
#define PWR_PDCRE_PE10_Pos (10U)
#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
#define PWR_PDCRE_PE9_Pos (9U)
#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
#define PWR_PDCRE_PE8_Pos (8U)
#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
#define PWR_PDCRE_PE7_Pos (7U)
#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
#define PWR_PDCRE_PE6_Pos (6U)
#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
#define PWR_PDCRE_PE5_Pos (5U)
#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
#define PWR_PDCRE_PE4_Pos (4U)
#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
#define PWR_PDCRE_PE3_Pos (3U)
#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
#define PWR_PDCRE_PE2_Pos (2U)
#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
#define PWR_PDCRE_PE1_Pos (1U)
#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
#define PWR_PDCRE_PE0_Pos (0U)
#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
/******************** Bit definition for PWR_PUCRF register ********************/
#define PWR_PUCRF_PF15_Pos (15U)
#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
#define PWR_PUCRF_PF14_Pos (14U)
#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
#define PWR_PUCRF_PF13_Pos (13U)
#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
#define PWR_PUCRF_PF12_Pos (12U)
#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
#define PWR_PUCRF_PF11_Pos (11U)
#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
#define PWR_PUCRF_PF10_Pos (10U)
#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
#define PWR_PUCRF_PF9_Pos (9U)
#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
#define PWR_PUCRF_PF8_Pos (8U)
#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
#define PWR_PUCRF_PF7_Pos (7U)
#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
#define PWR_PUCRF_PF6_Pos (6U)
#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
#define PWR_PUCRF_PF5_Pos (5U)
#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
#define PWR_PUCRF_PF4_Pos (4U)
#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
#define PWR_PUCRF_PF3_Pos (3U)
#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
#define PWR_PUCRF_PF2_Pos (2U)
#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
#define PWR_PUCRF_PF1_Pos (1U)
#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
#define PWR_PUCRF_PF0_Pos (0U)
#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
/******************** Bit definition for PWR_PDCRF register ********************/
#define PWR_PDCRF_PF15_Pos (15U)
#define PWR_PDCRF_PF15_Msk (0x1UL << PWR_PDCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PDCRF_PF15 PWR_PDCRF_PF15_Msk /*!< Port PF15 Pull-Down set */
#define PWR_PDCRF_PF14_Pos (14U)
#define PWR_PDCRF_PF14_Msk (0x1UL << PWR_PDCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PDCRF_PF14 PWR_PDCRF_PF14_Msk /*!< Port PF14 Pull-Down set */
#define PWR_PDCRF_PF13_Pos (13U)
#define PWR_PDCRF_PF13_Msk (0x1UL << PWR_PDCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PDCRF_PF13 PWR_PDCRF_PF13_Msk /*!< Port PF13 Pull-Down set */
#define PWR_PDCRF_PF12_Pos (12U)
#define PWR_PDCRF_PF12_Msk (0x1UL << PWR_PDCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PDCRF_PF12 PWR_PDCRF_PF12_Msk /*!< Port PF12 Pull-Down set */
#define PWR_PDCRF_PF11_Pos (11U)
#define PWR_PDCRF_PF11_Msk (0x1UL << PWR_PDCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PDCRF_PF11 PWR_PDCRF_PF11_Msk /*!< Port PF11 Pull-Down set */
#define PWR_PDCRF_PF10_Pos (10U)
#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
#define PWR_PDCRF_PF9_Pos (9U)
#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
#define PWR_PDCRF_PF8_Pos (8U)
#define PWR_PDCRF_PF8_Msk (0x1UL << PWR_PDCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PDCRF_PF8 PWR_PDCRF_PF8_Msk /*!< Port PF8 Pull-Down set */
#define PWR_PDCRF_PF7_Pos (7U)
#define PWR_PDCRF_PF7_Msk (0x1UL << PWR_PDCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PDCRF_PF7 PWR_PDCRF_PF7_Msk /*!< Port PF7 Pull-Down set */
#define PWR_PDCRF_PF6_Pos (6U)
#define PWR_PDCRF_PF6_Msk (0x1UL << PWR_PDCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PDCRF_PF6 PWR_PDCRF_PF6_Msk /*!< Port PF6 Pull-Down set */
#define PWR_PDCRF_PF5_Pos (5U)
#define PWR_PDCRF_PF5_Msk (0x1UL << PWR_PDCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PDCRF_PF5 PWR_PDCRF_PF5_Msk /*!< Port PF5 Pull-Down set */
#define PWR_PDCRF_PF4_Pos (4U)
#define PWR_PDCRF_PF4_Msk (0x1UL << PWR_PDCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PDCRF_PF4 PWR_PDCRF_PF4_Msk /*!< Port PF4 Pull-Down set */
#define PWR_PDCRF_PF3_Pos (3U)
#define PWR_PDCRF_PF3_Msk (0x1UL << PWR_PDCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PDCRF_PF3 PWR_PDCRF_PF3_Msk /*!< Port PF3 Pull-Down set */
#define PWR_PDCRF_PF2_Pos (2U)
#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
#define PWR_PDCRF_PF1_Pos (1U)
#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
#define PWR_PDCRF_PF0_Pos (0U)
#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
/******************** Bit definition for PWR_PUCRG register ********************/
#define PWR_PUCRG_PG15_Pos (15U)
#define PWR_PUCRG_PG15_Msk (0x1UL << PWR_PUCRG_PG15_Pos) /*!< 0x00008000 */
#define PWR_PUCRG_PG15 PWR_PUCRG_PG15_Msk /*!< Port PG15 Pull-Up set */
#define PWR_PUCRG_PG14_Pos (14U)
#define PWR_PUCRG_PG14_Msk (0x1UL << PWR_PUCRG_PG14_Pos) /*!< 0x00004000 */
#define PWR_PUCRG_PG14 PWR_PUCRG_PG14_Msk /*!< Port PG14 Pull-Up set */
#define PWR_PUCRG_PG13_Pos (13U)
#define PWR_PUCRG_PG13_Msk (0x1UL << PWR_PUCRG_PG13_Pos) /*!< 0x00002000 */
#define PWR_PUCRG_PG13 PWR_PUCRG_PG13_Msk /*!< Port PG13 Pull-Up set */
#define PWR_PUCRG_PG12_Pos (12U)
#define PWR_PUCRG_PG12_Msk (0x1UL << PWR_PUCRG_PG12_Pos) /*!< 0x00001000 */
#define PWR_PUCRG_PG12 PWR_PUCRG_PG12_Msk /*!< Port PG12 Pull-Up set */
#define PWR_PUCRG_PG11_Pos (11U)
#define PWR_PUCRG_PG11_Msk (0x1UL << PWR_PUCRG_PG11_Pos) /*!< 0x00000800 */
#define PWR_PUCRG_PG11 PWR_PUCRG_PG11_Msk /*!< Port PG11 Pull-Up set */
#define PWR_PUCRG_PG10_Pos (10U)
#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
#define PWR_PUCRG_PG9_Pos (9U)
#define PWR_PUCRG_PG9_Msk (0x1UL << PWR_PUCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PUCRG_PG9 PWR_PUCRG_PG9_Msk /*!< Port PG9 Pull-Up set */
#define PWR_PUCRG_PG8_Pos (8U)
#define PWR_PUCRG_PG8_Msk (0x1UL << PWR_PUCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PUCRG_PG8 PWR_PUCRG_PG8_Msk /*!< Port PG8 Pull-Up set */
#define PWR_PUCRG_PG7_Pos (7U)
#define PWR_PUCRG_PG7_Msk (0x1UL << PWR_PUCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PUCRG_PG7 PWR_PUCRG_PG7_Msk /*!< Port PG7 Pull-Up set */
#define PWR_PUCRG_PG6_Pos (6U)
#define PWR_PUCRG_PG6_Msk (0x1UL << PWR_PUCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PUCRG_PG6 PWR_PUCRG_PG6_Msk /*!< Port PG6 Pull-Up set */
#define PWR_PUCRG_PG5_Pos (5U)
#define PWR_PUCRG_PG5_Msk (0x1UL << PWR_PUCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PUCRG_PG5 PWR_PUCRG_PG5_Msk /*!< Port PG5 Pull-Up set */
#define PWR_PUCRG_PG4_Pos (4U)
#define PWR_PUCRG_PG4_Msk (0x1UL << PWR_PUCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PUCRG_PG4 PWR_PUCRG_PG4_Msk /*!< Port PG4 Pull-Up set */
#define PWR_PUCRG_PG3_Pos (3U)
#define PWR_PUCRG_PG3_Msk (0x1UL << PWR_PUCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PUCRG_PG3 PWR_PUCRG_PG3_Msk /*!< Port PG3 Pull-Up set */
#define PWR_PUCRG_PG2_Pos (2U)
#define PWR_PUCRG_PG2_Msk (0x1UL << PWR_PUCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PUCRG_PG2 PWR_PUCRG_PG2_Msk /*!< Port PG2 Pull-Up set */
#define PWR_PUCRG_PG1_Pos (1U)
#define PWR_PUCRG_PG1_Msk (0x1UL << PWR_PUCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PUCRG_PG1 PWR_PUCRG_PG1_Msk /*!< Port PG1 Pull-Up set */
#define PWR_PUCRG_PG0_Pos (0U)
#define PWR_PUCRG_PG0_Msk (0x1UL << PWR_PUCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PUCRG_PG0 PWR_PUCRG_PG0_Msk /*!< Port PG0 Pull-Up set */
/******************** Bit definition for PWR_PDCRG register ********************/
#define PWR_PDCRG_PG10_Pos (10U)
#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
#define PWR_PDCRG_PG9_Pos (9U)
#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
#define PWR_PDCRG_PG8_Pos (8U)
#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
#define PWR_PDCRG_PG7_Pos (7U)
#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
#define PWR_PDCRG_PG6_Pos (6U)
#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
#define PWR_PDCRG_PG5_Pos (5U)
#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
#define PWR_PDCRG_PG4_Pos (4U)
#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
#define PWR_PDCRG_PG3_Pos (3U)
#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
#define PWR_PDCRG_PG2_Pos (2U)
#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
#define PWR_PDCRG_PG1_Pos (1U)
#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
#define PWR_PDCRG_PG0_Pos (0U)
#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
/******************** Bit definition for PWR_CR5 register ********************/
#define PWR_CR5_R1MODE_Pos (8U)
#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
/******************************************************************************/
/* */
/* QUADSPI */
/* */
/******************************************************************************/
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
#define QUADSPI_CR_ABORT_Pos (1U)
#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
#define QUADSPI_CR_SSHIFT_Pos (4U)
#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
#define QUADSPI_CR_DFM_Pos (6U)
#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
#define QUADSPI_CR_FSEL_Pos (7U)
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
#define QUADSPI_CR_FTHRES_Pos (8U)
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
#define QUADSPI_CR_TEIE_Pos (16U)
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define QUADSPI_CR_TCIE_Pos (17U)
#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define QUADSPI_CR_FTIE_Pos (18U)
#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
#define QUADSPI_CR_SMIE_Pos (19U)
#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
#define QUADSPI_CR_TOIE_Pos (20U)
#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
#define QUADSPI_CR_APMS_Pos (22U)
#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
#define QUADSPI_CR_PMM_Pos (23U)
#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
#define QUADSPI_CR_PRESCALER_Pos (24U)
#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
/***************** Bit definition for QUADSPI_DCR register ******************/
#define QUADSPI_DCR_CKMODE_Pos (0U)
#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
#define QUADSPI_DCR_CSHT_Pos (8U)
#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_FSIZE_Pos (16U)
#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
/****************** Bit definition for QUADSPI_SR register *******************/
#define QUADSPI_SR_TEF_Pos (0U)
#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
#define QUADSPI_SR_TCF_Pos (1U)
#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
#define QUADSPI_SR_FTF_Pos (2U)
#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_SMF_Pos (3U)
#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
#define QUADSPI_SR_TOF_Pos (4U)
#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
#define QUADSPI_SR_BUSY_Pos (5U)
#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
#define QUADSPI_SR_FLEVEL_Pos (8U)
#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
/****************** Bit definition for QUADSPI_FCR register ******************/
#define QUADSPI_FCR_CTEF_Pos (0U)
#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
#define QUADSPI_FCR_CTCF_Pos (1U)
#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
#define QUADSPI_FCR_CSMF_Pos (3U)
#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
#define QUADSPI_FCR_CTOF_Pos (4U)
#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
/****************** Bit definition for QUADSPI_DLR register ******************/
#define QUADSPI_DLR_DL_Pos (0U)
#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
/****************** Bit definition for QUADSPI_CCR register ******************/
#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_IMODE_Pos (8U)
#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_ADMODE_Pos (10U)
#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADSIZE_Pos (12U)
#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ABMODE_Pos (14U)
#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABSIZE_Pos (16U)
#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_DCYC_Pos (18U)
#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DMODE_Pos (24U)
#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_FMODE_Pos (26U)
#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_SIOO_Pos (28U)
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_DHHC_Pos (30U)
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
#define QUADSPI_CCR_DDRM_Pos (31U)
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
/****************** Bit definition for QUADSPI_AR register *******************/
#define QUADSPI_AR_ADDRESS_Pos (0U)
#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
/****************** Bit definition for QUADSPI_ABR register ******************/
#define QUADSPI_ABR_ALTERNATE_Pos (0U)
#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
/****************** Bit definition for QUADSPI_DR register *******************/
#define QUADSPI_DR_DATA_Pos (0U)
#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
/****************** Bit definition for QUADSPI_PSMKR register ****************/
#define QUADSPI_PSMKR_MASK_Pos (0U)
#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
/****************** Bit definition for QUADSPI_PSMAR register ****************/
#define QUADSPI_PSMAR_MATCH_Pos (0U)
#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
/****************** Bit definition for QUADSPI_PIR register *****************/
#define QUADSPI_PIR_INTERVAL_Pos (0U)
#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
/****************** Bit definition for QUADSPI_LPTR register *****************/
#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (8U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
#define RCC_CR_HSIKERON_Pos (9U)
#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
#define RCC_CR_HSIRDY_Pos (10U)
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
#define RCC_CR_HSEON_Pos (16U)
#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
#define RCC_CR_PLLON_Pos (24U)
#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (16U)
#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
/*!< MCOSEL configuration */
#define RCC_CFGR_MCOSEL_Pos (24U)
#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
#define RCC_CFGR_MCOPRE_Pos (28U)
#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
/* Legacy aliases */
#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLSRC_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
#define RCC_PLLCFGR_PLLM_Pos (4U)
#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
#define RCC_PLLCFGR_PLLN_Pos (8U)
#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
#define RCC_PLLCFGR_PLLPEN_Pos (16U)
#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
#define RCC_PLLCFGR_PLLP_Pos (17U)
#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
#define RCC_PLLCFGR_PLLQEN_Pos (20U)
#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
#define RCC_PLLCFGR_PLLQ_Pos (21U)
#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
#define RCC_PLLCFGR_PLLREN_Pos (24U)
#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
#define RCC_PLLCFGR_PLLR_Pos (25U)
#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos (3U)
#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos (4U)
#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_PLLRDYIE_Pos (5U)
#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos (9U)
#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos (10U)
#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
/******************** Bit definition for RCC_CIFR register ******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos (3U)
#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos (4U)
#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_PLLRDYF_Pos (5U)
#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
#define RCC_CIFR_CSSF_Pos (8U)
#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
#define RCC_CIFR_LSECSSF_Pos (9U)
#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSI48RDYF_Pos (10U)
#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
/******************** Bit definition for RCC_CICR register ******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos (3U)
#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos (4U)
#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
#define RCC_CICR_PLLRDYC_Pos (5U)
#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
#define RCC_CICR_CSSC_Pos (8U)
#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
#define RCC_CICR_LSECSSC_Pos (9U)
#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSI48RDYC_Pos (10U)
#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
#define RCC_AHB1RSTR_CORDICRST_Pos (3U)
#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
#define RCC_AHB1RSTR_FMACRST_Pos (4U)
#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
#define RCC_AHB1RSTR_CRCRST_Pos (12U)
#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
#define RCC_AHB2RSTR_ADC12RST_Pos (13U)
#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
#define RCC_AHB2RSTR_ADC345RST_Pos (14U)
#define RCC_AHB2RSTR_ADC345RST_Msk (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
#define RCC_AHB2RSTR_ADC345RST RCC_AHB2RSTR_ADC345RST_Msk
#define RCC_AHB2RSTR_DAC1RST_Pos (16U)
#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
#define RCC_AHB2RSTR_DAC2RST_Pos (17U)
#define RCC_AHB2RSTR_DAC2RST_Msk (0x1UL << RCC_AHB2RSTR_DAC2RST_Pos)/*!< 0x00020000 */
#define RCC_AHB2RSTR_DAC2RST RCC_AHB2RSTR_DAC2RST_Msk
#define RCC_AHB2RSTR_DAC3RST_Pos (18U)
#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
#define RCC_AHB2RSTR_DAC4RST_Pos (19U)
#define RCC_AHB2RSTR_DAC4RST_Msk (0x1UL << RCC_AHB2RSTR_DAC4RST_Pos)/*!< 0x00080000 */
#define RCC_AHB2RSTR_DAC4RST RCC_AHB2RSTR_DAC4RST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (26U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
/******************** Bit definition for RCC_AHB3RSTR register **************/
#define RCC_AHB3RSTR_FMCRST_Pos (0U)
#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)/*!< 0x00000001 */
#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
/******************** Bit definition for RCC_APB1RSTR1 register **************/
#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM5RST_Pos (3U)
#define RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos)/*!< 0x00000008 */
#define RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
#define RCC_APB1RSTR1_CRSRST_Pos (8U)
#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
#define RCC_APB1RSTR1_USART2RST_Pos (17U)
#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
#define RCC_APB1RSTR1_USART3RST_Pos (18U)
#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
#define RCC_APB1RSTR1_UART4RST_Pos (19U)
#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
#define RCC_APB1RSTR1_UART5RST_Pos (20U)
#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
#define RCC_APB1RSTR1_USBRST_Pos (23U)
#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
#define RCC_APB1RSTR1_FDCANRST_Pos (25U)
#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
#define RCC_APB1RSTR1_PWRRST_Pos (28U)
#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
#define RCC_APB1RSTR1_I2C3RST_Pos (30U)
#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
#define RCC_APB1RSTR2_I2C4RST_Pos (1U)
#define RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk
#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
#define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_TIM8RST_Pos (13U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_SPI4RST_Pos (15U)
#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)/*!< 0x00008000 */
#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_TIM20RST_Pos (20U)
#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define RCC_AHB1ENR_DMA2EN_Pos (1U)
#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
#define RCC_AHB1ENR_CORDICEN_Pos (3U)
#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
#define RCC_AHB1ENR_FMACEN_Pos (4U)
#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
#define RCC_AHB1ENR_FLASHEN_Pos (8U)
#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
#define RCC_AHB1ENR_CRCEN_Pos (12U)
#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
#define RCC_AHB2ENR_GPIODEN_Pos (3U)
#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
#define RCC_AHB2ENR_ADC12EN_Pos (13U)
#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
#define RCC_AHB2ENR_ADC345EN_Pos (14U)
#define RCC_AHB2ENR_ADC345EN_Msk (0x1UL << RCC_AHB2ENR_ADC345EN_Pos) /*!< 0x00004000 */
#define RCC_AHB2ENR_ADC345EN RCC_AHB2ENR_ADC345EN_Msk
#define RCC_AHB2ENR_DAC1EN_Pos (16U)
#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
#define RCC_AHB2ENR_DAC2EN_Pos (17U)
#define RCC_AHB2ENR_DAC2EN_Msk (0x1UL << RCC_AHB2ENR_DAC2EN_Pos) /*!< 0x00020000 */
#define RCC_AHB2ENR_DAC2EN RCC_AHB2ENR_DAC2EN_Msk
#define RCC_AHB2ENR_DAC3EN_Pos (18U)
#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
#define RCC_AHB2ENR_DAC4EN_Pos (19U)
#define RCC_AHB2ENR_DAC4EN_Msk (0x1UL << RCC_AHB2ENR_DAC4EN_Pos) /*!< 0x00080000 */
#define RCC_AHB2ENR_DAC4EN RCC_AHB2ENR_DAC4EN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (26U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
/******************** Bit definition for RCC_AHB3ENR register ***************/
#define RCC_AHB3ENR_FMCEN_Pos (0U)
#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */
#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
#define RCC_AHB3ENR_QSPIEN_Pos (8U)
#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
/******************** Bit definition for RCC_APB1ENR1 register ***************/
#define RCC_APB1ENR1_TIM2EN_Pos (0U)
#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
#define RCC_APB1ENR1_TIM3EN_Pos (1U)
#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM5EN_Pos (3U)
#define RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos)/*!< 0x00000008 */
#define RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
#define RCC_APB1ENR1_TIM7EN_Pos (5U)
#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
#define RCC_APB1ENR1_CRSEN_Pos (8U)
#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
#define RCC_APB1ENR1_WWDGEN_Pos (11U)
#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
#define RCC_APB1ENR1_SPI2EN_Pos (14U)
#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
#define RCC_APB1ENR1_SPI3EN_Pos (15U)
#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
#define RCC_APB1ENR1_USART2EN_Pos (17U)
#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
#define RCC_APB1ENR1_USART3EN_Pos (18U)
#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
#define RCC_APB1ENR1_UART4EN_Pos (19U)
#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
#define RCC_APB1ENR1_UART5EN_Pos (20U)
#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
#define RCC_APB1ENR1_I2C1EN_Pos (21U)
#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
#define RCC_APB1ENR1_I2C2EN_Pos (22U)
#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
#define RCC_APB1ENR1_USBEN_Pos (23U)
#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
#define RCC_APB1ENR1_FDCANEN_Pos (25U)
#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
#define RCC_APB1ENR1_PWREN_Pos (28U)
#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
#define RCC_APB1ENR1_I2C3EN_Pos (30U)
#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
#define RCC_APB1ENR2_I2C4EN_Pos (1U)
#define RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk
#define RCC_APB1ENR2_UCPD1EN_Pos (8U)
#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
#define RCC_APB2ENR_TIM1EN_Pos (11U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_TIM8EN_Pos (13U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define RCC_APB2ENR_USART1EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_SPI4EN_Pos (15U)
#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00008000 */
#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_TIM20EN_Pos (20U)
#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
/******************** Bit definition for RCC_AHB2SMENR register *************/
#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
#define RCC_AHB2SMENR_ADC345SMEN_Pos (14U)
#define RCC_AHB2SMENR_ADC345SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
#define RCC_AHB2SMENR_ADC345SMEN RCC_AHB2SMENR_ADC345SMEN_Msk
#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
#define RCC_AHB2SMENR_DAC2SMEN_Pos (17U)
#define RCC_AHB2SMENR_DAC2SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC2SMEN_Pos)/*!< 0x00020000 */
#define RCC_AHB2SMENR_DAC2SMEN RCC_AHB2SMENR_DAC2SMEN_Msk
#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
#define RCC_AHB2SMENR_DAC4SMEN_Pos (19U)
#define RCC_AHB2SMENR_DAC4SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC4SMEN_Pos)/*!< 0x00080000 */
#define RCC_AHB2SMENR_DAC4SMEN RCC_AHB2SMENR_DAC4SMEN_Msk
#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register *************/
#define RCC_AHB3SMENR_FMCSMEN_Pos (0U)
#define RCC_AHB3SMENR_FMCSMEN_Msk (0x1UL << RCC_AHB3SMENR_FMCSMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB3SMENR_FMCSMEN RCC_AHB3SMENR_FMCSMEN_Msk
#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
/******************** Bit definition for RCC_APB1SMENR1 register *************/
#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
#define RCC_APB1SMENR1_TIM5SMEN_Pos (3U)
#define RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos)/*!< 0x00000008 */
#define RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
#define RCC_APB1SMENR1_USBSMEN_Pos (23U)
#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
/******************** Bit definition for RCC_APB1SMENR2 register *************/
#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
#define RCC_APB1SMENR2_I2C4SMEN_Pos (1U)
#define RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk
#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
/******************** Bit definition for RCC_APB2SMENR register *************/
#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
#define RCC_APB2SMENR_SPI4SMEN_Pos (15U)
#define RCC_APB2SMENR_SPI4SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI4SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB2SMENR_SPI4SMEN RCC_APB2SMENR_SPI4SMEN_Msk
#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
#define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
#define RCC_CCIPR_USART2SEL_Pos (2U)
#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
#define RCC_CCIPR_USART3SEL_Pos (4U)
#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
#define RCC_CCIPR_UART4SEL_Pos (6U)
#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR_UART5SEL_Pos (8U)
#define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
#define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR_LPUART1SEL_Pos (10U)
#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
#define RCC_CCIPR_I2C1SEL_Pos (12U)
#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR_I2C2SEL_Pos (14U)
#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR_I2C3SEL_Pos (16U)
#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
#define RCC_CCIPR_SAI1SEL_Pos (20U)
#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
#define RCC_CCIPR_I2S23SEL_Pos (22U)
#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
#define RCC_CCIPR_FDCANSEL_Pos (24U)
#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR_CLK48SEL_Pos (26U)
#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
#define RCC_CCIPR_ADC12SEL_Pos (28U)
#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
#define RCC_CCIPR_ADC345SEL_Pos (30U)
#define RCC_CCIPR_ADC345SEL_Msk (0x3UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
#define RCC_CCIPR_ADC345SEL RCC_CCIPR_ADC345SEL_Msk
#define RCC_CCIPR_ADC345SEL_0 (0x1UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x40000000 */
#define RCC_CCIPR_ADC345SEL_1 (0x2UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos (3U)
#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos (5U)
#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos (6U)
#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
#define RCC_BDCR_LSCOEN_Pos (24U)
#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
#define RCC_BDCR_LSCOSEL_Pos (25U)
#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION_Pos (0U)
#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos (1U)
#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
#define RCC_CSR_RMVF_Pos (23U)
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
#define RCC_CSR_OBLRSTF_Pos (25U)
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_BORRSTF_Pos (27U)
#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/******************** Bit definition for RCC_CRRCR register *****************/
#define RCC_CRRCR_HSI48ON_Pos (0U)
#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
#define RCC_CRRCR_HSI48RDY_Pos (1U)
#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos (7U)
#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
/******************** Bit definition for RCC_CCIPR2 register ******************/
#define RCC_CCIPR2_I2C4SEL_Pos (0U)
#define RCC_CCIPR2_I2C4SEL_Msk (0x3UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000003 */
#define RCC_CCIPR2_I2C4SEL RCC_CCIPR2_I2C4SEL_Msk
#define RCC_CCIPR2_I2C4SEL_0 (0x1UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000001 */
#define RCC_CCIPR2_I2C4SEL_1 (0x2UL << RCC_CCIPR2_I2C4SEL_Pos) /*!< 0x00000002 */
#define RCC_CCIPR2_QSPISEL_Pos (20U)
#define RCC_CCIPR2_QSPISEL_Msk (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR2_QSPISEL RCC_CCIPR2_QSPISEL_Msk
#define RCC_CCIPR2_QSPISEL_0 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR2_QSPISEL_1 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_ICSR register ******************/
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_ALRBWF_Pos (1U)
#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
#define RTC_ICSR_ALRAWF_Pos (0U)
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_SR register *******************/
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
/******************** Bits definition for RTC_MISR register *****************/
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
/******************** Bits definition for RTC_SCR register ******************/
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register *****************/
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos (21U)
#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
/******************** Bits definition for TAMP_CR2 register *****************/
#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
#define TAMP_CR2_TAMP1MF_Pos (16U)
#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
#define TAMP_CR2_TAMP2MF_Pos (17U)
#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
#define TAMP_CR2_TAMP3MF_Pos (18U)
#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_IER register *****************/
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos (21U)
#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
/******************** Bits definition for TAMP_SR register ******************/
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos (21U)
#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
/******************** Bits definition for TAMP_MISR register ****************/
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos (21U)
#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
/******************** Bits definition for TAMP_SCR register *****************/
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos (21U)
#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
/******************** Bits definition for TAMP_BKP1R register ***************/
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
/******************** Bits definition for TAMP_BKP2R register ***************/
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
/******************** Bits definition for TAMP_BKP3R register ***************/
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
/******************** Bits definition for TAMP_BKP4R register ***************/
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************** Bits definition for TAMP_BKP5R register ***************/
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
/******************** Bits definition for TAMP_BKP6R register ***************/
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
/******************** Bits definition for TAMP_BKP7R register ***************/
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
/******************** Bits definition for TAMP_BKP8R register ***************/
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
/******************** Bits definition for TAMP_BKP9R register ***************/
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
/******************** Bits definition for TAMP_BKP10R register ***************/
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
/******************** Bits definition for TAMP_BKP11R register ***************/
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
/******************** Bits definition for TAMP_BKP12R register ***************/
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
/******************** Bits definition for TAMP_BKP13R register ***************/
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
/******************** Bits definition for TAMP_BKP14R register ***************/
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
/******************** Bits definition for TAMP_BKP15R register ***************/
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
/******************** Bits definition for TAMP_BKP16R register ***************/
#define TAMP_BKP16R_Pos (0U)
#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP16R TAMP_BKP16R_Msk
/******************** Bits definition for TAMP_BKP17R register ***************/
#define TAMP_BKP17R_Pos (0U)
#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP17R TAMP_BKP17R_Msk
/******************** Bits definition for TAMP_BKP18R register ***************/
#define TAMP_BKP18R_Pos (0U)
#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP18R TAMP_BKP18R_Msk
/******************** Bits definition for TAMP_BKP19R register ***************/
#define TAMP_BKP19R_Pos (0U)
#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP19R TAMP_BKP19R_Msk
/******************** Bits definition for TAMP_BKP20R register ***************/
#define TAMP_BKP20R_Pos (0U)
#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP20R TAMP_BKP20R_Msk
/******************** Bits definition for TAMP_BKP21R register ***************/
#define TAMP_BKP21R_Pos (0U)
#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP21R TAMP_BKP21R_Msk
/******************** Bits definition for TAMP_BKP22R register ***************/
#define TAMP_BKP22R_Pos (0U)
#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP22R TAMP_BKP22R_Msk
/******************** Bits definition for TAMP_BKP23R register ***************/
#define TAMP_BKP23R_Pos (0U)
#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP23R TAMP_BKP23R_Msk
/******************** Bits definition for TAMP_BKP24R register ***************/
#define TAMP_BKP24R_Pos (0U)
#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP24R TAMP_BKP24R_Msk
/******************** Bits definition for TAMP_BKP25R register ***************/
#define TAMP_BKP25R_Pos (0U)
#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP25R TAMP_BKP25R_Msk
/******************** Bits definition for TAMP_BKP26R register ***************/
#define TAMP_BKP26R_Pos (0U)
#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP26R TAMP_BKP26R_Msk
/******************** Bits definition for TAMP_BKP27R register ***************/
#define TAMP_BKP27R_Pos (0U)
#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP27R TAMP_BKP27R_Msk
/******************** Bits definition for TAMP_BKP28R register ***************/
#define TAMP_BKP28R_Pos (0U)
#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP28R TAMP_BKP28R_Msk
/******************** Bits definition for TAMP_BKP29R register ***************/
#define TAMP_BKP29R_Pos (0U)
#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP29R TAMP_BKP29R_Msk
/******************** Bits definition for TAMP_BKP30R register ***************/
#define TAMP_BKP30R_Pos (0U)
#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP30R TAMP_BKP30R_Msk
/******************** Bits definition for TAMP_BKP31R register ***************/
#define TAMP_BKP31R_Pos (0U)
#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP31R TAMP_BKP31R_Msk
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/****************** Bit definition for SAI_PDMCR register *******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
#define SPI_CR1_CPOL_Pos (1U)
#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
#define SPI_CR1_MSTR_Pos (2U)
#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
#define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
#define SPI_CR1_LSBFIRST_Pos (7U)
#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
#define SPI_CR1_SSI_Pos (8U)
#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
#define SPI_CR1_SSM_Pos (9U)
#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
#define SPI_CR1_RXONLY_Pos (10U)
#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
#define SPI_CR1_CRCL_Pos (11U)
#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
#define SPI_CR1_CRCNEXT_Pos (12U)
#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
#define SPI_CR1_CRCEN_Pos (13U)
#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE_Pos (14U)
#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos (15U)
#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN_Pos (0U)
#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN_Pos (1U)
#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
#define SPI_CR2_SSOE_Pos (2U)
#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
#define SPI_CR2_NSSP_Pos (3U)
#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
#define SPI_CR2_FRF_Pos (4U)
#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
#define SPI_CR2_ERRIE_Pos (5U)
#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE_Pos (6U)
#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE_Pos (7U)
#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
#define SPI_CR2_LDMARX_Pos (13U)
#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
#define SPI_CR2_LDMATX_Pos (14U)
#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE_Pos (0U)
#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
#define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
#define SPI_SR_MODF_Pos (5U)
#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
#define SPI_SR_BSY_Pos (7U)
#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
#define SPI_SR_FRE_Pos (8U)
#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
#define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U)
#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY_Pos (0U)
#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC_Pos (0U)
#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC_Pos (0U)
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN_Pos (0U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN_Pos (1U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_CKPOL_Pos (3U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_I2SE_Pos (10U)
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD_Pos (8U)
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE_Pos (9U)
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
/****************** Bit definition for SYSCFG_CFGR1 register ******************/
#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_CFGR1_I2C4_FMP_Pos (23U)
#define SYSCFG_CFGR1_I2C4_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C4_FMP_Pos) /*!< 0x00800000 */
#define SYSCFG_CFGR1_I2C4_FMP SYSCFG_CFGR1_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
/****************** Bit definition for SYSCFG_SCSR register ****************/
#define SYSCFG_SCSR_CCMER_Pos (0U)
#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
#define SYSCFG_SCSR_CCMBSY_Pos (1U)
#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
/****************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_CLL_Pos (0U)
#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
#define SYSCFG_CFGR2_SPL_Pos (1U)
#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
#define SYSCFG_CFGR2_PVDL_Pos (2U)
#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
#define SYSCFG_CFGR2_ECCL_Pos (3U)
#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
#define SYSCFG_CFGR2_SPF_Pos (8U)
#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
#define SYSCFG_SWPR_PAGE16_Pos (16U)
#define SYSCFG_SWPR_PAGE16_Msk (0x1UL << SYSCFG_SWPR_PAGE16_Pos) /*!< 0x00010000 */
#define SYSCFG_SWPR_PAGE16 (SYSCFG_SWPR_PAGE16_Msk) /*!< CCMSRAM Write protection page 16*/
#define SYSCFG_SWPR_PAGE17_Pos (17U)
#define SYSCFG_SWPR_PAGE17_Msk (0x1UL << SYSCFG_SWPR_PAGE17_Pos) /*!< 0x00020000 */
#define SYSCFG_SWPR_PAGE17 (SYSCFG_SWPR_PAGE17_Msk) /*!< CCMSRAM Write protection page 17*/
#define SYSCFG_SWPR_PAGE18_Pos (18U)
#define SYSCFG_SWPR_PAGE18_Msk (0x1UL << SYSCFG_SWPR_PAGE18_Pos) /*!< 0x00040000 */
#define SYSCFG_SWPR_PAGE18 (SYSCFG_SWPR_PAGE18_Msk) /*!< CCMSRAM Write protection page 18*/
#define SYSCFG_SWPR_PAGE19_Pos (19U)
#define SYSCFG_SWPR_PAGE19_Msk (0x1UL << SYSCFG_SWPR_PAGE19_Pos) /*!< 0x00080000 */
#define SYSCFG_SWPR_PAGE19 (SYSCFG_SWPR_PAGE19_Msk) /*!< CCMSRAM Write protection page 19*/
#define SYSCFG_SWPR_PAGE20_Pos (20U)
#define SYSCFG_SWPR_PAGE20_Msk (0x1UL << SYSCFG_SWPR_PAGE20_Pos) /*!< 0x00100000 */
#define SYSCFG_SWPR_PAGE20 (SYSCFG_SWPR_PAGE20_Msk) /*!< CCMSRAM Write protection page 20*/
#define SYSCFG_SWPR_PAGE21_Pos (21U)
#define SYSCFG_SWPR_PAGE21_Msk (0x1UL << SYSCFG_SWPR_PAGE21_Pos) /*!< 0x00200000 */
#define SYSCFG_SWPR_PAGE21 (SYSCFG_SWPR_PAGE21_Msk) /*!< CCMSRAM Write protection page 21*/
#define SYSCFG_SWPR_PAGE22_Pos (22U)
#define SYSCFG_SWPR_PAGE22_Msk (0x1UL << SYSCFG_SWPR_PAGE22_Pos) /*!< 0x00400000 */
#define SYSCFG_SWPR_PAGE22 (SYSCFG_SWPR_PAGE22_Msk) /*!< CCMSRAM Write protection page 22*/
#define SYSCFG_SWPR_PAGE23_Pos (23U)
#define SYSCFG_SWPR_PAGE23_Msk (0x1UL << SYSCFG_SWPR_PAGE23_Pos) /*!< 0x00800000 */
#define SYSCFG_SWPR_PAGE23 (SYSCFG_SWPR_PAGE23_Msk) /*!< CCMSRAM Write protection page 23*/
#define SYSCFG_SWPR_PAGE24_Pos (24U)
#define SYSCFG_SWPR_PAGE24_Msk (0x1UL << SYSCFG_SWPR_PAGE24_Pos) /*!< 0x01000000 */
#define SYSCFG_SWPR_PAGE24 (SYSCFG_SWPR_PAGE24_Msk) /*!< CCMSRAM Write protection page 24*/
#define SYSCFG_SWPR_PAGE25_Pos (25U)
#define SYSCFG_SWPR_PAGE25_Msk (0x1UL << SYSCFG_SWPR_PAGE25_Pos) /*!< 0x02000000 */
#define SYSCFG_SWPR_PAGE25 (SYSCFG_SWPR_PAGE25_Msk) /*!< CCMSRAM Write protection page 25*/
#define SYSCFG_SWPR_PAGE26_Pos (26U)
#define SYSCFG_SWPR_PAGE26_Msk (0x1UL << SYSCFG_SWPR_PAGE26_Pos) /*!< 0x04000000 */
#define SYSCFG_SWPR_PAGE26 (SYSCFG_SWPR_PAGE26_Msk) /*!< CCMSRAM Write protection page 26*/
#define SYSCFG_SWPR_PAGE27_Pos (27U)
#define SYSCFG_SWPR_PAGE27_Msk (0x1UL << SYSCFG_SWPR_PAGE27_Pos) /*!< 0x08000000 */
#define SYSCFG_SWPR_PAGE27 (SYSCFG_SWPR_PAGE27_Msk) /*!< CCMSRAM Write protection page 27*/
#define SYSCFG_SWPR_PAGE28_Pos (28U)
#define SYSCFG_SWPR_PAGE28_Msk (0x1UL << SYSCFG_SWPR_PAGE28_Pos) /*!< 0x10000000 */
#define SYSCFG_SWPR_PAGE28 (SYSCFG_SWPR_PAGE28_Msk) /*!< CCMSRAM Write protection page 28*/
#define SYSCFG_SWPR_PAGE29_Pos (29U)
#define SYSCFG_SWPR_PAGE29_Msk (0x1UL << SYSCFG_SWPR_PAGE29_Pos) /*!< 0x20000000 */
#define SYSCFG_SWPR_PAGE29 (SYSCFG_SWPR_PAGE29_Msk) /*!< CCMSRAM Write protection page 29*/
#define SYSCFG_SWPR_PAGE30_Pos (30U)
#define SYSCFG_SWPR_PAGE30_Msk (0x1UL << SYSCFG_SWPR_PAGE30_Pos) /*!< 0x40000000 */
#define SYSCFG_SWPR_PAGE30 (SYSCFG_SWPR_PAGE30_Msk) /*!< CCMSRAM Write protection page 30*/
#define SYSCFG_SWPR_PAGE31_Pos (31U)
#define SYSCFG_SWPR_PAGE31_Msk (0x1UL << SYSCFG_SWPR_PAGE31_Pos) /*!< 0x80000000 */
#define SYSCFG_SWPR_PAGE31 (SYSCFG_SWPR_PAGE31_Msk) /*!< CCMSRAM Write protection page 31*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
#define TIM_CR1_CMS_Pos (5U)
#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos (7U)
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos (8U)
#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos (12U)
#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos (15U)
#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos (3U)
#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE_Pos (0U)
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos (1U)
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos (2U)
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos (3U)
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos (4U)
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos (5U)
#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos (6U)
#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos (7U)
#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos (8U)
#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos (9U)
#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos (10U)
#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos (11U)
#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos (12U)
#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos (13U)
#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos (14U)
#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos (20U)
#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos (21U)
#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos (20U)
#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
#define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos (21U)
#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
#define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos (22U)
#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
#define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos (23U)
#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
#define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG_Pos (0U)
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos (6U)
#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
#define TIM_EGR_BG_Pos (7U)
#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
#define TIM_EGR_B2G_Pos (8U)
#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos (4U)
#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos (12U)
#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA_Pos (0U)
#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos (8U)
#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
/******************* Bit definition for TIM1_AF1 register *******************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
#define TIM1_AF1_BKCMP1E_Pos (1U)
#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
#define TIM1_AF1_BKCMP2E_Pos (2U)
#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
#define TIM1_AF1_BKCMP3E_Pos (3U)
#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
#define TIM1_AF1_BKCMP4E_Pos (4U)
#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
#define TIM1_AF1_BKCMP5E_Pos (5U)
#define TIM1_AF1_BKCMP5E_Msk (0x1UL << TIM1_AF1_BKCMP5E_Pos) /*!< 0x00000020 */
#define TIM1_AF1_BKCMP5E TIM1_AF1_BKCMP5E_Msk /*!<BRK COMP5 enable */
#define TIM1_AF1_BKCMP6E_Pos (6U)
#define TIM1_AF1_BKCMP6E_Msk (0x1UL << TIM1_AF1_BKCMP6E_Pos) /*!< 0x00000040 */
#define TIM1_AF1_BKCMP6E TIM1_AF1_BKCMP6E_Msk /*!<BRK COMP6 enable */
#define TIM1_AF1_BKCMP7E_Pos (7U)
#define TIM1_AF1_BKCMP7E_Msk (0x1UL << TIM1_AF1_BKCMP7E_Pos) /*!< 0x00000080 */
#define TIM1_AF1_BKCMP7E TIM1_AF1_BKCMP7E_Msk /*!<BRK COMP7 enable */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
#define TIM1_AF1_BKCMP1P_Pos (10U)
#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
#define TIM1_AF1_BKCMP2P_Pos (11U)
#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
#define TIM1_AF1_BKCMP3P_Pos (12U)
#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
#define TIM1_AF1_BKCMP4P_Pos (13U)
#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
#define TIM1_AF1_ETRSEL_Pos (14U)
#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
#define TIM1_AF2_BK2CMP1E_Pos (1U)
#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
#define TIM1_AF2_BK2CMP2E_Pos (2U)
#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
#define TIM1_AF2_BK2CMP3E_Pos (3U)
#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
#define TIM1_AF2_BK2CMP4E_Pos (4U)
#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
#define TIM1_AF2_BK2CMP5E_Pos (5U)
#define TIM1_AF2_BK2CMP5E_Msk (0x1UL << TIM1_AF2_BK2CMP5E_Pos) /*!< 0x00000020 */
#define TIM1_AF2_BK2CMP5E TIM1_AF2_BK2CMP5E_Msk /*!<BRK2 COMP5 enable */
#define TIM1_AF2_BK2CMP6E_Pos (6U)
#define TIM1_AF2_BK2CMP6E_Msk (0x1UL << TIM1_AF2_BK2CMP6E_Pos) /*!< 0x00000040 */
#define TIM1_AF2_BK2CMP6E TIM1_AF2_BK2CMP6E_Msk /*!<BRK2 COMP6 enable */
#define TIM1_AF2_BK2CMP7E_Pos (7U)
#define TIM1_AF2_BK2CMP7E_Msk (0x1UL << TIM1_AF2_BK2CMP7E_Pos) /*!< 0x00000080 */
#define TIM1_AF2_BK2CMP7E TIM1_AF2_BK2CMP7E_Msk /*!<BRK2 COMP7 enable */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
#define TIM1_AF2_BK2CMP1P_Pos (10U)
#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
#define TIM1_AF2_BK2CMP2P_Pos (11U)
#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_BK2CMP3P_Pos (12U)
#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
#define TIM1_AF2_BK2CMP4P_Pos (13U)
#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
#define TIM1_AF2_OCRSEL_Pos (16U)
#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_HSE32EN_Pos (0U)
#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM_DTR2 register *********************/
#define TIM_DTR2_DTGF_Pos (0U)
#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos (16U)
#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos (17U)
#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
/******************* Bit definition for TIM_ECR register *********************/
#define TIM_ECR_IE_Pos (0U)
#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
#define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
#define TIM_ECR_IDIR_Pos (1U)
#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_FIDX_Pos (5U)
#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
#define TIM_ECR_IPOS_Pos (6U)
#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
#define TIM_ECR_PW_Pos (16U)
#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
#define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos (24U)
#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB_Pos (0U)
#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_OR register *******************/
#define LPTIM_OR_IN1_Pos (0U)
#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
#define LPTIM_OR_IN2_Pos (1U)
#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART_Pos (0U)
#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR_Pos (0U)
#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */
#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
/******************* Bit definition for VREFBUF_CCR register ******************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* USB Device FS Endpoint registers */
/* */
/******************************************************************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
/* bit positions */
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
/* */
/* USB Device FS General registers */
/* */
/******************************************************************************/
#define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
#define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
#define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
#define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
#define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
#define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
/****************** Bits definition for USB_CNTR register *******************/
#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/****************** Bits definition for USB_ISTR register *******************/
#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
/****************** Bits definition for USB_FNR register ********************/
#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
/****************** Bits definition for USB_DADDR register ****************/
#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
#define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
#define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
#define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
#define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
#define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
#define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
#define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
#define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
/****************** Bit definition for USB_BTABLE register ******************/
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
/****************** Bits definition for USB_BCDR register *******************/
#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
/******************* Bit definition for LPMCSR register *********************/
#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
/*!< Buffer descriptor table */
/***************** Bit definition for USB_ADDR0_TX register *****************/
#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_TX register *****************/
#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_TX register *****************/
#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_TX register *****************/
#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_TX register *****************/
#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_TX register *****************/
#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_TX register *****************/
#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_TX register *****************/
#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_TX register ****************/
#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
/***************** Bit definition for USB_COUNT1_TX register ****************/
#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
/***************** Bit definition for USB_COUNT2_TX register ****************/
#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
/***************** Bit definition for USB_COUNT3_TX register ****************/
#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
/***************** Bit definition for USB_COUNT4_TX register ****************/
#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
/***************** Bit definition for USB_COUNT5_TX register ****************/
#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
/***************** Bit definition for USB_COUNT6_TX register ****************/
#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
/***************** Bit definition for USB_COUNT7_TX register ****************/
#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_ADDR0_RX register *****************/
#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_RX register *****************/
#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_RX register *****************/
#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_RX register *****************/
#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_RX register *****************/
#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_RX register *****************/
#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_RX register *****************/
#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_RX register *****************/
#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_RX register ****************/
#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT0_RX_BLSIZE_Pos (15U)
#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT1_RX register ****************/
#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT1_RX_BLSIZE_Pos (15U)
#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT2_RX register ****************/
#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT2_RX_BLSIZE_Pos (15U)
#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT3_RX register ****************/
#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT3_RX_BLSIZE_Pos (15U)
#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT4_RX register ****************/
#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT4_RX_BLSIZE_Pos (15U)
#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT5_RX register ****************/
#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT5_RX_BLSIZE_Pos (15U)
#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT6_RX register ****************/
#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT6_RX_BLSIZE_Pos (15U)
#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT7_RX register ****************/
#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT7_RX_BLSIZE_Pos (15U)
#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
/* UCPD */
/* */
/******************************************************************************/
/******************** Bits definition for UCPD_CFG1 register *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos (6U)
#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos (11U)
#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos (20U)
#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos (29U)
#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define UCPD_CFG1_RXDMAEN_Pos (30U)
#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define UCPD_CFG1_UCPDEN_Pos (31U)
#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
/******************** Bits definition for UCPD_CFG2 register *******************/
#define UCPD_CFG2_RXFILTDIS_Pos (0U)
#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos (1U)
#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos (2U)
#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos (3U)
#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
/******************** Bits definition for UCPD_CR register ********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos (2U)
#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXHRST_Pos (3U)
#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
#define UCPD_CR_RXMODE_Pos (4U)
#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
#define UCPD_CR_PHYRXEN_Pos (5U)
#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
#define UCPD_CR_PHYCCSEL_Pos (6U)
#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
#define UCPD_CR_ANASUBMODE_Pos (7U)
#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos (9U)
#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
#define UCPD_CR_CCENABLE_Pos (10U)
#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
#define UCPD_CR_FRSRXEN_Pos (16U)
#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
#define UCPD_CR_FRSTX_Pos (17U)
#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos (18U)
#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
#define UCPD_CR_CC1TCDIS_Pos (20U)
#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos (21U)
#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
/******************** Bits definition for UCPD_IMR register *******************/
#define UCPD_IMR_TXISIE_Pos (0U)
#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
#define UCPD_IMR_TXMSGABTIE_Pos (3U)
#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
#define UCPD_IMR_HRSTDISCIE_Pos (4U)
#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
#define UCPD_IMR_HRSTSENTIE_Pos (5U)
#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
#define UCPD_IMR_TXUNDIE_Pos (6U)
#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
#define UCPD_IMR_RXNEIE_Pos (8U)
#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
#define UCPD_IMR_RXORDDETIE_Pos (9U)
#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
#define UCPD_IMR_RXOVRIE_Pos (11U)
#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
#define UCPD_IMR_RXMSGENDIE_Pos (12U)
#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
#define UCPD_IMR_FRSEVTIE_Pos (20U)
#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
/******************** Bits definition for UCPD_SR register ********************/
#define UCPD_SR_TXIS_Pos (0U)
#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
#define UCPD_SR_TXMSGDISC_Pos (1U)
#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
#define UCPD_SR_TXMSGSENT_Pos (2U)
#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
#define UCPD_SR_TXMSGABT_Pos (3U)
#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
#define UCPD_SR_HRSTDISC_Pos (4U)
#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
#define UCPD_SR_HRSTSENT_Pos (5U)
#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
#define UCPD_SR_TXUND_Pos (6U)
#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
#define UCPD_SR_RXNE_Pos (8U)
#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
#define UCPD_SR_RXORDDET_Pos (9U)
#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
#define UCPD_SR_RXHRSTDET_Pos (10U)
#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
#define UCPD_SR_RXOVR_Pos (11U)
#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
#define UCPD_SR_RXMSGEND_Pos (12U)
#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
#define UCPD_SR_RXERR_Pos (13U)
#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos (14U)
#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
#define UCPD_SR_TYPECEVT2_Pos (15U)
#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
#define UCPD_SR_FRSEVT_Pos (20U)
#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
/******************** Bits definition for UCPD_ICR register *******************/
#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
#define UCPD_ICR_TXMSGABTCF_Pos (3U)
#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
#define UCPD_ICR_HRSTDISCCF_Pos (4U)
#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
#define UCPD_ICR_HRSTSENTCF_Pos (5U)
#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
#define UCPD_ICR_TXUNDCF_Pos (6U)
#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
#define UCPD_ICR_RXORDDETCF_Pos (9U)
#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
#define UCPD_ICR_RXOVRCF_Pos (11U)
#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
#define UCPD_ICR_RXMSGENDCF_Pos (12U)
#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
#define UCPD_ICR_FRSEVTCF_Pos (20U)
#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
/******************** Bits definition for UCPD_TXORDSET register **************/
#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
/******************** Bits definition for UCPD_TXPAYSZ register ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
/******************** Bits definition for UCPD_TXDR register *******************/
#define UCPD_TXDR_TXDATA_Pos (0U)
#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
/******************** Bits definition for UCPD_RXORDSET register **************/
#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
/******************** Bits definition for UCPD_RXPAYSZ register ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
/******************** Bits definition for UCPD_RXDR register *******************/
#define UCPD_RXDR_RXDATA_Pos (0U)
#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/******************** Bits definition for UCPD_RXORDEXT1 register **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
/******************** Bits definition for UCPD_RXORDEXT2 register **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2) || \
((INSTANCE) == ADC3) || \
((INSTANCE) == ADC4) || \
((INSTANCE) == ADC5))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC3))
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
((INSTANCE) == ADC345_COMMON) )
/******************************** FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
((INSTANCE) == FDCAN2) || \
((INSTANCE) == FDCAN3))
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2) || \
((INSTANCE) == COMP3) || \
((INSTANCE) == COMP4) || \
((INSTANCE) == COMP5) || \
((INSTANCE) == COMP6) || \
((INSTANCE) == COMP7))
/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC2) || \
((INSTANCE) == DAC3) || \
((INSTANCE) == DAC4))
/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7) || \
((INSTANCE) == DMA1_Channel8) || \
((INSTANCE) == DMA2_Channel1) || \
((INSTANCE) == DMA2_Channel2) || \
((INSTANCE) == DMA2_Channel3) || \
((INSTANCE) == DMA2_Channel4) || \
((INSTANCE) == DMA2_Channel5) || \
((INSTANCE) == DMA2_Channel6) || \
((INSTANCE) == DMA2_Channel7) || \
((INSTANCE) == DMA2_Channel8))
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
/******************************* FMAC Instances *******************************/
#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances *****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4))
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3) || \
((INSTANCE) == OPAMP4) || \
((INSTANCE) == OPAMP5) || \
((INSTANCE) == OPAMP6))
/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/******************************* QSPI Instances *******************************/
#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3) || \
((INSTANCE) == I2C4))
/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3) || \
((INSTANCE) == SPI4))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
((__INSTANCE__) == SPI3))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
((INSTANCE) == TIM5))
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM5) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM5) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** UCPD Instances ********************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
/******************************* USB Instances *******************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/**
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32G4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32G4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
/* Aliases for __IRQHandler */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32G473xx_H */
/**
* @}
*/
/**
* @}
*/
| 1,099,865 | C | 74.592165 | 180 | 0.511624 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g431xx.h | /**
******************************************************************************
* @file stm32g431xx.h
* @author MCD Application Team
* @brief CMSIS STM32G431xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32g431xx
* @{
*/
#ifndef __STM32G431xx_H
#define __STM32G431xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32G4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ***************************************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_IRQn = 19, /*!< USB HP Interrupt */
USB_LP_IRQn = 20, /*!< USB LP Interrupt */
FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupts */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
COMP4_IRQn = 65, /*!< COMP4 */
CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
RNG_IRQn = 90, /*!< RNG global interrupt */
LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
FMAC_IRQn = 101 /*!< FMAC global Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32g4xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
__IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
} FDCAN_Config_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
__IO uint32_t RESERVED[2];
__IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
__IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
__IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
__IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
__IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
__IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
__IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */
__IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
} FLASH_TypeDef;
/**
* @brief FMAC
*/
typedef struct
{
__IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
__IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
__IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
__IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
} FMAC_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
} OPAMP_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
__IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
/*
* @brief Specific device feature definitions
*/
#define RTC_TAMP_INT_6_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 3u
#define RTC_BACKUP_NB 16u
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
} RTC_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
} TAMP_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
__IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
__IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
__IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
__IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
__IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
__IO uint16_t RESERVEDD; /*!< Reserved */
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
__IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief CORDIC
*/
typedef struct
{
__IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
__IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
__IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
} CORDIC_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */
#define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */
#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */
#define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
#define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */
#define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */
#define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
/*!< AHB1 peripherals */
#define DMA1_BASE (AHB1PERIPH_BASE)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
/*!< AHB2 peripherals */
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0042000UL)
#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos (15U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
#define ADC_CFGR2_GCOMP_Pos (16U)
#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
#define ADC_CFGR2_SWTRIG_Pos (25U)
#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
#define ADC_CFGR2_BULB_Pos (26U)
#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
#define ADC_CFGR2_SMPTRIG_Pos (27U)
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_AWDFILT_Pos (12U)
#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSETPOS_Pos (24U)
#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
#define ADC_OFR1_SATEN_Pos (25U)
#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSETPOS_Pos (24U)
#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
#define ADC_OFR2_SATEN_Pos (25U)
#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSETPOS_Pos (24U)
#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
#define ADC_OFR3_SATEN_Pos (25U)
#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSETPOS_Pos (24U)
#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
#define ADC_OFR4_SATEN_Pos (25U)
#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
/******************** Bit definition for ADC_GCOMP register *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos (13U)
#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
#define ADC_CCR_MDMA_Pos (14U)
#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_VSENSESEL_Pos (23U)
#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATSEL_Pos (24U)
#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_INMSEL_Pos (4U)
#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_Pos (8U)
#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
#define COMP_CSR_BLANKING_Pos (19U)
#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
/* CORDIC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CORDIC_CSR register *****************/
#define CORDIC_CSR_FUNC_Pos (0U)
#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos (4U)
#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos (8U)
#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos (16U)
#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos (17U)
#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos (18U)
#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos (19U)
#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos (20U)
#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos (21U)
#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos (22U)
#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos (31U)
#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
/******************* Bit definition for CORDIC_WDATA register ***************/
#define CORDIC_WDATA_ARG_Pos (0U)
#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
/******************* Bit definition for CORDIC_RDATA register ***************/
#define CORDIC_RDATA_RES_Pos (0U)
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_Pos (16U)
#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
#define DAC_DOR2_DACC2DORB_Pos (16U)
#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DAC1RDY_Pos (11U)
#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
#define DAC_SR_DORSTAT1_Pos (12U)
#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
#define DAC_SR_DORSTAT2_Pos (28U)
#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos (8U)
#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos (9U)
#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
#define DAC_MCR_HFSEL_Pos (14U)
#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
#define DAC_MCR_DMADOUBLE2_Pos (24U)
#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
#define DAC_MCR_SINFORMAT2_Pos (25U)
#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR2_TSAMPLE2_Pos (0U)
#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/****************** Bit definition for DAC_STR1 register ******************/
#define DAC_STR1_STRSTDATA1_Pos (0U)
#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
#define DAC_STR1_STDIR1_Pos (12U)
#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
#define DAC_STR1_STINCDATA1_Pos (16U)
#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STR2 register ******************/
#define DAC_STR2_STRSTDATA2_Pos (0U)
#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
#define DAC_STR2_STDIR2_Pos (12U)
#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
#define DAC_STR2_STINCDATA2_Pos (16U)
#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STMODR register ****************/
#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
#define DBGMCU_CR_TRACE_MODE_Pos (6U)
#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register ****************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
/******************** Bits definition for DMAMUX_CFR register ****************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
/******************** Bits definition for DMAMUX_RGCFR register ************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x7FFFFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
/****************** Bit definition for EXTI_RTSR1 register ******************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT19_Pos (19U)
#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR1_RT22_Pos (22U)
#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR1_RT29_Pos (29U)
#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR1_RT30_Pos (30U)
#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_FT16_Pos (16U)
#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_FT17_Pos (17U)
#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_FT19_Pos (19U)
#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR1_FT22_Pos (22U)
#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR1_FT29_Pos (29U)
#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR1_FT30_Pos (30U)
#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos (16U)
#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos (17U)
#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI19_Pos (19U)
#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos (22U)
#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER1_SWI29_Pos (29U)
#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER1_SWI30_Pos (30U)
#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
/******************* Bit definition for EXTI_PR1 register *******************/
#define EXTI_PR1_PIF0_Pos (0U)
#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PIF1_Pos (1U)
#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PIF2_Pos (2U)
#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PIF3_Pos (3U)
#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PIF4_Pos (4U)
#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PIF5_Pos (5U)
#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PIF6_Pos (6U)
#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PIF7_Pos (7U)
#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PIF8_Pos (8U)
#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PIF9_Pos (9U)
#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PIF10_Pos (10U)
#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PIF11_Pos (11U)
#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PIF12_Pos (12U)
#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PIF13_Pos (13U)
#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PIF14_Pos (14U)
#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PIF15_Pos (15U)
#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PIF16_Pos (16U)
#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PIF17_Pos (17U)
#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR1_PIF19_Pos (19U)
#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PIF20_Pos (20U)
#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PIF21_Pos (21U)
#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR1_PIF22_Pos (22U)
#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR1_PIF29_Pos (29U)
#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR1_PIF30_Pos (30U)
#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x3F4UL << EXTI_IMR2_IM_Pos) /*!< 0x000003F4 */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x3F4UL << EXTI_EMR2_EM_Pos) /*!< 0x000003F4 */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT38_Pos (6U)
#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
#define EXTI_RTSR2_RT39_Pos (7U)
#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
#define EXTI_RTSR2_RT40_Pos (8U)
#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
#define EXTI_RTSR2_RT41_Pos (9U)
#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_FT38_Pos (6U)
#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
#define EXTI_FTSR2_FT39_Pos (7U)
#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
#define EXTI_FTSR2_FT40_Pos (8U)
#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
#define EXTI_FTSR2_FT41_Pos (9U)
#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI38_Pos (6U)
#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
#define EXTI_SWIER2_SWI39_Pos (7U)
#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
#define EXTI_SWIER2_SWI40_Pos (8U)
#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
#define EXTI_SWIER2_SWI41_Pos (9U)
#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PIF38_Pos (6U)
#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
#define EXTI_PR2_PIF39_Pos (7U)
#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
#define EXTI_PR2_PIF40_Pos (8U)
#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
#define EXTI_PR2_PIF41_Pos (9U)
#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0F_Pos (1U)
#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (2U)
#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (3U)
#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1F_Pos (4U)
#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (5U)
#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (6U)
#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (7U)
#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (8U)
#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (9U)
#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (10U)
#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFF_Pos (11U)
#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (12U)
#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (13U)
#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (14U)
#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (15U)
#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_ELO_Pos (16U)
#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (17U)
#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (18U)
#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (19U)
#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (20U)
#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (21U)
#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (22U)
#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (23U)
#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0FE_Pos (1U)
#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (2U)
#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (3U)
#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1FE_Pos (4U)
#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (5U)
#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (6U)
#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (7U)
#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (8U)
#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos (9U)
#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (10U)
#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFFE_Pos (11U)
#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (12U)
#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (13U)
#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (14U)
#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (15U)
#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_ELOE_Pos (16U)
#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (17U)
#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (18U)
#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (19U)
#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (20U)
#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (21U)
#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos (22U)
#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (23U)
#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RXFIFO0_Pos (0U)
#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
Rx FIFO 0 is Full
Rx FIFO 0 Has New Message */
#define FDCAN_ILS_RXFIFO1_Pos (1U)
#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
Rx FIFO 1 is Full
Rx FIFO 1 Has New Message */
#define FDCAN_ILS_SMSG_Pos (2U)
#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
Transmission Completed
High Priority Message */
#define FDCAN_ILS_TFERR_Pos (3U)
#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
Tx Event FIFO Full
Tx Event FIFO New Entry
Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_MISC_Pos (4U)
#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
Message RAM Access Failure
Timestamp Wraparound */
#define FDCAN_ILS_BERR_Pos (5U)
#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
Error Logging Overflow */
#define FDCAN_ILS_PERR_Pos (6U)
#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
Protocol Error in Data Phase Line
Protocol Error in Arbitration Phase Line
Watchdog Interrupt Line
Bus_Off Status
Warning Status */
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_RXGFC register ********************/
#define FDCAN_RXGFC_RRFE_Pos (0U)
#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_RXGFC_RRFS_Pos (1U)
#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_RXGFC_ANFE_Pos (2U)
#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_RXGFC_ANFS_Pos (4U)
#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
#define FDCAN_RXGFC_F1OM_Pos (8U)
#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
#define FDCAN_RXGFC_F0OM_Pos (9U)
#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
#define FDCAN_RXGFC_LSS_Pos (16U)
#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
#define FDCAN_RXGFC_LSE_Pos (24U)
#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TFQM_Pos (24U)
#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CFIE_Pos (0U)
#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/*!<FDCAN config registers */
/***************** Bit definition for FDCAN_CKDIV register *********************/
#define FDCAN_CKDIV_PDIV_Pos (0U)
#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS (0x00000000U)
#define FLASH_ACR_LATENCY_1WS (0x00000001U)
#define FLASH_ACR_LATENCY_2WS (0x00000002U)
#define FLASH_ACR_LATENCY_3WS (0x00000003U)
#define FLASH_ACR_LATENCY_4WS (0x00000004U)
#define FLASH_ACR_LATENCY_5WS (0x00000005U)
#define FLASH_ACR_LATENCY_6WS (0x00000006U)
#define FLASH_ACR_LATENCY_7WS (0x00000007U)
#define FLASH_ACR_LATENCY_8WS (0x00000008U)
#define FLASH_ACR_LATENCY_9WS (0x00000009U)
#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_RUN_PD_Pos (13U)
#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
#define FLASH_ACR_SLEEP_PD_Pos (14U)
#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
#define FLASH_ACR_DBG_SWEN_Pos (18U)
#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_OPERR_Pos (1U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_PROGERR_Pos (3U)
#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_SIZERR_Pos (6U)
#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_MISERR_Pos (8U)
#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
#define FLASH_SR_FASTERR_Pos (9U)
#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
#define FLASH_SR_RDERR_Pos (14U)
#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_OPTVERR_Pos (15U)
#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PER_Pos (1U)
#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
#define FLASH_CR_PER FLASH_CR_PER_Msk
#define FLASH_CR_MER1_Pos (2U)
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_OPTSTRT_Pos (17U)
#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
#define FLASH_CR_FSTPG_Pos (18U)
#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_RDERRIE_Pos (26U)
#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
#define FLASH_CR_SEC_PROT1_Pos (28U)
#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
#define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_ECCR register ***************/
#define FLASH_ECCR_ADDR_ECC_Pos (0U)
#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0003FFFF */
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
#define FLASH_ECCR_SYSF_ECC_Pos (22U)
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
#define FLASH_ECCR_ECCIE_Pos (24U)
#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
#define FLASH_ECCR_ECCC_Pos (30U)
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
#define FLASH_ECCR_ECCD_Pos (31U)
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
/******************* Bits definition for FLASH_OPTR register ***************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
#define FLASH_OPTR_BOR_LEV_Pos (8U)
#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
#define FLASH_OPTR_nRST_STOP_Pos (12U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
#define FLASH_OPTR_nRST_STDBY_Pos (13U)
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
#define FLASH_OPTR_WWDG_SW_Pos (19U)
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
#define FLASH_OPTR_nBOOT1_Pos (23U)
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
#define FLASH_OPTR_SRAM_PE_Pos (24U)
#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
#define FLASH_OPTR_nSWBOOT0_Pos (26U)
#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
#define FLASH_OPTR_nBOOT0_Pos (27U)
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
#define FLASH_OPTR_NRST_MODE_Pos (28U)
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
#define FLASH_OPTR_IRHEN_Pos (30U)
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
/****************** Bits definition for FLASH_PCROP1SR register **********/
#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00003FFF */
#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
/****************** Bits definition for FLASH_PCROP1ER register ***********/
#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
#define FLASH_PCROP1ER_PCROP1_END_Msk (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00003FFF */
#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000003F */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x003F0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000003F */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x003F0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_SEC1R register **************/
#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
#define FLASH_SEC1R_SEC_SIZE1_Msk (0x7FUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x0000007F */
#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
/******************************************************************************/
/* */
/* Filter Mathematical ACcelerator unit (FMAC) */
/* */
/******************************************************************************/
/***************** Bit definition for FMAC_X1BUFCFG register ****************/
#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
/***************** Bit definition for FMAC_X2BUFCFG register ****************/
#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
/***************** Bit definition for FMAC_YBUFCFG register *****************/
#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
/****************** Bit definition for FMAC_PARAM register ******************/
#define FMAC_PARAM_P_Pos (0U)
#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
#define FMAC_PARAM_Q_Pos (8U)
#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
#define FMAC_PARAM_R_Pos (16U)
#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
#define FMAC_PARAM_FUNC_Pos (24U)
#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
#define FMAC_PARAM_START_Pos (31U)
#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
/******************** Bit definition for FMAC_CR register *******************/
#define FMAC_CR_RIEN_Pos (0U)
#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
#define FMAC_CR_WIEN_Pos (1U)
#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
#define FMAC_CR_OVFLIEN_Pos (2U)
#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
#define FMAC_CR_UNFLIEN_Pos (3U)
#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
#define FMAC_CR_SATIEN_Pos (4U)
#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
#define FMAC_CR_DMAREN_Pos (8U)
#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
#define FMAC_CR_DMAWEN_Pos (9U)
#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
#define FMAC_CR_CLIPEN_Pos (15U)
#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
#define FMAC_CR_RESET_Pos (16U)
#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
/******************* Bit definition for FMAC_SR register ********************/
#define FMAC_SR_YEMPTY_Pos (0U)
#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
#define FMAC_SR_X1FULL_Pos (1U)
#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
#define FMAC_SR_OVFL_Pos (8U)
#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
#define FMAC_SR_UNFL_Pos (9U)
#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
#define FMAC_SR_SAT_Pos (10U)
#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
/****************** Bit definition for FMAC_WDATA register ******************/
#define FMAC_WDATA_WDATA_Pos (0U)
#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
/****************** Bit definition for FMACX_RDATA register *****************/
#define FMAC_RDATA_RDATA_Pos (0U)
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/* Legacy defines */
#define GPIO_BRR_BR_0 GPIO_BRR_BR0
#define GPIO_BRR_BR_1 GPIO_BRR_BR1
#define GPIO_BRR_BR_2 GPIO_BRR_BR2
#define GPIO_BRR_BR_3 GPIO_BRR_BR3
#define GPIO_BRR_BR_4 GPIO_BRR_BR4
#define GPIO_BRR_BR_5 GPIO_BRR_BR5
#define GPIO_BRR_BR_6 GPIO_BRR_BR6
#define GPIO_BRR_BR_7 GPIO_BRR_BR7
#define GPIO_BRR_BR_8 GPIO_BRR_BR8
#define GPIO_BRR_BR_9 GPIO_BRR_BR9
#define GPIO_BRR_BR_10 GPIO_BRR_BR10
#define GPIO_BRR_BR_11 GPIO_BRR_BR11
#define GPIO_BRR_BR_12 GPIO_BRR_BR12
#define GPIO_BRR_BR_13 GPIO_BRR_BR13
#define GPIO_BRR_BR_14 GPIO_BRR_BR14
#define GPIO_BRR_BR_15 GPIO_BRR_BR15
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_USERTRIM_Pos (4U)
#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
#define OPAMP_CSR_OPAMPINTEN_Pos (8U)
#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
#define OPAMP_CSR_OUTCAL_Pos (30U)
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
#define OPAMP_CSR_LOCK_Pos (31U)
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
/********************* Bit definition for OPAMPx_TCMR register ***************/
#define OPAMP_TCMR_VMSSEL_Pos (0U)
#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
#define OPAMP_TCMR_VPSSEL_Pos (1U)
#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
#define OPAMP_TCMR_T1CMEN_Pos (3U)
#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
#define OPAMP_TCMR_T8CMEN_Pos (4U)
#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
#define OPAMP_TCMR_T20CMEN_Pos (5U)
#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
#define OPAMP_TCMR_LOCK_Pos (31U)
#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_LPR_Pos (14U)
#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
#define PWR_CR1_VOS_Pos (9U)
#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_LPMS_Pos (0U)
#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
#define PWR_CR1_LPMS_STOP1_Pos (0U)
#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
#define PWR_CR1_LPMS_STANDBY_Pos (0U)
#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
/******************** Bit definition for PWR_CR2 register ********************/
/*!< PVME Peripheral Voltage Monitor Enable */
#define PWR_CR2_PVME_Pos (4U)
#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
#define PWR_CR2_PVME4_Pos (7U)
#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
#define PWR_CR2_PVME3_Pos (6U)
#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
#define PWR_CR2_PVME2_Pos (5U)
#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
#define PWR_CR2_PVME1_Pos (4U)
#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
/*!< PVD level configuration */
#define PWR_CR2_PLS_Pos (1U)
#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
#define PWR_CR2_PLS_LEV1_Pos (1U)
#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR2_PLS_LEV2_Pos (2U)
#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR2_PLS_LEV3_Pos (1U)
#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR2_PLS_LEV4_Pos (3U)
#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR2_PLS_LEV5_Pos (1U)
#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR2_PLS_LEV6_Pos (2U)
#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR2_PLS_LEV7_Pos (1U)
#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
#define PWR_CR2_PVDE_Pos (0U)
#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EIWF_Pos (15U)
#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
#define PWR_CR3_UCPD_DBDIS_Pos (14U)
#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
#define PWR_CR3_UCPD_STDBY_Pos (13U)
#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
#define PWR_CR3_APC_Pos (10U)
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
#define PWR_CR3_RRS_Pos (8U)
#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
#define PWR_CR3_EWUP5_Pos (4U)
#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
#define PWR_CR3_EWUP4_Pos (3U)
#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
#define PWR_CR3_EWUP3_Pos (2U)
#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
#define PWR_CR3_EWUP2_Pos (1U)
#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
#define PWR_CR3_EWUP1_Pos (0U)
#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
#define PWR_CR3_EWUP_Pos (0U)
#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
/******************** Bit definition for PWR_CR4 register ********************/
#define PWR_CR4_VBRS_Pos (9U)
#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
#define PWR_CR4_VBE_Pos (8U)
#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
#define PWR_CR4_WP5_Pos (4U)
#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
#define PWR_CR4_WP4_Pos (3U)
#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
#define PWR_CR4_WP3_Pos (2U)
#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
#define PWR_CR4_WP2_Pos (1U)
#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
#define PWR_CR4_WP1_Pos (0U)
#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
/******************** Bit definition for PWR_SR1 register ********************/
#define PWR_SR1_WUFI_Pos (15U)
#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
#define PWR_SR1_SBF_Pos (8U)
#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
#define PWR_SR1_WUF_Pos (0U)
#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
#define PWR_SR1_WUF5_Pos (4U)
#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
#define PWR_SR1_WUF4_Pos (3U)
#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
#define PWR_SR1_WUF3_Pos (2U)
#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
#define PWR_SR1_WUF2_Pos (1U)
#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
#define PWR_SR1_WUF1_Pos (0U)
#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
/******************** Bit definition for PWR_SR2 register ********************/
#define PWR_SR2_PVMO4_Pos (15U)
#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
#define PWR_SR2_PVMO3_Pos (14U)
#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
#define PWR_SR2_PVMO2_Pos (13U)
#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
#define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
#define PWR_SR2_VOSF_Pos (10U)
#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
#define PWR_SR2_REGLPF_Pos (9U)
#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
#define PWR_SR2_REGLPS_Pos (8U)
#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CSBF_Pos (8U)
#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
#define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
#define PWR_SCR_CWUF5_Pos (4U)
#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
#define PWR_SCR_CWUF4_Pos (3U)
#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
#define PWR_SCR_CWUF3_Pos (2U)
#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
#define PWR_SCR_CWUF2_Pos (1U)
#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
#define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
/******************** Bit definition for PWR_PUCRA register ********************/
#define PWR_PUCRA_PA15_Pos (15U)
#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
#define PWR_PUCRA_PA13_Pos (13U)
#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
#define PWR_PUCRA_PA12_Pos (12U)
#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
#define PWR_PUCRA_PA11_Pos (11U)
#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
#define PWR_PUCRA_PA10_Pos (10U)
#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
#define PWR_PUCRA_PA9_Pos (9U)
#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
#define PWR_PUCRA_PA8_Pos (8U)
#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
#define PWR_PUCRA_PA7_Pos (7U)
#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
#define PWR_PUCRA_PA6_Pos (6U)
#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
#define PWR_PUCRA_PA5_Pos (5U)
#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
#define PWR_PUCRA_PA4_Pos (4U)
#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
#define PWR_PUCRA_PA3_Pos (3U)
#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
#define PWR_PUCRA_PA2_Pos (2U)
#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
#define PWR_PUCRA_PA1_Pos (1U)
#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
#define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
/******************** Bit definition for PWR_PDCRA register ********************/
#define PWR_PDCRA_PA14_Pos (14U)
#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
#define PWR_PDCRA_PA12_Pos (12U)
#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
#define PWR_PDCRA_PA11_Pos (11U)
#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
#define PWR_PDCRA_PA10_Pos (10U)
#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
#define PWR_PDCRA_PA9_Pos (9U)
#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
#define PWR_PDCRA_PA8_Pos (8U)
#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
#define PWR_PDCRA_PA7_Pos (7U)
#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
#define PWR_PDCRA_PA6_Pos (6U)
#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
#define PWR_PDCRA_PA5_Pos (5U)
#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
#define PWR_PDCRA_PA4_Pos (4U)
#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
#define PWR_PDCRA_PA3_Pos (3U)
#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
#define PWR_PDCRA_PA2_Pos (2U)
#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
#define PWR_PDCRA_PA1_Pos (1U)
#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
#define PWR_PDCRA_PA0_Pos (0U)
#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
/******************** Bit definition for PWR_PUCRB register ********************/
#define PWR_PUCRB_PB15_Pos (15U)
#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
#define PWR_PUCRB_PB14_Pos (14U)
#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
#define PWR_PUCRB_PB13_Pos (13U)
#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
#define PWR_PUCRB_PB12_Pos (12U)
#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
#define PWR_PUCRB_PB11_Pos (11U)
#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
#define PWR_PUCRB_PB10_Pos (10U)
#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
#define PWR_PUCRB_PB9_Pos (9U)
#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
#define PWR_PUCRB_PB8_Pos (8U)
#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
#define PWR_PUCRB_PB7_Pos (7U)
#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
#define PWR_PUCRB_PB6_Pos (6U)
#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
#define PWR_PUCRB_PB5_Pos (5U)
#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
#define PWR_PUCRB_PB4_Pos (4U)
#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
#define PWR_PUCRB_PB3_Pos (3U)
#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
#define PWR_PUCRB_PB2_Pos (2U)
#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
#define PWR_PUCRB_PB1_Pos (1U)
#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
#define PWR_PUCRB_PB0_Pos (0U)
#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
/******************** Bit definition for PWR_PDCRB register ********************/
#define PWR_PDCRB_PB15_Pos (15U)
#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
#define PWR_PDCRB_PB14_Pos (14U)
#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
#define PWR_PDCRB_PB13_Pos (13U)
#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
#define PWR_PDCRB_PB12_Pos (12U)
#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
#define PWR_PDCRB_PB11_Pos (11U)
#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
#define PWR_PDCRB_PB10_Pos (10U)
#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
#define PWR_PDCRB_PB9_Pos (9U)
#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
#define PWR_PDCRB_PB8_Pos (8U)
#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
#define PWR_PDCRB_PB7_Pos (7U)
#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
#define PWR_PDCRB_PB6_Pos (6U)
#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
#define PWR_PDCRB_PB5_Pos (5U)
#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
#define PWR_PDCRB_PB3_Pos (3U)
#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
#define PWR_PDCRB_PB2_Pos (2U)
#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
#define PWR_PDCRB_PB1_Pos (1U)
#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
#define PWR_PDCRB_PB0_Pos (0U)
#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
/******************** Bit definition for PWR_PUCRC register ********************/
#define PWR_PUCRC_PC15_Pos (15U)
#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
#define PWR_PUCRC_PC14_Pos (14U)
#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
#define PWR_PUCRC_PC13_Pos (13U)
#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
#define PWR_PUCRC_PC12_Pos (12U)
#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
#define PWR_PUCRC_PC11_Pos (11U)
#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
#define PWR_PUCRC_PC10_Pos (10U)
#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
#define PWR_PUCRC_PC9_Pos (9U)
#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
#define PWR_PUCRC_PC8_Pos (8U)
#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
#define PWR_PUCRC_PC7_Pos (7U)
#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
#define PWR_PUCRC_PC6_Pos (6U)
#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
#define PWR_PUCRC_PC5_Pos (5U)
#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
#define PWR_PUCRC_PC4_Pos (4U)
#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
#define PWR_PUCRC_PC3_Pos (3U)
#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
#define PWR_PUCRC_PC2_Pos (2U)
#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
#define PWR_PUCRC_PC1_Pos (1U)
#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
#define PWR_PUCRC_PC0_Pos (0U)
#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
/******************** Bit definition for PWR_PDCRC register ********************/
#define PWR_PDCRC_PC15_Pos (15U)
#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
#define PWR_PDCRC_PC14_Pos (14U)
#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
#define PWR_PDCRC_PC13_Pos (13U)
#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
#define PWR_PDCRC_PC12_Pos (12U)
#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
#define PWR_PDCRC_PC11_Pos (11U)
#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
#define PWR_PDCRC_PC10_Pos (10U)
#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
#define PWR_PDCRC_PC9_Pos (9U)
#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
#define PWR_PDCRC_PC8_Pos (8U)
#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
#define PWR_PDCRC_PC7_Pos (7U)
#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
#define PWR_PDCRC_PC6_Pos (6U)
#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
#define PWR_PDCRC_PC5_Pos (5U)
#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
#define PWR_PDCRC_PC4_Pos (4U)
#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
#define PWR_PDCRC_PC3_Pos (3U)
#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
#define PWR_PDCRC_PC2_Pos (2U)
#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
#define PWR_PDCRC_PC1_Pos (1U)
#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
#define PWR_PDCRC_PC0_Pos (0U)
#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
/******************** Bit definition for PWR_PUCRD register ********************/
#define PWR_PUCRD_PD15_Pos (15U)
#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
#define PWR_PUCRD_PD14_Pos (14U)
#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
#define PWR_PUCRD_PD13_Pos (13U)
#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
#define PWR_PUCRD_PD12_Pos (12U)
#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
#define PWR_PUCRD_PD11_Pos (11U)
#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
#define PWR_PUCRD_PD10_Pos (10U)
#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
#define PWR_PUCRD_PD9_Pos (9U)
#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
#define PWR_PUCRD_PD8_Pos (8U)
#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
#define PWR_PUCRD_PD7_Pos (7U)
#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
#define PWR_PUCRD_PD6_Pos (6U)
#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
#define PWR_PUCRD_PD5_Pos (5U)
#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
#define PWR_PUCRD_PD4_Pos (4U)
#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
#define PWR_PUCRD_PD3_Pos (3U)
#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
#define PWR_PUCRD_PD2_Pos (2U)
#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
#define PWR_PUCRD_PD1_Pos (1U)
#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
#define PWR_PUCRD_PD0_Pos (0U)
#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register ********************/
#define PWR_PDCRD_PD15_Pos (15U)
#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
#define PWR_PDCRD_PD14_Pos (14U)
#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
#define PWR_PDCRD_PD13_Pos (13U)
#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
#define PWR_PDCRD_PD12_Pos (12U)
#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
#define PWR_PDCRD_PD11_Pos (11U)
#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
#define PWR_PDCRD_PD10_Pos (10U)
#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
#define PWR_PDCRD_PD9_Pos (9U)
#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
#define PWR_PDCRD_PD8_Pos (8U)
#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
#define PWR_PDCRD_PD7_Pos (7U)
#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
#define PWR_PDCRD_PD6_Pos (6U)
#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
#define PWR_PDCRD_PD5_Pos (5U)
#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
#define PWR_PDCRD_PD4_Pos (4U)
#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
#define PWR_PDCRD_PD3_Pos (3U)
#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
#define PWR_PDCRD_PD2_Pos (2U)
#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
#define PWR_PDCRD_PD1_Pos (1U)
#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
/******************** Bit definition for PWR_PUCRE register ********************/
#define PWR_PUCRE_PE15_Pos (15U)
#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
#define PWR_PUCRE_PE14_Pos (14U)
#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
#define PWR_PUCRE_PE13_Pos (13U)
#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
#define PWR_PUCRE_PE12_Pos (12U)
#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
#define PWR_PUCRE_PE11_Pos (11U)
#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
#define PWR_PUCRE_PE10_Pos (10U)
#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
#define PWR_PUCRE_PE9_Pos (9U)
#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
#define PWR_PUCRE_PE8_Pos (8U)
#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
#define PWR_PUCRE_PE7_Pos (7U)
#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
#define PWR_PUCRE_PE6_Pos (6U)
#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
#define PWR_PUCRE_PE5_Pos (5U)
#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
#define PWR_PUCRE_PE4_Pos (4U)
#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
#define PWR_PUCRE_PE3_Pos (3U)
#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
#define PWR_PUCRE_PE2_Pos (2U)
#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
#define PWR_PUCRE_PE1_Pos (1U)
#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
#define PWR_PUCRE_PE0_Pos (0U)
#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
/******************** Bit definition for PWR_PDCRE register ********************/
#define PWR_PDCRE_PE15_Pos (15U)
#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
#define PWR_PDCRE_PE14_Pos (14U)
#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
#define PWR_PDCRE_PE13_Pos (13U)
#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
#define PWR_PDCRE_PE12_Pos (12U)
#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
#define PWR_PDCRE_PE11_Pos (11U)
#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
#define PWR_PDCRE_PE10_Pos (10U)
#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
#define PWR_PDCRE_PE9_Pos (9U)
#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
#define PWR_PDCRE_PE8_Pos (8U)
#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
#define PWR_PDCRE_PE7_Pos (7U)
#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
#define PWR_PDCRE_PE6_Pos (6U)
#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
#define PWR_PDCRE_PE5_Pos (5U)
#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
#define PWR_PDCRE_PE4_Pos (4U)
#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
#define PWR_PDCRE_PE3_Pos (3U)
#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
#define PWR_PDCRE_PE2_Pos (2U)
#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
#define PWR_PDCRE_PE1_Pos (1U)
#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
#define PWR_PDCRE_PE0_Pos (0U)
#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
/******************** Bit definition for PWR_PUCRF register ********************/
#define PWR_PUCRF_PF15_Pos (15U)
#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
#define PWR_PUCRF_PF14_Pos (14U)
#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
#define PWR_PUCRF_PF13_Pos (13U)
#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
#define PWR_PUCRF_PF12_Pos (12U)
#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
#define PWR_PUCRF_PF11_Pos (11U)
#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
#define PWR_PUCRF_PF10_Pos (10U)
#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
#define PWR_PUCRF_PF9_Pos (9U)
#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
#define PWR_PUCRF_PF8_Pos (8U)
#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
#define PWR_PUCRF_PF7_Pos (7U)
#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
#define PWR_PUCRF_PF6_Pos (6U)
#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
#define PWR_PUCRF_PF5_Pos (5U)
#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
#define PWR_PUCRF_PF4_Pos (4U)
#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
#define PWR_PUCRF_PF3_Pos (3U)
#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
#define PWR_PUCRF_PF2_Pos (2U)
#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
#define PWR_PUCRF_PF1_Pos (1U)
#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
#define PWR_PUCRF_PF0_Pos (0U)
#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
/******************** Bit definition for PWR_PDCRF register ********************/
#define PWR_PDCRF_PF10_Pos (10U)
#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
#define PWR_PDCRF_PF9_Pos (9U)
#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
#define PWR_PDCRF_PF2_Pos (2U)
#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
#define PWR_PDCRF_PF1_Pos (1U)
#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
#define PWR_PDCRF_PF0_Pos (0U)
#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
/******************** Bit definition for PWR_PUCRG register ********************/
#define PWR_PUCRG_PG10_Pos (10U)
#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
/******************** Bit definition for PWR_PDCRG register ********************/
#define PWR_PDCRG_PG10_Pos (10U)
#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
#define PWR_PDCRG_PG9_Pos (9U)
#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
#define PWR_PDCRG_PG8_Pos (8U)
#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
#define PWR_PDCRG_PG7_Pos (7U)
#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
#define PWR_PDCRG_PG6_Pos (6U)
#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
#define PWR_PDCRG_PG5_Pos (5U)
#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
#define PWR_PDCRG_PG4_Pos (4U)
#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
#define PWR_PDCRG_PG3_Pos (3U)
#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
#define PWR_PDCRG_PG2_Pos (2U)
#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
#define PWR_PDCRG_PG1_Pos (1U)
#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
#define PWR_PDCRG_PG0_Pos (0U)
#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
/******************** Bit definition for PWR_CR5 register ********************/
#define PWR_CR5_R1MODE_Pos (8U)
#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (8U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
#define RCC_CR_HSIKERON_Pos (9U)
#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
#define RCC_CR_HSIRDY_Pos (10U)
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
#define RCC_CR_HSEON_Pos (16U)
#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
#define RCC_CR_PLLON_Pos (24U)
#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (16U)
#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
/*!< MCOSEL configuration */
#define RCC_CFGR_MCOSEL_Pos (24U)
#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
#define RCC_CFGR_MCOPRE_Pos (28U)
#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
/* Legacy aliases */
#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLSRC_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
#define RCC_PLLCFGR_PLLM_Pos (4U)
#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
#define RCC_PLLCFGR_PLLN_Pos (8U)
#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
#define RCC_PLLCFGR_PLLPEN_Pos (16U)
#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
#define RCC_PLLCFGR_PLLP_Pos (17U)
#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
#define RCC_PLLCFGR_PLLQEN_Pos (20U)
#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
#define RCC_PLLCFGR_PLLQ_Pos (21U)
#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
#define RCC_PLLCFGR_PLLREN_Pos (24U)
#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
#define RCC_PLLCFGR_PLLR_Pos (25U)
#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos (3U)
#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos (4U)
#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_PLLRDYIE_Pos (5U)
#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos (9U)
#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos (10U)
#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
/******************** Bit definition for RCC_CIFR register ******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos (3U)
#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos (4U)
#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_PLLRDYF_Pos (5U)
#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
#define RCC_CIFR_CSSF_Pos (8U)
#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
#define RCC_CIFR_LSECSSF_Pos (9U)
#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSI48RDYF_Pos (10U)
#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
/******************** Bit definition for RCC_CICR register ******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos (3U)
#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos (4U)
#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
#define RCC_CICR_PLLRDYC_Pos (5U)
#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
#define RCC_CICR_CSSC_Pos (8U)
#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
#define RCC_CICR_LSECSSC_Pos (9U)
#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSI48RDYC_Pos (10U)
#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
#define RCC_AHB1RSTR_CORDICRST_Pos (3U)
#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
#define RCC_AHB1RSTR_FMACRST_Pos (4U)
#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
#define RCC_AHB1RSTR_CRCRST_Pos (12U)
#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
#define RCC_AHB2RSTR_ADC12RST_Pos (13U)
#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
#define RCC_AHB2RSTR_DAC1RST_Pos (16U)
#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
#define RCC_AHB2RSTR_DAC3RST_Pos (18U)
#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (26U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
/******************** Bit definition for RCC_AHB3RSTR register **************/
/******************** Bit definition for RCC_APB1RSTR1 register **************/
#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
#define RCC_APB1RSTR1_CRSRST_Pos (8U)
#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
#define RCC_APB1RSTR1_USART2RST_Pos (17U)
#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
#define RCC_APB1RSTR1_USART3RST_Pos (18U)
#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
#define RCC_APB1RSTR1_UART4RST_Pos (19U)
#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
#define RCC_APB1RSTR1_USBRST_Pos (23U)
#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
#define RCC_APB1RSTR1_FDCANRST_Pos (25U)
#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
#define RCC_APB1RSTR1_PWRRST_Pos (28U)
#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
#define RCC_APB1RSTR1_I2C3RST_Pos (30U)
#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
#define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_TIM8RST_Pos (13U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define RCC_AHB1ENR_DMA2EN_Pos (1U)
#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
#define RCC_AHB1ENR_CORDICEN_Pos (3U)
#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
#define RCC_AHB1ENR_FMACEN_Pos (4U)
#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
#define RCC_AHB1ENR_FLASHEN_Pos (8U)
#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
#define RCC_AHB1ENR_CRCEN_Pos (12U)
#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
#define RCC_AHB2ENR_GPIODEN_Pos (3U)
#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
#define RCC_AHB2ENR_ADC12EN_Pos (13U)
#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
#define RCC_AHB2ENR_DAC1EN_Pos (16U)
#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
#define RCC_AHB2ENR_DAC3EN_Pos (18U)
#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (26U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
/******************** Bit definition for RCC_AHB3ENR register ***************/
/******************** Bit definition for RCC_APB1ENR1 register ***************/
#define RCC_APB1ENR1_TIM2EN_Pos (0U)
#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
#define RCC_APB1ENR1_TIM3EN_Pos (1U)
#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
#define RCC_APB1ENR1_TIM7EN_Pos (5U)
#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
#define RCC_APB1ENR1_CRSEN_Pos (8U)
#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
#define RCC_APB1ENR1_WWDGEN_Pos (11U)
#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
#define RCC_APB1ENR1_SPI2EN_Pos (14U)
#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
#define RCC_APB1ENR1_SPI3EN_Pos (15U)
#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
#define RCC_APB1ENR1_USART2EN_Pos (17U)
#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
#define RCC_APB1ENR1_USART3EN_Pos (18U)
#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
#define RCC_APB1ENR1_UART4EN_Pos (19U)
#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
#define RCC_APB1ENR1_I2C1EN_Pos (21U)
#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
#define RCC_APB1ENR1_I2C2EN_Pos (22U)
#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
#define RCC_APB1ENR1_USBEN_Pos (23U)
#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
#define RCC_APB1ENR1_FDCANEN_Pos (25U)
#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
#define RCC_APB1ENR1_PWREN_Pos (28U)
#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
#define RCC_APB1ENR1_I2C3EN_Pos (30U)
#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
#define RCC_APB1ENR2_UCPD1EN_Pos (8U)
#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
#define RCC_APB2ENR_TIM1EN_Pos (11U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_TIM8EN_Pos (13U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define RCC_APB2ENR_USART1EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
/******************** Bit definition for RCC_AHB2SMENR register *************/
#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register *************/
/******************** Bit definition for RCC_APB1SMENR1 register *************/
#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
#define RCC_APB1SMENR1_USBSMEN_Pos (23U)
#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
/******************** Bit definition for RCC_APB1SMENR2 register *************/
#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
/******************** Bit definition for RCC_APB2SMENR register *************/
#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
#define RCC_CCIPR_USART2SEL_Pos (2U)
#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
#define RCC_CCIPR_USART3SEL_Pos (4U)
#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
#define RCC_CCIPR_UART4SEL_Pos (6U)
#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR_LPUART1SEL_Pos (10U)
#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
#define RCC_CCIPR_I2C1SEL_Pos (12U)
#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR_I2C2SEL_Pos (14U)
#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR_I2C3SEL_Pos (16U)
#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
#define RCC_CCIPR_SAI1SEL_Pos (20U)
#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
#define RCC_CCIPR_I2S23SEL_Pos (22U)
#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
#define RCC_CCIPR_FDCANSEL_Pos (24U)
#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR_CLK48SEL_Pos (26U)
#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
#define RCC_CCIPR_ADC12SEL_Pos (28U)
#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos (3U)
#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos (5U)
#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos (6U)
#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
#define RCC_BDCR_LSCOEN_Pos (24U)
#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
#define RCC_BDCR_LSCOSEL_Pos (25U)
#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION_Pos (0U)
#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos (1U)
#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
#define RCC_CSR_RMVF_Pos (23U)
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
#define RCC_CSR_OBLRSTF_Pos (25U)
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_BORRSTF_Pos (27U)
#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/******************** Bit definition for RCC_CRRCR register *****************/
#define RCC_CRRCR_HSI48ON_Pos (0U)
#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
#define RCC_CRRCR_HSI48RDY_Pos (1U)
#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos (7U)
#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
/******************** Bit definition for RCC_CCIPR2 register ******************/
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_ICSR register ******************/
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_ALRBWF_Pos (1U)
#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
#define RTC_ICSR_ALRAWF_Pos (0U)
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_SR register *******************/
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
/******************** Bits definition for RTC_MISR register *****************/
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
/******************** Bits definition for RTC_SCR register ******************/
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register *****************/
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos (21U)
#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
/******************** Bits definition for TAMP_CR2 register *****************/
#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
#define TAMP_CR2_TAMP1MF_Pos (16U)
#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
#define TAMP_CR2_TAMP2MF_Pos (17U)
#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
#define TAMP_CR2_TAMP3MF_Pos (18U)
#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_IER register *****************/
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos (21U)
#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
/******************** Bits definition for TAMP_SR register ******************/
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos (21U)
#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
/******************** Bits definition for TAMP_MISR register ****************/
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos (21U)
#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
/******************** Bits definition for TAMP_SCR register *****************/
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos (21U)
#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
/******************** Bits definition for TAMP_BKP1R register ***************/
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
/******************** Bits definition for TAMP_BKP2R register ***************/
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
/******************** Bits definition for TAMP_BKP3R register ***************/
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
/******************** Bits definition for TAMP_BKP4R register ***************/
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************** Bits definition for TAMP_BKP5R register ***************/
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
/******************** Bits definition for TAMP_BKP6R register ***************/
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
/******************** Bits definition for TAMP_BKP7R register ***************/
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
/******************** Bits definition for TAMP_BKP8R register ***************/
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
/******************** Bits definition for TAMP_BKP9R register ***************/
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
/******************** Bits definition for TAMP_BKP10R register ***************/
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
/******************** Bits definition for TAMP_BKP11R register ***************/
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
/******************** Bits definition for TAMP_BKP12R register ***************/
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
/******************** Bits definition for TAMP_BKP13R register ***************/
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
/******************** Bits definition for TAMP_BKP14R register ***************/
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
/******************** Bits definition for TAMP_BKP15R register ***************/
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/****************** Bit definition for SAI_PDMCR register *******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
#define SPI_CR1_CPOL_Pos (1U)
#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
#define SPI_CR1_MSTR_Pos (2U)
#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
#define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
#define SPI_CR1_LSBFIRST_Pos (7U)
#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
#define SPI_CR1_SSI_Pos (8U)
#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
#define SPI_CR1_SSM_Pos (9U)
#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
#define SPI_CR1_RXONLY_Pos (10U)
#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
#define SPI_CR1_CRCL_Pos (11U)
#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
#define SPI_CR1_CRCNEXT_Pos (12U)
#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
#define SPI_CR1_CRCEN_Pos (13U)
#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE_Pos (14U)
#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos (15U)
#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN_Pos (0U)
#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN_Pos (1U)
#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
#define SPI_CR2_SSOE_Pos (2U)
#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
#define SPI_CR2_NSSP_Pos (3U)
#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
#define SPI_CR2_FRF_Pos (4U)
#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
#define SPI_CR2_ERRIE_Pos (5U)
#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE_Pos (6U)
#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE_Pos (7U)
#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
#define SPI_CR2_LDMARX_Pos (13U)
#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
#define SPI_CR2_LDMATX_Pos (14U)
#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE_Pos (0U)
#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
#define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
#define SPI_SR_MODF_Pos (5U)
#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
#define SPI_SR_BSY_Pos (7U)
#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
#define SPI_SR_FRE_Pos (8U)
#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
#define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U)
#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY_Pos (0U)
#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC_Pos (0U)
#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC_Pos (0U)
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN_Pos (0U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN_Pos (1U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_CKPOL_Pos (3U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_I2SE_Pos (10U)
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD_Pos (8U)
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE_Pos (9U)
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
/****************** Bit definition for SYSCFG_CFGR1 register ******************/
#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
/****************** Bit definition for SYSCFG_SCSR register ****************/
#define SYSCFG_SCSR_CCMER_Pos (0U)
#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
#define SYSCFG_SCSR_CCMBSY_Pos (1U)
#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
/****************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_CLL_Pos (0U)
#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
#define SYSCFG_CFGR2_SPL_Pos (1U)
#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
#define SYSCFG_CFGR2_PVDL_Pos (2U)
#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
#define SYSCFG_CFGR2_ECCL_Pos (3U)
#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
#define SYSCFG_CFGR2_SPF_Pos (8U)
#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
#define TIM_CR1_CMS_Pos (5U)
#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos (7U)
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos (8U)
#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos (12U)
#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos (15U)
#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos (3U)
#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE_Pos (0U)
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos (1U)
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos (2U)
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos (3U)
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos (4U)
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos (5U)
#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos (6U)
#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos (7U)
#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos (8U)
#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos (9U)
#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos (10U)
#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos (11U)
#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos (12U)
#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos (13U)
#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos (14U)
#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos (20U)
#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos (21U)
#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos (20U)
#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
#define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos (21U)
#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
#define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos (22U)
#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
#define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos (23U)
#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
#define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG_Pos (0U)
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos (6U)
#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
#define TIM_EGR_BG_Pos (7U)
#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
#define TIM_EGR_B2G_Pos (8U)
#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos (4U)
#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos (12U)
#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA_Pos (0U)
#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos (8U)
#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
/******************* Bit definition for TIM1_AF1 register *******************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
#define TIM1_AF1_BKCMP1E_Pos (1U)
#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
#define TIM1_AF1_BKCMP2E_Pos (2U)
#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
#define TIM1_AF1_BKCMP3E_Pos (3U)
#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
#define TIM1_AF1_BKCMP4E_Pos (4U)
#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
#define TIM1_AF1_BKCMP1P_Pos (10U)
#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
#define TIM1_AF1_BKCMP2P_Pos (11U)
#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
#define TIM1_AF1_BKCMP3P_Pos (12U)
#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
#define TIM1_AF1_BKCMP4P_Pos (13U)
#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
#define TIM1_AF1_ETRSEL_Pos (14U)
#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
#define TIM1_AF2_BK2CMP1E_Pos (1U)
#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
#define TIM1_AF2_BK2CMP2E_Pos (2U)
#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
#define TIM1_AF2_BK2CMP3E_Pos (3U)
#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
#define TIM1_AF2_BK2CMP4E_Pos (4U)
#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
#define TIM1_AF2_BK2CMP1P_Pos (10U)
#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
#define TIM1_AF2_BK2CMP2P_Pos (11U)
#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_BK2CMP3P_Pos (12U)
#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
#define TIM1_AF2_BK2CMP4P_Pos (13U)
#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
#define TIM1_AF2_OCRSEL_Pos (16U)
#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_HSE32EN_Pos (0U)
#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM_DTR2 register *********************/
#define TIM_DTR2_DTGF_Pos (0U)
#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos (16U)
#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos (17U)
#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
/******************* Bit definition for TIM_ECR register *********************/
#define TIM_ECR_IE_Pos (0U)
#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
#define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
#define TIM_ECR_IDIR_Pos (1U)
#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_FIDX_Pos (5U)
#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
#define TIM_ECR_IPOS_Pos (6U)
#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
#define TIM_ECR_PW_Pos (16U)
#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
#define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos (24U)
#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB_Pos (0U)
#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_OR register *******************/
#define LPTIM_OR_IN1_Pos (0U)
#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
#define LPTIM_OR_IN2_Pos (1U)
#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART_Pos (0U)
#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR_Pos (0U)
#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */
#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
/******************* Bit definition for VREFBUF_CCR register ******************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* USB Device FS Endpoint registers */
/* */
/******************************************************************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
/* bit positions */
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
/* */
/* USB Device FS General registers */
/* */
/******************************************************************************/
#define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
#define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
#define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
#define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
#define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
#define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
/****************** Bits definition for USB_CNTR register *******************/
#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/****************** Bits definition for USB_ISTR register *******************/
#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
/****************** Bits definition for USB_FNR register ********************/
#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
/****************** Bits definition for USB_DADDR register ****************/
#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
#define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
#define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
#define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
#define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
#define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
#define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
#define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
#define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
/****************** Bit definition for USB_BTABLE register ******************/
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
/****************** Bits definition for USB_BCDR register *******************/
#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
/******************* Bit definition for LPMCSR register *********************/
#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
/*!< Buffer descriptor table */
/***************** Bit definition for USB_ADDR0_TX register *****************/
#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_TX register *****************/
#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_TX register *****************/
#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_TX register *****************/
#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_TX register *****************/
#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_TX register *****************/
#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_TX register *****************/
#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_TX register *****************/
#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_TX register ****************/
#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
/***************** Bit definition for USB_COUNT1_TX register ****************/
#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
/***************** Bit definition for USB_COUNT2_TX register ****************/
#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
/***************** Bit definition for USB_COUNT3_TX register ****************/
#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
/***************** Bit definition for USB_COUNT4_TX register ****************/
#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
/***************** Bit definition for USB_COUNT5_TX register ****************/
#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
/***************** Bit definition for USB_COUNT6_TX register ****************/
#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
/***************** Bit definition for USB_COUNT7_TX register ****************/
#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_ADDR0_RX register *****************/
#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_RX register *****************/
#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_RX register *****************/
#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_RX register *****************/
#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_RX register *****************/
#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_RX register *****************/
#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_RX register *****************/
#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_RX register *****************/
#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_RX register ****************/
#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT0_RX_BLSIZE_Pos (15U)
#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT1_RX register ****************/
#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT1_RX_BLSIZE_Pos (15U)
#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT2_RX register ****************/
#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT2_RX_BLSIZE_Pos (15U)
#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT3_RX register ****************/
#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT3_RX_BLSIZE_Pos (15U)
#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT4_RX register ****************/
#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT4_RX_BLSIZE_Pos (15U)
#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT5_RX register ****************/
#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT5_RX_BLSIZE_Pos (15U)
#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT6_RX register ****************/
#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT6_RX_BLSIZE_Pos (15U)
#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT7_RX register ****************/
#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT7_RX_BLSIZE_Pos (15U)
#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
/* UCPD */
/* */
/******************************************************************************/
/******************** Bits definition for UCPD_CFG1 register *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos (6U)
#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos (11U)
#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos (20U)
#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos (29U)
#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define UCPD_CFG1_RXDMAEN_Pos (30U)
#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define UCPD_CFG1_UCPDEN_Pos (31U)
#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
/******************** Bits definition for UCPD_CFG2 register *******************/
#define UCPD_CFG2_RXFILTDIS_Pos (0U)
#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos (1U)
#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos (2U)
#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos (3U)
#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
/******************** Bits definition for UCPD_CR register ********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos (2U)
#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXHRST_Pos (3U)
#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
#define UCPD_CR_RXMODE_Pos (4U)
#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
#define UCPD_CR_PHYRXEN_Pos (5U)
#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
#define UCPD_CR_PHYCCSEL_Pos (6U)
#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
#define UCPD_CR_ANASUBMODE_Pos (7U)
#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos (9U)
#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
#define UCPD_CR_CCENABLE_Pos (10U)
#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
#define UCPD_CR_FRSRXEN_Pos (16U)
#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
#define UCPD_CR_FRSTX_Pos (17U)
#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos (18U)
#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
#define UCPD_CR_CC1TCDIS_Pos (20U)
#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos (21U)
#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
/******************** Bits definition for UCPD_IMR register *******************/
#define UCPD_IMR_TXISIE_Pos (0U)
#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
#define UCPD_IMR_TXMSGABTIE_Pos (3U)
#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
#define UCPD_IMR_HRSTDISCIE_Pos (4U)
#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
#define UCPD_IMR_HRSTSENTIE_Pos (5U)
#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
#define UCPD_IMR_TXUNDIE_Pos (6U)
#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
#define UCPD_IMR_RXNEIE_Pos (8U)
#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
#define UCPD_IMR_RXORDDETIE_Pos (9U)
#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
#define UCPD_IMR_RXOVRIE_Pos (11U)
#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
#define UCPD_IMR_RXMSGENDIE_Pos (12U)
#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
#define UCPD_IMR_FRSEVTIE_Pos (20U)
#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
/******************** Bits definition for UCPD_SR register ********************/
#define UCPD_SR_TXIS_Pos (0U)
#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
#define UCPD_SR_TXMSGDISC_Pos (1U)
#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
#define UCPD_SR_TXMSGSENT_Pos (2U)
#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
#define UCPD_SR_TXMSGABT_Pos (3U)
#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
#define UCPD_SR_HRSTDISC_Pos (4U)
#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
#define UCPD_SR_HRSTSENT_Pos (5U)
#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
#define UCPD_SR_TXUND_Pos (6U)
#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
#define UCPD_SR_RXNE_Pos (8U)
#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
#define UCPD_SR_RXORDDET_Pos (9U)
#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
#define UCPD_SR_RXHRSTDET_Pos (10U)
#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
#define UCPD_SR_RXOVR_Pos (11U)
#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
#define UCPD_SR_RXMSGEND_Pos (12U)
#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
#define UCPD_SR_RXERR_Pos (13U)
#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos (14U)
#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
#define UCPD_SR_TYPECEVT2_Pos (15U)
#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
#define UCPD_SR_FRSEVT_Pos (20U)
#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
/******************** Bits definition for UCPD_ICR register *******************/
#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
#define UCPD_ICR_TXMSGABTCF_Pos (3U)
#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
#define UCPD_ICR_HRSTDISCCF_Pos (4U)
#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
#define UCPD_ICR_HRSTSENTCF_Pos (5U)
#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
#define UCPD_ICR_TXUNDCF_Pos (6U)
#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
#define UCPD_ICR_RXORDDETCF_Pos (9U)
#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
#define UCPD_ICR_RXOVRCF_Pos (11U)
#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
#define UCPD_ICR_RXMSGENDCF_Pos (12U)
#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
#define UCPD_ICR_FRSEVTCF_Pos (20U)
#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
/******************** Bits definition for UCPD_TXORDSET register **************/
#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
/******************** Bits definition for UCPD_TXPAYSZ register ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
/******************** Bits definition for UCPD_TXDR register *******************/
#define UCPD_TXDR_TXDATA_Pos (0U)
#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
/******************** Bits definition for UCPD_RXORDSET register **************/
#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
/******************** Bits definition for UCPD_RXPAYSZ register ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
/******************** Bits definition for UCPD_RXDR register *******************/
#define UCPD_RXDR_RXDATA_Pos (0U)
#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/******************** Bits definition for UCPD_RXORDEXT1 register **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
/******************** Bits definition for UCPD_RXORDEXT2 register **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
/******************************** FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2) || \
((INSTANCE) == COMP3) || \
((INSTANCE) == COMP4))
/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC3))
/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA2_Channel1) || \
((INSTANCE) == DMA2_Channel2) || \
((INSTANCE) == DMA2_Channel3) || \
((INSTANCE) == DMA2_Channel4) || \
((INSTANCE) == DMA2_Channel5) || \
((INSTANCE) == DMA2_Channel6))
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
/******************************* FMAC Instances *******************************/
#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances *****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3))
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3))
/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3))
/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
((__INSTANCE__) == SPI3))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4))
/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4))
/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4))
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4))
/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** UCPD Instances ********************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
/******************************* USB Instances *******************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/**
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32G4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32G4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
#define TIM7_DAC_IRQn TIM7_IRQn
#define COMP4_5_6_IRQn COMP4_IRQn
/* Aliases for __IRQHandler */
#define TIM7_DAC_IRQHandler TIM7_IRQHandler
#define COMP4_5_6_IRQHandler COMP4_IRQHandler
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32G431xx_H */
/**
* @}
*/
/**
* @}
*/
| 989,958 | C | 74.339346 | 180 | 0.511839 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g441xx.h | /**
******************************************************************************
* @file stm32g441xx.h
* @author MCD Application Team
* @brief CMSIS STM32G441xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32g441xx
* @{
*/
#ifndef __STM32G441xx_H
#define __STM32G441xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32G4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ***************************************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_IRQn = 19, /*!< USB HP Interrupt */
USB_LP_IRQn = 20, /*!< USB LP Interrupt */
FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupts */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
COMP4_IRQn = 65, /*!< COMP4 */
CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
AES_IRQn = 85, /*!< AES global interrupt */
RNG_IRQn = 90, /*!< RNG global interrupt */
LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
FMAC_IRQn = 101 /*!< FMAC global Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32g4xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
__IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
} FDCAN_Config_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
__IO uint32_t RESERVED[2];
__IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
__IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
__IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
__IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
__IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
__IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
__IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */
__IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
} FLASH_TypeDef;
/**
* @brief FMAC
*/
typedef struct
{
__IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
__IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
__IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
__IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
} FMAC_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
} OPAMP_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
__IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
/*
* @brief Specific device feature definitions
*/
#define RTC_TAMP_INT_6_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 3u
#define RTC_BACKUP_NB 16u
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
} RTC_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
} TAMP_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
__IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
__IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
__IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
__IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
__IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
__IO uint16_t RESERVEDD; /*!< Reserved */
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
__IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief AES hardware accelerator
*/
typedef struct
{
__IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
__IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
__IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
__IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
__IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
__IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
__IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
__IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
__IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
__IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
__IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
__IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
__IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
__IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
__IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
__IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
__IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
__IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
__IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
__IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
__IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
__IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
__IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
} AES_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief CORDIC
*/
typedef struct
{
__IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
__IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
__IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
} CORDIC_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 128 kB) base address */
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 16 KB) base address */
#define SRAM2_BASE (0x20004000UL) /*!< SRAM2(6 KB) base address */
#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(10 KB) base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(16 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (0x22080000UL) /*!< SRAM2(6 KB) base address in the bit-band region */
#define CCMSRAM_BB_BASE (0x220B0000UL) /*!< CCMSRAM(10 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
#define SRAM1_SIZE_MAX (0x00004000UL) /*!< maximum SRAM1 size (up to 16 KBytes) */
#define SRAM2_SIZE (0x00001800UL) /*!< SRAM2 size (6 KBytes) */
#define CCMSRAM_SIZE (0x00002800UL) /*!< CCMSRAM size (10 KBytes) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
/*!< AHB1 peripherals */
#define DMA1_BASE (AHB1PERIPH_BASE)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0020UL)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x0024UL)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0028UL)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x002CUL)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0030UL)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x0034UL)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
/*!< AHB2 peripherals */
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL)
#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0042000UL)
#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
#define AES ((AES_TypeDef *) AES_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos (15U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
#define ADC_CFGR2_GCOMP_Pos (16U)
#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
#define ADC_CFGR2_SWTRIG_Pos (25U)
#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
#define ADC_CFGR2_BULB_Pos (26U)
#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
#define ADC_CFGR2_SMPTRIG_Pos (27U)
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_AWDFILT_Pos (12U)
#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSETPOS_Pos (24U)
#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
#define ADC_OFR1_SATEN_Pos (25U)
#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSETPOS_Pos (24U)
#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
#define ADC_OFR2_SATEN_Pos (25U)
#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSETPOS_Pos (24U)
#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
#define ADC_OFR3_SATEN_Pos (25U)
#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSETPOS_Pos (24U)
#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
#define ADC_OFR4_SATEN_Pos (25U)
#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
/******************** Bit definition for ADC_GCOMP register *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos (13U)
#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
#define ADC_CCR_MDMA_Pos (14U)
#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_VSENSESEL_Pos (23U)
#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATSEL_Pos (24U)
#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
/******************************************************************************/
/* */
/* Advanced Encryption Standard (AES) */
/* */
/******************************************************************************/
/******************* Bit definition for AES_CR register *********************/
#define AES_CR_EN_Pos (0U)
#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
#define AES_CR_DATATYPE_Pos (1U)
#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
#define AES_CR_MODE_Pos (3U)
#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
#define AES_CR_CHMOD_Pos (5U)
#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
#define AES_CR_CCFC_Pos (7U)
#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
#define AES_CR_ERRC_Pos (8U)
#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
#define AES_CR_CCFIE_Pos (9U)
#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
#define AES_CR_ERRIE_Pos (10U)
#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
#define AES_CR_DMAINEN_Pos (11U)
#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
#define AES_CR_DMAOUTEN_Pos (12U)
#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
#define AES_CR_GCMPH_Pos (13U)
#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
#define AES_CR_KEYSIZE_Pos (18U)
#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
#define AES_CR_NPBLB_Pos (20U)
#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */
#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */
#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */
#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */
#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */
#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */
/******************* Bit definition for AES_SR register *********************/
#define AES_SR_CCF_Pos (0U)
#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
#define AES_SR_RDERR_Pos (1U)
#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
#define AES_SR_WRERR_Pos (2U)
#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
#define AES_SR_BUSY_Pos (3U)
#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */
#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
/******************* Bit definition for AES_DINR register *******************/
#define AES_DINR_Pos (0U)
#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */
#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
/******************* Bit definition for AES_DOUTR register ******************/
#define AES_DOUTR_Pos (0U)
#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
/******************* Bit definition for AES_KEYR0 register ******************/
#define AES_KEYR0_Pos (0U)
#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
/******************* Bit definition for AES_KEYR1 register ******************/
#define AES_KEYR1_Pos (0U)
#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
/******************* Bit definition for AES_KEYR2 register ******************/
#define AES_KEYR2_Pos (0U)
#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
/******************* Bit definition for AES_KEYR3 register ******************/
#define AES_KEYR3_Pos (0U)
#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
/******************* Bit definition for AES_KEYR4 register ******************/
#define AES_KEYR4_Pos (0U)
#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
/******************* Bit definition for AES_KEYR5 register ******************/
#define AES_KEYR5_Pos (0U)
#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
/******************* Bit definition for AES_KEYR6 register ******************/
#define AES_KEYR6_Pos (0U)
#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
/******************* Bit definition for AES_KEYR7 register ******************/
#define AES_KEYR7_Pos (0U)
#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
/******************* Bit definition for AES_IVR0 register ******************/
#define AES_IVR0_Pos (0U)
#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
/******************* Bit definition for AES_IVR1 register ******************/
#define AES_IVR1_Pos (0U)
#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
/******************* Bit definition for AES_IVR2 register ******************/
#define AES_IVR2_Pos (0U)
#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
/******************* Bit definition for AES_IVR3 register ******************/
#define AES_IVR3_Pos (0U)
#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
/******************* Bit definition for AES_SUSP0R register ******************/
#define AES_SUSP0R_Pos (0U)
#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
/******************* Bit definition for AES_SUSP1R register ******************/
#define AES_SUSP1R_Pos (0U)
#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
/******************* Bit definition for AES_SUSP2R register ******************/
#define AES_SUSP2R_Pos (0U)
#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
/******************* Bit definition for AES_SUSP3R register ******************/
#define AES_SUSP3R_Pos (0U)
#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
/******************* Bit definition for AES_SUSP4R register ******************/
#define AES_SUSP4R_Pos (0U)
#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
/******************* Bit definition for AES_SUSP5R register ******************/
#define AES_SUSP5R_Pos (0U)
#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
/******************* Bit definition for AES_SUSP6R register ******************/
#define AES_SUSP6R_Pos (0U)
#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
/******************* Bit definition for AES_SUSP7R register ******************/
#define AES_SUSP7R_Pos (0U)
#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_INMSEL_Pos (4U)
#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_Pos (8U)
#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
#define COMP_CSR_BLANKING_Pos (19U)
#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
/* CORDIC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CORDIC_CSR register *****************/
#define CORDIC_CSR_FUNC_Pos (0U)
#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos (4U)
#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos (8U)
#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos (16U)
#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos (17U)
#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos (18U)
#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos (19U)
#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos (20U)
#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos (21U)
#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos (22U)
#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos (31U)
#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
/******************* Bit definition for CORDIC_WDATA register ***************/
#define CORDIC_WDATA_ARG_Pos (0U)
#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
/******************* Bit definition for CORDIC_RDATA register ***************/
#define CORDIC_RDATA_RES_Pos (0U)
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_Pos (16U)
#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
#define DAC_DOR2_DACC2DORB_Pos (16U)
#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DAC1RDY_Pos (11U)
#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
#define DAC_SR_DORSTAT1_Pos (12U)
#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
#define DAC_SR_DORSTAT2_Pos (28U)
#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos (8U)
#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos (9U)
#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
#define DAC_MCR_HFSEL_Pos (14U)
#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
#define DAC_MCR_DMADOUBLE2_Pos (24U)
#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
#define DAC_MCR_SINFORMAT2_Pos (25U)
#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR2_TSAMPLE2_Pos (0U)
#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/****************** Bit definition for DAC_STR1 register ******************/
#define DAC_STR1_STRSTDATA1_Pos (0U)
#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
#define DAC_STR1_STDIR1_Pos (12U)
#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
#define DAC_STR1_STINCDATA1_Pos (16U)
#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STR2 register ******************/
#define DAC_STR2_STRSTDATA2_Pos (0U)
#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
#define DAC_STR2_STDIR2_Pos (12U)
#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
#define DAC_STR2_STINCDATA2_Pos (16U)
#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STMODR register ****************/
#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
#define DBGMCU_CR_TRACE_MODE_Pos (6U)
#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register ****************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
/******************** Bits definition for DMAMUX_CFR register ****************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
/******************** Bits definition for DMAMUX_RGCFR register ************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x7FFFFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
/****************** Bit definition for EXTI_RTSR1 register ******************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT19_Pos (19U)
#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR1_RT22_Pos (22U)
#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR1_RT29_Pos (29U)
#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR1_RT30_Pos (30U)
#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_FT16_Pos (16U)
#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_FT17_Pos (17U)
#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_FT19_Pos (19U)
#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR1_FT22_Pos (22U)
#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR1_FT29_Pos (29U)
#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR1_FT30_Pos (30U)
#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos (16U)
#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos (17U)
#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI19_Pos (19U)
#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos (22U)
#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER1_SWI29_Pos (29U)
#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER1_SWI30_Pos (30U)
#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
/******************* Bit definition for EXTI_PR1 register *******************/
#define EXTI_PR1_PIF0_Pos (0U)
#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PIF1_Pos (1U)
#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PIF2_Pos (2U)
#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PIF3_Pos (3U)
#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PIF4_Pos (4U)
#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PIF5_Pos (5U)
#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PIF6_Pos (6U)
#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PIF7_Pos (7U)
#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PIF8_Pos (8U)
#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PIF9_Pos (9U)
#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PIF10_Pos (10U)
#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PIF11_Pos (11U)
#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PIF12_Pos (12U)
#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PIF13_Pos (13U)
#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PIF14_Pos (14U)
#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PIF15_Pos (15U)
#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PIF16_Pos (16U)
#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PIF17_Pos (17U)
#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR1_PIF19_Pos (19U)
#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PIF20_Pos (20U)
#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PIF21_Pos (21U)
#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR1_PIF22_Pos (22U)
#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR1_PIF29_Pos (29U)
#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR1_PIF30_Pos (30U)
#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x3F4UL << EXTI_IMR2_IM_Pos) /*!< 0x000003F4 */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x3F4UL << EXTI_EMR2_EM_Pos) /*!< 0x000003F4 */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT38_Pos (6U)
#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
#define EXTI_RTSR2_RT39_Pos (7U)
#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
#define EXTI_RTSR2_RT40_Pos (8U)
#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
#define EXTI_RTSR2_RT41_Pos (9U)
#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_FT38_Pos (6U)
#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
#define EXTI_FTSR2_FT39_Pos (7U)
#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
#define EXTI_FTSR2_FT40_Pos (8U)
#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
#define EXTI_FTSR2_FT41_Pos (9U)
#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI38_Pos (6U)
#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
#define EXTI_SWIER2_SWI39_Pos (7U)
#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
#define EXTI_SWIER2_SWI40_Pos (8U)
#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
#define EXTI_SWIER2_SWI41_Pos (9U)
#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PIF38_Pos (6U)
#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
#define EXTI_PR2_PIF39_Pos (7U)
#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
#define EXTI_PR2_PIF40_Pos (8U)
#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
#define EXTI_PR2_PIF41_Pos (9U)
#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0F_Pos (1U)
#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (2U)
#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (3U)
#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1F_Pos (4U)
#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (5U)
#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (6U)
#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (7U)
#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (8U)
#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (9U)
#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (10U)
#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFF_Pos (11U)
#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (12U)
#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (13U)
#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (14U)
#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (15U)
#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_ELO_Pos (16U)
#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (17U)
#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (18U)
#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (19U)
#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (20U)
#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (21U)
#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (22U)
#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (23U)
#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0FE_Pos (1U)
#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (2U)
#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (3U)
#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1FE_Pos (4U)
#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (5U)
#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (6U)
#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (7U)
#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (8U)
#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos (9U)
#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (10U)
#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFFE_Pos (11U)
#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (12U)
#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (13U)
#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (14U)
#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (15U)
#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_ELOE_Pos (16U)
#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (17U)
#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (18U)
#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (19U)
#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (20U)
#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (21U)
#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos (22U)
#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (23U)
#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RXFIFO0_Pos (0U)
#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
Rx FIFO 0 is Full
Rx FIFO 0 Has New Message */
#define FDCAN_ILS_RXFIFO1_Pos (1U)
#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
Rx FIFO 1 is Full
Rx FIFO 1 Has New Message */
#define FDCAN_ILS_SMSG_Pos (2U)
#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
Transmission Completed
High Priority Message */
#define FDCAN_ILS_TFERR_Pos (3U)
#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
Tx Event FIFO Full
Tx Event FIFO New Entry
Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_MISC_Pos (4U)
#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
Message RAM Access Failure
Timestamp Wraparound */
#define FDCAN_ILS_BERR_Pos (5U)
#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
Error Logging Overflow */
#define FDCAN_ILS_PERR_Pos (6U)
#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
Protocol Error in Data Phase Line
Protocol Error in Arbitration Phase Line
Watchdog Interrupt Line
Bus_Off Status
Warning Status */
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_RXGFC register ********************/
#define FDCAN_RXGFC_RRFE_Pos (0U)
#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_RXGFC_RRFS_Pos (1U)
#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_RXGFC_ANFE_Pos (2U)
#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_RXGFC_ANFS_Pos (4U)
#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
#define FDCAN_RXGFC_F1OM_Pos (8U)
#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
#define FDCAN_RXGFC_F0OM_Pos (9U)
#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
#define FDCAN_RXGFC_LSS_Pos (16U)
#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
#define FDCAN_RXGFC_LSE_Pos (24U)
#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TFQM_Pos (24U)
#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CFIE_Pos (0U)
#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/*!<FDCAN config registers */
/***************** Bit definition for FDCAN_CKDIV register *********************/
#define FDCAN_CKDIV_PDIV_Pos (0U)
#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS (0x00000000U)
#define FLASH_ACR_LATENCY_1WS (0x00000001U)
#define FLASH_ACR_LATENCY_2WS (0x00000002U)
#define FLASH_ACR_LATENCY_3WS (0x00000003U)
#define FLASH_ACR_LATENCY_4WS (0x00000004U)
#define FLASH_ACR_LATENCY_5WS (0x00000005U)
#define FLASH_ACR_LATENCY_6WS (0x00000006U)
#define FLASH_ACR_LATENCY_7WS (0x00000007U)
#define FLASH_ACR_LATENCY_8WS (0x00000008U)
#define FLASH_ACR_LATENCY_9WS (0x00000009U)
#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_RUN_PD_Pos (13U)
#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
#define FLASH_ACR_SLEEP_PD_Pos (14U)
#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
#define FLASH_ACR_DBG_SWEN_Pos (18U)
#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_OPERR_Pos (1U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_PROGERR_Pos (3U)
#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_SIZERR_Pos (6U)
#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_MISERR_Pos (8U)
#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
#define FLASH_SR_FASTERR_Pos (9U)
#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
#define FLASH_SR_RDERR_Pos (14U)
#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_OPTVERR_Pos (15U)
#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PER_Pos (1U)
#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
#define FLASH_CR_PER FLASH_CR_PER_Msk
#define FLASH_CR_MER1_Pos (2U)
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
#define FLASH_CR_PNB_Msk (0x3FUL << FLASH_CR_PNB_Pos) /*!< 0x000001F8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_OPTSTRT_Pos (17U)
#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
#define FLASH_CR_FSTPG_Pos (18U)
#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_RDERRIE_Pos (26U)
#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
#define FLASH_CR_SEC_PROT1_Pos (28U)
#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
#define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_ECCR register ***************/
#define FLASH_ECCR_ADDR_ECC_Pos (0U)
#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0003FFFF */
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
#define FLASH_ECCR_SYSF_ECC_Pos (22U)
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
#define FLASH_ECCR_ECCIE_Pos (24U)
#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
#define FLASH_ECCR_ECCC_Pos (30U)
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
#define FLASH_ECCR_ECCD_Pos (31U)
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
/******************* Bits definition for FLASH_OPTR register ***************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
#define FLASH_OPTR_BOR_LEV_Pos (8U)
#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
#define FLASH_OPTR_nRST_STOP_Pos (12U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
#define FLASH_OPTR_nRST_STDBY_Pos (13U)
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
#define FLASH_OPTR_WWDG_SW_Pos (19U)
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
#define FLASH_OPTR_nBOOT1_Pos (23U)
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
#define FLASH_OPTR_SRAM_PE_Pos (24U)
#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
#define FLASH_OPTR_nSWBOOT0_Pos (26U)
#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
#define FLASH_OPTR_nBOOT0_Pos (27U)
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
#define FLASH_OPTR_NRST_MODE_Pos (28U)
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
#define FLASH_OPTR_IRHEN_Pos (30U)
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
/****************** Bits definition for FLASH_PCROP1SR register **********/
#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x3FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00003FFF */
#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
/****************** Bits definition for FLASH_PCROP1ER register ***********/
#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
#define FLASH_PCROP1ER_PCROP1_END_Msk (0x3FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00003FFF */
#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000003F */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0x3FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x003F0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000003F */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0x3FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x003F0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_SEC1R register **************/
#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
#define FLASH_SEC1R_SEC_SIZE1_Msk (0x7FUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x0000007F */
#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
/******************************************************************************/
/* */
/* Filter Mathematical ACcelerator unit (FMAC) */
/* */
/******************************************************************************/
/***************** Bit definition for FMAC_X1BUFCFG register ****************/
#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
/***************** Bit definition for FMAC_X2BUFCFG register ****************/
#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
/***************** Bit definition for FMAC_YBUFCFG register *****************/
#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
/****************** Bit definition for FMAC_PARAM register ******************/
#define FMAC_PARAM_P_Pos (0U)
#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
#define FMAC_PARAM_Q_Pos (8U)
#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
#define FMAC_PARAM_R_Pos (16U)
#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
#define FMAC_PARAM_FUNC_Pos (24U)
#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
#define FMAC_PARAM_START_Pos (31U)
#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
/******************** Bit definition for FMAC_CR register *******************/
#define FMAC_CR_RIEN_Pos (0U)
#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
#define FMAC_CR_WIEN_Pos (1U)
#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
#define FMAC_CR_OVFLIEN_Pos (2U)
#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
#define FMAC_CR_UNFLIEN_Pos (3U)
#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
#define FMAC_CR_SATIEN_Pos (4U)
#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
#define FMAC_CR_DMAREN_Pos (8U)
#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
#define FMAC_CR_DMAWEN_Pos (9U)
#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
#define FMAC_CR_CLIPEN_Pos (15U)
#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
#define FMAC_CR_RESET_Pos (16U)
#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
/******************* Bit definition for FMAC_SR register ********************/
#define FMAC_SR_YEMPTY_Pos (0U)
#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
#define FMAC_SR_X1FULL_Pos (1U)
#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
#define FMAC_SR_OVFL_Pos (8U)
#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
#define FMAC_SR_UNFL_Pos (9U)
#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
#define FMAC_SR_SAT_Pos (10U)
#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
/****************** Bit definition for FMAC_WDATA register ******************/
#define FMAC_WDATA_WDATA_Pos (0U)
#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
/****************** Bit definition for FMACX_RDATA register *****************/
#define FMAC_RDATA_RDATA_Pos (0U)
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/* Legacy defines */
#define GPIO_BRR_BR_0 GPIO_BRR_BR0
#define GPIO_BRR_BR_1 GPIO_BRR_BR1
#define GPIO_BRR_BR_2 GPIO_BRR_BR2
#define GPIO_BRR_BR_3 GPIO_BRR_BR3
#define GPIO_BRR_BR_4 GPIO_BRR_BR4
#define GPIO_BRR_BR_5 GPIO_BRR_BR5
#define GPIO_BRR_BR_6 GPIO_BRR_BR6
#define GPIO_BRR_BR_7 GPIO_BRR_BR7
#define GPIO_BRR_BR_8 GPIO_BRR_BR8
#define GPIO_BRR_BR_9 GPIO_BRR_BR9
#define GPIO_BRR_BR_10 GPIO_BRR_BR10
#define GPIO_BRR_BR_11 GPIO_BRR_BR11
#define GPIO_BRR_BR_12 GPIO_BRR_BR12
#define GPIO_BRR_BR_13 GPIO_BRR_BR13
#define GPIO_BRR_BR_14 GPIO_BRR_BR14
#define GPIO_BRR_BR_15 GPIO_BRR_BR15
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_USERTRIM_Pos (4U)
#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
#define OPAMP_CSR_OPAMPINTEN_Pos (8U)
#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
#define OPAMP_CSR_OUTCAL_Pos (30U)
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
#define OPAMP_CSR_LOCK_Pos (31U)
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
/********************* Bit definition for OPAMPx_TCMR register ***************/
#define OPAMP_TCMR_VMSSEL_Pos (0U)
#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
#define OPAMP_TCMR_VPSSEL_Pos (1U)
#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
#define OPAMP_TCMR_T1CMEN_Pos (3U)
#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
#define OPAMP_TCMR_T8CMEN_Pos (4U)
#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
#define OPAMP_TCMR_T20CMEN_Pos (5U)
#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
#define OPAMP_TCMR_LOCK_Pos (31U)
#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_LPR_Pos (14U)
#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
#define PWR_CR1_VOS_Pos (9U)
#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_LPMS_Pos (0U)
#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
#define PWR_CR1_LPMS_STOP1_Pos (0U)
#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
#define PWR_CR1_LPMS_STANDBY_Pos (0U)
#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
/******************** Bit definition for PWR_CR2 register ********************/
/*!< PVME Peripheral Voltage Monitor Enable */
#define PWR_CR2_PVME_Pos (4U)
#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
#define PWR_CR2_PVME4_Pos (7U)
#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
#define PWR_CR2_PVME3_Pos (6U)
#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
#define PWR_CR2_PVME2_Pos (5U)
#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
#define PWR_CR2_PVME1_Pos (4U)
#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
/*!< PVD level configuration */
#define PWR_CR2_PLS_Pos (1U)
#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
#define PWR_CR2_PLS_LEV1_Pos (1U)
#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR2_PLS_LEV2_Pos (2U)
#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR2_PLS_LEV3_Pos (1U)
#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR2_PLS_LEV4_Pos (3U)
#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR2_PLS_LEV5_Pos (1U)
#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR2_PLS_LEV6_Pos (2U)
#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR2_PLS_LEV7_Pos (1U)
#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
#define PWR_CR2_PVDE_Pos (0U)
#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EIWF_Pos (15U)
#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
#define PWR_CR3_UCPD_DBDIS_Pos (14U)
#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
#define PWR_CR3_UCPD_STDBY_Pos (13U)
#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
#define PWR_CR3_APC_Pos (10U)
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
#define PWR_CR3_RRS_Pos (8U)
#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
#define PWR_CR3_EWUP5_Pos (4U)
#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
#define PWR_CR3_EWUP4_Pos (3U)
#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
#define PWR_CR3_EWUP3_Pos (2U)
#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
#define PWR_CR3_EWUP2_Pos (1U)
#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
#define PWR_CR3_EWUP1_Pos (0U)
#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
#define PWR_CR3_EWUP_Pos (0U)
#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
/******************** Bit definition for PWR_CR4 register ********************/
#define PWR_CR4_VBRS_Pos (9U)
#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
#define PWR_CR4_VBE_Pos (8U)
#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
#define PWR_CR4_WP5_Pos (4U)
#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
#define PWR_CR4_WP4_Pos (3U)
#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
#define PWR_CR4_WP3_Pos (2U)
#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
#define PWR_CR4_WP2_Pos (1U)
#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
#define PWR_CR4_WP1_Pos (0U)
#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
/******************** Bit definition for PWR_SR1 register ********************/
#define PWR_SR1_WUFI_Pos (15U)
#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
#define PWR_SR1_SBF_Pos (8U)
#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
#define PWR_SR1_WUF_Pos (0U)
#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
#define PWR_SR1_WUF5_Pos (4U)
#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
#define PWR_SR1_WUF4_Pos (3U)
#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
#define PWR_SR1_WUF3_Pos (2U)
#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
#define PWR_SR1_WUF2_Pos (1U)
#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
#define PWR_SR1_WUF1_Pos (0U)
#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
/******************** Bit definition for PWR_SR2 register ********************/
#define PWR_SR2_PVMO4_Pos (15U)
#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
#define PWR_SR2_PVMO3_Pos (14U)
#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
#define PWR_SR2_PVMO2_Pos (13U)
#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
#define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
#define PWR_SR2_VOSF_Pos (10U)
#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
#define PWR_SR2_REGLPF_Pos (9U)
#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
#define PWR_SR2_REGLPS_Pos (8U)
#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CSBF_Pos (8U)
#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
#define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
#define PWR_SCR_CWUF5_Pos (4U)
#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
#define PWR_SCR_CWUF4_Pos (3U)
#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
#define PWR_SCR_CWUF3_Pos (2U)
#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
#define PWR_SCR_CWUF2_Pos (1U)
#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
#define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
/******************** Bit definition for PWR_PUCRA register ********************/
#define PWR_PUCRA_PA15_Pos (15U)
#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
#define PWR_PUCRA_PA13_Pos (13U)
#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
#define PWR_PUCRA_PA12_Pos (12U)
#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
#define PWR_PUCRA_PA11_Pos (11U)
#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
#define PWR_PUCRA_PA10_Pos (10U)
#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
#define PWR_PUCRA_PA9_Pos (9U)
#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
#define PWR_PUCRA_PA8_Pos (8U)
#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
#define PWR_PUCRA_PA7_Pos (7U)
#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
#define PWR_PUCRA_PA6_Pos (6U)
#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
#define PWR_PUCRA_PA5_Pos (5U)
#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
#define PWR_PUCRA_PA4_Pos (4U)
#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
#define PWR_PUCRA_PA3_Pos (3U)
#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
#define PWR_PUCRA_PA2_Pos (2U)
#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
#define PWR_PUCRA_PA1_Pos (1U)
#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
#define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
/******************** Bit definition for PWR_PDCRA register ********************/
#define PWR_PDCRA_PA14_Pos (14U)
#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
#define PWR_PDCRA_PA12_Pos (12U)
#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
#define PWR_PDCRA_PA11_Pos (11U)
#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
#define PWR_PDCRA_PA10_Pos (10U)
#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
#define PWR_PDCRA_PA9_Pos (9U)
#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
#define PWR_PDCRA_PA8_Pos (8U)
#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
#define PWR_PDCRA_PA7_Pos (7U)
#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
#define PWR_PDCRA_PA6_Pos (6U)
#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
#define PWR_PDCRA_PA5_Pos (5U)
#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
#define PWR_PDCRA_PA4_Pos (4U)
#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
#define PWR_PDCRA_PA3_Pos (3U)
#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
#define PWR_PDCRA_PA2_Pos (2U)
#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
#define PWR_PDCRA_PA1_Pos (1U)
#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
#define PWR_PDCRA_PA0_Pos (0U)
#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
/******************** Bit definition for PWR_PUCRB register ********************/
#define PWR_PUCRB_PB15_Pos (15U)
#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
#define PWR_PUCRB_PB14_Pos (14U)
#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
#define PWR_PUCRB_PB13_Pos (13U)
#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
#define PWR_PUCRB_PB12_Pos (12U)
#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
#define PWR_PUCRB_PB11_Pos (11U)
#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
#define PWR_PUCRB_PB10_Pos (10U)
#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
#define PWR_PUCRB_PB9_Pos (9U)
#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
#define PWR_PUCRB_PB8_Pos (8U)
#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
#define PWR_PUCRB_PB7_Pos (7U)
#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
#define PWR_PUCRB_PB6_Pos (6U)
#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
#define PWR_PUCRB_PB5_Pos (5U)
#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
#define PWR_PUCRB_PB4_Pos (4U)
#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
#define PWR_PUCRB_PB3_Pos (3U)
#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
#define PWR_PUCRB_PB2_Pos (2U)
#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
#define PWR_PUCRB_PB1_Pos (1U)
#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
#define PWR_PUCRB_PB0_Pos (0U)
#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
/******************** Bit definition for PWR_PDCRB register ********************/
#define PWR_PDCRB_PB15_Pos (15U)
#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
#define PWR_PDCRB_PB14_Pos (14U)
#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
#define PWR_PDCRB_PB13_Pos (13U)
#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
#define PWR_PDCRB_PB12_Pos (12U)
#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
#define PWR_PDCRB_PB11_Pos (11U)
#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
#define PWR_PDCRB_PB10_Pos (10U)
#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
#define PWR_PDCRB_PB9_Pos (9U)
#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
#define PWR_PDCRB_PB8_Pos (8U)
#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
#define PWR_PDCRB_PB7_Pos (7U)
#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
#define PWR_PDCRB_PB6_Pos (6U)
#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
#define PWR_PDCRB_PB5_Pos (5U)
#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
#define PWR_PDCRB_PB3_Pos (3U)
#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
#define PWR_PDCRB_PB2_Pos (2U)
#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
#define PWR_PDCRB_PB1_Pos (1U)
#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
#define PWR_PDCRB_PB0_Pos (0U)
#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
/******************** Bit definition for PWR_PUCRC register ********************/
#define PWR_PUCRC_PC15_Pos (15U)
#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
#define PWR_PUCRC_PC14_Pos (14U)
#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
#define PWR_PUCRC_PC13_Pos (13U)
#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
#define PWR_PUCRC_PC12_Pos (12U)
#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
#define PWR_PUCRC_PC11_Pos (11U)
#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
#define PWR_PUCRC_PC10_Pos (10U)
#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
#define PWR_PUCRC_PC9_Pos (9U)
#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
#define PWR_PUCRC_PC8_Pos (8U)
#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
#define PWR_PUCRC_PC7_Pos (7U)
#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
#define PWR_PUCRC_PC6_Pos (6U)
#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
#define PWR_PUCRC_PC5_Pos (5U)
#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
#define PWR_PUCRC_PC4_Pos (4U)
#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
#define PWR_PUCRC_PC3_Pos (3U)
#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
#define PWR_PUCRC_PC2_Pos (2U)
#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
#define PWR_PUCRC_PC1_Pos (1U)
#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
#define PWR_PUCRC_PC0_Pos (0U)
#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
/******************** Bit definition for PWR_PDCRC register ********************/
#define PWR_PDCRC_PC15_Pos (15U)
#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
#define PWR_PDCRC_PC14_Pos (14U)
#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
#define PWR_PDCRC_PC13_Pos (13U)
#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
#define PWR_PDCRC_PC12_Pos (12U)
#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
#define PWR_PDCRC_PC11_Pos (11U)
#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
#define PWR_PDCRC_PC10_Pos (10U)
#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
#define PWR_PDCRC_PC9_Pos (9U)
#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
#define PWR_PDCRC_PC8_Pos (8U)
#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
#define PWR_PDCRC_PC7_Pos (7U)
#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
#define PWR_PDCRC_PC6_Pos (6U)
#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
#define PWR_PDCRC_PC5_Pos (5U)
#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
#define PWR_PDCRC_PC4_Pos (4U)
#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
#define PWR_PDCRC_PC3_Pos (3U)
#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
#define PWR_PDCRC_PC2_Pos (2U)
#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
#define PWR_PDCRC_PC1_Pos (1U)
#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
#define PWR_PDCRC_PC0_Pos (0U)
#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
/******************** Bit definition for PWR_PUCRD register ********************/
#define PWR_PUCRD_PD15_Pos (15U)
#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
#define PWR_PUCRD_PD14_Pos (14U)
#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
#define PWR_PUCRD_PD13_Pos (13U)
#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
#define PWR_PUCRD_PD12_Pos (12U)
#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
#define PWR_PUCRD_PD11_Pos (11U)
#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
#define PWR_PUCRD_PD10_Pos (10U)
#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
#define PWR_PUCRD_PD9_Pos (9U)
#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
#define PWR_PUCRD_PD8_Pos (8U)
#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
#define PWR_PUCRD_PD7_Pos (7U)
#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
#define PWR_PUCRD_PD6_Pos (6U)
#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
#define PWR_PUCRD_PD5_Pos (5U)
#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
#define PWR_PUCRD_PD4_Pos (4U)
#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
#define PWR_PUCRD_PD3_Pos (3U)
#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
#define PWR_PUCRD_PD2_Pos (2U)
#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
#define PWR_PUCRD_PD1_Pos (1U)
#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
#define PWR_PUCRD_PD0_Pos (0U)
#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register ********************/
#define PWR_PDCRD_PD15_Pos (15U)
#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
#define PWR_PDCRD_PD14_Pos (14U)
#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
#define PWR_PDCRD_PD13_Pos (13U)
#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
#define PWR_PDCRD_PD12_Pos (12U)
#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
#define PWR_PDCRD_PD11_Pos (11U)
#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
#define PWR_PDCRD_PD10_Pos (10U)
#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
#define PWR_PDCRD_PD9_Pos (9U)
#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
#define PWR_PDCRD_PD8_Pos (8U)
#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
#define PWR_PDCRD_PD7_Pos (7U)
#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
#define PWR_PDCRD_PD6_Pos (6U)
#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
#define PWR_PDCRD_PD5_Pos (5U)
#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
#define PWR_PDCRD_PD4_Pos (4U)
#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
#define PWR_PDCRD_PD3_Pos (3U)
#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
#define PWR_PDCRD_PD2_Pos (2U)
#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
#define PWR_PDCRD_PD1_Pos (1U)
#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
/******************** Bit definition for PWR_PUCRE register ********************/
#define PWR_PUCRE_PE15_Pos (15U)
#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
#define PWR_PUCRE_PE14_Pos (14U)
#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
#define PWR_PUCRE_PE13_Pos (13U)
#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
#define PWR_PUCRE_PE12_Pos (12U)
#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
#define PWR_PUCRE_PE11_Pos (11U)
#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
#define PWR_PUCRE_PE10_Pos (10U)
#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
#define PWR_PUCRE_PE9_Pos (9U)
#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
#define PWR_PUCRE_PE8_Pos (8U)
#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
#define PWR_PUCRE_PE7_Pos (7U)
#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
#define PWR_PUCRE_PE6_Pos (6U)
#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
#define PWR_PUCRE_PE5_Pos (5U)
#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
#define PWR_PUCRE_PE4_Pos (4U)
#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
#define PWR_PUCRE_PE3_Pos (3U)
#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
#define PWR_PUCRE_PE2_Pos (2U)
#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
#define PWR_PUCRE_PE1_Pos (1U)
#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
#define PWR_PUCRE_PE0_Pos (0U)
#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
/******************** Bit definition for PWR_PDCRE register ********************/
#define PWR_PDCRE_PE15_Pos (15U)
#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
#define PWR_PDCRE_PE14_Pos (14U)
#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
#define PWR_PDCRE_PE13_Pos (13U)
#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
#define PWR_PDCRE_PE12_Pos (12U)
#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
#define PWR_PDCRE_PE11_Pos (11U)
#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
#define PWR_PDCRE_PE10_Pos (10U)
#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
#define PWR_PDCRE_PE9_Pos (9U)
#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
#define PWR_PDCRE_PE8_Pos (8U)
#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
#define PWR_PDCRE_PE7_Pos (7U)
#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
#define PWR_PDCRE_PE6_Pos (6U)
#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
#define PWR_PDCRE_PE5_Pos (5U)
#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
#define PWR_PDCRE_PE4_Pos (4U)
#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
#define PWR_PDCRE_PE3_Pos (3U)
#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
#define PWR_PDCRE_PE2_Pos (2U)
#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
#define PWR_PDCRE_PE1_Pos (1U)
#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
#define PWR_PDCRE_PE0_Pos (0U)
#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
/******************** Bit definition for PWR_PUCRF register ********************/
#define PWR_PUCRF_PF15_Pos (15U)
#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
#define PWR_PUCRF_PF14_Pos (14U)
#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
#define PWR_PUCRF_PF13_Pos (13U)
#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
#define PWR_PUCRF_PF12_Pos (12U)
#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
#define PWR_PUCRF_PF11_Pos (11U)
#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
#define PWR_PUCRF_PF10_Pos (10U)
#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
#define PWR_PUCRF_PF9_Pos (9U)
#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
#define PWR_PUCRF_PF8_Pos (8U)
#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
#define PWR_PUCRF_PF7_Pos (7U)
#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
#define PWR_PUCRF_PF6_Pos (6U)
#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
#define PWR_PUCRF_PF5_Pos (5U)
#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
#define PWR_PUCRF_PF4_Pos (4U)
#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
#define PWR_PUCRF_PF3_Pos (3U)
#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
#define PWR_PUCRF_PF2_Pos (2U)
#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
#define PWR_PUCRF_PF1_Pos (1U)
#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
#define PWR_PUCRF_PF0_Pos (0U)
#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
/******************** Bit definition for PWR_PDCRF register ********************/
#define PWR_PDCRF_PF10_Pos (10U)
#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
#define PWR_PDCRF_PF9_Pos (9U)
#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
#define PWR_PDCRF_PF2_Pos (2U)
#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
#define PWR_PDCRF_PF1_Pos (1U)
#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
#define PWR_PDCRF_PF0_Pos (0U)
#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
/******************** Bit definition for PWR_PUCRG register ********************/
#define PWR_PUCRG_PG10_Pos (10U)
#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
/******************** Bit definition for PWR_PDCRG register ********************/
#define PWR_PDCRG_PG10_Pos (10U)
#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
#define PWR_PDCRG_PG9_Pos (9U)
#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
#define PWR_PDCRG_PG8_Pos (8U)
#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
#define PWR_PDCRG_PG7_Pos (7U)
#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
#define PWR_PDCRG_PG6_Pos (6U)
#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
#define PWR_PDCRG_PG5_Pos (5U)
#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
#define PWR_PDCRG_PG4_Pos (4U)
#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
#define PWR_PDCRG_PG3_Pos (3U)
#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
#define PWR_PDCRG_PG2_Pos (2U)
#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
#define PWR_PDCRG_PG1_Pos (1U)
#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
#define PWR_PDCRG_PG0_Pos (0U)
#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
/******************** Bit definition for PWR_CR5 register ********************/
#define PWR_CR5_R1MODE_Pos (8U)
#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (8U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
#define RCC_CR_HSIKERON_Pos (9U)
#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
#define RCC_CR_HSIRDY_Pos (10U)
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
#define RCC_CR_HSEON_Pos (16U)
#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
#define RCC_CR_PLLON_Pos (24U)
#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (16U)
#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
/*!< MCOSEL configuration */
#define RCC_CFGR_MCOSEL_Pos (24U)
#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
#define RCC_CFGR_MCOPRE_Pos (28U)
#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
/* Legacy aliases */
#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLSRC_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
#define RCC_PLLCFGR_PLLM_Pos (4U)
#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
#define RCC_PLLCFGR_PLLN_Pos (8U)
#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
#define RCC_PLLCFGR_PLLPEN_Pos (16U)
#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
#define RCC_PLLCFGR_PLLP_Pos (17U)
#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
#define RCC_PLLCFGR_PLLQEN_Pos (20U)
#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
#define RCC_PLLCFGR_PLLQ_Pos (21U)
#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
#define RCC_PLLCFGR_PLLREN_Pos (24U)
#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
#define RCC_PLLCFGR_PLLR_Pos (25U)
#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos (3U)
#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos (4U)
#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_PLLRDYIE_Pos (5U)
#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos (9U)
#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos (10U)
#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
/******************** Bit definition for RCC_CIFR register ******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos (3U)
#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos (4U)
#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_PLLRDYF_Pos (5U)
#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
#define RCC_CIFR_CSSF_Pos (8U)
#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
#define RCC_CIFR_LSECSSF_Pos (9U)
#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSI48RDYF_Pos (10U)
#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
/******************** Bit definition for RCC_CICR register ******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos (3U)
#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos (4U)
#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
#define RCC_CICR_PLLRDYC_Pos (5U)
#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
#define RCC_CICR_CSSC_Pos (8U)
#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
#define RCC_CICR_LSECSSC_Pos (9U)
#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSI48RDYC_Pos (10U)
#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
#define RCC_AHB1RSTR_CORDICRST_Pos (3U)
#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
#define RCC_AHB1RSTR_FMACRST_Pos (4U)
#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
#define RCC_AHB1RSTR_CRCRST_Pos (12U)
#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
#define RCC_AHB2RSTR_ADC12RST_Pos (13U)
#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
#define RCC_AHB2RSTR_DAC1RST_Pos (16U)
#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
#define RCC_AHB2RSTR_DAC3RST_Pos (18U)
#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
#define RCC_AHB2RSTR_AESRST_Pos (24U)
#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos)/*!< 0x01000000 */
#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (26U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
/******************** Bit definition for RCC_AHB3RSTR register **************/
/******************** Bit definition for RCC_APB1RSTR1 register **************/
#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
#define RCC_APB1RSTR1_CRSRST_Pos (8U)
#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
#define RCC_APB1RSTR1_USART2RST_Pos (17U)
#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
#define RCC_APB1RSTR1_USART3RST_Pos (18U)
#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
#define RCC_APB1RSTR1_UART4RST_Pos (19U)
#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
#define RCC_APB1RSTR1_USBRST_Pos (23U)
#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
#define RCC_APB1RSTR1_FDCANRST_Pos (25U)
#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
#define RCC_APB1RSTR1_PWRRST_Pos (28U)
#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
#define RCC_APB1RSTR1_I2C3RST_Pos (30U)
#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
#define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_TIM8RST_Pos (13U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define RCC_AHB1ENR_DMA2EN_Pos (1U)
#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
#define RCC_AHB1ENR_CORDICEN_Pos (3U)
#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
#define RCC_AHB1ENR_FMACEN_Pos (4U)
#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
#define RCC_AHB1ENR_FLASHEN_Pos (8U)
#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
#define RCC_AHB1ENR_CRCEN_Pos (12U)
#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
#define RCC_AHB2ENR_GPIODEN_Pos (3U)
#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
#define RCC_AHB2ENR_ADC12EN_Pos (13U)
#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
#define RCC_AHB2ENR_DAC1EN_Pos (16U)
#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
#define RCC_AHB2ENR_DAC3EN_Pos (18U)
#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
#define RCC_AHB2ENR_AESEN_Pos (24U)
#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x01000000 */
#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (26U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
/******************** Bit definition for RCC_AHB3ENR register ***************/
/******************** Bit definition for RCC_APB1ENR1 register ***************/
#define RCC_APB1ENR1_TIM2EN_Pos (0U)
#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
#define RCC_APB1ENR1_TIM3EN_Pos (1U)
#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
#define RCC_APB1ENR1_TIM7EN_Pos (5U)
#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
#define RCC_APB1ENR1_CRSEN_Pos (8U)
#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
#define RCC_APB1ENR1_WWDGEN_Pos (11U)
#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
#define RCC_APB1ENR1_SPI2EN_Pos (14U)
#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
#define RCC_APB1ENR1_SPI3EN_Pos (15U)
#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
#define RCC_APB1ENR1_USART2EN_Pos (17U)
#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
#define RCC_APB1ENR1_USART3EN_Pos (18U)
#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
#define RCC_APB1ENR1_UART4EN_Pos (19U)
#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
#define RCC_APB1ENR1_I2C1EN_Pos (21U)
#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
#define RCC_APB1ENR1_I2C2EN_Pos (22U)
#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
#define RCC_APB1ENR1_USBEN_Pos (23U)
#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
#define RCC_APB1ENR1_FDCANEN_Pos (25U)
#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
#define RCC_APB1ENR1_PWREN_Pos (28U)
#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
#define RCC_APB1ENR1_I2C3EN_Pos (30U)
#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
#define RCC_APB1ENR2_UCPD1EN_Pos (8U)
#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
#define RCC_APB2ENR_TIM1EN_Pos (11U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_TIM8EN_Pos (13U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define RCC_APB2ENR_USART1EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
/******************** Bit definition for RCC_AHB2SMENR register *************/
#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
#define RCC_AHB2SMENR_AESSMEN_Pos (24U)
#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos)/*!< 0x01000000 */
#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk
#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register *************/
/******************** Bit definition for RCC_APB1SMENR1 register *************/
#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
#define RCC_APB1SMENR1_USBSMEN_Pos (23U)
#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
/******************** Bit definition for RCC_APB1SMENR2 register *************/
#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
/******************** Bit definition for RCC_APB2SMENR register *************/
#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
#define RCC_CCIPR_USART2SEL_Pos (2U)
#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
#define RCC_CCIPR_USART3SEL_Pos (4U)
#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
#define RCC_CCIPR_UART4SEL_Pos (6U)
#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR_LPUART1SEL_Pos (10U)
#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
#define RCC_CCIPR_I2C1SEL_Pos (12U)
#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR_I2C2SEL_Pos (14U)
#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR_I2C3SEL_Pos (16U)
#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
#define RCC_CCIPR_SAI1SEL_Pos (20U)
#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
#define RCC_CCIPR_I2S23SEL_Pos (22U)
#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
#define RCC_CCIPR_FDCANSEL_Pos (24U)
#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR_CLK48SEL_Pos (26U)
#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
#define RCC_CCIPR_ADC12SEL_Pos (28U)
#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos (3U)
#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos (5U)
#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos (6U)
#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
#define RCC_BDCR_LSCOEN_Pos (24U)
#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
#define RCC_BDCR_LSCOSEL_Pos (25U)
#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION_Pos (0U)
#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos (1U)
#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
#define RCC_CSR_RMVF_Pos (23U)
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
#define RCC_CSR_OBLRSTF_Pos (25U)
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_BORRSTF_Pos (27U)
#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/******************** Bit definition for RCC_CRRCR register *****************/
#define RCC_CRRCR_HSI48ON_Pos (0U)
#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
#define RCC_CRRCR_HSI48RDY_Pos (1U)
#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos (7U)
#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
/******************** Bit definition for RCC_CCIPR2 register ******************/
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_ICSR register ******************/
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_ALRBWF_Pos (1U)
#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
#define RTC_ICSR_ALRAWF_Pos (0U)
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_SR register *******************/
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
/******************** Bits definition for RTC_MISR register *****************/
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
/******************** Bits definition for RTC_SCR register ******************/
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register *****************/
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos (21U)
#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
/******************** Bits definition for TAMP_CR2 register *****************/
#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
#define TAMP_CR2_TAMP1MF_Pos (16U)
#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
#define TAMP_CR2_TAMP2MF_Pos (17U)
#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
#define TAMP_CR2_TAMP3MF_Pos (18U)
#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_IER register *****************/
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos (21U)
#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
/******************** Bits definition for TAMP_SR register ******************/
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos (21U)
#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
/******************** Bits definition for TAMP_MISR register ****************/
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos (21U)
#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
/******************** Bits definition for TAMP_SCR register *****************/
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos (21U)
#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
/******************** Bits definition for TAMP_BKP1R register ***************/
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
/******************** Bits definition for TAMP_BKP2R register ***************/
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
/******************** Bits definition for TAMP_BKP3R register ***************/
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
/******************** Bits definition for TAMP_BKP4R register ***************/
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************** Bits definition for TAMP_BKP5R register ***************/
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
/******************** Bits definition for TAMP_BKP6R register ***************/
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
/******************** Bits definition for TAMP_BKP7R register ***************/
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
/******************** Bits definition for TAMP_BKP8R register ***************/
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
/******************** Bits definition for TAMP_BKP9R register ***************/
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
/******************** Bits definition for TAMP_BKP10R register ***************/
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
/******************** Bits definition for TAMP_BKP11R register ***************/
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
/******************** Bits definition for TAMP_BKP12R register ***************/
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
/******************** Bits definition for TAMP_BKP13R register ***************/
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
/******************** Bits definition for TAMP_BKP14R register ***************/
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
/******************** Bits definition for TAMP_BKP15R register ***************/
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/****************** Bit definition for SAI_PDMCR register *******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
#define SPI_CR1_CPOL_Pos (1U)
#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
#define SPI_CR1_MSTR_Pos (2U)
#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
#define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
#define SPI_CR1_LSBFIRST_Pos (7U)
#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
#define SPI_CR1_SSI_Pos (8U)
#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
#define SPI_CR1_SSM_Pos (9U)
#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
#define SPI_CR1_RXONLY_Pos (10U)
#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
#define SPI_CR1_CRCL_Pos (11U)
#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
#define SPI_CR1_CRCNEXT_Pos (12U)
#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
#define SPI_CR1_CRCEN_Pos (13U)
#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE_Pos (14U)
#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos (15U)
#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN_Pos (0U)
#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN_Pos (1U)
#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
#define SPI_CR2_SSOE_Pos (2U)
#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
#define SPI_CR2_NSSP_Pos (3U)
#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
#define SPI_CR2_FRF_Pos (4U)
#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
#define SPI_CR2_ERRIE_Pos (5U)
#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE_Pos (6U)
#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE_Pos (7U)
#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
#define SPI_CR2_LDMARX_Pos (13U)
#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
#define SPI_CR2_LDMATX_Pos (14U)
#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE_Pos (0U)
#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
#define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
#define SPI_SR_MODF_Pos (5U)
#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
#define SPI_SR_BSY_Pos (7U)
#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
#define SPI_SR_FRE_Pos (8U)
#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
#define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U)
#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY_Pos (0U)
#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC_Pos (0U)
#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC_Pos (0U)
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN_Pos (0U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN_Pos (1U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_CKPOL_Pos (3U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_I2SE_Pos (10U)
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD_Pos (8U)
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE_Pos (9U)
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
/****************** Bit definition for SYSCFG_CFGR1 register ******************/
#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
/****************** Bit definition for SYSCFG_SCSR register ****************/
#define SYSCFG_SCSR_CCMER_Pos (0U)
#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
#define SYSCFG_SCSR_CCMBSY_Pos (1U)
#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
/****************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_CLL_Pos (0U)
#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
#define SYSCFG_CFGR2_SPL_Pos (1U)
#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
#define SYSCFG_CFGR2_PVDL_Pos (2U)
#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
#define SYSCFG_CFGR2_ECCL_Pos (3U)
#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
#define SYSCFG_CFGR2_SPF_Pos (8U)
#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
#define TIM_CR1_CMS_Pos (5U)
#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos (7U)
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos (8U)
#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos (12U)
#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos (15U)
#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos (3U)
#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE_Pos (0U)
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos (1U)
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos (2U)
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos (3U)
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos (4U)
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos (5U)
#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos (6U)
#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos (7U)
#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos (8U)
#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos (9U)
#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos (10U)
#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos (11U)
#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos (12U)
#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos (13U)
#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos (14U)
#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos (20U)
#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos (21U)
#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos (20U)
#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
#define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos (21U)
#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
#define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos (22U)
#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
#define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos (23U)
#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
#define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG_Pos (0U)
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos (6U)
#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
#define TIM_EGR_BG_Pos (7U)
#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
#define TIM_EGR_B2G_Pos (8U)
#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos (4U)
#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos (12U)
#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA_Pos (0U)
#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos (8U)
#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
/******************* Bit definition for TIM1_AF1 register *******************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
#define TIM1_AF1_BKCMP1E_Pos (1U)
#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
#define TIM1_AF1_BKCMP2E_Pos (2U)
#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
#define TIM1_AF1_BKCMP3E_Pos (3U)
#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
#define TIM1_AF1_BKCMP4E_Pos (4U)
#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
#define TIM1_AF1_BKCMP1P_Pos (10U)
#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
#define TIM1_AF1_BKCMP2P_Pos (11U)
#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
#define TIM1_AF1_BKCMP3P_Pos (12U)
#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
#define TIM1_AF1_BKCMP4P_Pos (13U)
#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
#define TIM1_AF1_ETRSEL_Pos (14U)
#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
#define TIM1_AF2_BK2CMP1E_Pos (1U)
#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
#define TIM1_AF2_BK2CMP2E_Pos (2U)
#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
#define TIM1_AF2_BK2CMP3E_Pos (3U)
#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
#define TIM1_AF2_BK2CMP4E_Pos (4U)
#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
#define TIM1_AF2_BK2CMP1P_Pos (10U)
#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
#define TIM1_AF2_BK2CMP2P_Pos (11U)
#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_BK2CMP3P_Pos (12U)
#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
#define TIM1_AF2_BK2CMP4P_Pos (13U)
#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
#define TIM1_AF2_OCRSEL_Pos (16U)
#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_HSE32EN_Pos (0U)
#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM_DTR2 register *********************/
#define TIM_DTR2_DTGF_Pos (0U)
#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos (16U)
#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos (17U)
#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
/******************* Bit definition for TIM_ECR register *********************/
#define TIM_ECR_IE_Pos (0U)
#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
#define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
#define TIM_ECR_IDIR_Pos (1U)
#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_FIDX_Pos (5U)
#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
#define TIM_ECR_IPOS_Pos (6U)
#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
#define TIM_ECR_PW_Pos (16U)
#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
#define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos (24U)
#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB_Pos (0U)
#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_OR register *******************/
#define LPTIM_OR_IN1_Pos (0U)
#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
#define LPTIM_OR_IN2_Pos (1U)
#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART_Pos (0U)
#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR_Pos (0U)
#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */
#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
/******************* Bit definition for VREFBUF_CCR register ******************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* USB Device FS Endpoint registers */
/* */
/******************************************************************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
/* bit positions */
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
/* */
/* USB Device FS General registers */
/* */
/******************************************************************************/
#define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
#define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
#define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
#define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
#define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
#define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
/****************** Bits definition for USB_CNTR register *******************/
#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/****************** Bits definition for USB_ISTR register *******************/
#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
/****************** Bits definition for USB_FNR register ********************/
#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
/****************** Bits definition for USB_DADDR register ****************/
#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
#define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
#define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
#define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
#define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
#define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
#define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
#define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
#define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
/****************** Bit definition for USB_BTABLE register ******************/
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
/****************** Bits definition for USB_BCDR register *******************/
#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
/******************* Bit definition for LPMCSR register *********************/
#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
/*!< Buffer descriptor table */
/***************** Bit definition for USB_ADDR0_TX register *****************/
#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_TX register *****************/
#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_TX register *****************/
#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_TX register *****************/
#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_TX register *****************/
#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_TX register *****************/
#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_TX register *****************/
#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_TX register *****************/
#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_TX register ****************/
#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
/***************** Bit definition for USB_COUNT1_TX register ****************/
#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
/***************** Bit definition for USB_COUNT2_TX register ****************/
#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
/***************** Bit definition for USB_COUNT3_TX register ****************/
#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
/***************** Bit definition for USB_COUNT4_TX register ****************/
#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
/***************** Bit definition for USB_COUNT5_TX register ****************/
#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
/***************** Bit definition for USB_COUNT6_TX register ****************/
#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
/***************** Bit definition for USB_COUNT7_TX register ****************/
#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_ADDR0_RX register *****************/
#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_RX register *****************/
#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_RX register *****************/
#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_RX register *****************/
#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_RX register *****************/
#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_RX register *****************/
#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_RX register *****************/
#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_RX register *****************/
#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_RX register ****************/
#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT0_RX_BLSIZE_Pos (15U)
#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT1_RX register ****************/
#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT1_RX_BLSIZE_Pos (15U)
#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT2_RX register ****************/
#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT2_RX_BLSIZE_Pos (15U)
#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT3_RX register ****************/
#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT3_RX_BLSIZE_Pos (15U)
#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT4_RX register ****************/
#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT4_RX_BLSIZE_Pos (15U)
#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT5_RX register ****************/
#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT5_RX_BLSIZE_Pos (15U)
#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT6_RX register ****************/
#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT6_RX_BLSIZE_Pos (15U)
#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT7_RX register ****************/
#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT7_RX_BLSIZE_Pos (15U)
#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
/* UCPD */
/* */
/******************************************************************************/
/******************** Bits definition for UCPD_CFG1 register *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos (6U)
#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos (11U)
#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos (20U)
#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos (29U)
#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define UCPD_CFG1_RXDMAEN_Pos (30U)
#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define UCPD_CFG1_UCPDEN_Pos (31U)
#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
/******************** Bits definition for UCPD_CFG2 register *******************/
#define UCPD_CFG2_RXFILTDIS_Pos (0U)
#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos (1U)
#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos (2U)
#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos (3U)
#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
/******************** Bits definition for UCPD_CR register ********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos (2U)
#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXHRST_Pos (3U)
#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
#define UCPD_CR_RXMODE_Pos (4U)
#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
#define UCPD_CR_PHYRXEN_Pos (5U)
#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
#define UCPD_CR_PHYCCSEL_Pos (6U)
#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
#define UCPD_CR_ANASUBMODE_Pos (7U)
#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos (9U)
#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
#define UCPD_CR_CCENABLE_Pos (10U)
#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
#define UCPD_CR_FRSRXEN_Pos (16U)
#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
#define UCPD_CR_FRSTX_Pos (17U)
#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos (18U)
#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
#define UCPD_CR_CC1TCDIS_Pos (20U)
#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos (21U)
#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
/******************** Bits definition for UCPD_IMR register *******************/
#define UCPD_IMR_TXISIE_Pos (0U)
#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
#define UCPD_IMR_TXMSGABTIE_Pos (3U)
#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
#define UCPD_IMR_HRSTDISCIE_Pos (4U)
#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
#define UCPD_IMR_HRSTSENTIE_Pos (5U)
#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
#define UCPD_IMR_TXUNDIE_Pos (6U)
#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
#define UCPD_IMR_RXNEIE_Pos (8U)
#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
#define UCPD_IMR_RXORDDETIE_Pos (9U)
#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
#define UCPD_IMR_RXOVRIE_Pos (11U)
#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
#define UCPD_IMR_RXMSGENDIE_Pos (12U)
#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
#define UCPD_IMR_FRSEVTIE_Pos (20U)
#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
/******************** Bits definition for UCPD_SR register ********************/
#define UCPD_SR_TXIS_Pos (0U)
#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
#define UCPD_SR_TXMSGDISC_Pos (1U)
#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
#define UCPD_SR_TXMSGSENT_Pos (2U)
#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
#define UCPD_SR_TXMSGABT_Pos (3U)
#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
#define UCPD_SR_HRSTDISC_Pos (4U)
#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
#define UCPD_SR_HRSTSENT_Pos (5U)
#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
#define UCPD_SR_TXUND_Pos (6U)
#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
#define UCPD_SR_RXNE_Pos (8U)
#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
#define UCPD_SR_RXORDDET_Pos (9U)
#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
#define UCPD_SR_RXHRSTDET_Pos (10U)
#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
#define UCPD_SR_RXOVR_Pos (11U)
#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
#define UCPD_SR_RXMSGEND_Pos (12U)
#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
#define UCPD_SR_RXERR_Pos (13U)
#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos (14U)
#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
#define UCPD_SR_TYPECEVT2_Pos (15U)
#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
#define UCPD_SR_FRSEVT_Pos (20U)
#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
/******************** Bits definition for UCPD_ICR register *******************/
#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
#define UCPD_ICR_TXMSGABTCF_Pos (3U)
#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
#define UCPD_ICR_HRSTDISCCF_Pos (4U)
#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
#define UCPD_ICR_HRSTSENTCF_Pos (5U)
#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
#define UCPD_ICR_TXUNDCF_Pos (6U)
#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
#define UCPD_ICR_RXORDDETCF_Pos (9U)
#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
#define UCPD_ICR_RXOVRCF_Pos (11U)
#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
#define UCPD_ICR_RXMSGENDCF_Pos (12U)
#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
#define UCPD_ICR_FRSEVTCF_Pos (20U)
#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
/******************** Bits definition for UCPD_TXORDSET register **************/
#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
/******************** Bits definition for UCPD_TXPAYSZ register ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
/******************** Bits definition for UCPD_TXDR register *******************/
#define UCPD_TXDR_TXDATA_Pos (0U)
#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
/******************** Bits definition for UCPD_RXORDSET register **************/
#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
/******************** Bits definition for UCPD_RXPAYSZ register ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
/******************** Bits definition for UCPD_RXDR register *******************/
#define UCPD_RXDR_RXDATA_Pos (0U)
#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/******************** Bits definition for UCPD_RXORDEXT1 register **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
/******************** Bits definition for UCPD_RXORDEXT2 register **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
/******************************* AES Instances ********************************/
#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
/******************************** FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN1)
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2) || \
((INSTANCE) == COMP3) || \
((INSTANCE) == COMP4))
/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC3))
/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA2_Channel1) || \
((INSTANCE) == DMA2_Channel2) || \
((INSTANCE) == DMA2_Channel3) || \
((INSTANCE) == DMA2_Channel4) || \
((INSTANCE) == DMA2_Channel5) || \
((INSTANCE) == DMA2_Channel6))
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
/******************************* FMAC Instances *******************************/
#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances *****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3))
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3))
/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3))
/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
((__INSTANCE__) == SPI3))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8))
/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4))
/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4))
/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4))
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4))
/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** UCPD Instances ********************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
/******************************* USB Instances *******************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/**
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32G4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32G4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
#define TIM7_DAC_IRQn TIM7_IRQn
#define COMP4_5_6_IRQn COMP4_IRQn
/* Aliases for __IRQHandler */
#define TIM7_DAC_IRQHandler TIM7_IRQHandler
#define COMP4_5_6_IRQHandler COMP4_IRQHandler
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32G441xx_H */
/**
* @}
*/
/**
* @}
*/
| 1,006,860 | C | 74.296216 | 180 | 0.510934 |
Tbarkin121/GuardDog/stm32/MotorDrive/LegDay/Drivers/CMSIS/Device/ST/STM32G4xx/Include/stm32g4a1xx.h | /**
******************************************************************************
* @file stm32g4a1xx.h
* @author MCD Application Team
* @brief CMSIS STM32G4A1xx Device Peripheral Access Layer Header File.
*
* This file contains:
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
* - Macros to access peripheral's registers hardware
*
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS_Device
* @{
*/
/** @addtogroup stm32g4a1xx
* @{
*/
#ifndef __STM32G4A1xx_H
#define __STM32G4A1xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
*/
#define __CM4_REV 0x0001U /*!< Cortex-M4 revision r0p1 */
#define __MPU_PRESENT 1U /*!< STM32G4XX provides an MPU */
#define __NVIC_PRIO_BITS 4U /*!< STM32G4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
#define __FPU_PRESENT 1U /*!< FPU present */
/**
* @}
*/
/** @addtogroup Peripheral_interrupt_number_definition
* @{
*/
/**
* @brief STM32G4XX Interrupt Number Definition, according to the selected device
* in @ref Library_configuration_section
*/
typedef enum
{
/****** Cortex-M4 Processor Exceptions Numbers *********************************************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
/****** STM32 specific Interrupt Numbers ***************************************************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
RTC_TAMP_LSECSS_IRQn = 2, /*!< RTC Tamper and TimeStamp and RCC LSE CSS interrupts through the EXTI */
RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
FLASH_IRQn = 4, /*!< FLASH global Interrupt */
RCC_IRQn = 5, /*!< RCC global Interrupt */
EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
USB_HP_IRQn = 19, /*!< USB HP Interrupt */
USB_LP_IRQn = 20, /*!< USB LP Interrupt */
FDCAN1_IT0_IRQn = 21, /*!< FDCAN1 IT0 Interrupt */
FDCAN1_IT1_IRQn = 22, /*!< FDCAN1 IT1 Interrupt */
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break, Transition error, Index error and TIM15 global interrupt */
TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 TIM1 Trigger, Commutation, Direction change, Index and TIM17 global interrupt */
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
USART1_IRQn = 37, /*!< USART1 global Interrupt */
USART2_IRQn = 38, /*!< USART2 global Interrupt */
USART3_IRQn = 39, /*!< USART3 global Interrupt */
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
USBWakeUp_IRQn = 42, /*!< USB Wakeup through EXTI line Interrupt */
TIM8_BRK_IRQn = 43, /*!< TIM8 Break, Transition error and Index error Interrupt */
TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger, Commutation, Direction change and Index Interrupt */
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
LPTIM1_IRQn = 49, /*!< LP TIM1 Interrupt */
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
UART4_IRQn = 52, /*!< UART4 global Interrupt */
UART5_IRQn = 53, /*!< UART5 global Interrupt */
TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&3 underrun error interrupts */
TIM7_IRQn = 55, /*!< TIM7 global interrupts */
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
UCPD1_IRQn = 63, /*!< UCPD global Interrupt */
COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 Interrupts */
COMP4_IRQn = 65, /*!< COMP4 */
CRS_IRQn = 75, /*!< CRS global interrupt */
SAI1_IRQn = 76, /*!< Serial Audio Interface global interrupt */
TIM20_BRK_IRQn = 77, /*!< TIM20 Break, Transition error and Index error Interrupt */
TIM20_UP_IRQn = 78, /*!< TIM20 Update interrupt */
TIM20_TRG_COM_IRQn = 79, /*!< TIM20 Trigger, Commutation, Direction change and Index Interrupt */
TIM20_CC_IRQn = 80, /*!< TIM20 Capture Compare interrupt */
FPU_IRQn = 81, /*!< FPU global interrupt */
AES_IRQn = 85, /*!< AES global interrupt */
FDCAN2_IT0_IRQn = 86, /*!< FDCAN2 interrupt line 0 interrupt */
FDCAN2_IT1_IRQn = 87, /*!< FDCAN2 interrupt line 1 interrupt */
RNG_IRQn = 90, /*!< RNG global interrupt */
LPUART1_IRQn = 91, /*!< LP UART 1 Interrupt */
I2C3_EV_IRQn = 92, /*!< I2C3 Event Interrupt */
I2C3_ER_IRQn = 93, /*!< I2C3 Error interrupt */
DMAMUX_OVR_IRQn = 94, /*!< DMAMUX overrun global interrupt */
QUADSPI_IRQn = 95, /*!< QUADSPI interrupt */
DMA1_Channel8_IRQn = 96, /*!< DMA1 Channel 8 interrupt */
DMA2_Channel6_IRQn = 97, /*!< DMA2 Channel 6 interrupt */
DMA2_Channel7_IRQn = 98, /*!< DMA2 Channel 7 interrupt */
DMA2_Channel8_IRQn = 99, /*!< DMA2 Channel 8 interrupt */
CORDIC_IRQn = 100, /*!< CORDIC global Interrupt */
FMAC_IRQn = 101 /*!< FMAC global Interrupt */
} IRQn_Type;
/**
* @}
*/
#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
#include "system_stm32g4xx.h"
#include <stdint.h>
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @brief Analog to Digital Converter
*/
typedef struct
{
__IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
__IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
__IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
__IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
__IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
__IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved, 0x1C */
__IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
__IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
__IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
uint32_t RESERVED2; /*!< Reserved, 0x2C */
__IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
__IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
__IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
__IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
__IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
uint32_t RESERVED3; /*!< Reserved, 0x44 */
uint32_t RESERVED4; /*!< Reserved, 0x48 */
__IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
__IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
__IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
__IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
__IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
__IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
__IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
__IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
__IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
__IO uint32_t AWD2CR; /*!< ADC analog watchdog 2 configuration register, Address offset: 0xA0 */
__IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
uint32_t RESERVED9; /*!< Reserved, 0x0AC */
__IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
__IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
uint32_t RESERVED10[2];/*!< Reserved, 0x0B8 - 0x0BC */
__IO uint32_t GCOMP; /*!< ADC calibration factors, Address offset: 0xC0 */
} ADC_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 + 0x00 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x300 + 0x04 */
__IO uint32_t CCR; /*!< ADC common configuration register, Address offset: 0x300 + 0x08 */
__IO uint32_t CDR; /*!< ADC common group regular data register Address offset: 0x300 + 0x0C */
} ADC_Common_TypeDef;
/**
* @brief FD Controller Area Network
*/
typedef struct
{
__IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
__IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
uint32_t RESERVED1; /*!< Reserved, 0x008 */
__IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
__IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
__IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
__IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
__IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
__IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
__IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
__IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
__IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
__IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
__IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
__IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
uint32_t RESERVED3; /*!< Reserved, 0x04C */
__IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
__IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
__IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
__IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
__IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
__IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */
__IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */
uint32_t RESERVED5; /*!< Reserved, 0x08C */
__IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */
__IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */
__IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */
__IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */
uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */
__IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
__IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
__IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */
__IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */
__IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */
__IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */
__IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */
__IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */
__IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */
__IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */
__IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */
} FDCAN_GlobalTypeDef;
/**
* @brief FD Controller Area Network Configuration
*/
typedef struct
{
__IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */
} FDCAN_Config_TypeDef;
/**
* @brief Comparator
*/
typedef struct
{
__IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
} COMP_TypeDef;
/**
* @brief CRC calculation unit
*/
typedef struct
{
__IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
__IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
__IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
uint32_t RESERVED0; /*!< Reserved, 0x0C */
__IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
__IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
} CRC_TypeDef;
/**
* @brief Clock Recovery System
*/
typedef struct
{
__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef;
/**
* @brief Digital to Analog Converter
*/
typedef struct
{
__IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
__IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
__IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
__IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
__IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
__IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
__IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
__IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
__IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
__IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
__IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
__IO uint32_t RESERVED[2];
__IO uint32_t STR1; /*!< DAC Sawtooth register, Address offset: 0x58 */
__IO uint32_t STR2; /*!< DAC Sawtooth register, Address offset: 0x5C */
__IO uint32_t STMODR; /*!< DAC Sawtooth Mode register, Address offset: 0x60 */
} DAC_TypeDef;
/**
* @brief Debug MCU
*/
typedef struct
{
__IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
__IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
__IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
__IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
__IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
} DBGMCU_TypeDef;
/**
* @brief DMA Controller
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA channel x configuration register */
__IO uint32_t CNDTR; /*!< DMA channel x number of data register */
__IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
__IO uint32_t CMAR; /*!< DMA channel x memory address register */
} DMA_Channel_TypeDef;
typedef struct
{
__IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
__IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
} DMA_TypeDef;
/**
* @brief DMA Multiplexer
*/
typedef struct
{
__IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register Address offset: 0x0004 * (channel x) */
}DMAMUX_Channel_TypeDef;
typedef struct
{
__IO uint32_t CSR; /*!< DMA Channel Status Register Address offset: 0x0080 */
__IO uint32_t CFR; /*!< DMA Channel Clear Flag Register Address offset: 0x0084 */
}DMAMUX_ChannelStatus_TypeDef;
typedef struct
{
__IO uint32_t RGCR; /*!< DMA Request Generator x Control Register Address offset: 0x0100 + 0x0004 * (Req Gen x) */
}DMAMUX_RequestGen_TypeDef;
typedef struct
{
__IO uint32_t RGSR; /*!< DMA Request Generator Status Register Address offset: 0x0140 */
__IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register Address offset: 0x0144 */
}DMAMUX_RequestGenStatus_TypeDef;
/**
* @brief External Interrupt/Event Controller
*/
typedef struct
{
__IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
__IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
__IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
__IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
__IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
__IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, 0x18 */
uint32_t RESERVED2; /*!< Reserved, 0x1C */
__IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
__IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
__IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
__IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
__IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
__IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
} EXTI_TypeDef;
/**
* @brief FLASH Registers
*/
typedef struct
{
__IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
__IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
__IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
__IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
__IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
__IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
__IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
__IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
uint32_t RESERVED2[15]; /*!< Reserved2, Address offset: 0x34 */
__IO uint32_t SEC1R; /*!< FLASH Securable memory register bank1, Address offset: 0x70 */
} FLASH_TypeDef;
/**
* @brief FMAC
*/
typedef struct
{
__IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */
__IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */
__IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */
__IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */
__IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */
__IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */
__IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */
__IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */
} FMAC_TypeDef;
/**
* @brief General Purpose I/O
*/
typedef struct
{
__IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
__IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
__IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
__IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
__IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
__IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
__IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
__IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
} GPIO_TypeDef;
/**
* @brief Inter-integrated Circuit Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
__IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
__IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
__IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
__IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
__IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
__IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
__IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
__IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
__IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
} I2C_TypeDef;
/**
* @brief Independent WATCHDOG
*/
typedef struct
{
__IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
__IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
__IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
__IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
} IWDG_TypeDef;
/**
* @brief LPTIMER
*/
typedef struct
{
__IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
__IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
__IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
__IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
__IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
__IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
__IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
__IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
__IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
} LPTIM_TypeDef;
/**
* @brief Operational Amplifier (OPAMP)
*/
typedef struct
{
__IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
__IO uint32_t RESERVED[5]; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
__IO uint32_t TCMR; /*!< OPAMP timer controlled mux mode register, Address offset: 0x18 */
} OPAMP_TypeDef;
/**
* @brief Power Control
*/
typedef struct
{
__IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
__IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
__IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
__IO uint32_t PUCRF; /*!< Pull_up control register of portF, Address offset: 0x48 */
__IO uint32_t PDCRF; /*!< Pull_Down control register of portF, Address offset: 0x4C */
__IO uint32_t PUCRG; /*!< Pull_up control register of portG, Address offset: 0x50 */
__IO uint32_t PDCRG; /*!< Pull_Down control register of portG, Address offset: 0x54 */
uint32_t RESERVED1[10]; /*!< Reserved Address offset: 0x58 - 0x7C */
__IO uint32_t CR5; /*!< PWR power control register 5, Address offset: 0x80 */
} PWR_TypeDef;
/**
* @brief QUAD Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
__IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
__IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
__IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
__IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
__IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
__IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
__IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
__IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
__IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
__IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef;
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
__IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
__IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
__IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
uint32_t RESERVED0; /*!< Reserved, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
__IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x34 */
__IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
__IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
__IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
uint32_t RESERVED4; /*!< Reserved, Address offset: 0x44 */
__IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
__IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
__IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
uint32_t RESERVED5; /*!< Reserved, Address offset: 0x54 */
__IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
__IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
__IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
uint32_t RESERVED6; /*!< Reserved, Address offset: 0x64 */
__IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
__IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
__IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
uint32_t RESERVED7; /*!< Reserved, Address offset: 0x74 */
__IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
__IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
__IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
uint32_t RESERVED8; /*!< Reserved, Address offset: 0x84 */
__IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
uint32_t RESERVED9; /*!< Reserved, Address offset: 0x8C */
__IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
__IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
__IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
__IO uint32_t CCIPR2; /*!< RCC peripherals independent clock configuration register 2, Address offset: 0x9C */
} RCC_TypeDef;
/**
* @brief Real-Time Clock
*/
/*
* @brief Specific device feature definitions
*/
#define RTC_TAMP_INT_6_SUPPORT
#define RTC_TAMP_INT_NB 4u
#define RTC_TAMP_NB 3u
#define RTC_BACKUP_NB 32u
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
__IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
__IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
uint32_t RESERVED0; /*!< Reserved Address offset: 0x1C */
uint32_t RESERVED1; /*!< Reserved Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
__IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
__IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x3C */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
__IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
__IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
__IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
__IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
__IO uint32_t MISR; /*!< RTC Masked Interrupt Status register, Address offset: 0x54 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x58 */
__IO uint32_t SCR; /*!< RTC Status Clear register, Address offset: 0x5C */
} RTC_TypeDef;
/**
* @brief Tamper and backup registers
*/
typedef struct
{
__IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
uint32_t RESERVED0; /*!< no configuration register 3, Address offset: 0x08 */
__IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
uint32_t RESERVED1[6]; /*!< Reserved Address offset: 0x10 - 0x24 */
uint32_t RESERVED2; /*!< Reserved Address offset: 0x28 */
__IO uint32_t IER; /*!< TAMP Interrupt enable register, Address offset: 0x2C */
__IO uint32_t SR; /*!< TAMP Status register, Address offset: 0x30 */
__IO uint32_t MISR; /*!< TAMP Masked Interrupt Status register Address offset: 0x34 */
uint32_t RESERVED3; /*!< Reserved Address offset: 0x38 */
__IO uint32_t SCR; /*!< TAMP Status clear register, Address offset: 0x3C */
uint32_t RESERVED4[48]; /*!< Reserved Address offset: 0x040 - 0xFC */
__IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
__IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
__IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
__IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
__IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
__IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
__IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
__IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
__IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
__IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
__IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
__IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
__IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
__IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
__IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
__IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
__IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
__IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
__IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
__IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
__IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
__IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
__IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
__IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
__IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
__IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
__IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
__IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
__IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
__IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
__IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
__IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
} TAMP_TypeDef;
/**
* @brief Serial Audio Interface
*/
typedef struct
{
__IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */
__IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
__IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
} SAI_TypeDef;
typedef struct
{
__IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
__IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
__IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
__IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
__IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
__IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
__IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
__IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
} SAI_Block_TypeDef;
/**
* @brief Serial Peripheral Interface
*/
typedef struct
{
__IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
} SPI_TypeDef;
/**
* @brief System configuration controller
*/
typedef struct
{
__IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
__IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
__IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
__IO uint32_t SCSR; /*!< SYSCFG CCMSRAM control and status register, Address offset: 0x18 */
__IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
__IO uint32_t SWPR; /*!< SYSCFG CCMSRAM write protection register, Address offset: 0x20 */
__IO uint32_t SKR; /*!< SYSCFG CCMSRAM Key Register, Address offset: 0x24 */
} SYSCFG_TypeDef;
/**
* @brief TIM
*/
typedef struct
{
__IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
__IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
__IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
__IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
__IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
__IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
__IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
__IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
__IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
__IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
__IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
__IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
__IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
__IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
__IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
__IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
__IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
__IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */
__IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */
__IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */
__IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */
__IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */
__IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */
__IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
__IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
__IO uint32_t OR ; /*!< TIM option register, Address offset: 0x68 */
uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */
__IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */
__IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */
} TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
typedef struct
{
__IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
__IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
__IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
__IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
__IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
__IO uint32_t RTOR; /*!< USART Receiver Timeout register, Address offset: 0x14 */
__IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
__IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
__IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
__IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
__IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
__IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */
} USART_TypeDef;
/**
* @brief Universal Serial Bus Full Speed Device
*/
typedef struct
{
__IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
__IO uint16_t RESERVED0; /*!< Reserved */
__IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
__IO uint16_t RESERVED1; /*!< Reserved */
__IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
__IO uint16_t RESERVED2; /*!< Reserved */
__IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
__IO uint16_t RESERVED3; /*!< Reserved */
__IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
__IO uint16_t RESERVED4; /*!< Reserved */
__IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
__IO uint16_t RESERVED5; /*!< Reserved */
__IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
__IO uint16_t RESERVED6; /*!< Reserved */
__IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
__IO uint16_t RESERVED7[17]; /*!< Reserved */
__IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
__IO uint16_t RESERVED8; /*!< Reserved */
__IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
__IO uint16_t RESERVED9; /*!< Reserved */
__IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
__IO uint16_t RESERVEDA; /*!< Reserved */
__IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
__IO uint16_t RESERVEDB; /*!< Reserved */
__IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
__IO uint16_t RESERVEDC; /*!< Reserved */
__IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
__IO uint16_t RESERVEDD; /*!< Reserved */
__IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
__IO uint16_t RESERVEDE; /*!< Reserved */
} USB_TypeDef;
/**
* @brief VREFBUF
*/
typedef struct
{
__IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
__IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
} VREFBUF_TypeDef;
/**
* @brief Window WATCHDOG
*/
typedef struct
{
__IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
__IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
__IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
} WWDG_TypeDef;
/**
* @brief AES hardware accelerator
*/
typedef struct
{
__IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
__IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
__IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
__IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
__IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
__IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
__IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
__IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
__IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
__IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
__IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
__IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */
__IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */
__IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */
__IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */
__IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */
__IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */
__IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */
__IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */
__IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */
__IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */
__IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */
__IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */
} AES_TypeDef;
/**
* @brief RNG
*/
typedef struct
{
__IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
__IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef;
/**
* @brief CORDIC
*/
typedef struct
{
__IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */
__IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */
__IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */
} CORDIC_TypeDef;
/**
* @brief UCPD
*/
typedef struct
{
__IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */
__IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */
__IO uint32_t RESERVED0; /*!< UCPD reserved register, Address offset: 0x08 */
__IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */
__IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */
__IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */
__IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */
__IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */
__IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */
__IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */
__IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */
__IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */
__IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */
__IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */
__IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */
} UCPD_TypeDef;
/**
* @}
*/
/** @addtogroup Peripheral_memory_map
* @{
*/
#define FLASH_BASE (0x08000000UL) /*!< FLASH (up to 512 kB) base address */
#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 80 KB) base address */
#define SRAM2_BASE (0x20014000UL) /*!< SRAM2(16 KB) base address */
#define CCMSRAM_BASE (0x10000000UL) /*!< CCMSRAM(16 KB) base address */
#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */
#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(80 KB) base address in the bit-band region */
#define SRAM2_BB_BASE (0x22280000UL) /*!< SRAM2(16 KB) base address in the bit-band region */
#define CCMSRAM_BB_BASE (0x22300000UL) /*!< CCMSRAM(16 KB) base address in the bit-band region */
#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
/* Legacy defines */
#define SRAM_BASE SRAM1_BASE
#define SRAM_BB_BASE SRAM1_BB_BASE
#define SRAM1_SIZE_MAX (0x00014000UL) /*!< maximum SRAM1 size (up to 80 KBytes) */
#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
#define CCMSRAM_SIZE (0x00004000UL) /*!< CCMSRAM size (16 KBytes) */
/*!< Peripheral memory map */
#define APB1PERIPH_BASE PERIPH_BASE
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
/*!< APB1 peripherals */
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
#define CRS_BASE (APB1PERIPH_BASE + 0x2000UL)
#define TAMP_BASE (APB1PERIPH_BASE + 0x2400UL)
#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
#define USB_BASE (APB1PERIPH_BASE + 0x5C00UL) /*!< USB_IP Peripheral Registers base address */
#define USB_PMAADDR (APB1PERIPH_BASE + 0x6000UL) /*!< USB_IP Packet Memory Area base address */
#define FDCAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
#define FDCAN_CONFIG_BASE (APB1PERIPH_BASE + 0x6500UL) /*!< FDCAN configuration registers base address */
#define FDCAN2_BASE (APB1PERIPH_BASE + 0x6800UL)
#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
#define I2C3_BASE (APB1PERIPH_BASE + 0x7800UL)
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
#define UCPD1_BASE (APB1PERIPH_BASE + 0xA000UL)
#define SRAMCAN_BASE (APB1PERIPH_BASE + 0xA400UL)
/*!< APB2 peripherals */
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
#define COMP3_BASE (APB2PERIPH_BASE + 0x0208UL)
#define COMP4_BASE (APB2PERIPH_BASE + 0x020CUL)
#define OPAMP_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP1_BASE (APB2PERIPH_BASE + 0x0300UL)
#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0304UL)
#define OPAMP3_BASE (APB2PERIPH_BASE + 0x0308UL)
#define OPAMP6_BASE (APB2PERIPH_BASE + 0x0314UL)
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400UL)
#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800UL)
#define TIM20_BASE (APB2PERIPH_BASE + 0x5000UL)
#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
/*!< AHB1 peripherals */
#define DMA1_BASE (AHB1PERIPH_BASE)
#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
#define DMAMUX1_BASE (AHB1PERIPH_BASE + 0x0800UL)
#define CORDIC_BASE (AHB1PERIPH_BASE + 0x0C00UL)
#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
#define FMAC_BASE (AHB1PERIPH_BASE + 0x1400UL)
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
#define DMA1_Channel8_BASE (DMA1_BASE + 0x0094UL)
#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
#define DMA2_Channel8_BASE (DMA2_BASE + 0x0094UL)
#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
/*!< AHB2 peripherals */
#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE (AHB2PERIPH_BASE + 0x1800UL)
#define ADC1_BASE (AHB2PERIPH_BASE + 0x08000000UL)
#define ADC2_BASE (AHB2PERIPH_BASE + 0x08000100UL)
#define ADC12_COMMON_BASE (AHB2PERIPH_BASE + 0x08000300UL)
#define ADC3_BASE (AHB2PERIPH_BASE + 0x08000400UL)
#define ADC345_COMMON_BASE (AHB2PERIPH_BASE + 0x08000700UL)
#define DAC_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC1_BASE (AHB2PERIPH_BASE + 0x08000800UL)
#define DAC3_BASE (AHB2PERIPH_BASE + 0x08001000UL)
#define AES_BASE (AHB2PERIPH_BASE + 0x08060000UL)
#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
/* Debug MCU registers base address */
#define DBGMCU_BASE (0xE0042000UL)
#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
/**
* @}
*/
/** @addtogroup Peripheral_declaration
* @{
*/
#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
#define CRS ((CRS_TypeDef *) CRS_BASE)
#define TAMP ((TAMP_TypeDef *) TAMP_BASE)
#define RTC ((RTC_TypeDef *) RTC_BASE)
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#define USART2 ((USART_TypeDef *) USART2_BASE)
#define USART3 ((USART_TypeDef *) USART3_BASE)
#define UART4 ((USART_TypeDef *) UART4_BASE)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
#define USB ((USB_TypeDef *) USB_BASE)
#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
#define FDCAN_CONFIG ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE)
#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
#define PWR ((PWR_TypeDef *) PWR_BASE)
#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
#define UCPD1 ((UCPD_TypeDef *) UCPD1_BASE)
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
#define OPAMP6 ((OPAMP_TypeDef *) OPAMP6_BASE)
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#define USART1 ((USART_TypeDef *) USART1_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
#define TIM20 ((TIM_TypeDef *) TIM20_BASE)
#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
#define CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)
#define RCC ((RCC_TypeDef *) RCC_BASE)
#define FMAC ((FMAC_TypeDef *) FMAC_BASE)
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
#define CRC ((CRC_TypeDef *) CRC_BASE)
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define ADC345_COMMON ((ADC_Common_TypeDef *) ADC345_COMMON_BASE)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
#define DAC3 ((DAC_TypeDef *) DAC3_BASE)
#define AES ((AES_TypeDef *) AES_BASE)
#define RNG ((RNG_TypeDef *) RNG_BASE)
#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
#define DMA1_Channel8 ((DMA_Channel_TypeDef *) DMA1_Channel8_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
/**
* @}
*/
/** @addtogroup Exported_constants
* @{
*/
/** @addtogroup Hardware_Constant_Definition
* @{
*/
#define LSI_STARTUP_TIME 130U /*!< LSI Maximum startup time in us */
/**
* @}
*/
/** @addtogroup Peripheral_Registers_Bits_Definition
* @{
*/
/******************************************************************************/
/* Peripheral Registers_Bits_Definition */
/******************************************************************************/
/******************************************************************************/
/* */
/* Analog to Digital Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
/******************** Bit definition for ADC_ISR register *******************/
#define ADC_ISR_ADRDY_Pos (0U)
#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
#define ADC_ISR_EOSMP_Pos (1U)
#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
#define ADC_ISR_EOC_Pos (2U)
#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
#define ADC_ISR_EOS_Pos (3U)
#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
#define ADC_ISR_OVR_Pos (4U)
#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
#define ADC_ISR_JEOC_Pos (5U)
#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
#define ADC_ISR_JEOS_Pos (6U)
#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
#define ADC_ISR_AWD1_Pos (7U)
#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
#define ADC_ISR_AWD2_Pos (8U)
#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
#define ADC_ISR_AWD3_Pos (9U)
#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
#define ADC_ISR_JQOVF_Pos (10U)
#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
/******************** Bit definition for ADC_IER register *******************/
#define ADC_IER_ADRDYIE_Pos (0U)
#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
#define ADC_IER_EOSMPIE_Pos (1U)
#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
#define ADC_IER_EOCIE_Pos (2U)
#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
#define ADC_IER_EOSIE_Pos (3U)
#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
#define ADC_IER_OVRIE_Pos (4U)
#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
#define ADC_IER_JEOCIE_Pos (5U)
#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
#define ADC_IER_JEOSIE_Pos (6U)
#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
#define ADC_IER_AWD1IE_Pos (7U)
#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
#define ADC_IER_AWD2IE_Pos (8U)
#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
#define ADC_IER_AWD3IE_Pos (9U)
#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
#define ADC_IER_JQOVFIE_Pos (10U)
#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
/******************** Bit definition for ADC_CR register ********************/
#define ADC_CR_ADEN_Pos (0U)
#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
#define ADC_CR_ADDIS_Pos (1U)
#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
#define ADC_CR_ADSTART_Pos (2U)
#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
#define ADC_CR_JADSTART_Pos (3U)
#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
#define ADC_CR_ADSTP_Pos (4U)
#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
#define ADC_CR_JADSTP_Pos (5U)
#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
#define ADC_CR_ADVREGEN_Pos (28U)
#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
#define ADC_CR_DEEPPWD_Pos (29U)
#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
#define ADC_CR_ADCALDIF_Pos (30U)
#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
#define ADC_CR_ADCAL_Pos (31U)
#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
/******************** Bit definition for ADC_CFGR register ******************/
#define ADC_CFGR_DMAEN_Pos (0U)
#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
#define ADC_CFGR_DMACFG_Pos (1U)
#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
#define ADC_CFGR_RES_Pos (3U)
#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
#define ADC_CFGR_EXTSEL_Pos (5U)
#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
#define ADC_CFGR_EXTEN_Pos (10U)
#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
#define ADC_CFGR_OVRMOD_Pos (12U)
#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
#define ADC_CFGR_CONT_Pos (13U)
#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
#define ADC_CFGR_AUTDLY_Pos (14U)
#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
#define ADC_CFGR_ALIGN_Pos (15U)
#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */
#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
#define ADC_CFGR_DISCEN_Pos (16U)
#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
#define ADC_CFGR_DISCNUM_Pos (17U)
#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
#define ADC_CFGR_JDISCEN_Pos (20U)
#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
#define ADC_CFGR_JQM_Pos (21U)
#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
#define ADC_CFGR_AWD1SGL_Pos (22U)
#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
#define ADC_CFGR_AWD1EN_Pos (23U)
#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
#define ADC_CFGR_JAWD1EN_Pos (24U)
#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
#define ADC_CFGR_JAUTO_Pos (25U)
#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
#define ADC_CFGR_AWD1CH_Pos (26U)
#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
#define ADC_CFGR_JQDIS_Pos (31U)
#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
/******************** Bit definition for ADC_CFGR2 register *****************/
#define ADC_CFGR2_ROVSE_Pos (0U)
#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
#define ADC_CFGR2_JOVSE_Pos (1U)
#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
#define ADC_CFGR2_OVSR_Pos (2U)
#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
#define ADC_CFGR2_OVSS_Pos (5U)
#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
#define ADC_CFGR2_TROVS_Pos (9U)
#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
#define ADC_CFGR2_ROVSM_Pos (10U)
#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
#define ADC_CFGR2_GCOMP_Pos (16U)
#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */
#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */
#define ADC_CFGR2_SWTRIG_Pos (25U)
#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */
#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */
#define ADC_CFGR2_BULB_Pos (26U)
#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */
#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */
#define ADC_CFGR2_SMPTRIG_Pos (27U)
#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */
#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */
/******************** Bit definition for ADC_SMPR1 register *****************/
#define ADC_SMPR1_SMP0_Pos (0U)
#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
#define ADC_SMPR1_SMP1_Pos (3U)
#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
#define ADC_SMPR1_SMP2_Pos (6U)
#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
#define ADC_SMPR1_SMP3_Pos (9U)
#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
#define ADC_SMPR1_SMP4_Pos (12U)
#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
#define ADC_SMPR1_SMP5_Pos (15U)
#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
#define ADC_SMPR1_SMP6_Pos (18U)
#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
#define ADC_SMPR1_SMP7_Pos (21U)
#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
#define ADC_SMPR1_SMP8_Pos (24U)
#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
#define ADC_SMPR1_SMP9_Pos (27U)
#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
#define ADC_SMPR1_SMPPLUS_Pos (31U)
#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */
#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */
/******************** Bit definition for ADC_SMPR2 register *****************/
#define ADC_SMPR2_SMP10_Pos (0U)
#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
#define ADC_SMPR2_SMP11_Pos (3U)
#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
#define ADC_SMPR2_SMP12_Pos (6U)
#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
#define ADC_SMPR2_SMP13_Pos (9U)
#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
#define ADC_SMPR2_SMP14_Pos (12U)
#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
#define ADC_SMPR2_SMP15_Pos (15U)
#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
#define ADC_SMPR2_SMP16_Pos (18U)
#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
#define ADC_SMPR2_SMP17_Pos (21U)
#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
#define ADC_SMPR2_SMP18_Pos (24U)
#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
/******************** Bit definition for ADC_TR1 register *******************/
#define ADC_TR1_LT1_Pos (0U)
#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
#define ADC_TR1_AWDFILT_Pos (12U)
#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */
#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */
#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */
#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */
#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */
#define ADC_TR1_HT1_Pos (16U)
#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */
/******************** Bit definition for ADC_TR2 register *******************/
#define ADC_TR2_LT2_Pos (0U)
#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
#define ADC_TR2_HT2_Pos (16U)
#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
/******************** Bit definition for ADC_TR3 register *******************/
#define ADC_TR3_LT3_Pos (0U)
#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
#define ADC_TR3_HT3_Pos (16U)
#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
/******************** Bit definition for ADC_SQR1 register ******************/
#define ADC_SQR1_L_Pos (0U)
#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
#define ADC_SQR1_SQ1_Pos (6U)
#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
#define ADC_SQR1_SQ2_Pos (12U)
#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
#define ADC_SQR1_SQ3_Pos (18U)
#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
#define ADC_SQR1_SQ4_Pos (24U)
#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR2 register ******************/
#define ADC_SQR2_SQ5_Pos (0U)
#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
#define ADC_SQR2_SQ6_Pos (6U)
#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
#define ADC_SQR2_SQ7_Pos (12U)
#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
#define ADC_SQR2_SQ8_Pos (18U)
#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
#define ADC_SQR2_SQ9_Pos (24U)
#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR3 register ******************/
#define ADC_SQR3_SQ10_Pos (0U)
#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
#define ADC_SQR3_SQ11_Pos (6U)
#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
#define ADC_SQR3_SQ12_Pos (12U)
#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
#define ADC_SQR3_SQ13_Pos (18U)
#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
#define ADC_SQR3_SQ14_Pos (24U)
#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
/******************** Bit definition for ADC_SQR4 register ******************/
#define ADC_SQR4_SQ15_Pos (0U)
#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
#define ADC_SQR4_SQ16_Pos (6U)
#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
/******************** Bit definition for ADC_DR register ********************/
#define ADC_DR_RDATA_Pos (0U)
#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
/******************** Bit definition for ADC_JSQR register ******************/
#define ADC_JSQR_JL_Pos (0U)
#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
#define ADC_JSQR_JEXTSEL_Pos (2U)
#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
#define ADC_JSQR_JEXTEN_Pos (7U)
#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
#define ADC_JSQR_JSQ1_Pos (9U)
#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
#define ADC_JSQR_JSQ2_Pos (15U)
#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
#define ADC_JSQR_JSQ3_Pos (21U)
#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
#define ADC_JSQR_JSQ4_Pos (27U)
#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
/******************** Bit definition for ADC_OFR1 register ******************/
#define ADC_OFR1_OFFSET1_Pos (0U)
#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
#define ADC_OFR1_OFFSETPOS_Pos (24U)
#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */
#define ADC_OFR1_SATEN_Pos (25U)
#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */
#define ADC_OFR1_OFFSET1_CH_Pos (26U)
#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR1_OFFSET1_EN_Pos (31U)
#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
/******************** Bit definition for ADC_OFR2 register ******************/
#define ADC_OFR2_OFFSET2_Pos (0U)
#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
#define ADC_OFR2_OFFSETPOS_Pos (24U)
#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */
#define ADC_OFR2_SATEN_Pos (25U)
#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */
#define ADC_OFR2_OFFSET2_CH_Pos (26U)
#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR2_OFFSET2_EN_Pos (31U)
#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
/******************** Bit definition for ADC_OFR3 register ******************/
#define ADC_OFR3_OFFSET3_Pos (0U)
#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
#define ADC_OFR3_OFFSETPOS_Pos (24U)
#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */
#define ADC_OFR3_SATEN_Pos (25U)
#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */
#define ADC_OFR3_OFFSET3_CH_Pos (26U)
#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR3_OFFSET3_EN_Pos (31U)
#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
/******************** Bit definition for ADC_OFR4 register ******************/
#define ADC_OFR4_OFFSET4_Pos (0U)
#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
#define ADC_OFR4_OFFSETPOS_Pos (24U)
#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */
#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */
#define ADC_OFR4_SATEN_Pos (25U)
#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */
#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */
#define ADC_OFR4_OFFSET4_CH_Pos (26U)
#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
#define ADC_OFR4_OFFSET4_EN_Pos (31U)
#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
/******************** Bit definition for ADC_JDR1 register ******************/
#define ADC_JDR1_JDATA_Pos (0U)
#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
/******************** Bit definition for ADC_JDR2 register ******************/
#define ADC_JDR2_JDATA_Pos (0U)
#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
/******************** Bit definition for ADC_JDR3 register ******************/
#define ADC_JDR3_JDATA_Pos (0U)
#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
/******************** Bit definition for ADC_JDR4 register ******************/
#define ADC_JDR4_JDATA_Pos (0U)
#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
/******************** Bit definition for ADC_AWD2CR register ****************/
#define ADC_AWD2CR_AWD2CH_Pos (0U)
#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_AWD3CR register ****************/
#define ADC_AWD3CR_AWD3CH_Pos (0U)
#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_DIFSEL register ****************/
#define ADC_DIFSEL_DIFSEL_Pos (0U)
#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
/******************** Bit definition for ADC_CALFACT register ***************/
#define ADC_CALFACT_CALFACT_S_Pos (0U)
#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */
#define ADC_CALFACT_CALFACT_D_Pos (16U)
#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */
/******************** Bit definition for ADC_GCOMP register *****************/
#define ADC_GCOMP_GCOMPCOEFF_Pos (0U)
#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) /*!< 0x00003FFF */
#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Gain Compensation Coefficient */
/************************* ADC Common registers *****************************/
/******************** Bit definition for ADC_CSR register *******************/
#define ADC_CSR_ADRDY_MST_Pos (0U)
#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */
#define ADC_CSR_EOSMP_MST_Pos (1U)
#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */
#define ADC_CSR_EOC_MST_Pos (2U)
#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */
#define ADC_CSR_EOS_MST_Pos (3U)
#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */
#define ADC_CSR_OVR_MST_Pos (4U)
#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */
#define ADC_CSR_JEOC_MST_Pos (5U)
#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_MST_Pos (6U)
#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_MST_Pos (7U)
#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */
#define ADC_CSR_AWD2_MST_Pos (8U)
#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */
#define ADC_CSR_AWD3_MST_Pos (9U)
#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */
#define ADC_CSR_JQOVF_MST_Pos (10U)
#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */
#define ADC_CSR_ADRDY_SLV_Pos (16U)
#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */
#define ADC_CSR_EOSMP_SLV_Pos (17U)
#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */
#define ADC_CSR_EOC_SLV_Pos (18U)
#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */
#define ADC_CSR_EOS_SLV_Pos (19U)
#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */
#define ADC_CSR_OVR_SLV_Pos (20U)
#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */
#define ADC_CSR_JEOC_SLV_Pos (21U)
#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */
#define ADC_CSR_JEOS_SLV_Pos (22U)
#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */
#define ADC_CSR_AWD1_SLV_Pos (23U)
#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */
#define ADC_CSR_AWD2_SLV_Pos (24U)
#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */
#define ADC_CSR_AWD3_SLV_Pos (25U)
#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */
#define ADC_CSR_JQOVF_SLV_Pos (26U)
#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */
/******************** Bit definition for ADC_CCR register *******************/
#define ADC_CCR_DUAL_Pos (0U)
#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */
#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
#define ADC_CCR_DELAY_Pos (8U)
#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */
#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
#define ADC_CCR_DMACFG_Pos (13U)
#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */
#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */
#define ADC_CCR_MDMA_Pos (14U)
#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */
#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */
#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */
#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */
#define ADC_CCR_CKMODE_Pos (16U)
#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
#define ADC_CCR_PRESC_Pos (18U)
#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
#define ADC_CCR_VREFEN_Pos (22U)
#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
#define ADC_CCR_VSENSESEL_Pos (23U)
#define ADC_CCR_VSENSESEL_Msk (0x1UL << ADC_CCR_VSENSESEL_Pos) /*!< 0x00800000 */
#define ADC_CCR_VSENSESEL ADC_CCR_VSENSESEL_Msk /*!< ADC internal path to temperature sensor enable */
#define ADC_CCR_VBATSEL_Pos (24U)
#define ADC_CCR_VBATSEL_Msk (0x1UL << ADC_CCR_VBATSEL_Pos) /*!< 0x01000000 */
#define ADC_CCR_VBATSEL ADC_CCR_VBATSEL_Msk /*!< ADC internal path to battery voltage enable */
/******************** Bit definition for ADC_CDR register *******************/
#define ADC_CDR_RDATA_MST_Pos (0U)
#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
#define ADC_CDR_RDATA_SLV_Pos (16U)
#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
/******************************************************************************/
/* */
/* Advanced Encryption Standard (AES) */
/* */
/******************************************************************************/
/******************* Bit definition for AES_CR register *********************/
#define AES_CR_EN_Pos (0U)
#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */
#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */
#define AES_CR_DATATYPE_Pos (1U)
#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */
#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */
#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */
#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */
#define AES_CR_MODE_Pos (3U)
#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */
#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */
#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */
#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */
#define AES_CR_CHMOD_Pos (5U)
#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */
#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */
#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */
#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */
#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */
#define AES_CR_CCFC_Pos (7U)
#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */
#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */
#define AES_CR_ERRC_Pos (8U)
#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */
#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */
#define AES_CR_CCFIE_Pos (9U)
#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */
#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */
#define AES_CR_ERRIE_Pos (10U)
#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */
#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */
#define AES_CR_DMAINEN_Pos (11U)
#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */
#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */
#define AES_CR_DMAOUTEN_Pos (12U)
#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */
#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */
#define AES_CR_GCMPH_Pos (13U)
#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */
#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */
#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */
#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */
#define AES_CR_KEYSIZE_Pos (18U)
#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */
#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */
#define AES_CR_NPBLB_Pos (20U)
#define AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) /*!< 0x00F00000 */
#define AES_CR_NPBLB AES_CR_NPBLB_Msk /*!< Number of padding bytes in payload last block */
#define AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) /*!< 0x00100000 */
#define AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) /*!< 0x00200000 */
#define AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) /*!< 0x00400000 */
#define AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) /*!< 0x00800000 */
/******************* Bit definition for AES_SR register *********************/
#define AES_SR_CCF_Pos (0U)
#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */
#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */
#define AES_SR_RDERR_Pos (1U)
#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */
#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */
#define AES_SR_WRERR_Pos (2U)
#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */
#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */
#define AES_SR_BUSY_Pos (3U)
#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */
#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */
/******************* Bit definition for AES_DINR register *******************/
#define AES_DINR_Pos (0U)
#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */
#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */
/******************* Bit definition for AES_DOUTR register ******************/
#define AES_DOUTR_Pos (0U)
#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */
#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */
/******************* Bit definition for AES_KEYR0 register ******************/
#define AES_KEYR0_Pos (0U)
#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */
/******************* Bit definition for AES_KEYR1 register ******************/
#define AES_KEYR1_Pos (0U)
#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */
/******************* Bit definition for AES_KEYR2 register ******************/
#define AES_KEYR2_Pos (0U)
#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */
/******************* Bit definition for AES_KEYR3 register ******************/
#define AES_KEYR3_Pos (0U)
#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */
/******************* Bit definition for AES_KEYR4 register ******************/
#define AES_KEYR4_Pos (0U)
#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */
/******************* Bit definition for AES_KEYR5 register ******************/
#define AES_KEYR5_Pos (0U)
#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */
/******************* Bit definition for AES_KEYR6 register ******************/
#define AES_KEYR6_Pos (0U)
#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */
/******************* Bit definition for AES_KEYR7 register ******************/
#define AES_KEYR7_Pos (0U)
#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */
#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */
/******************* Bit definition for AES_IVR0 register ******************/
#define AES_IVR0_Pos (0U)
#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */
/******************* Bit definition for AES_IVR1 register ******************/
#define AES_IVR1_Pos (0U)
#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */
/******************* Bit definition for AES_IVR2 register ******************/
#define AES_IVR2_Pos (0U)
#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */
/******************* Bit definition for AES_IVR3 register ******************/
#define AES_IVR3_Pos (0U)
#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */
#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */
/******************* Bit definition for AES_SUSP0R register ******************/
#define AES_SUSP0R_Pos (0U)
#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */
/******************* Bit definition for AES_SUSP1R register ******************/
#define AES_SUSP1R_Pos (0U)
#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */
/******************* Bit definition for AES_SUSP2R register ******************/
#define AES_SUSP2R_Pos (0U)
#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */
/******************* Bit definition for AES_SUSP3R register ******************/
#define AES_SUSP3R_Pos (0U)
#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */
/******************* Bit definition for AES_SUSP4R register ******************/
#define AES_SUSP4R_Pos (0U)
#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */
/******************* Bit definition for AES_SUSP5R register ******************/
#define AES_SUSP5R_Pos (0U)
#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */
/******************* Bit definition for AES_SUSP6R register ******************/
#define AES_SUSP6R_Pos (0U)
#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */
/******************* Bit definition for AES_SUSP7R register ******************/
#define AES_SUSP7R_Pos (0U)
#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */
#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
/* */
/******************************************************************************/
/********************** Bit definition for COMP_CSR register ****************/
#define COMP_CSR_EN_Pos (0U)
#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */
#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */
#define COMP_CSR_INMSEL_Pos (4U)
#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x00000070 */
#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */
#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */
#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */
#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */
#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */
#define COMP_CSR_INPSEL_Pos (8U)
#define COMP_CSR_INPSEL_Msk (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */
#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */
#define COMP_CSR_POLARITY_Pos (15U)
#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */
#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */
#define COMP_CSR_HYST_Pos (16U)
#define COMP_CSR_HYST_Msk (0x7UL << COMP_CSR_HYST_Pos) /*!< 0x00070000 */
#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis */
#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */
#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */
#define COMP_CSR_HYST_2 (0x4UL << COMP_CSR_HYST_Pos) /*!< 0x00040000 */
#define COMP_CSR_BLANKING_Pos (19U)
#define COMP_CSR_BLANKING_Msk (0x7UL << COMP_CSR_BLANKING_Pos) /*!< 0x00380000 */
#define COMP_CSR_BLANKING COMP_CSR_BLANKING_Msk /*!< Comparator blanking source */
#define COMP_CSR_BLANKING_0 (0x1UL << COMP_CSR_BLANKING_Pos) /*!< 0x00080000 */
#define COMP_CSR_BLANKING_1 (0x2UL << COMP_CSR_BLANKING_Pos) /*!< 0x00100000 */
#define COMP_CSR_BLANKING_2 (0x4UL << COMP_CSR_BLANKING_Pos) /*!< 0x00200000 */
#define COMP_CSR_BRGEN_Pos (22U)
#define COMP_CSR_BRGEN_Msk (0x1UL << COMP_CSR_BRGEN_Pos) /*!< 0x00400000 */
#define COMP_CSR_BRGEN COMP_CSR_BRGEN_Msk /*!< Comparator scaler bridge enable */
#define COMP_CSR_SCALEN_Pos (23U)
#define COMP_CSR_SCALEN_Msk (0x1UL << COMP_CSR_SCALEN_Pos) /*!< 0x00800000 */
#define COMP_CSR_SCALEN COMP_CSR_SCALEN_Msk /*!< Comparator voltage scaler enable */
#define COMP_CSR_VALUE_Pos (30U)
#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */
#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */
#define COMP_CSR_LOCK_Pos (31U)
#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */
/******************************************************************************/
/* */
/* CORDIC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CORDIC_CSR register *****************/
#define CORDIC_CSR_FUNC_Pos (0U)
#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */
#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */
#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */
#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */
#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */
#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */
#define CORDIC_CSR_PRECISION_Pos (4U)
#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */
#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */
#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */
#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */
#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */
#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */
#define CORDIC_CSR_SCALE_Pos (8U)
#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */
#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */
#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */
#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */
#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */
#define CORDIC_CSR_IEN_Pos (16U)
#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */
#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */
#define CORDIC_CSR_DMAREN_Pos (17U)
#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */
#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */
#define CORDIC_CSR_DMAWEN_Pos (18U)
#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */
#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */
#define CORDIC_CSR_NRES_Pos (19U)
#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */
#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */
#define CORDIC_CSR_NARGS_Pos (20U)
#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */
#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */
#define CORDIC_CSR_RESSIZE_Pos (21U)
#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */
#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */
#define CORDIC_CSR_ARGSIZE_Pos (22U)
#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */
#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */
#define CORDIC_CSR_RRDY_Pos (31U)
#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */
#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */
/******************* Bit definition for CORDIC_WDATA register ***************/
#define CORDIC_WDATA_ARG_Pos (0U)
#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */
/******************* Bit definition for CORDIC_RDATA register ***************/
#define CORDIC_RDATA_RES_Pos (0U)
#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */
#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */
/******************************************************************************/
/* */
/* CRC calculation unit */
/* */
/******************************************************************************/
/******************* Bit definition for CRC_DR register *********************/
#define CRC_DR_DR_Pos (0U)
#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
/******************* Bit definition for CRC_IDR register ********************/
#define CRC_IDR_IDR_Pos (0U)
#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
/******************** Bit definition for CRC_CR register ********************/
#define CRC_CR_RESET_Pos (0U)
#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
#define CRC_CR_POLYSIZE_Pos (3U)
#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
#define CRC_CR_REV_IN_Pos (5U)
#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
#define CRC_CR_REV_OUT_Pos (7U)
#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT_Pos (0U)
#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
/******************* Bit definition for CRC_POL register ********************/
#define CRC_POL_POL_Pos (0U)
#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
/******************************************************************************/
/* */
/* CRS Clock Recovery System */
/******************************************************************************/
/******************* Bit definition for CRS_CR register *********************/
#define CRS_CR_SYNCOKIE_Pos (0U)
#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
#define CRS_CR_SYNCWARNIE_Pos (1U)
#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
#define CRS_CR_ERRIE_Pos (2U)
#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
#define CRS_CR_ESYNCIE_Pos (3U)
#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
#define CRS_CR_CEN_Pos (5U)
#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
#define CRS_CR_AUTOTRIMEN_Pos (6U)
#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
#define CRS_CR_SWSYNC_Pos (7U)
#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
#define CRS_CR_TRIM_Pos (8U)
#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */
#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
/******************* Bit definition for CRS_CFGR register *********************/
#define CRS_CFGR_RELOAD_Pos (0U)
#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
#define CRS_CFGR_FELIM_Pos (16U)
#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
#define CRS_CFGR_SYNCDIV_Pos (24U)
#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
#define CRS_CFGR_SYNCSRC_Pos (28U)
#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
#define CRS_CFGR_SYNCPOL_Pos (31U)
#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
/******************* Bit definition for CRS_ISR register *********************/
#define CRS_ISR_SYNCOKF_Pos (0U)
#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
#define CRS_ISR_SYNCWARNF_Pos (1U)
#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
#define CRS_ISR_ERRF_Pos (2U)
#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
#define CRS_ISR_ESYNCF_Pos (3U)
#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
#define CRS_ISR_SYNCERR_Pos (8U)
#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
#define CRS_ISR_SYNCMISS_Pos (9U)
#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
#define CRS_ISR_TRIMOVF_Pos (10U)
#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
#define CRS_ISR_FEDIR_Pos (15U)
#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
#define CRS_ISR_FECAP_Pos (16U)
#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
/******************* Bit definition for CRS_ICR register *********************/
#define CRS_ICR_SYNCOKC_Pos (0U)
#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
#define CRS_ICR_SYNCWARNC_Pos (1U)
#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
#define CRS_ICR_ERRC_Pos (2U)
#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
#define CRS_ICR_ESYNCC_Pos (3U)
#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
/******************************************************************************/
/* */
/* Digital to Analog Converter */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 series)
*/
#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */
/******************** Bit definition for DAC_CR register ********************/
#define DAC_CR_EN1_Pos (0U)
#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
#define DAC_CR_TEN1_Pos (1U)
#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
#define DAC_CR_TSEL1_Pos (2U)
#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
#define DAC_CR_WAVE1_Pos (6U)
#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
#define DAC_CR_MAMP1_Pos (8U)
#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
#define DAC_CR_DMAEN1_Pos (12U)
#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
#define DAC_CR_DMAUDRIE1_Pos (13U)
#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
#define DAC_CR_CEN1_Pos (14U)
#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
#define DAC_CR_HFSEL_Pos (15U)
#define DAC_CR_HFSEL_Msk (0x1UL << DAC_CR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_CR_HFSEL DAC_CR_HFSEL_Msk /*!<DAC channel 1 and 2 high frequency mode enable >*/
#define DAC_CR_EN2_Pos (16U)
#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
#define DAC_CR_TEN2_Pos (17U)
#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
#define DAC_CR_TSEL2_Pos (18U)
#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[3:0] (DAC channel2 Trigger selection) */
#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
#define DAC_CR_WAVE2_Pos (22U)
#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
#define DAC_CR_MAMP2_Pos (24U)
#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
#define DAC_CR_DMAEN2_Pos (28U)
#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
#define DAC_CR_DMAUDRIE2_Pos (29U)
#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
#define DAC_CR_CEN2_Pos (30U)
#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
/***************** Bit definition for DAC_SWTRIGR register ******************/
#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
#define DAC_SWTRIGR_SWTRIGB1_Pos (16U)
#define DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) /*!< 0x00010000 */
#define DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk /*!<DAC channel1 software trigger B */
#define DAC_SWTRIGR_SWTRIGB2_Pos (17U)
#define DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) /*!< 0x00020000 */
#define DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk /*!<DAC channel2 software trigger B */
/***************** Bit definition for DAC_DHR12R1 register ******************/
#define DAC_DHR12R1_DACC1DHR_Pos (0U)
#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12R1_DACC1DHRB_Pos (16U)
#define DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L1 register ******************/
#define DAC_DHR12L1_DACC1DHR_Pos (4U)
#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12L1_DACC1DHRB_Pos (20U)
#define DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R1 register ******************/
#define DAC_DHR8R1_DACC1DHR_Pos (0U)
#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8R1_DACC1DHRB_Pos (8U)
#define DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12R2 register ******************/
#define DAC_DHR12R2_DACC2DHR_Pos (0U)
#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
#define DAC_DHR12R2_DACC2DHRB_Pos (16U)
#define DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
/***************** Bit definition for DAC_DHR12L2 register ******************/
#define DAC_DHR12L2_DACC2DHR_Pos (4U)
#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
#define DAC_DHR12L2_DACC2DHRB_Pos (20U)
#define DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data B */
/****************** Bit definition for DAC_DHR8R2 register ******************/
#define DAC_DHR8R2_DACC2DHR_Pos (0U)
#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
#define DAC_DHR8R2_DACC2DHRB_Pos (8U)
#define DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned data B */
/***************** Bit definition for DAC_DHR12RD register ******************/
#define DAC_DHR12RD_DACC1DHR_Pos (0U)
#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DHR12RD_DACC2DHR_Pos (16U)
#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
/***************** Bit definition for DAC_DHR12LD register ******************/
#define DAC_DHR12LD_DACC1DHR_Pos (4U)
#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DHR12LD_DACC2DHR_Pos (20U)
#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
/****************** Bit definition for DAC_DHR8RD register ******************/
#define DAC_DHR8RD_DACC1DHR_Pos (0U)
#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DHR8RD_DACC2DHR_Pos (8U)
#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
/******************* Bit definition for DAC_DOR1 register *******************/
#define DAC_DOR1_DACC1DOR_Pos (0U)
#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
#define DAC_DOR1_DACC1DORB_Pos (16U)
#define DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk /*!<DAC channel1 data output B */
/******************* Bit definition for DAC_DOR2 register *******************/
#define DAC_DOR2_DACC2DOR_Pos (0U)
#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
#define DAC_DOR2_DACC2DORB_Pos (16U)
#define DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) /*!< 0x0FFF0000 */
#define DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk /*!<DAC channel2 data output B */
/******************** Bit definition for DAC_SR register ********************/
#define DAC_SR_DAC1RDY_Pos (11U)
#define DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) /*!< 0x00000800 */
#define DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk /*!<DAC channel 1 ready status bit */
#define DAC_SR_DORSTAT1_Pos (12U)
#define DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) /*!< 0x00001000 */
#define DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk /*!<DAC channel 1 output register status bit */
#define DAC_SR_DMAUDR1_Pos (13U)
#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
#define DAC_SR_CAL_FLAG1_Pos (14U)
#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
#define DAC_SR_BWST1_Pos (15U)
#define DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) /*!< 0x00008000 */
#define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
#define DAC_SR_DAC2RDY_Pos (27U)
#define DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) /*!< 0x08000000 */
#define DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk /*!<DAC channel 2 ready status bit */
#define DAC_SR_DORSTAT2_Pos (28U)
#define DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) /*!< 0x10000000 */
#define DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk /*!<DAC channel 2 output register status bit */
#define DAC_SR_DMAUDR2_Pos (29U)
#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
#define DAC_SR_CAL_FLAG2_Pos (30U)
#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
#define DAC_SR_BWST2_Pos (31U)
#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
#define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
/******************* Bit definition for DAC_CCR register ********************/
#define DAC_CCR_OTRIM1_Pos (0U)
#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
#define DAC_CCR_OTRIM2_Pos (16U)
#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
/******************* Bit definition for DAC_MCR register *******************/
#define DAC_MCR_MODE1_Pos (0U)
#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
#define DAC_MCR_DMADOUBLE1_Pos (8U)
#define DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) /*!< 0x00000100 */
#define DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk /*!<DAC Channel 1 DMA double data mode */
#define DAC_MCR_SINFORMAT1_Pos (9U)
#define DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) /*!< 0x00000200 */
#define DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk /*!<DAC Channel 1 enable signed format */
#define DAC_MCR_HFSEL_Pos (14U)
#define DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) /*!< 0x0000C000 */
#define DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk /*!<HFSEL[1:0] (High Frequency interface mode selection) */
#define DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) /*!< 0x00004000 */
#define DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) /*!< 0x00008000 */
#define DAC_MCR_MODE2_Pos (16U)
#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
#define DAC_MCR_DMADOUBLE2_Pos (24U)
#define DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) /*!< 0x01000000 */
#define DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk /*!<DAC Channel 2 DMA double data mode */
#define DAC_MCR_SINFORMAT2_Pos (25U)
#define DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) /*!< 0x02000000 */
#define DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk /*!<DAC Channel 2 enable signed format */
/****************** Bit definition for DAC_SHSR1 register ******************/
#define DAC_SHSR1_TSAMPLE1_Pos (0U)
#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
/****************** Bit definition for DAC_SHSR2 register ******************/
#define DAC_SHSR2_TSAMPLE2_Pos (0U)
#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
/****************** Bit definition for DAC_SHHR register ******************/
#define DAC_SHHR_THOLD1_Pos (0U)
#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
#define DAC_SHHR_THOLD2_Pos (16U)
#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
/****************** Bit definition for DAC_SHRR register ******************/
#define DAC_SHRR_TREFRESH1_Pos (0U)
#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
#define DAC_SHRR_TREFRESH2_Pos (16U)
#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
/****************** Bit definition for DAC_STR1 register ******************/
#define DAC_STR1_STRSTDATA1_Pos (0U)
#define DAC_STR1_STRSTDATA1_Msk (0xFFFUL << DAC_STR1_STRSTDATA1_Pos) /*!< 0x00000FFF */
#define DAC_STR1_STRSTDATA1 DAC_STR1_STRSTDATA1_Msk /*!<DAC Channel 1 Sawtooth starting value */
#define DAC_STR1_STDIR1_Pos (12U)
#define DAC_STR1_STDIR1_Msk (0x1UL << DAC_STR1_STDIR1_Pos) /*!< 0x00001000 */
#define DAC_STR1_STDIR1 DAC_STR1_STDIR1_Msk /*!<DAC Channel 1 Sawtooth direction setting */
#define DAC_STR1_STINCDATA1_Pos (16U)
#define DAC_STR1_STINCDATA1_Msk (0xFFFFUL << DAC_STR1_STINCDATA1_Pos) /*!< 0xFFFF0000 */
#define DAC_STR1_STINCDATA1 DAC_STR1_STINCDATA1_Msk /*!<DAC Channel 1 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STR2 register ******************/
#define DAC_STR2_STRSTDATA2_Pos (0U)
#define DAC_STR2_STRSTDATA2_Msk (0xFFFUL << DAC_STR2_STRSTDATA2_Pos) /*!< 0x00000FFF */
#define DAC_STR2_STRSTDATA2 DAC_STR2_STRSTDATA2_Msk /*!<DAC Channel 2 Sawtooth starting value */
#define DAC_STR2_STDIR2_Pos (12U)
#define DAC_STR2_STDIR2_Msk (0x1UL << DAC_STR2_STDIR2_Pos) /*!< 0x00001000 */
#define DAC_STR2_STDIR2 DAC_STR2_STDIR2_Msk /*!<DAC Channel 2 Sawtooth direction setting */
#define DAC_STR2_STINCDATA2_Pos (16U)
#define DAC_STR2_STINCDATA2_Msk (0xFFFFUL << DAC_STR2_STINCDATA2_Pos) /*!< 0xFFFF0000 */
#define DAC_STR2_STINCDATA2 DAC_STR2_STINCDATA2_Msk /*!<DAC Channel 2 Sawtooth increment value (12.4 bit format) */
/****************** Bit definition for DAC_STMODR register ****************/
#define DAC_STMODR_STRSTTRIGSEL1_Pos (0U)
#define DAC_STMODR_STRSTTRIGSEL1_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL1 DAC_STMODR_STRSTTRIGSEL1_Msk /*!<STRSTTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL1_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL1_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL1_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL1_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL1_Pos (8U)
#define DAC_STMODR_STINCTRIGSEL1_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL1 DAC_STMODR_STINCTRIGSEL1_Msk /*!<STINCTRIGSEL1[3:0] (DAC Channel 1 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL1_0 (0x1UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL1_1 (0x2UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL1_2 (0x4UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL1_3 (0x8UL << DAC_STMODR_STINCTRIGSEL1_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STRSTTRIGSEL2_Pos (16U)
#define DAC_STMODR_STRSTTRIGSEL2_Msk (0xFUL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STRSTTRIGSEL2 DAC_STMODR_STRSTTRIGSEL2_Msk /*!<STRSTTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STRSTTRIGSEL2_0 (0x1UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STRSTTRIGSEL2_1 (0x2UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STRSTTRIGSEL2_2 (0x4UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STRSTTRIGSEL2_3 (0x8UL << DAC_STMODR_STRSTTRIGSEL2_Pos) /*!< 0x00000008 */
#define DAC_STMODR_STINCTRIGSEL2_Pos (24U)
#define DAC_STMODR_STINCTRIGSEL2_Msk (0xFUL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x0000000F */
#define DAC_STMODR_STINCTRIGSEL2 DAC_STMODR_STINCTRIGSEL2_Msk /*!<STINCTRIGSEL2[3:0] (DAC Channel 2 Sawtooth Increment trigger selection) */
#define DAC_STMODR_STINCTRIGSEL2_0 (0x1UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000001 */
#define DAC_STMODR_STINCTRIGSEL2_1 (0x2UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000002 */
#define DAC_STMODR_STINCTRIGSEL2_2 (0x4UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000004 */
#define DAC_STMODR_STINCTRIGSEL2_3 (0x8UL << DAC_STMODR_STINCTRIGSEL2_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* Debug MCU */
/* */
/******************************************************************************/
/******************** Bit definition for DBGMCU_IDCODE register *************/
#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)/*!< 0x00000FFF */
#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
#define DBGMCU_IDCODE_REV_ID_Pos (16U)
#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)/*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
/******************** Bit definition for DBGMCU_CR register *****************/
#define DBGMCU_CR_DBG_SLEEP_Pos (0U)
#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)/*!< 0x00000001 */
#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
#define DBGMCU_CR_DBG_STOP_Pos (1U)
#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
#define DBGMCU_CR_DBG_STANDBY_Pos (2U)
#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)/*!< 0x00000004 */
#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
#define DBGMCU_CR_TRACE_IOEN_Pos (5U)
#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)/*!< 0x00000020 */
#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
#define DBGMCU_CR_TRACE_MODE_Pos (6U)
#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x000000C0 */
#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000040 */
#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)/*!< 0x00000080 */
/******************** Bit definition for DBGMCU_APB1FZR1 register ***********/
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U)
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos)/*!< 0x00000001 */
#define DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U)
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos)/*!< 0x00000002 */
#define DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U)
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos)/*!< 0x00000004 */
#define DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U)
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos)/*!< 0x00000010 */
#define DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U)
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos)/*!< 0x00000020 */
#define DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos (10U)
#define DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_RTC_STOP_Pos)/*!< 0x00000400 */
#define DBGMCU_APB1FZR1_DBG_RTC_STOP DBGMCU_APB1FZR1_DBG_RTC_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U)
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U)
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos)/*!< 0x00001000 */
#define DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U)
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos)/*!< 0x00200000 */
#define DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U)
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos)/*!< 0x00400000 */
#define DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos (30U)
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C3_STOP_Pos)/*!< 0x40000000 */
#define DBGMCU_APB1FZR1_DBG_I2C3_STOP DBGMCU_APB1FZR1_DBG_I2C3_STOP_Msk
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos (31U)
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Pos)/*!< 0x80000000 */
#define DBGMCU_APB1FZR1_DBG_LPTIM1_STOP DBGMCU_APB1FZR1_DBG_LPTIM1_STOP_Msk
/******************** Bit definition for DBGMCU_APB2FZ register ************/
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos (11U)
#define DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM1_STOP_Pos)/*!< 0x00000800 */
#define DBGMCU_APB2FZ_DBG_TIM1_STOP DBGMCU_APB2FZ_DBG_TIM1_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos (13U)
#define DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM8_STOP_Pos)/*!< 0x00002000 */
#define DBGMCU_APB2FZ_DBG_TIM8_STOP DBGMCU_APB2FZ_DBG_TIM8_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos (16U)
#define DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM15_STOP_Pos)/*!< 0x00010000 */
#define DBGMCU_APB2FZ_DBG_TIM15_STOP DBGMCU_APB2FZ_DBG_TIM15_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos (17U)
#define DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM16_STOP_Pos)/*!< 0x00020000 */
#define DBGMCU_APB2FZ_DBG_TIM16_STOP DBGMCU_APB2FZ_DBG_TIM16_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos (18U)
#define DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM17_STOP_Pos)/*!< 0x00040000 */
#define DBGMCU_APB2FZ_DBG_TIM17_STOP DBGMCU_APB2FZ_DBG_TIM17_STOP_Msk
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos (20U)
#define DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk (0x1UL << DBGMCU_APB2FZ_DBG_TIM20_STOP_Pos)/*!< 0x00100000 */
#define DBGMCU_APB2FZ_DBG_TIM20_STOP DBGMCU_APB2FZ_DBG_TIM20_STOP_Msk
/******************************************************************************/
/* */
/* DMA Controller (DMA) */
/* */
/******************************************************************************/
/******************* Bit definition for DMA_ISR register ********************/
#define DMA_ISR_GIF1_Pos (0U)
#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
#define DMA_ISR_TCIF1_Pos (1U)
#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
#define DMA_ISR_HTIF1_Pos (2U)
#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
#define DMA_ISR_TEIF1_Pos (3U)
#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
#define DMA_ISR_GIF2_Pos (4U)
#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
#define DMA_ISR_TCIF2_Pos (5U)
#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
#define DMA_ISR_HTIF2_Pos (6U)
#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
#define DMA_ISR_TEIF2_Pos (7U)
#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
#define DMA_ISR_GIF3_Pos (8U)
#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
#define DMA_ISR_TCIF3_Pos (9U)
#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
#define DMA_ISR_HTIF3_Pos (10U)
#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
#define DMA_ISR_TEIF3_Pos (11U)
#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
#define DMA_ISR_GIF4_Pos (12U)
#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
#define DMA_ISR_TCIF4_Pos (13U)
#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
#define DMA_ISR_HTIF4_Pos (14U)
#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
#define DMA_ISR_TEIF4_Pos (15U)
#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
#define DMA_ISR_GIF5_Pos (16U)
#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
#define DMA_ISR_TCIF5_Pos (17U)
#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
#define DMA_ISR_HTIF5_Pos (18U)
#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
#define DMA_ISR_TEIF5_Pos (19U)
#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
#define DMA_ISR_GIF6_Pos (20U)
#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
#define DMA_ISR_TCIF6_Pos (21U)
#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
#define DMA_ISR_HTIF6_Pos (22U)
#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
#define DMA_ISR_TEIF6_Pos (23U)
#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
#define DMA_ISR_GIF7_Pos (24U)
#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
#define DMA_ISR_TCIF7_Pos (25U)
#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
#define DMA_ISR_HTIF7_Pos (26U)
#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
#define DMA_ISR_TEIF7_Pos (27U)
#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
#define DMA_ISR_GIF8_Pos (28U)
#define DMA_ISR_GIF8_Msk (0x1UL << DMA_ISR_GIF8_Pos) /*!< 0x10000000 */
#define DMA_ISR_GIF8 DMA_ISR_GIF8_Msk /*!< Channel 8 Global interrupt flag */
#define DMA_ISR_TCIF8_Pos (29U)
#define DMA_ISR_TCIF8_Msk (0x1UL << DMA_ISR_TCIF8_Pos) /*!< 0x20000000 */
#define DMA_ISR_TCIF8 DMA_ISR_TCIF8_Msk /*!< Channel 8 Transfer Complete flag */
#define DMA_ISR_HTIF8_Pos (30U)
#define DMA_ISR_HTIF8_Msk (0x1UL << DMA_ISR_HTIF8_Pos) /*!< 0x40000000 */
#define DMA_ISR_HTIF8 DMA_ISR_HTIF8_Msk /*!< Channel 8 Half Transfer flag */
#define DMA_ISR_TEIF8_Pos (31U)
#define DMA_ISR_TEIF8_Msk (0x1UL << DMA_ISR_TEIF8_Pos) /*!< 0x80000000 */
#define DMA_ISR_TEIF8 DMA_ISR_TEIF8_Msk /*!< Channel 8 Transfer Error flag */
/******************* Bit definition for DMA_IFCR register *******************/
#define DMA_IFCR_CGIF1_Pos (0U)
#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */
#define DMA_IFCR_CTCIF1_Pos (1U)
#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
#define DMA_IFCR_CHTIF1_Pos (2U)
#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
#define DMA_IFCR_CTEIF1_Pos (3U)
#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
#define DMA_IFCR_CGIF2_Pos (4U)
#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
#define DMA_IFCR_CTCIF2_Pos (5U)
#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
#define DMA_IFCR_CHTIF2_Pos (6U)
#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
#define DMA_IFCR_CTEIF2_Pos (7U)
#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
#define DMA_IFCR_CGIF3_Pos (8U)
#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
#define DMA_IFCR_CTCIF3_Pos (9U)
#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
#define DMA_IFCR_CHTIF3_Pos (10U)
#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
#define DMA_IFCR_CTEIF3_Pos (11U)
#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
#define DMA_IFCR_CGIF4_Pos (12U)
#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
#define DMA_IFCR_CTCIF4_Pos (13U)
#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
#define DMA_IFCR_CHTIF4_Pos (14U)
#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
#define DMA_IFCR_CTEIF4_Pos (15U)
#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
#define DMA_IFCR_CGIF5_Pos (16U)
#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
#define DMA_IFCR_CTCIF5_Pos (17U)
#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
#define DMA_IFCR_CHTIF5_Pos (18U)
#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
#define DMA_IFCR_CTEIF5_Pos (19U)
#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
#define DMA_IFCR_CGIF6_Pos (20U)
#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
#define DMA_IFCR_CTCIF6_Pos (21U)
#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
#define DMA_IFCR_CHTIF6_Pos (22U)
#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
#define DMA_IFCR_CTEIF6_Pos (23U)
#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
#define DMA_IFCR_CGIF7_Pos (24U)
#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
#define DMA_IFCR_CTCIF7_Pos (25U)
#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
#define DMA_IFCR_CHTIF7_Pos (26U)
#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
#define DMA_IFCR_CTEIF7_Pos (27U)
#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
#define DMA_IFCR_CGIF8_Pos (28U)
#define DMA_IFCR_CGIF8_Msk (0x1UL << DMA_IFCR_CGIF8_Pos) /*!< 0x10000000 */
#define DMA_IFCR_CGIF8 DMA_IFCR_CGIF8_Msk /*!< Channel 8 Global interrupt clear */
#define DMA_IFCR_CTCIF8_Pos (29U)
#define DMA_IFCR_CTCIF8_Msk (0x1UL << DMA_IFCR_CTCIF8_Pos) /*!< 0x20000000 */
#define DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8_Msk /*!< Channel 8 Transfer Complete clear */
#define DMA_IFCR_CHTIF8_Pos (30U)
#define DMA_IFCR_CHTIF8_Msk (0x1UL << DMA_IFCR_CHTIF8_Pos) /*!< 0x40000000 */
#define DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8_Msk /*!< Channel 8 Half Transfer clear */
#define DMA_IFCR_CTEIF8_Pos (31U)
#define DMA_IFCR_CTEIF8_Msk (0x1UL << DMA_IFCR_CTEIF8_Pos) /*!< 0x80000000 */
#define DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8_Msk /*!< Channel 8 Transfer Error clear */
/******************* Bit definition for DMA_CCR register ********************/
#define DMA_CCR_EN_Pos (0U)
#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
#define DMA_CCR_TCIE_Pos (1U)
#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
#define DMA_CCR_HTIE_Pos (2U)
#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
#define DMA_CCR_TEIE_Pos (3U)
#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
#define DMA_CCR_DIR_Pos (4U)
#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
#define DMA_CCR_CIRC_Pos (5U)
#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
#define DMA_CCR_PINC_Pos (6U)
#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
#define DMA_CCR_MINC_Pos (7U)
#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
#define DMA_CCR_PSIZE_Pos (8U)
#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
#define DMA_CCR_MSIZE_Pos (10U)
#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
#define DMA_CCR_PL_Pos (12U)
#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
#define DMA_CCR_MEM2MEM_Pos (14U)
#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
/****************** Bit definition for DMA_CNDTR register *******************/
#define DMA_CNDTR_NDT_Pos (0U)
#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
/****************** Bit definition for DMA_CPAR register ********************/
#define DMA_CPAR_PA_Pos (0U)
#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
/****************** Bit definition for DMA_CMAR register ********************/
#define DMA_CMAR_MA_Pos (0U)
#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
/******************************************************************************/
/* */
/* DMAMUX Controller */
/* */
/******************************************************************************/
/******************** Bits definition for DMAMUX_CxCR register **************/
#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x000000FF */
#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000020 */
#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000040 */
#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)/*!< 0x00000080 */
#define DMAMUX_CxCR_SOIE_Pos (8U)
#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)/*!< 0x00000100 */
#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
#define DMAMUX_CxCR_EGE_Pos (9U)
#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)/*!< 0x00000200 */
#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
#define DMAMUX_CxCR_SE_Pos (16U)
#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)/*!< 0x00010000 */
#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
#define DMAMUX_CxCR_SPOL_Pos (17U)
#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_CxCR_NBREQ_Pos (19U)
#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)/*!< 0x00800000 */
#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x1F000000 */
#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x01000000 */
#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x02000000 */
#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x04000000 */
#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x08000000 */
#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)/*!< 0x10000000 */
/******************** Bits definition for DMAMUX_CSR register ****************/
#define DMAMUX_CSR_SOF0_Pos (0U)
#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
#define DMAMUX_CSR_SOF1_Pos (1U)
#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
#define DMAMUX_CSR_SOF2_Pos (2U)
#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
#define DMAMUX_CSR_SOF3_Pos (3U)
#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
#define DMAMUX_CSR_SOF4_Pos (4U)
#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
#define DMAMUX_CSR_SOF5_Pos (5U)
#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
#define DMAMUX_CSR_SOF6_Pos (6U)
#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
#define DMAMUX_CSR_SOF7_Pos (7U)
#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
#define DMAMUX_CSR_SOF8_Pos (8U)
#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
#define DMAMUX_CSR_SOF9_Pos (9U)
#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
#define DMAMUX_CSR_SOF10_Pos (10U)
#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
#define DMAMUX_CSR_SOF11_Pos (11U)
#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
#define DMAMUX_CSR_SOF12_Pos (12U)
#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
#define DMAMUX_CSR_SOF13_Pos (13U)
#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
#define DMAMUX_CSR_SOF14_Pos (14U)
#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
#define DMAMUX_CSR_SOF15_Pos (15U)
#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
/******************** Bits definition for DMAMUX_CFR register ****************/
#define DMAMUX_CFR_CSOF0_Pos (0U)
#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)/*!< 0x00000001 */
#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
#define DMAMUX_CFR_CSOF1_Pos (1U)
#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)/*!< 0x00000002 */
#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
#define DMAMUX_CFR_CSOF2_Pos (2U)
#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)/*!< 0x00000004 */
#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
#define DMAMUX_CFR_CSOF3_Pos (3U)
#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)/*!< 0x00000008 */
#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
#define DMAMUX_CFR_CSOF4_Pos (4U)
#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)/*!< 0x00000010 */
#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
#define DMAMUX_CFR_CSOF5_Pos (5U)
#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)/*!< 0x00000020 */
#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
#define DMAMUX_CFR_CSOF6_Pos (6U)
#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)/*!< 0x00000040 */
#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
#define DMAMUX_CFR_CSOF7_Pos (7U)
#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)/*!< 0x00000080 */
#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
#define DMAMUX_CFR_CSOF8_Pos (8U)
#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)/*!< 0x00000100 */
#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
#define DMAMUX_CFR_CSOF9_Pos (9U)
#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)/*!< 0x00000200 */
#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
#define DMAMUX_CFR_CSOF10_Pos (10U)
#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)/*!< 0x00000400 */
#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
#define DMAMUX_CFR_CSOF11_Pos (11U)
#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)/*!< 0x00000800 */
#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
#define DMAMUX_CFR_CSOF12_Pos (12U)
#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)/*!< 0x00001000 */
#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
#define DMAMUX_CFR_CSOF13_Pos (13U)
#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)/*!< 0x00002000 */
#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
#define DMAMUX_CFR_CSOF14_Pos (14U)
#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)/*!< 0x00004000 */
#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
#define DMAMUX_CFR_CSOF15_Pos (15U)
#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)/*!< 0x00008000 */
#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
/******************** Bits definition for DMAMUX_RGxCR register ************/
#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x0000001F */
#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000001 */
#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000002 */
#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000004 */
#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000008 */
#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)/*!< 0x00000010 */
#define DMAMUX_RGxCR_OIE_Pos (8U)
#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)/*!< 0x00000100 */
#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
#define DMAMUX_RGxCR_GE_Pos (16U)
#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)/*!< 0x00010000 */
#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
#define DMAMUX_RGxCR_GPOL_Pos (17U)
#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00060000 */
#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00020000 */
#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)/*!< 0x00040000 */
#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00F80000 */
#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00080000 */
#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00100000 */
#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00200000 */
#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00400000 */
#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)/*!< 0x00800000 */
/******************** Bits definition for DMAMUX_RGSR register **************/
#define DMAMUX_RGSR_OF0_Pos (0U)
#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
#define DMAMUX_RGSR_OF1_Pos (1U)
#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
#define DMAMUX_RGSR_OF2_Pos (2U)
#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
#define DMAMUX_RGSR_OF3_Pos (3U)
#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
/******************** Bits definition for DMAMUX_RGCFR register ************/
#define DMAMUX_RGCFR_COF0_Pos (0U)
#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)/*!< 0x00000001 */
#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
#define DMAMUX_RGCFR_COF1_Pos (1U)
#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)/*!< 0x00000002 */
#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
#define DMAMUX_RGCFR_COF2_Pos (2U)
#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)/*!< 0x00000004 */
#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
#define DMAMUX_RGCFR_COF3_Pos (3U)
#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)/*!< 0x00000008 */
#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR2 ******************/
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos (0U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ0_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos (1U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ1_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos (2U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ2_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos (3U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ3_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos (4U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ4_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos (5U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ5_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos (6U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ6_Msk
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos (7U)
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7 DMAMUX_IPHW_CFGR2_NUM_DMA_EXT_REQ7_Msk
/******************** Bits definition for DMAMUX_IPHW_CFGR1 ******************/
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos (0U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Pos)/*!< 0x00000001 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos (1U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Pos)/*!< 0x00000002 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos (2U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Pos)/*!< 0x00000004 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos (3U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Pos)/*!< 0x00000008 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos (4U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Pos)/*!< 0x00000010 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos (5U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Pos)/*!< 0x00000020 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos (6U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Pos)/*!< 0x00000040 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos (7U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Pos)/*!< 0x00000080 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7 DMAMUX_IPHW_CFGR1_NUM_DMA_STREAMS7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos (8U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Pos)/*!< 0x00000100 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos (9U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Pos)/*!< 0x00000200 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos (10U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Pos)/*!< 0x00000400 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos (11U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Pos)/*!< 0x00000800 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos (12U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Pos)/*!< 0x00001000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos (13U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Pos)/*!< 0x00002000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos (14U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Pos)/*!< 0x00004000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos (15U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Pos)/*!< 0x00008000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7 DMAMUX_IPHW_CFGR1_NUM_DMA_PERIPH_REQ7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos (16U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Pos)/*!< 0x00010000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos (17U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Pos)/*!< 0x00020000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos (18U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Pos)/*!< 0x00040000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos (19U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Pos)/*!< 0x00080000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos (20U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Pos)/*!< 0x00100000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos (21U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Pos)/*!< 0x00200000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos (22U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Pos)/*!< 0x00400000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos (23U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Pos)/*!< 0x00800000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7 DMAMUX_IPHW_CFGR1_NUM_DMA_TRIG7_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos (24U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Pos)/*!< 0x01000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN0_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos (25U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Pos)/*!< 0x02000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN1_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos (26U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Pos)/*!< 0x04000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN2_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos (27U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Pos)/*!< 0x08000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN3_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos (28U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Pos)/*!< 0x10000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN4_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos (29U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Pos)/*!< 0x20000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN5_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos (30U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Pos)/*!< 0x40000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN6_Msk
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos (31U)
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk (0x1UL << DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Pos)/*!< 0x80000000 */
#define DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7 DMAMUX_IPHW_CFGR1_NUM_DMA_REQGEN7_Msk
/******************************************************************************/
/* */
/* External Interrupt/Event Controller */
/* */
/******************************************************************************/
/******************* Bit definition for EXTI_IMR1 register ******************/
#define EXTI_IMR1_IM0_Pos (0U)
#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
#define EXTI_IMR1_IM1_Pos (1U)
#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
#define EXTI_IMR1_IM2_Pos (2U)
#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
#define EXTI_IMR1_IM3_Pos (3U)
#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
#define EXTI_IMR1_IM4_Pos (4U)
#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
#define EXTI_IMR1_IM5_Pos (5U)
#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
#define EXTI_IMR1_IM6_Pos (6U)
#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
#define EXTI_IMR1_IM7_Pos (7U)
#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
#define EXTI_IMR1_IM8_Pos (8U)
#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
#define EXTI_IMR1_IM9_Pos (9U)
#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
#define EXTI_IMR1_IM10_Pos (10U)
#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
#define EXTI_IMR1_IM11_Pos (11U)
#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
#define EXTI_IMR1_IM12_Pos (12U)
#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
#define EXTI_IMR1_IM13_Pos (13U)
#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
#define EXTI_IMR1_IM14_Pos (14U)
#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
#define EXTI_IMR1_IM15_Pos (15U)
#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
#define EXTI_IMR1_IM16_Pos (16U)
#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
#define EXTI_IMR1_IM17_Pos (17U)
#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
#define EXTI_IMR1_IM18_Pos (18U)
#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
#define EXTI_IMR1_IM19_Pos (19U)
#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
#define EXTI_IMR1_IM20_Pos (20U)
#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
#define EXTI_IMR1_IM21_Pos (21U)
#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
#define EXTI_IMR1_IM22_Pos (22U)
#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
#define EXTI_IMR1_IM23_Pos (23U)
#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
#define EXTI_IMR1_IM24_Pos (24U)
#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
#define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
#define EXTI_IMR1_IM29_Pos (29U)
#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
#define EXTI_IMR1_IM30_Pos (30U)
#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
#define EXTI_IMR1_IM_Pos (0U)
#define EXTI_IMR1_IM_Msk (0x7FFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0x7FFFFFFF */
#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask All */
/******************* Bit definition for EXTI_EMR1 register ******************/
#define EXTI_EMR1_EM0_Pos (0U)
#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
#define EXTI_EMR1_EM1_Pos (1U)
#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
#define EXTI_EMR1_EM2_Pos (2U)
#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
#define EXTI_EMR1_EM3_Pos (3U)
#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
#define EXTI_EMR1_EM4_Pos (4U)
#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
#define EXTI_EMR1_EM5_Pos (5U)
#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
#define EXTI_EMR1_EM6_Pos (6U)
#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
#define EXTI_EMR1_EM7_Pos (7U)
#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
#define EXTI_EMR1_EM8_Pos (8U)
#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
#define EXTI_EMR1_EM9_Pos (9U)
#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
#define EXTI_EMR1_EM10_Pos (10U)
#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
#define EXTI_EMR1_EM11_Pos (11U)
#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
#define EXTI_EMR1_EM12_Pos (12U)
#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
#define EXTI_EMR1_EM13_Pos (13U)
#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
#define EXTI_EMR1_EM14_Pos (14U)
#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
#define EXTI_EMR1_EM15_Pos (15U)
#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
#define EXTI_EMR1_EM16_Pos (16U)
#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
#define EXTI_EMR1_EM17_Pos (17U)
#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
#define EXTI_EMR1_EM18_Pos (18U)
#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
#define EXTI_EMR1_EM19_Pos (19U)
#define EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) /*!< 0x00080000 */
#define EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk /*!< Event Mask on line 19 */
#define EXTI_EMR1_EM20_Pos (20U)
#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
#define EXTI_EMR1_EM21_Pos (21U)
#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
#define EXTI_EMR1_EM22_Pos (22U)
#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
#define EXTI_EMR1_EM23_Pos (23U)
#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
#define EXTI_EMR1_EM24_Pos (24U)
#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
#define EXTI_EMR1_EM25_Pos (25U)
#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
#define EXTI_EMR1_EM26_Pos (26U)
#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
#define EXTI_EMR1_EM27_Pos (27U)
#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
#define EXTI_EMR1_EM28_Pos (28U)
#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
#define EXTI_EMR1_EM29_Pos (29U)
#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
#define EXTI_EMR1_EM30_Pos (30U)
#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
/****************** Bit definition for EXTI_RTSR1 register ******************/
#define EXTI_RTSR1_RT0_Pos (0U)
#define EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) /*!< 0x00000001 */
#define EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */
#define EXTI_RTSR1_RT1_Pos (1U)
#define EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) /*!< 0x00000002 */
#define EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */
#define EXTI_RTSR1_RT2_Pos (2U)
#define EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) /*!< 0x00000004 */
#define EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */
#define EXTI_RTSR1_RT3_Pos (3U)
#define EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) /*!< 0x00000008 */
#define EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */
#define EXTI_RTSR1_RT4_Pos (4U)
#define EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) /*!< 0x00000010 */
#define EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */
#define EXTI_RTSR1_RT5_Pos (5U)
#define EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) /*!< 0x00000020 */
#define EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */
#define EXTI_RTSR1_RT6_Pos (6U)
#define EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) /*!< 0x00000040 */
#define EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */
#define EXTI_RTSR1_RT7_Pos (7U)
#define EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) /*!< 0x00000080 */
#define EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */
#define EXTI_RTSR1_RT8_Pos (8U)
#define EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) /*!< 0x00000100 */
#define EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */
#define EXTI_RTSR1_RT9_Pos (9U)
#define EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) /*!< 0x00000200 */
#define EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */
#define EXTI_RTSR1_RT10_Pos (10U)
#define EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) /*!< 0x00000400 */
#define EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */
#define EXTI_RTSR1_RT11_Pos (11U)
#define EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) /*!< 0x00000800 */
#define EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */
#define EXTI_RTSR1_RT12_Pos (12U)
#define EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) /*!< 0x00001000 */
#define EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */
#define EXTI_RTSR1_RT13_Pos (13U)
#define EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) /*!< 0x00002000 */
#define EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */
#define EXTI_RTSR1_RT14_Pos (14U)
#define EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) /*!< 0x00004000 */
#define EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */
#define EXTI_RTSR1_RT15_Pos (15U)
#define EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) /*!< 0x00008000 */
#define EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */
#define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT19_Pos (19U)
#define EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) /*!< 0x00080000 */
#define EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR1_RT20_Pos (20U)
#define EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) /*!< 0x00100000 */
#define EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR1_RT21_Pos (21U)
#define EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) /*!< 0x00200000 */
#define EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR1_RT22_Pos (22U)
#define EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) /*!< 0x00400000 */
#define EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */
#define EXTI_RTSR1_RT29_Pos (29U)
#define EXTI_RTSR1_RT29_Msk (0x1UL << EXTI_RTSR1_RT29_Pos) /*!< 0x20000000 */
#define EXTI_RTSR1_RT29 EXTI_RTSR1_RT29_Msk /*!< Rising trigger event configuration bit of line 29 */
#define EXTI_RTSR1_RT30_Pos (30U)
#define EXTI_RTSR1_RT30_Msk (0x1UL << EXTI_RTSR1_RT30_Pos) /*!< 0x40000000 */
#define EXTI_RTSR1_RT30 EXTI_RTSR1_RT30_Msk /*!< Rising trigger event configuration bit of line 30 */
/****************** Bit definition for EXTI_FTSR1 register ******************/
#define EXTI_FTSR1_FT0_Pos (0U)
#define EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) /*!< 0x00000001 */
#define EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */
#define EXTI_FTSR1_FT1_Pos (1U)
#define EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) /*!< 0x00000002 */
#define EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */
#define EXTI_FTSR1_FT2_Pos (2U)
#define EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) /*!< 0x00000004 */
#define EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */
#define EXTI_FTSR1_FT3_Pos (3U)
#define EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) /*!< 0x00000008 */
#define EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */
#define EXTI_FTSR1_FT4_Pos (4U)
#define EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) /*!< 0x00000010 */
#define EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */
#define EXTI_FTSR1_FT5_Pos (5U)
#define EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) /*!< 0x00000020 */
#define EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */
#define EXTI_FTSR1_FT6_Pos (6U)
#define EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) /*!< 0x00000040 */
#define EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */
#define EXTI_FTSR1_FT7_Pos (7U)
#define EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) /*!< 0x00000080 */
#define EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */
#define EXTI_FTSR1_FT8_Pos (8U)
#define EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) /*!< 0x00000100 */
#define EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */
#define EXTI_FTSR1_FT9_Pos (9U)
#define EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) /*!< 0x00000200 */
#define EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */
#define EXTI_FTSR1_FT10_Pos (10U)
#define EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) /*!< 0x00000400 */
#define EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */
#define EXTI_FTSR1_FT11_Pos (11U)
#define EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) /*!< 0x00000800 */
#define EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */
#define EXTI_FTSR1_FT12_Pos (12U)
#define EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) /*!< 0x00001000 */
#define EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */
#define EXTI_FTSR1_FT13_Pos (13U)
#define EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) /*!< 0x00002000 */
#define EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */
#define EXTI_FTSR1_FT14_Pos (14U)
#define EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) /*!< 0x00004000 */
#define EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */
#define EXTI_FTSR1_FT15_Pos (15U)
#define EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) /*!< 0x00008000 */
#define EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */
#define EXTI_FTSR1_FT16_Pos (16U)
#define EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) /*!< 0x00010000 */
#define EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR1_FT17_Pos (17U)
#define EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) /*!< 0x00020000 */
#define EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR1_FT19_Pos (19U)
#define EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) /*!< 0x00080000 */
#define EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR1_FT20_Pos (20U)
#define EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) /*!< 0x00100000 */
#define EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR1_FT21_Pos (21U)
#define EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) /*!< 0x00200000 */
#define EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR1_FT22_Pos (22U)
#define EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) /*!< 0x00400000 */
#define EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */
#define EXTI_FTSR1_FT29_Pos (29U)
#define EXTI_FTSR1_FT29_Msk (0x1UL << EXTI_FTSR1_FT29_Pos) /*!< 0x20000000 */
#define EXTI_FTSR1_FT29 EXTI_FTSR1_FT29_Msk /*!< Falling trigger event configuration bit of line 29 */
#define EXTI_FTSR1_FT30_Pos (30U)
#define EXTI_FTSR1_FT30_Msk (0x1UL << EXTI_FTSR1_FT30_Pos) /*!< 0x40000000 */
#define EXTI_FTSR1_FT30 EXTI_FTSR1_FT30_Msk /*!< Falling trigger event configuration bit of line 30 */
/****************** Bit definition for EXTI_SWIER1 register *****************/
#define EXTI_SWIER1_SWI0_Pos (0U)
#define EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) /*!< 0x00000001 */
#define EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk /*!< Software Interrupt on line 0 */
#define EXTI_SWIER1_SWI1_Pos (1U)
#define EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) /*!< 0x00000002 */
#define EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk /*!< Software Interrupt on line 1 */
#define EXTI_SWIER1_SWI2_Pos (2U)
#define EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) /*!< 0x00000004 */
#define EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk /*!< Software Interrupt on line 2 */
#define EXTI_SWIER1_SWI3_Pos (3U)
#define EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) /*!< 0x00000008 */
#define EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk /*!< Software Interrupt on line 3 */
#define EXTI_SWIER1_SWI4_Pos (4U)
#define EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) /*!< 0x00000010 */
#define EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk /*!< Software Interrupt on line 4 */
#define EXTI_SWIER1_SWI5_Pos (5U)
#define EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) /*!< 0x00000020 */
#define EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk /*!< Software Interrupt on line 5 */
#define EXTI_SWIER1_SWI6_Pos (6U)
#define EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) /*!< 0x00000040 */
#define EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk /*!< Software Interrupt on line 6 */
#define EXTI_SWIER1_SWI7_Pos (7U)
#define EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) /*!< 0x00000080 */
#define EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk /*!< Software Interrupt on line 7 */
#define EXTI_SWIER1_SWI8_Pos (8U)
#define EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) /*!< 0x00000100 */
#define EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk /*!< Software Interrupt on line 8 */
#define EXTI_SWIER1_SWI9_Pos (9U)
#define EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) /*!< 0x00000200 */
#define EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk /*!< Software Interrupt on line 9 */
#define EXTI_SWIER1_SWI10_Pos (10U)
#define EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) /*!< 0x00000400 */
#define EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk /*!< Software Interrupt on line 10 */
#define EXTI_SWIER1_SWI11_Pos (11U)
#define EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) /*!< 0x00000800 */
#define EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk /*!< Software Interrupt on line 11 */
#define EXTI_SWIER1_SWI12_Pos (12U)
#define EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) /*!< 0x00001000 */
#define EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk /*!< Software Interrupt on line 12 */
#define EXTI_SWIER1_SWI13_Pos (13U)
#define EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) /*!< 0x00002000 */
#define EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk /*!< Software Interrupt on line 13 */
#define EXTI_SWIER1_SWI14_Pos (14U)
#define EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) /*!< 0x00004000 */
#define EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk /*!< Software Interrupt on line 14 */
#define EXTI_SWIER1_SWI15_Pos (15U)
#define EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) /*!< 0x00008000 */
#define EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk /*!< Software Interrupt on line 15 */
#define EXTI_SWIER1_SWI16_Pos (16U)
#define EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) /*!< 0x00010000 */
#define EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk /*!< Software Interrupt on line 16 */
#define EXTI_SWIER1_SWI17_Pos (17U)
#define EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) /*!< 0x00020000 */
#define EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk /*!< Software Interrupt on line 17 */
#define EXTI_SWIER1_SWI19_Pos (19U)
#define EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) /*!< 0x00080000 */
#define EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk /*!< Software Interrupt on line 19 */
#define EXTI_SWIER1_SWI20_Pos (20U)
#define EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) /*!< 0x00100000 */
#define EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk /*!< Software Interrupt on line 20 */
#define EXTI_SWIER1_SWI21_Pos (21U)
#define EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) /*!< 0x00200000 */
#define EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk /*!< Software Interrupt on line 21 */
#define EXTI_SWIER1_SWI22_Pos (22U)
#define EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) /*!< 0x00400000 */
#define EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk /*!< Software Interrupt on line 22 */
#define EXTI_SWIER1_SWI29_Pos (29U)
#define EXTI_SWIER1_SWI29_Msk (0x1UL << EXTI_SWIER1_SWI29_Pos) /*!< 0x20000000 */
#define EXTI_SWIER1_SWI29 EXTI_SWIER1_SWI29_Msk /*!< Software Interrupt on line 29 */
#define EXTI_SWIER1_SWI30_Pos (30U)
#define EXTI_SWIER1_SWI30_Msk (0x1UL << EXTI_SWIER1_SWI30_Pos) /*!< 0x40000000 */
#define EXTI_SWIER1_SWI30 EXTI_SWIER1_SWI30_Msk /*!< Software Interrupt on line 30 */
/******************* Bit definition for EXTI_PR1 register *******************/
#define EXTI_PR1_PIF0_Pos (0U)
#define EXTI_PR1_PIF0_Msk (0x1UL << EXTI_PR1_PIF0_Pos) /*!< 0x00000001 */
#define EXTI_PR1_PIF0 EXTI_PR1_PIF0_Msk /*!< Pending bit for line 0 */
#define EXTI_PR1_PIF1_Pos (1U)
#define EXTI_PR1_PIF1_Msk (0x1UL << EXTI_PR1_PIF1_Pos) /*!< 0x00000002 */
#define EXTI_PR1_PIF1 EXTI_PR1_PIF1_Msk /*!< Pending bit for line 1 */
#define EXTI_PR1_PIF2_Pos (2U)
#define EXTI_PR1_PIF2_Msk (0x1UL << EXTI_PR1_PIF2_Pos) /*!< 0x00000004 */
#define EXTI_PR1_PIF2 EXTI_PR1_PIF2_Msk /*!< Pending bit for line 2 */
#define EXTI_PR1_PIF3_Pos (3U)
#define EXTI_PR1_PIF3_Msk (0x1UL << EXTI_PR1_PIF3_Pos) /*!< 0x00000008 */
#define EXTI_PR1_PIF3 EXTI_PR1_PIF3_Msk /*!< Pending bit for line 3 */
#define EXTI_PR1_PIF4_Pos (4U)
#define EXTI_PR1_PIF4_Msk (0x1UL << EXTI_PR1_PIF4_Pos) /*!< 0x00000010 */
#define EXTI_PR1_PIF4 EXTI_PR1_PIF4_Msk /*!< Pending bit for line 4 */
#define EXTI_PR1_PIF5_Pos (5U)
#define EXTI_PR1_PIF5_Msk (0x1UL << EXTI_PR1_PIF5_Pos) /*!< 0x00000020 */
#define EXTI_PR1_PIF5 EXTI_PR1_PIF5_Msk /*!< Pending bit for line 5 */
#define EXTI_PR1_PIF6_Pos (6U)
#define EXTI_PR1_PIF6_Msk (0x1UL << EXTI_PR1_PIF6_Pos) /*!< 0x00000040 */
#define EXTI_PR1_PIF6 EXTI_PR1_PIF6_Msk /*!< Pending bit for line 6 */
#define EXTI_PR1_PIF7_Pos (7U)
#define EXTI_PR1_PIF7_Msk (0x1UL << EXTI_PR1_PIF7_Pos) /*!< 0x00000080 */
#define EXTI_PR1_PIF7 EXTI_PR1_PIF7_Msk /*!< Pending bit for line 7 */
#define EXTI_PR1_PIF8_Pos (8U)
#define EXTI_PR1_PIF8_Msk (0x1UL << EXTI_PR1_PIF8_Pos) /*!< 0x00000100 */
#define EXTI_PR1_PIF8 EXTI_PR1_PIF8_Msk /*!< Pending bit for line 8 */
#define EXTI_PR1_PIF9_Pos (9U)
#define EXTI_PR1_PIF9_Msk (0x1UL << EXTI_PR1_PIF9_Pos) /*!< 0x00000200 */
#define EXTI_PR1_PIF9 EXTI_PR1_PIF9_Msk /*!< Pending bit for line 9 */
#define EXTI_PR1_PIF10_Pos (10U)
#define EXTI_PR1_PIF10_Msk (0x1UL << EXTI_PR1_PIF10_Pos) /*!< 0x00000400 */
#define EXTI_PR1_PIF10 EXTI_PR1_PIF10_Msk /*!< Pending bit for line 10 */
#define EXTI_PR1_PIF11_Pos (11U)
#define EXTI_PR1_PIF11_Msk (0x1UL << EXTI_PR1_PIF11_Pos) /*!< 0x00000800 */
#define EXTI_PR1_PIF11 EXTI_PR1_PIF11_Msk /*!< Pending bit for line 11 */
#define EXTI_PR1_PIF12_Pos (12U)
#define EXTI_PR1_PIF12_Msk (0x1UL << EXTI_PR1_PIF12_Pos) /*!< 0x00001000 */
#define EXTI_PR1_PIF12 EXTI_PR1_PIF12_Msk /*!< Pending bit for line 12 */
#define EXTI_PR1_PIF13_Pos (13U)
#define EXTI_PR1_PIF13_Msk (0x1UL << EXTI_PR1_PIF13_Pos) /*!< 0x00002000 */
#define EXTI_PR1_PIF13 EXTI_PR1_PIF13_Msk /*!< Pending bit for line 13 */
#define EXTI_PR1_PIF14_Pos (14U)
#define EXTI_PR1_PIF14_Msk (0x1UL << EXTI_PR1_PIF14_Pos) /*!< 0x00004000 */
#define EXTI_PR1_PIF14 EXTI_PR1_PIF14_Msk /*!< Pending bit for line 14 */
#define EXTI_PR1_PIF15_Pos (15U)
#define EXTI_PR1_PIF15_Msk (0x1UL << EXTI_PR1_PIF15_Pos) /*!< 0x00008000 */
#define EXTI_PR1_PIF15 EXTI_PR1_PIF15_Msk /*!< Pending bit for line 15 */
#define EXTI_PR1_PIF16_Pos (16U)
#define EXTI_PR1_PIF16_Msk (0x1UL << EXTI_PR1_PIF16_Pos) /*!< 0x00010000 */
#define EXTI_PR1_PIF16 EXTI_PR1_PIF16_Msk /*!< Pending bit for line 16 */
#define EXTI_PR1_PIF17_Pos (17U)
#define EXTI_PR1_PIF17_Msk (0x1UL << EXTI_PR1_PIF17_Pos) /*!< 0x00020000 */
#define EXTI_PR1_PIF17 EXTI_PR1_PIF17_Msk /*!< Pending bit for line 17 */
#define EXTI_PR1_PIF19_Pos (19U)
#define EXTI_PR1_PIF19_Msk (0x1UL << EXTI_PR1_PIF19_Pos) /*!< 0x00080000 */
#define EXTI_PR1_PIF19 EXTI_PR1_PIF19_Msk /*!< Pending bit for line 19 */
#define EXTI_PR1_PIF20_Pos (20U)
#define EXTI_PR1_PIF20_Msk (0x1UL << EXTI_PR1_PIF20_Pos) /*!< 0x00100000 */
#define EXTI_PR1_PIF20 EXTI_PR1_PIF20_Msk /*!< Pending bit for line 20 */
#define EXTI_PR1_PIF21_Pos (21U)
#define EXTI_PR1_PIF21_Msk (0x1UL << EXTI_PR1_PIF21_Pos) /*!< 0x00200000 */
#define EXTI_PR1_PIF21 EXTI_PR1_PIF21_Msk /*!< Pending bit for line 21 */
#define EXTI_PR1_PIF22_Pos (22U)
#define EXTI_PR1_PIF22_Msk (0x1UL << EXTI_PR1_PIF22_Pos) /*!< 0x00400000 */
#define EXTI_PR1_PIF22 EXTI_PR1_PIF22_Msk /*!< Pending bit for line 22 */
#define EXTI_PR1_PIF29_Pos (29U)
#define EXTI_PR1_PIF29_Msk (0x1UL << EXTI_PR1_PIF29_Pos) /*!< 0x20000000 */
#define EXTI_PR1_PIF29 EXTI_PR1_PIF29_Msk /*!< Pending bit for line 29 */
#define EXTI_PR1_PIF30_Pos (30U)
#define EXTI_PR1_PIF30_Msk (0x1UL << EXTI_PR1_PIF30_Pos) /*!< 0x40000000 */
#define EXTI_PR1_PIF30 EXTI_PR1_PIF30_Msk /*!< Pending bit for line 30 */
/******************* Bit definition for EXTI_IMR2 register ******************/
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
#define EXTI_IMR2_IM37_Pos (5U)
#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
#define EXTI_IMR2_IM38_Pos (6U)
#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
#define EXTI_IMR2_IM39_Pos (7U)
#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
#define EXTI_IMR2_IM40_Pos (8U)
#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
#define EXTI_IMR2_IM41_Pos (9U)
#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
#define EXTI_IMR2_IM_Pos (0U)
#define EXTI_IMR2_IM_Msk (0x2FCUL << EXTI_IMR2_IM_Pos) /*!< 0x000002FC */
#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask all */
/******************* Bit definition for EXTI_EMR2 register ******************/
#define EXTI_EMR2_EM34_Pos (2U)
#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34 */
#define EXTI_EMR2_EM36_Pos (4U)
#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36 */
#define EXTI_EMR2_EM37_Pos (5U)
#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37 */
#define EXTI_EMR2_EM38_Pos (6U)
#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38 */
#define EXTI_EMR2_EM39_Pos (7U)
#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39 */
#define EXTI_EMR2_EM40_Pos (8U)
#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40 */
#define EXTI_EMR2_EM41_Pos (9U)
#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41 */
#define EXTI_EMR2_EM_Pos (0U)
#define EXTI_EMR2_EM_Msk (0x2FCUL << EXTI_EMR2_EM_Pos) /*!< 0x000002FC */
#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Interrupt Mask all */
/****************** Bit definition for EXTI_RTSR2 register ******************/
#define EXTI_RTSR2_RT38_Pos (6U)
#define EXTI_RTSR2_RT38_Msk (0x1UL << EXTI_RTSR2_RT38_Pos) /*!< 0x00000040 */
#define EXTI_RTSR2_RT38 EXTI_RTSR2_RT38_Msk /*!< Rising trigger event configuration bit of line 38 */
#define EXTI_RTSR2_RT39_Pos (7U)
#define EXTI_RTSR2_RT39_Msk (0x1UL << EXTI_RTSR2_RT39_Pos) /*!< 0x00000080 */
#define EXTI_RTSR2_RT39 EXTI_RTSR2_RT39_Msk /*!< Rising trigger event configuration bit of line 39 */
#define EXTI_RTSR2_RT40_Pos (8U)
#define EXTI_RTSR2_RT40_Msk (0x1UL << EXTI_RTSR2_RT40_Pos) /*!< 0x00000100 */
#define EXTI_RTSR2_RT40 EXTI_RTSR2_RT40_Msk /*!< Rising trigger event configuration bit of line 40 */
#define EXTI_RTSR2_RT41_Pos (9U)
#define EXTI_RTSR2_RT41_Msk (0x1UL << EXTI_RTSR2_RT41_Pos) /*!< 0x00000200 */
#define EXTI_RTSR2_RT41 EXTI_RTSR2_RT41_Msk /*!< Rising trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_FTSR2 register ******************/
#define EXTI_FTSR2_FT38_Pos (6U)
#define EXTI_FTSR2_FT38_Msk (0x1UL << EXTI_FTSR2_FT38_Pos) /*!< 0x00000040 */
#define EXTI_FTSR2_FT38 EXTI_FTSR2_FT38_Msk /*!< Falling trigger event configuration bit of line 37 */
#define EXTI_FTSR2_FT39_Pos (7U)
#define EXTI_FTSR2_FT39_Msk (0x1UL << EXTI_FTSR2_FT39_Pos) /*!< 0x00000080 */
#define EXTI_FTSR2_FT39 EXTI_FTSR2_FT39_Msk /*!< Falling trigger event configuration bit of line 39 */
#define EXTI_FTSR2_FT40_Pos (8U)
#define EXTI_FTSR2_FT40_Msk (0x1UL << EXTI_FTSR2_FT40_Pos) /*!< 0x00000100 */
#define EXTI_FTSR2_FT40 EXTI_FTSR2_FT40_Msk /*!< Falling trigger event configuration bit of line 40 */
#define EXTI_FTSR2_FT41_Pos (9U)
#define EXTI_FTSR2_FT41_Msk (0x1UL << EXTI_FTSR2_FT41_Pos) /*!< 0x00000200 */
#define EXTI_FTSR2_FT41 EXTI_FTSR2_FT41_Msk /*!< Falling trigger event configuration bit of line 41 */
/****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI38_Pos (6U)
#define EXTI_SWIER2_SWI38_Msk (0x1UL << EXTI_SWIER2_SWI38_Pos) /*!< 0x00000040 */
#define EXTI_SWIER2_SWI38 EXTI_SWIER2_SWI38_Msk /*!< Software Interrupt on line 38 */
#define EXTI_SWIER2_SWI39_Pos (7U)
#define EXTI_SWIER2_SWI39_Msk (0x1UL << EXTI_SWIER2_SWI39_Pos) /*!< 0x00000080 */
#define EXTI_SWIER2_SWI39 EXTI_SWIER2_SWI39_Msk /*!< Software Interrupt on line 39 */
#define EXTI_SWIER2_SWI40_Pos (8U)
#define EXTI_SWIER2_SWI40_Msk (0x1UL << EXTI_SWIER2_SWI40_Pos) /*!< 0x00000100 */
#define EXTI_SWIER2_SWI40 EXTI_SWIER2_SWI40_Msk /*!< Software Interrupt on line 40 */
#define EXTI_SWIER2_SWI41_Pos (9U)
#define EXTI_SWIER2_SWI41_Msk (0x1UL << EXTI_SWIER2_SWI41_Pos) /*!< 0x00000200 */
#define EXTI_SWIER2_SWI41 EXTI_SWIER2_SWI41_Msk /*!< Software Interrupt on line 41 */
/******************* Bit definition for EXTI_PR2 register *******************/
#define EXTI_PR2_PIF38_Pos (6U)
#define EXTI_PR2_PIF38_Msk (0x1UL << EXTI_PR2_PIF38_Pos) /*!< 0x00000040 */
#define EXTI_PR2_PIF38 EXTI_PR2_PIF38_Msk /*!< Pending bit for line 38 */
#define EXTI_PR2_PIF39_Pos (7U)
#define EXTI_PR2_PIF39_Msk (0x1UL << EXTI_PR2_PIF39_Pos) /*!< 0x00000080 */
#define EXTI_PR2_PIF39 EXTI_PR2_PIF39_Msk /*!< Pending bit for line 39 */
#define EXTI_PR2_PIF40_Pos (8U)
#define EXTI_PR2_PIF40_Msk (0x1UL << EXTI_PR2_PIF40_Pos) /*!< 0x00000100 */
#define EXTI_PR2_PIF40 EXTI_PR2_PIF40_Msk /*!< Pending bit for line 40 */
#define EXTI_PR2_PIF41_Pos (9U)
#define EXTI_PR2_PIF41_Msk (0x1UL << EXTI_PR2_PIF41_Pos) /*!< 0x00000200 */
#define EXTI_PR2_PIF41 EXTI_PR2_PIF41_Msk /*!< Pending bit for line 41 */
/******************************************************************************/
/* */
/* Flexible Datarate Controller Area Network */
/* */
/******************************************************************************/
/*!<FDCAN control and status registers */
/***************** Bit definition for FDCAN_CREL register *******************/
#define FDCAN_CREL_DAY_Pos (0U)
#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
#define FDCAN_CREL_MON_Pos (8U)
#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
#define FDCAN_CREL_YEAR_Pos (16U)
#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
#define FDCAN_CREL_SUBSTEP_Pos (20U)
#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
#define FDCAN_CREL_STEP_Pos (24U)
#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
#define FDCAN_CREL_REL_Pos (28U)
#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
/***************** Bit definition for FDCAN_ENDN register *******************/
#define FDCAN_ENDN_ETV_Pos (0U)
#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
/***************** Bit definition for FDCAN_DBTP register *******************/
#define FDCAN_DBTP_DSJW_Pos (0U)
#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
#define FDCAN_DBTP_DTSEG2_Pos (4U)
#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_Pos (8U)
#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
#define FDCAN_DBTP_DBRP_Pos (16U)
#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
#define FDCAN_DBTP_TDC_Pos (23U)
#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
/***************** Bit definition for FDCAN_TEST register *******************/
#define FDCAN_TEST_LBCK_Pos (4U)
#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
#define FDCAN_TEST_TX_Pos (5U)
#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
#define FDCAN_TEST_RX_Pos (7U)
#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
/***************** Bit definition for FDCAN_RWD register ********************/
#define FDCAN_RWD_WDC_Pos (0U)
#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
#define FDCAN_RWD_WDV_Pos (8U)
#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
/***************** Bit definition for FDCAN_CCCR register ********************/
#define FDCAN_CCCR_INIT_Pos (0U)
#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
#define FDCAN_CCCR_CCE_Pos (1U)
#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
#define FDCAN_CCCR_ASM_Pos (2U)
#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
#define FDCAN_CCCR_CSA_Pos (3U)
#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
#define FDCAN_CCCR_CSR_Pos (4U)
#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
#define FDCAN_CCCR_MON_Pos (5U)
#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
#define FDCAN_CCCR_DAR_Pos (6U)
#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
#define FDCAN_CCCR_TEST_Pos (7U)
#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
#define FDCAN_CCCR_FDOE_Pos (8U)
#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
#define FDCAN_CCCR_BRSE_Pos (9U)
#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
#define FDCAN_CCCR_PXHD_Pos (12U)
#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
#define FDCAN_CCCR_EFBI_Pos (13U)
#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
#define FDCAN_CCCR_TXP_Pos (14U)
#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
#define FDCAN_CCCR_NISO_Pos (15U)
#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
/***************** Bit definition for FDCAN_NBTP register ********************/
#define FDCAN_NBTP_NTSEG2_Pos (0U)
#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
#define FDCAN_NBTP_NTSEG1_Pos (8U)
#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
#define FDCAN_NBTP_NBRP_Pos (16U)
#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
#define FDCAN_NBTP_NSJW_Pos (25U)
#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
/***************** Bit definition for FDCAN_TSCC register ********************/
#define FDCAN_TSCC_TSS_Pos (0U)
#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
#define FDCAN_TSCC_TCP_Pos (16U)
#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
/***************** Bit definition for FDCAN_TSCV register ********************/
#define FDCAN_TSCV_TSC_Pos (0U)
#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
/***************** Bit definition for FDCAN_TOCC register ********************/
#define FDCAN_TOCC_ETOC_Pos (0U)
#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
#define FDCAN_TOCC_TOS_Pos (1U)
#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
#define FDCAN_TOCC_TOP_Pos (16U)
#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
/***************** Bit definition for FDCAN_TOCV register ********************/
#define FDCAN_TOCV_TOC_Pos (0U)
#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
/***************** Bit definition for FDCAN_ECR register *********************/
#define FDCAN_ECR_TEC_Pos (0U)
#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
#define FDCAN_ECR_REC_Pos (8U)
#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
#define FDCAN_ECR_RP_Pos (15U)
#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
#define FDCAN_ECR_CEL_Pos (16U)
#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
/***************** Bit definition for FDCAN_PSR register *********************/
#define FDCAN_PSR_LEC_Pos (0U)
#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
#define FDCAN_PSR_ACT_Pos (3U)
#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
#define FDCAN_PSR_EP_Pos (5U)
#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
#define FDCAN_PSR_EW_Pos (6U)
#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
#define FDCAN_PSR_BO_Pos (7U)
#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_PSR_DLEC_Pos (8U)
#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
#define FDCAN_PSR_RESI_Pos (11U)
#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
#define FDCAN_PSR_RBRS_Pos (12U)
#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
#define FDCAN_PSR_REDL_Pos (13U)
#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
#define FDCAN_PSR_PXE_Pos (14U)
#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
#define FDCAN_PSR_TDCV_Pos (16U)
#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
/***************** Bit definition for FDCAN_TDCR register ********************/
#define FDCAN_TDCR_TDCF_Pos (0U)
#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
#define FDCAN_TDCR_TDCO_Pos (8U)
#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
/***************** Bit definition for FDCAN_IR register **********************/
#define FDCAN_IR_RF0N_Pos (0U)
#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
#define FDCAN_IR_RF0F_Pos (1U)
#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000002 */
#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_IR_RF0L_Pos (2U)
#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000004 */
#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
#define FDCAN_IR_RF1N_Pos (3U)
#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000008 */
#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
#define FDCAN_IR_RF1F_Pos (4U)
#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000010 */
#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_IR_RF1L_Pos (5U)
#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000020 */
#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
#define FDCAN_IR_HPM_Pos (6U)
#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000040 */
#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
#define FDCAN_IR_TC_Pos (7U)
#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000080 */
#define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
#define FDCAN_IR_TCF_Pos (8U)
#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000100 */
#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
#define FDCAN_IR_TFE_Pos (9U)
#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000200 */
#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
#define FDCAN_IR_TEFN_Pos (10U)
#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00000400 */
#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
#define FDCAN_IR_TEFF_Pos (11U)
#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00000800 */
#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
#define FDCAN_IR_TEFL_Pos (12U)
#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00001000 */
#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
#define FDCAN_IR_TSW_Pos (13U)
#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00002000 */
#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
#define FDCAN_IR_MRAF_Pos (14U)
#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00004000 */
#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
#define FDCAN_IR_TOO_Pos (15U)
#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00008000 */
#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
#define FDCAN_IR_ELO_Pos (16U)
#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00010000 */
#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
#define FDCAN_IR_EP_Pos (17U)
#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00020000 */
#define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
#define FDCAN_IR_EW_Pos (18U)
#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x00040000 */
#define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
#define FDCAN_IR_BO_Pos (19U)
#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x00080000 */
#define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
#define FDCAN_IR_WDI_Pos (20U)
#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x00100000 */
#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
#define FDCAN_IR_PEA_Pos (21U)
#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x00200000 */
#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
#define FDCAN_IR_PED_Pos (22U)
#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x00400000 */
#define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
#define FDCAN_IR_ARA_Pos (23U)
#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x00800000 */
#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
/***************** Bit definition for FDCAN_IE register **********************/
#define FDCAN_IE_RF0NE_Pos (0U)
#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
#define FDCAN_IE_RF0FE_Pos (1U)
#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000002 */
#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
#define FDCAN_IE_RF0LE_Pos (2U)
#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000004 */
#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
#define FDCAN_IE_RF1NE_Pos (3U)
#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000008 */
#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
#define FDCAN_IE_RF1FE_Pos (4U)
#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000010 */
#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
#define FDCAN_IE_RF1LE_Pos (5U)
#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000020 */
#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
#define FDCAN_IE_HPME_Pos (6U)
#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000040 */
#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
#define FDCAN_IE_TCE_Pos (7U)
#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000080 */
#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
#define FDCAN_IE_TCFE_Pos (8U)
#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000100 */
#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable*/
#define FDCAN_IE_TFEE_Pos (9U)
#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000200 */
#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
#define FDCAN_IE_TEFNE_Pos (10U)
#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00000400 */
#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
#define FDCAN_IE_TEFFE_Pos (11U)
#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00000800 */
#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
#define FDCAN_IE_TEFLE_Pos (12U)
#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00001000 */
#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
#define FDCAN_IE_TSWE_Pos (13U)
#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00002000 */
#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
#define FDCAN_IE_MRAFE_Pos (14U)
#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00004000 */
#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
#define FDCAN_IE_TOOE_Pos (15U)
#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00008000 */
#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
#define FDCAN_IE_ELOE_Pos (16U)
#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00010000 */
#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
#define FDCAN_IE_EPE_Pos (17U)
#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00020000 */
#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
#define FDCAN_IE_EWE_Pos (18U)
#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x00040000 */
#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
#define FDCAN_IE_BOE_Pos (19U)
#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x00080000 */
#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
#define FDCAN_IE_WDIE_Pos (20U)
#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x00100000 */
#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
#define FDCAN_IE_PEAE_Pos (21U)
#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x00200000 */
#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable*/
#define FDCAN_IE_PEDE_Pos (22U)
#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x00400000 */
#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
#define FDCAN_IE_ARAE_Pos (23U)
#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x00800000 */
#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
/***************** Bit definition for FDCAN_ILS register **********************/
#define FDCAN_ILS_RXFIFO0_Pos (0U)
#define FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) /*!< 0x00000001 */
#define FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk /*!<Rx FIFO 0 Message Lost
Rx FIFO 0 is Full
Rx FIFO 0 Has New Message */
#define FDCAN_ILS_RXFIFO1_Pos (1U)
#define FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) /*!< 0x00000002 */
#define FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk /*!<Rx FIFO 1 Message Lost
Rx FIFO 1 is Full
Rx FIFO 1 Has New Message */
#define FDCAN_ILS_SMSG_Pos (2U)
#define FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) /*!< 0x00000004 */
#define FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk /*!<Transmission Cancellation Finished
Transmission Completed
High Priority Message */
#define FDCAN_ILS_TFERR_Pos (3U)
#define FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) /*!< 0x00000008 */
#define FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk /*!<Tx Event FIFO Element Lost
Tx Event FIFO Full
Tx Event FIFO New Entry
Tx FIFO Empty Interrupt Line */
#define FDCAN_ILS_MISC_Pos (4U)
#define FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) /*!< 0x00000010 */
#define FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk /*!<Timeout Occurred
Message RAM Access Failure
Timestamp Wraparound */
#define FDCAN_ILS_BERR_Pos (5U)
#define FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) /*!< 0x00000020 */
#define FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk /*!<Error Passive
Error Logging Overflow */
#define FDCAN_ILS_PERR_Pos (6U)
#define FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) /*!< 0x00000040 */
#define FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk /*!<Access to Reserved Address Line
Protocol Error in Data Phase Line
Protocol Error in Arbitration Phase Line
Watchdog Interrupt Line
Bus_Off Status
Warning Status */
/***************** Bit definition for FDCAN_ILE register **********************/
#define FDCAN_ILE_EINT0_Pos (0U)
#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
#define FDCAN_ILE_EINT1_Pos (1U)
#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
/***************** Bit definition for FDCAN_RXGFC register ********************/
#define FDCAN_RXGFC_RRFE_Pos (0U)
#define FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) /*!< 0x00000001 */
#define FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk /*!<Reject Remote Frames Extended */
#define FDCAN_RXGFC_RRFS_Pos (1U)
#define FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) /*!< 0x00000002 */
#define FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk /*!<Reject Remote Frames Standard */
#define FDCAN_RXGFC_ANFE_Pos (2U)
#define FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) /*!< 0x0000000C */
#define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
#define FDCAN_RXGFC_ANFS_Pos (4U)
#define FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) /*!< 0x00000030 */
#define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
#define FDCAN_RXGFC_F1OM_Pos (8U)
#define FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) /*!< 0x00000100 */
#define FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk /*!<FIFO 1 operation mode */
#define FDCAN_RXGFC_F0OM_Pos (9U)
#define FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) /*!< 0x00000200 */
#define FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk /*!<FIFO 0 operation mode */
#define FDCAN_RXGFC_LSS_Pos (16U)
#define FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) /*!< 0x001F0000 */
#define FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk /*!<List Size Standard */
#define FDCAN_RXGFC_LSE_Pos (24U)
#define FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) /*!< 0x0F000000 */
#define FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk /*!<List Size Extended */
/***************** Bit definition for FDCAN_XIDAM register ********************/
#define FDCAN_XIDAM_EIDM_Pos (0U)
#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
/***************** Bit definition for FDCAN_HPMS register *********************/
#define FDCAN_HPMS_BIDX_Pos (0U)
#define FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) /*!< 0x00000007 */
#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
#define FDCAN_HPMS_MSI_Pos (6U)
#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
#define FDCAN_HPMS_FIDX_Pos (8U)
#define FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00001F00 */
#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
#define FDCAN_HPMS_FLST_Pos (15U)
#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
/***************** Bit definition for FDCAN_RXF0S register ********************/
#define FDCAN_RXF0S_F0FL_Pos (0U)
#define FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
#define FDCAN_RXF0S_F0GI_Pos (8U)
#define FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
#define FDCAN_RXF0S_F0PI_Pos (16U)
#define FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
#define FDCAN_RXF0S_F0F_Pos (24U)
#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
#define FDCAN_RXF0S_RF0L_Pos (25U)
#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
/***************** Bit definition for FDCAN_RXF0A register ********************/
#define FDCAN_RXF0A_F0AI_Pos (0U)
#define FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
/***************** Bit definition for FDCAN_RXF1S register ********************/
#define FDCAN_RXF1S_F1FL_Pos (0U)
#define FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000000F */
#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
#define FDCAN_RXF1S_F1GI_Pos (8U)
#define FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00000300 */
#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
#define FDCAN_RXF1S_F1PI_Pos (16U)
#define FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x00030000 */
#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
#define FDCAN_RXF1S_F1F_Pos (24U)
#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
#define FDCAN_RXF1S_RF1L_Pos (25U)
#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
/***************** Bit definition for FDCAN_RXF1A register ********************/
#define FDCAN_RXF1A_F1AI_Pos (0U)
#define FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x00000007 */
#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
/***************** Bit definition for FDCAN_TXBC register *********************/
#define FDCAN_TXBC_TFQM_Pos (24U)
#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x01000000 */
#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
/***************** Bit definition for FDCAN_TXFQS register *********************/
#define FDCAN_TXFQS_TFFL_Pos (0U)
#define FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
#define FDCAN_TXFQS_TFGI_Pos (8U)
#define FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
#define FDCAN_TXFQS_TFQPI_Pos (16U)
#define FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
#define FDCAN_TXFQS_TFQF_Pos (21U)
#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
/***************** Bit definition for FDCAN_TXBRP register *********************/
#define FDCAN_TXBRP_TRP_Pos (0U)
#define FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) /*!< 0x00000007 */
#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
/***************** Bit definition for FDCAN_TXBAR register *********************/
#define FDCAN_TXBAR_AR_Pos (0U)
#define FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
/***************** Bit definition for FDCAN_TXBCR register *********************/
#define FDCAN_TXBCR_CR_Pos (0U)
#define FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
/***************** Bit definition for FDCAN_TXBTO register *********************/
#define FDCAN_TXBTO_TO_Pos (0U)
#define FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
/***************** Bit definition for FDCAN_TXBCF register *********************/
#define FDCAN_TXBCF_CF_Pos (0U)
#define FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
/***************** Bit definition for FDCAN_TXBTIE register ********************/
#define FDCAN_TXBTIE_TIE_Pos (0U)
#define FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
/***************** Bit definition for FDCAN_ TXBCIE register *******************/
#define FDCAN_TXBCIE_CFIE_Pos (0U)
#define FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0x00000007 */
#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
/***************** Bit definition for FDCAN_TXEFS register *********************/
#define FDCAN_TXEFS_EFFL_Pos (0U)
#define FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x00000007 */
#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
#define FDCAN_TXEFS_EFGI_Pos (8U)
#define FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00000300 */
#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
#define FDCAN_TXEFS_EFPI_Pos (16U)
#define FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x00030000 */
#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
#define FDCAN_TXEFS_EFF_Pos (24U)
#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
#define FDCAN_TXEFS_TEFL_Pos (25U)
#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
/***************** Bit definition for FDCAN_TXEFA register *********************/
#define FDCAN_TXEFA_EFAI_Pos (0U)
#define FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x00000003 */
#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
/*!<FDCAN config registers */
/***************** Bit definition for FDCAN_CKDIV register *********************/
#define FDCAN_CKDIV_PDIV_Pos (0U)
#define FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) /*!< 0x0000000F */
#define FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk /*!<Input Clock Divider */
/******************************************************************************/
/* */
/* FLASH */
/* */
/******************************************************************************/
/******************* Bits definition for FLASH_ACR register *****************/
#define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
#define FLASH_ACR_LATENCY_0WS (0x00000000U)
#define FLASH_ACR_LATENCY_1WS (0x00000001U)
#define FLASH_ACR_LATENCY_2WS (0x00000002U)
#define FLASH_ACR_LATENCY_3WS (0x00000003U)
#define FLASH_ACR_LATENCY_4WS (0x00000004U)
#define FLASH_ACR_LATENCY_5WS (0x00000005U)
#define FLASH_ACR_LATENCY_6WS (0x00000006U)
#define FLASH_ACR_LATENCY_7WS (0x00000007U)
#define FLASH_ACR_LATENCY_8WS (0x00000008U)
#define FLASH_ACR_LATENCY_9WS (0x00000009U)
#define FLASH_ACR_LATENCY_10WS (0x0000000AU)
#define FLASH_ACR_LATENCY_11WS (0x0000000BU)
#define FLASH_ACR_LATENCY_12WS (0x0000000CU)
#define FLASH_ACR_LATENCY_13WS (0x0000000DU)
#define FLASH_ACR_LATENCY_14WS (0x0000000EU)
#define FLASH_ACR_LATENCY_15WS (0x0000000FU)
#define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk
#define FLASH_ACR_ICEN_Pos (9U)
#define FLASH_ACR_ICEN_Msk (0x1UL << FLASH_ACR_ICEN_Pos) /*!< 0x00000200 */
#define FLASH_ACR_ICEN FLASH_ACR_ICEN_Msk
#define FLASH_ACR_DCEN_Pos (10U)
#define FLASH_ACR_DCEN_Msk (0x1UL << FLASH_ACR_DCEN_Pos) /*!< 0x00000400 */
#define FLASH_ACR_DCEN FLASH_ACR_DCEN_Msk
#define FLASH_ACR_ICRST_Pos (11U)
#define FLASH_ACR_ICRST_Msk (0x1UL << FLASH_ACR_ICRST_Pos) /*!< 0x00000800 */
#define FLASH_ACR_ICRST FLASH_ACR_ICRST_Msk
#define FLASH_ACR_DCRST_Pos (12U)
#define FLASH_ACR_DCRST_Msk (0x1UL << FLASH_ACR_DCRST_Pos) /*!< 0x00001000 */
#define FLASH_ACR_DCRST FLASH_ACR_DCRST_Msk
#define FLASH_ACR_RUN_PD_Pos (13U)
#define FLASH_ACR_RUN_PD_Msk (0x1UL << FLASH_ACR_RUN_PD_Pos) /*!< 0x00002000 */
#define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash power down mode during run */
#define FLASH_ACR_SLEEP_PD_Pos (14U)
#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */
#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power down mode during sleep */
#define FLASH_ACR_DBG_SWEN_Pos (18U)
#define FLASH_ACR_DBG_SWEN_Msk (0x1UL << FLASH_ACR_DBG_SWEN_Pos) /*!< 0x00040000 */
#define FLASH_ACR_DBG_SWEN FLASH_ACR_DBG_SWEN_Msk /*!< Software disable for debugger */
/******************* Bits definition for FLASH_SR register ******************/
#define FLASH_SR_EOP_Pos (0U)
#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
#define FLASH_SR_EOP FLASH_SR_EOP_Msk
#define FLASH_SR_OPERR_Pos (1U)
#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */
#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
#define FLASH_SR_PROGERR_Pos (3U)
#define FLASH_SR_PROGERR_Msk (0x1UL << FLASH_SR_PROGERR_Pos) /*!< 0x00000008 */
#define FLASH_SR_PROGERR FLASH_SR_PROGERR_Msk
#define FLASH_SR_WRPERR_Pos (4U)
#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
#define FLASH_SR_PGAERR_Pos (5U)
#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */
#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk
#define FLASH_SR_SIZERR_Pos (6U)
#define FLASH_SR_SIZERR_Msk (0x1UL << FLASH_SR_SIZERR_Pos) /*!< 0x00000040 */
#define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk
#define FLASH_SR_PGSERR_Pos (7U)
#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00000080 */
#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
#define FLASH_SR_MISERR_Pos (8U)
#define FLASH_SR_MISERR_Msk (0x1UL << FLASH_SR_MISERR_Pos) /*!< 0x00000100 */
#define FLASH_SR_MISERR FLASH_SR_MISERR_Msk
#define FLASH_SR_FASTERR_Pos (9U)
#define FLASH_SR_FASTERR_Msk (0x1UL << FLASH_SR_FASTERR_Pos) /*!< 0x00000200 */
#define FLASH_SR_FASTERR FLASH_SR_FASTERR_Msk
#define FLASH_SR_RDERR_Pos (14U)
#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00004000 */
#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk
#define FLASH_SR_OPTVERR_Pos (15U)
#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
#define FLASH_SR_BSY_Pos (16U)
#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
#define FLASH_SR_BSY FLASH_SR_BSY_Msk
/******************* Bits definition for FLASH_CR register ******************/
#define FLASH_CR_PG_Pos (0U)
#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
#define FLASH_CR_PG FLASH_CR_PG_Msk
#define FLASH_CR_PER_Pos (1U)
#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
#define FLASH_CR_PER FLASH_CR_PER_Msk
#define FLASH_CR_MER1_Pos (2U)
#define FLASH_CR_MER1_Msk (0x1UL << FLASH_CR_MER1_Pos) /*!< 0x00000004 */
#define FLASH_CR_MER1 FLASH_CR_MER1_Msk
#define FLASH_CR_PNB_Pos (3U)
#define FLASH_CR_PNB_Msk (0xFFUL << FLASH_CR_PNB_Pos) /*!< 0x000007F8 */
#define FLASH_CR_PNB FLASH_CR_PNB_Msk
#define FLASH_CR_STRT_Pos (16U)
#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */
#define FLASH_CR_STRT FLASH_CR_STRT_Msk
#define FLASH_CR_OPTSTRT_Pos (17U)
#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
#define FLASH_CR_FSTPG_Pos (18U)
#define FLASH_CR_FSTPG_Msk (0x1UL << FLASH_CR_FSTPG_Pos) /*!< 0x00040000 */
#define FLASH_CR_FSTPG FLASH_CR_FSTPG_Msk
#define FLASH_CR_EOPIE_Pos (24U)
#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
#define FLASH_CR_ERRIE_Pos (25U)
#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
#define FLASH_CR_RDERRIE_Pos (26U)
#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk
#define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
#define FLASH_CR_SEC_PROT1_Pos (28U)
#define FLASH_CR_SEC_PROT1_Msk (0x1UL << FLASH_CR_SEC_PROT1_Pos) /*!< 0x10000000 */
#define FLASH_CR_SEC_PROT1 FLASH_CR_SEC_PROT1_Msk
#define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
#define FLASH_CR_LOCK_Pos (31U)
#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
/******************* Bits definition for FLASH_ECCR register ***************/
#define FLASH_ECCR_ADDR_ECC_Pos (0U)
#define FLASH_ECCR_ADDR_ECC_Msk (0x7FFFFUL << FLASH_ECCR_ADDR_ECC_Pos)/*!< 0x0007FFFF */
#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk
#define FLASH_ECCR_BK_ECC_Pos (21U)
#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */
#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk
#define FLASH_ECCR_SYSF_ECC_Pos (22U)
#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */
#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk
#define FLASH_ECCR_ECCIE_Pos (24U)
#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */
#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk
#define FLASH_ECCR_ECCC_Pos (30U)
#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */
#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk
#define FLASH_ECCR_ECCD_Pos (31U)
#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */
#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk
/******************* Bits definition for FLASH_OPTR register ***************/
#define FLASH_OPTR_RDP_Pos (0U)
#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */
#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk
#define FLASH_OPTR_BOR_LEV_Pos (8U)
#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */
#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk
#define FLASH_OPTR_BOR_LEV_0 (0x0UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000000 */
#define FLASH_OPTR_BOR_LEV_1 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */
#define FLASH_OPTR_BOR_LEV_2 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */
#define FLASH_OPTR_BOR_LEV_3 (0x3UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000300 */
#define FLASH_OPTR_BOR_LEV_4 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */
#define FLASH_OPTR_nRST_STOP_Pos (12U)
#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */
#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk
#define FLASH_OPTR_nRST_STDBY_Pos (13U)
#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */
#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk
#define FLASH_OPTR_nRST_SHDW_Pos (14U)
#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */
#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk
#define FLASH_OPTR_IWDG_SW_Pos (16U)
#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
#define FLASH_OPTR_IWDG_STOP_Pos (17U)
#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */
#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk
#define FLASH_OPTR_IWDG_STDBY_Pos (18U)
#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */
#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk
#define FLASH_OPTR_WWDG_SW_Pos (19U)
#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
#define FLASH_OPTR_PB4_PUPEN_Pos (22U)
#define FLASH_OPTR_PB4_PUPEN_Msk (0x1UL << FLASH_OPTR_PB4_PUPEN_Pos) /*!< 0x00400000 */
#define FLASH_OPTR_PB4_PUPEN FLASH_OPTR_PB4_PUPEN_Msk
#define FLASH_OPTR_nBOOT1_Pos (23U)
#define FLASH_OPTR_nBOOT1_Msk (0x1UL << FLASH_OPTR_nBOOT1_Pos) /*!< 0x00800000 */
#define FLASH_OPTR_nBOOT1 FLASH_OPTR_nBOOT1_Msk
#define FLASH_OPTR_SRAM_PE_Pos (24U)
#define FLASH_OPTR_SRAM_PE_Msk (0x1UL << FLASH_OPTR_SRAM_PE_Pos) /*!< 0x01000000 */
#define FLASH_OPTR_SRAM_PE FLASH_OPTR_SRAM_PE_Msk
#define FLASH_OPTR_CCMSRAM_RST_Pos (25U)
#define FLASH_OPTR_CCMSRAM_RST_Msk (0x1UL << FLASH_OPTR_CCMSRAM_RST_Pos)/*!< 0x02000000 */
#define FLASH_OPTR_CCMSRAM_RST FLASH_OPTR_CCMSRAM_RST_Msk
#define FLASH_OPTR_nSWBOOT0_Pos (26U)
#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */
#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk
#define FLASH_OPTR_nBOOT0_Pos (27U)
#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */
#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk
#define FLASH_OPTR_NRST_MODE_Pos (28U)
#define FLASH_OPTR_NRST_MODE_Msk (0x3UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x30000000 */
#define FLASH_OPTR_NRST_MODE FLASH_OPTR_NRST_MODE_Msk
#define FLASH_OPTR_NRST_MODE_0 (0x1UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x10000000 */
#define FLASH_OPTR_NRST_MODE_1 (0x2UL << FLASH_OPTR_NRST_MODE_Pos) /*!< 0x20000000 */
#define FLASH_OPTR_IRHEN_Pos (30U)
#define FLASH_OPTR_IRHEN_Msk (0x1UL << FLASH_OPTR_IRHEN_Pos) /*!< 0x40000000 */
#define FLASH_OPTR_IRHEN FLASH_OPTR_IRHEN_Msk
/****************** Bits definition for FLASH_PCROP1SR register **********/
#define FLASH_PCROP1SR_PCROP1_STRT_Pos (0U)
#define FLASH_PCROP1SR_PCROP1_STRT_Msk (0x7FFFUL << FLASH_PCROP1SR_PCROP1_STRT_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1SR_PCROP1_STRT FLASH_PCROP1SR_PCROP1_STRT_Msk
/****************** Bits definition for FLASH_PCROP1ER register ***********/
#define FLASH_PCROP1ER_PCROP1_END_Pos (0U)
#define FLASH_PCROP1ER_PCROP1_END_Msk (0x7FFFUL << FLASH_PCROP1ER_PCROP1_END_Pos)/*!< 0x00007FFF */
#define FLASH_PCROP1ER_PCROP1_END FLASH_PCROP1ER_PCROP1_END_Msk
#define FLASH_PCROP1ER_PCROP_RDP_Pos (31U)
#define FLASH_PCROP1ER_PCROP_RDP_Msk (0x1UL << FLASH_PCROP1ER_PCROP_RDP_Pos)/*!< 0x80000000 */
#define FLASH_PCROP1ER_PCROP_RDP FLASH_PCROP1ER_PCROP_RDP_Msk
/****************** Bits definition for FLASH_WRP1AR register ***************/
#define FLASH_WRP1AR_WRP1A_STRT_Pos (0U)
#define FLASH_WRP1AR_WRP1A_STRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1AR_WRP1A_STRT FLASH_WRP1AR_WRP1A_STRT_Msk
#define FLASH_WRP1AR_WRP1A_END_Pos (16U)
#define FLASH_WRP1AR_WRP1A_END_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1AR_WRP1A_END FLASH_WRP1AR_WRP1A_END_Msk
/****************** Bits definition for FLASH_WRPB1R register ***************/
#define FLASH_WRP1BR_WRP1B_STRT_Pos (0U)
#define FLASH_WRP1BR_WRP1B_STRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_STRT_Pos)/*!< 0x0000007F */
#define FLASH_WRP1BR_WRP1B_STRT FLASH_WRP1BR_WRP1B_STRT_Msk
#define FLASH_WRP1BR_WRP1B_END_Pos (16U)
#define FLASH_WRP1BR_WRP1B_END_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_END_Pos)/*!< 0x007F0000 */
#define FLASH_WRP1BR_WRP1B_END FLASH_WRP1BR_WRP1B_END_Msk
/****************** Bits definition for FLASH_SEC1R register **************/
#define FLASH_SEC1R_SEC_SIZE1_Pos (0U)
#define FLASH_SEC1R_SEC_SIZE1_Msk (0xFFUL << FLASH_SEC1R_SEC_SIZE1_Pos)/*!< 0x000000FF */
#define FLASH_SEC1R_SEC_SIZE1 FLASH_SEC1R_SEC_SIZE1_Msk
#define FLASH_SEC1R_BOOT_LOCK_Pos (16U)
#define FLASH_SEC1R_BOOT_LOCK_Msk (0x1UL << FLASH_SEC1R_BOOT_LOCK_Pos)/*!< 0x00010000 */
#define FLASH_SEC1R_BOOT_LOCK FLASH_SEC1R_BOOT_LOCK_Msk
/******************************************************************************/
/* */
/* Filter Mathematical ACcelerator unit (FMAC) */
/* */
/******************************************************************************/
/***************** Bit definition for FMAC_X1BUFCFG register ****************/
#define FMAC_X1BUFCFG_X1_BASE_Pos (0U)
#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U)
#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
#define FMAC_X1BUFCFG_FULL_WM_Pos (24U)
#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */
#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */
/***************** Bit definition for FMAC_X2BUFCFG register ****************/
#define FMAC_X2BUFCFG_X2_BASE_Pos (0U)
#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */
#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U)
#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos)/*!< 0x0000FF00 */
#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
/***************** Bit definition for FMAC_YBUFCFG register *****************/
#define FMAC_YBUFCFG_Y_BASE_Pos (0U)
#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */
#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */
#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U)
#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */
#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U)
#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */
#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */
/****************** Bit definition for FMAC_PARAM register ******************/
#define FMAC_PARAM_P_Pos (0U)
#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */
#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */
#define FMAC_PARAM_Q_Pos (8U)
#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */
#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */
#define FMAC_PARAM_R_Pos (16U)
#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */
#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */
#define FMAC_PARAM_FUNC_Pos (24U)
#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */
#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */
#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */
#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */
#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */
#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */
#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */
#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */
#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */
#define FMAC_PARAM_START_Pos (31U)
#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */
#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */
/******************** Bit definition for FMAC_CR register *******************/
#define FMAC_CR_RIEN_Pos (0U)
#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */
#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */
#define FMAC_CR_WIEN_Pos (1U)
#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */
#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */
#define FMAC_CR_OVFLIEN_Pos (2U)
#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */
#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */
#define FMAC_CR_UNFLIEN_Pos (3U)
#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */
#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */
#define FMAC_CR_SATIEN_Pos (4U)
#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */
#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */
#define FMAC_CR_DMAREN_Pos (8U)
#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */
#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */
#define FMAC_CR_DMAWEN_Pos (9U)
#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */
#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */
#define FMAC_CR_CLIPEN_Pos (15U)
#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */
#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */
#define FMAC_CR_RESET_Pos (16U)
#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */
#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */
/******************* Bit definition for FMAC_SR register ********************/
#define FMAC_SR_YEMPTY_Pos (0U)
#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */
#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */
#define FMAC_SR_X1FULL_Pos (1U)
#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */
#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */
#define FMAC_SR_OVFL_Pos (8U)
#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */
#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */
#define FMAC_SR_UNFL_Pos (9U)
#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */
#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */
#define FMAC_SR_SAT_Pos (10U)
#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */
#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */
/****************** Bit definition for FMAC_WDATA register ******************/
#define FMAC_WDATA_WDATA_Pos (0U)
#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */
/****************** Bit definition for FMACX_RDATA register *****************/
#define FMAC_RDATA_RDATA_Pos (0U)
#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */
#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */
/******************************************************************************/
/* */
/* General Purpose IOs (GPIO) */
/* */
/******************************************************************************/
/****************** Bits definition for GPIO_MODER register *****************/
#define GPIO_MODER_MODE0_Pos (0U)
#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
#define GPIO_MODER_MODE1_Pos (2U)
#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
#define GPIO_MODER_MODE2_Pos (4U)
#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
#define GPIO_MODER_MODE3_Pos (6U)
#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
#define GPIO_MODER_MODE4_Pos (8U)
#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
#define GPIO_MODER_MODE5_Pos (10U)
#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
#define GPIO_MODER_MODE6_Pos (12U)
#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
#define GPIO_MODER_MODE7_Pos (14U)
#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
#define GPIO_MODER_MODE8_Pos (16U)
#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
#define GPIO_MODER_MODE9_Pos (18U)
#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
#define GPIO_MODER_MODE10_Pos (20U)
#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
#define GPIO_MODER_MODE11_Pos (22U)
#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
#define GPIO_MODER_MODE12_Pos (24U)
#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
#define GPIO_MODER_MODE13_Pos (26U)
#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
#define GPIO_MODER_MODE14_Pos (28U)
#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
#define GPIO_MODER_MODE15_Pos (30U)
#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_MODER_MODER0 GPIO_MODER_MODE0
#define GPIO_MODER_MODER0_0 GPIO_MODER_MODE0_0
#define GPIO_MODER_MODER0_1 GPIO_MODER_MODE0_1
#define GPIO_MODER_MODER1 GPIO_MODER_MODE1
#define GPIO_MODER_MODER1_0 GPIO_MODER_MODE1_0
#define GPIO_MODER_MODER1_1 GPIO_MODER_MODE1_1
#define GPIO_MODER_MODER2 GPIO_MODER_MODE2
#define GPIO_MODER_MODER2_0 GPIO_MODER_MODE2_0
#define GPIO_MODER_MODER2_1 GPIO_MODER_MODE2_1
#define GPIO_MODER_MODER3 GPIO_MODER_MODE3
#define GPIO_MODER_MODER3_0 GPIO_MODER_MODE3_0
#define GPIO_MODER_MODER3_1 GPIO_MODER_MODE3_1
#define GPIO_MODER_MODER4 GPIO_MODER_MODE4
#define GPIO_MODER_MODER4_0 GPIO_MODER_MODE4_0
#define GPIO_MODER_MODER4_1 GPIO_MODER_MODE4_1
#define GPIO_MODER_MODER5 GPIO_MODER_MODE5
#define GPIO_MODER_MODER5_0 GPIO_MODER_MODE5_0
#define GPIO_MODER_MODER5_1 GPIO_MODER_MODE5_1
#define GPIO_MODER_MODER6 GPIO_MODER_MODE6
#define GPIO_MODER_MODER6_0 GPIO_MODER_MODE6_0
#define GPIO_MODER_MODER6_1 GPIO_MODER_MODE6_1
#define GPIO_MODER_MODER7 GPIO_MODER_MODE7
#define GPIO_MODER_MODER7_0 GPIO_MODER_MODE7_0
#define GPIO_MODER_MODER7_1 GPIO_MODER_MODE7_1
#define GPIO_MODER_MODER8 GPIO_MODER_MODE8
#define GPIO_MODER_MODER8_0 GPIO_MODER_MODE8_0
#define GPIO_MODER_MODER8_1 GPIO_MODER_MODE8_1
#define GPIO_MODER_MODER9 GPIO_MODER_MODE9
#define GPIO_MODER_MODER9_0 GPIO_MODER_MODE9_0
#define GPIO_MODER_MODER9_1 GPIO_MODER_MODE9_1
#define GPIO_MODER_MODER10 GPIO_MODER_MODE10
#define GPIO_MODER_MODER10_0 GPIO_MODER_MODE10_0
#define GPIO_MODER_MODER10_1 GPIO_MODER_MODE10_1
#define GPIO_MODER_MODER11 GPIO_MODER_MODE11
#define GPIO_MODER_MODER11_0 GPIO_MODER_MODE11_0
#define GPIO_MODER_MODER11_1 GPIO_MODER_MODE11_1
#define GPIO_MODER_MODER12 GPIO_MODER_MODE12
#define GPIO_MODER_MODER12_0 GPIO_MODER_MODE12_0
#define GPIO_MODER_MODER12_1 GPIO_MODER_MODE12_1
#define GPIO_MODER_MODER13 GPIO_MODER_MODE13
#define GPIO_MODER_MODER13_0 GPIO_MODER_MODE13_0
#define GPIO_MODER_MODER13_1 GPIO_MODER_MODE13_1
#define GPIO_MODER_MODER14 GPIO_MODER_MODE14
#define GPIO_MODER_MODER14_0 GPIO_MODER_MODE14_0
#define GPIO_MODER_MODER14_1 GPIO_MODER_MODE14_1
#define GPIO_MODER_MODER15 GPIO_MODER_MODE15
#define GPIO_MODER_MODER15_0 GPIO_MODER_MODE15_0
#define GPIO_MODER_MODER15_1 GPIO_MODER_MODE15_1
/****************** Bits definition for GPIO_OTYPER register ****************/
#define GPIO_OTYPER_OT0_Pos (0U)
#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
#define GPIO_OTYPER_OT1_Pos (1U)
#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
#define GPIO_OTYPER_OT2_Pos (2U)
#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
#define GPIO_OTYPER_OT3_Pos (3U)
#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
#define GPIO_OTYPER_OT4_Pos (4U)
#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
#define GPIO_OTYPER_OT5_Pos (5U)
#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
#define GPIO_OTYPER_OT6_Pos (6U)
#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
#define GPIO_OTYPER_OT7_Pos (7U)
#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
#define GPIO_OTYPER_OT8_Pos (8U)
#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
#define GPIO_OTYPER_OT9_Pos (9U)
#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
#define GPIO_OTYPER_OT10_Pos (10U)
#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
#define GPIO_OTYPER_OT11_Pos (11U)
#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
#define GPIO_OTYPER_OT12_Pos (12U)
#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
#define GPIO_OTYPER_OT13_Pos (13U)
#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
#define GPIO_OTYPER_OT14_Pos (14U)
#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
#define GPIO_OTYPER_OT15_Pos (15U)
#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
/* Legacy defines */
#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0
#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1
#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2
#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3
#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4
#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5
#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6
#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7
#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8
#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9
#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10
#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11
#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12
#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13
#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14
#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15
/****************** Bits definition for GPIO_OSPEEDR register ***************/
#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEED0
#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEED0_0
#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEED0_1
#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEED1
#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEED1_0
#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEED1_1
#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEED2
#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEED2_0
#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEED2_1
#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEED3
#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEED3_0
#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEED3_1
#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEED4
#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEED4_0
#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEED4_1
#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEED5
#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEED5_0
#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEED5_1
#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEED6
#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEED6_0
#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEED6_1
#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEED7
#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEED7_0
#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEED7_1
#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEED8
#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEED8_0
#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEED8_1
#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEED9
#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEED9_0
#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEED9_1
#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEED10
#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEED10_0
#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEED10_1
#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEED11
#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEED11_0
#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEED11_1
#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEED12
#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEED12_0
#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEED12_1
#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEED13
#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEED13_0
#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEED13_1
#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEED14
#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEED14_0
#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEED14_1
#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEED15
#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEED15_0
#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEED15_1
/****************** Bits definition for GPIO_PUPDR register *****************/
#define GPIO_PUPDR_PUPD0_Pos (0U)
#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
#define GPIO_PUPDR_PUPD1_Pos (2U)
#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
#define GPIO_PUPDR_PUPD2_Pos (4U)
#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
#define GPIO_PUPDR_PUPD3_Pos (6U)
#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
#define GPIO_PUPDR_PUPD4_Pos (8U)
#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
#define GPIO_PUPDR_PUPD5_Pos (10U)
#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
#define GPIO_PUPDR_PUPD6_Pos (12U)
#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
#define GPIO_PUPDR_PUPD7_Pos (14U)
#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
#define GPIO_PUPDR_PUPD8_Pos (16U)
#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
#define GPIO_PUPDR_PUPD9_Pos (18U)
#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
#define GPIO_PUPDR_PUPD10_Pos (20U)
#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
#define GPIO_PUPDR_PUPD11_Pos (22U)
#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
#define GPIO_PUPDR_PUPD12_Pos (24U)
#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
#define GPIO_PUPDR_PUPD13_Pos (26U)
#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
#define GPIO_PUPDR_PUPD14_Pos (28U)
#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
#define GPIO_PUPDR_PUPD15_Pos (30U)
#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPD0
#define GPIO_PUPDR_PUPDR0_0 GPIO_PUPDR_PUPD0_0
#define GPIO_PUPDR_PUPDR0_1 GPIO_PUPDR_PUPD0_1
#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPD1
#define GPIO_PUPDR_PUPDR1_0 GPIO_PUPDR_PUPD1_0
#define GPIO_PUPDR_PUPDR1_1 GPIO_PUPDR_PUPD1_1
#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPD2
#define GPIO_PUPDR_PUPDR2_0 GPIO_PUPDR_PUPD2_0
#define GPIO_PUPDR_PUPDR2_1 GPIO_PUPDR_PUPD2_1
#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPD3
#define GPIO_PUPDR_PUPDR3_0 GPIO_PUPDR_PUPD3_0
#define GPIO_PUPDR_PUPDR3_1 GPIO_PUPDR_PUPD3_1
#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPD4
#define GPIO_PUPDR_PUPDR4_0 GPIO_PUPDR_PUPD4_0
#define GPIO_PUPDR_PUPDR4_1 GPIO_PUPDR_PUPD4_1
#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPD5
#define GPIO_PUPDR_PUPDR5_0 GPIO_PUPDR_PUPD5_0
#define GPIO_PUPDR_PUPDR5_1 GPIO_PUPDR_PUPD5_1
#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPD6
#define GPIO_PUPDR_PUPDR6_0 GPIO_PUPDR_PUPD6_0
#define GPIO_PUPDR_PUPDR6_1 GPIO_PUPDR_PUPD6_1
#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPD7
#define GPIO_PUPDR_PUPDR7_0 GPIO_PUPDR_PUPD7_0
#define GPIO_PUPDR_PUPDR7_1 GPIO_PUPDR_PUPD7_1
#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPD8
#define GPIO_PUPDR_PUPDR8_0 GPIO_PUPDR_PUPD8_0
#define GPIO_PUPDR_PUPDR8_1 GPIO_PUPDR_PUPD8_1
#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPD9
#define GPIO_PUPDR_PUPDR9_0 GPIO_PUPDR_PUPD9_0
#define GPIO_PUPDR_PUPDR9_1 GPIO_PUPDR_PUPD9_1
#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPD10
#define GPIO_PUPDR_PUPDR10_0 GPIO_PUPDR_PUPD10_0
#define GPIO_PUPDR_PUPDR10_1 GPIO_PUPDR_PUPD10_1
#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPD11
#define GPIO_PUPDR_PUPDR11_0 GPIO_PUPDR_PUPD11_0
#define GPIO_PUPDR_PUPDR11_1 GPIO_PUPDR_PUPD11_1
#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPD12
#define GPIO_PUPDR_PUPDR12_0 GPIO_PUPDR_PUPD12_0
#define GPIO_PUPDR_PUPDR12_1 GPIO_PUPDR_PUPD12_1
#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPD13
#define GPIO_PUPDR_PUPDR13_0 GPIO_PUPDR_PUPD13_0
#define GPIO_PUPDR_PUPDR13_1 GPIO_PUPDR_PUPD13_1
#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPD14
#define GPIO_PUPDR_PUPDR14_0 GPIO_PUPDR_PUPD14_0
#define GPIO_PUPDR_PUPDR14_1 GPIO_PUPDR_PUPD14_1
#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPD15
#define GPIO_PUPDR_PUPDR15_0 GPIO_PUPDR_PUPD15_0
#define GPIO_PUPDR_PUPDR15_1 GPIO_PUPDR_PUPD15_1
/****************** Bits definition for GPIO_IDR register *******************/
#define GPIO_IDR_ID0_Pos (0U)
#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
#define GPIO_IDR_ID1_Pos (1U)
#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
#define GPIO_IDR_ID2_Pos (2U)
#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
#define GPIO_IDR_ID3_Pos (3U)
#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
#define GPIO_IDR_ID4_Pos (4U)
#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
#define GPIO_IDR_ID5_Pos (5U)
#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
#define GPIO_IDR_ID6_Pos (6U)
#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
#define GPIO_IDR_ID7_Pos (7U)
#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
#define GPIO_IDR_ID8_Pos (8U)
#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
#define GPIO_IDR_ID9_Pos (9U)
#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
#define GPIO_IDR_ID10_Pos (10U)
#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
#define GPIO_IDR_ID11_Pos (11U)
#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
#define GPIO_IDR_ID12_Pos (12U)
#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
#define GPIO_IDR_ID13_Pos (13U)
#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
#define GPIO_IDR_ID14_Pos (14U)
#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
#define GPIO_IDR_ID15_Pos (15U)
#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
/* Legacy defines */
#define GPIO_IDR_IDR_0 GPIO_IDR_ID0
#define GPIO_IDR_IDR_1 GPIO_IDR_ID1
#define GPIO_IDR_IDR_2 GPIO_IDR_ID2
#define GPIO_IDR_IDR_3 GPIO_IDR_ID3
#define GPIO_IDR_IDR_4 GPIO_IDR_ID4
#define GPIO_IDR_IDR_5 GPIO_IDR_ID5
#define GPIO_IDR_IDR_6 GPIO_IDR_ID6
#define GPIO_IDR_IDR_7 GPIO_IDR_ID7
#define GPIO_IDR_IDR_8 GPIO_IDR_ID8
#define GPIO_IDR_IDR_9 GPIO_IDR_ID9
#define GPIO_IDR_IDR_10 GPIO_IDR_ID10
#define GPIO_IDR_IDR_11 GPIO_IDR_ID11
#define GPIO_IDR_IDR_12 GPIO_IDR_ID12
#define GPIO_IDR_IDR_13 GPIO_IDR_ID13
#define GPIO_IDR_IDR_14 GPIO_IDR_ID14
#define GPIO_IDR_IDR_15 GPIO_IDR_ID15
/* Old GPIO_IDR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_IDR_0 GPIO_IDR_ID0
#define GPIO_OTYPER_IDR_1 GPIO_IDR_ID1
#define GPIO_OTYPER_IDR_2 GPIO_IDR_ID2
#define GPIO_OTYPER_IDR_3 GPIO_IDR_ID3
#define GPIO_OTYPER_IDR_4 GPIO_IDR_ID4
#define GPIO_OTYPER_IDR_5 GPIO_IDR_ID5
#define GPIO_OTYPER_IDR_6 GPIO_IDR_ID6
#define GPIO_OTYPER_IDR_7 GPIO_IDR_ID7
#define GPIO_OTYPER_IDR_8 GPIO_IDR_ID8
#define GPIO_OTYPER_IDR_9 GPIO_IDR_ID9
#define GPIO_OTYPER_IDR_10 GPIO_IDR_ID10
#define GPIO_OTYPER_IDR_11 GPIO_IDR_ID11
#define GPIO_OTYPER_IDR_12 GPIO_IDR_ID12
#define GPIO_OTYPER_IDR_13 GPIO_IDR_ID13
#define GPIO_OTYPER_IDR_14 GPIO_IDR_ID14
#define GPIO_OTYPER_IDR_15 GPIO_IDR_ID15
/****************** Bits definition for GPIO_ODR register *******************/
#define GPIO_ODR_OD0_Pos (0U)
#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
#define GPIO_ODR_OD1_Pos (1U)
#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
#define GPIO_ODR_OD2_Pos (2U)
#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
#define GPIO_ODR_OD3_Pos (3U)
#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
#define GPIO_ODR_OD4_Pos (4U)
#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
#define GPIO_ODR_OD5_Pos (5U)
#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
#define GPIO_ODR_OD6_Pos (6U)
#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
#define GPIO_ODR_OD7_Pos (7U)
#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
#define GPIO_ODR_OD8_Pos (8U)
#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
#define GPIO_ODR_OD9_Pos (9U)
#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
#define GPIO_ODR_OD10_Pos (10U)
#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
#define GPIO_ODR_OD11_Pos (11U)
#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
#define GPIO_ODR_OD12_Pos (12U)
#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
#define GPIO_ODR_OD13_Pos (13U)
#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
#define GPIO_ODR_OD14_Pos (14U)
#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
#define GPIO_ODR_OD15_Pos (15U)
#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
/* Legacy defines */
#define GPIO_ODR_ODR_0 GPIO_ODR_OD0
#define GPIO_ODR_ODR_1 GPIO_ODR_OD1
#define GPIO_ODR_ODR_2 GPIO_ODR_OD2
#define GPIO_ODR_ODR_3 GPIO_ODR_OD3
#define GPIO_ODR_ODR_4 GPIO_ODR_OD4
#define GPIO_ODR_ODR_5 GPIO_ODR_OD5
#define GPIO_ODR_ODR_6 GPIO_ODR_OD6
#define GPIO_ODR_ODR_7 GPIO_ODR_OD7
#define GPIO_ODR_ODR_8 GPIO_ODR_OD8
#define GPIO_ODR_ODR_9 GPIO_ODR_OD9
#define GPIO_ODR_ODR_10 GPIO_ODR_OD10
#define GPIO_ODR_ODR_11 GPIO_ODR_OD11
#define GPIO_ODR_ODR_12 GPIO_ODR_OD12
#define GPIO_ODR_ODR_13 GPIO_ODR_OD13
#define GPIO_ODR_ODR_14 GPIO_ODR_OD14
#define GPIO_ODR_ODR_15 GPIO_ODR_OD15
/* Old GPIO_ODR register bits definition, maintained for legacy purpose */
#define GPIO_OTYPER_ODR_0 GPIO_ODR_OD0
#define GPIO_OTYPER_ODR_1 GPIO_ODR_OD1
#define GPIO_OTYPER_ODR_2 GPIO_ODR_OD2
#define GPIO_OTYPER_ODR_3 GPIO_ODR_OD3
#define GPIO_OTYPER_ODR_4 GPIO_ODR_OD4
#define GPIO_OTYPER_ODR_5 GPIO_ODR_OD5
#define GPIO_OTYPER_ODR_6 GPIO_ODR_OD6
#define GPIO_OTYPER_ODR_7 GPIO_ODR_OD7
#define GPIO_OTYPER_ODR_8 GPIO_ODR_OD8
#define GPIO_OTYPER_ODR_9 GPIO_ODR_OD9
#define GPIO_OTYPER_ODR_10 GPIO_ODR_OD10
#define GPIO_OTYPER_ODR_11 GPIO_ODR_OD11
#define GPIO_OTYPER_ODR_12 GPIO_ODR_OD12
#define GPIO_OTYPER_ODR_13 GPIO_ODR_OD13
#define GPIO_OTYPER_ODR_14 GPIO_ODR_OD14
#define GPIO_OTYPER_ODR_15 GPIO_ODR_OD15
/****************** Bits definition for GPIO_BSRR register ******************/
#define GPIO_BSRR_BS0_Pos (0U)
#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
#define GPIO_BSRR_BS1_Pos (1U)
#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
#define GPIO_BSRR_BS2_Pos (2U)
#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
#define GPIO_BSRR_BS3_Pos (3U)
#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
#define GPIO_BSRR_BS4_Pos (4U)
#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
#define GPIO_BSRR_BS5_Pos (5U)
#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
#define GPIO_BSRR_BS6_Pos (6U)
#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
#define GPIO_BSRR_BS7_Pos (7U)
#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
#define GPIO_BSRR_BS8_Pos (8U)
#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
#define GPIO_BSRR_BS9_Pos (9U)
#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
#define GPIO_BSRR_BS10_Pos (10U)
#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
#define GPIO_BSRR_BS11_Pos (11U)
#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
#define GPIO_BSRR_BS12_Pos (12U)
#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
#define GPIO_BSRR_BS13_Pos (13U)
#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
#define GPIO_BSRR_BS14_Pos (14U)
#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
#define GPIO_BSRR_BS15_Pos (15U)
#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
#define GPIO_BSRR_BR0_Pos (16U)
#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
#define GPIO_BSRR_BR1_Pos (17U)
#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
#define GPIO_BSRR_BR2_Pos (18U)
#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
#define GPIO_BSRR_BR3_Pos (19U)
#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
#define GPIO_BSRR_BR4_Pos (20U)
#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
#define GPIO_BSRR_BR5_Pos (21U)
#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
#define GPIO_BSRR_BR6_Pos (22U)
#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
#define GPIO_BSRR_BR7_Pos (23U)
#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
#define GPIO_BSRR_BR8_Pos (24U)
#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
#define GPIO_BSRR_BR9_Pos (25U)
#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
#define GPIO_BSRR_BR10_Pos (26U)
#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
#define GPIO_BSRR_BR11_Pos (27U)
#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
#define GPIO_BSRR_BR12_Pos (28U)
#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
#define GPIO_BSRR_BR13_Pos (29U)
#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
#define GPIO_BSRR_BR14_Pos (30U)
#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
#define GPIO_BSRR_BR15_Pos (31U)
#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
/* Legacy defines */
#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0
#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1
#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2
#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3
#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4
#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5
#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6
#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7
#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8
#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9
#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10
#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11
#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12
#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13
#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14
#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15
#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0
#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1
#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2
#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3
#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4
#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5
#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6
#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7
#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8
#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9
#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10
#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11
#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12
#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13
#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14
#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15
/****************** Bit definition for GPIO_LCKR register *********************/
#define GPIO_LCKR_LCK0_Pos (0U)
#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
#define GPIO_LCKR_LCK1_Pos (1U)
#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
#define GPIO_LCKR_LCK2_Pos (2U)
#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
#define GPIO_LCKR_LCK3_Pos (3U)
#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
#define GPIO_LCKR_LCK4_Pos (4U)
#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
#define GPIO_LCKR_LCK5_Pos (5U)
#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
#define GPIO_LCKR_LCK6_Pos (6U)
#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
#define GPIO_LCKR_LCK7_Pos (7U)
#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
#define GPIO_LCKR_LCK8_Pos (8U)
#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
#define GPIO_LCKR_LCK9_Pos (9U)
#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
#define GPIO_LCKR_LCK10_Pos (10U)
#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
#define GPIO_LCKR_LCK11_Pos (11U)
#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
#define GPIO_LCKR_LCK12_Pos (12U)
#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
#define GPIO_LCKR_LCK13_Pos (13U)
#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
#define GPIO_LCKR_LCK14_Pos (14U)
#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
#define GPIO_LCKR_LCK15_Pos (15U)
#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
#define GPIO_LCKR_LCKK_Pos (16U)
#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
/****************** Bit definition for GPIO_AFRL register *********************/
#define GPIO_AFRL_AFSEL0_Pos (0U)
#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
#define GPIO_AFRL_AFSEL1_Pos (4U)
#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
#define GPIO_AFRL_AFSEL2_Pos (8U)
#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
#define GPIO_AFRL_AFSEL3_Pos (12U)
#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
#define GPIO_AFRL_AFSEL4_Pos (16U)
#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
#define GPIO_AFRL_AFSEL5_Pos (20U)
#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
#define GPIO_AFRL_AFSEL6_Pos (24U)
#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
#define GPIO_AFRL_AFSEL7_Pos (28U)
#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
/****************** Bit definition for GPIO_AFRH register *********************/
#define GPIO_AFRH_AFSEL8_Pos (0U)
#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
#define GPIO_AFRH_AFSEL9_Pos (4U)
#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
#define GPIO_AFRH_AFSEL10_Pos (8U)
#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
#define GPIO_AFRH_AFSEL11_Pos (12U)
#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
#define GPIO_AFRH_AFSEL12_Pos (16U)
#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
#define GPIO_AFRH_AFSEL13_Pos (20U)
#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
#define GPIO_AFRH_AFSEL14_Pos (24U)
#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
#define GPIO_AFRH_AFSEL15_Pos (28U)
#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
/* Legacy defines */
#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
/****************** Bits definition for GPIO_BRR register ******************/
#define GPIO_BRR_BR0_Pos (0U)
#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
#define GPIO_BRR_BR1_Pos (1U)
#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
#define GPIO_BRR_BR2_Pos (2U)
#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
#define GPIO_BRR_BR3_Pos (3U)
#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
#define GPIO_BRR_BR4_Pos (4U)
#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
#define GPIO_BRR_BR5_Pos (5U)
#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
#define GPIO_BRR_BR6_Pos (6U)
#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
#define GPIO_BRR_BR7_Pos (7U)
#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
#define GPIO_BRR_BR8_Pos (8U)
#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
#define GPIO_BRR_BR9_Pos (9U)
#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
#define GPIO_BRR_BR10_Pos (10U)
#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
#define GPIO_BRR_BR11_Pos (11U)
#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
#define GPIO_BRR_BR12_Pos (12U)
#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
#define GPIO_BRR_BR13_Pos (13U)
#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
#define GPIO_BRR_BR14_Pos (14U)
#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
#define GPIO_BRR_BR15_Pos (15U)
#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
/* Legacy defines */
#define GPIO_BRR_BR_0 GPIO_BRR_BR0
#define GPIO_BRR_BR_1 GPIO_BRR_BR1
#define GPIO_BRR_BR_2 GPIO_BRR_BR2
#define GPIO_BRR_BR_3 GPIO_BRR_BR3
#define GPIO_BRR_BR_4 GPIO_BRR_BR4
#define GPIO_BRR_BR_5 GPIO_BRR_BR5
#define GPIO_BRR_BR_6 GPIO_BRR_BR6
#define GPIO_BRR_BR_7 GPIO_BRR_BR7
#define GPIO_BRR_BR_8 GPIO_BRR_BR8
#define GPIO_BRR_BR_9 GPIO_BRR_BR9
#define GPIO_BRR_BR_10 GPIO_BRR_BR10
#define GPIO_BRR_BR_11 GPIO_BRR_BR11
#define GPIO_BRR_BR_12 GPIO_BRR_BR12
#define GPIO_BRR_BR_13 GPIO_BRR_BR13
#define GPIO_BRR_BR_14 GPIO_BRR_BR14
#define GPIO_BRR_BR_15 GPIO_BRR_BR15
/******************************************************************************/
/* */
/* Inter-integrated Circuit Interface (I2C) */
/* */
/******************************************************************************/
/******************* Bit definition for I2C_CR1 register *******************/
#define I2C_CR1_PE_Pos (0U)
#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
#define I2C_CR1_TXIE_Pos (1U)
#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
#define I2C_CR1_RXIE_Pos (2U)
#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
#define I2C_CR1_ADDRIE_Pos (3U)
#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
#define I2C_CR1_NACKIE_Pos (4U)
#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
#define I2C_CR1_STOPIE_Pos (5U)
#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
#define I2C_CR1_TCIE_Pos (6U)
#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
#define I2C_CR1_ERRIE_Pos (7U)
#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
#define I2C_CR1_DNF_Pos (8U)
#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
#define I2C_CR1_ANFOFF_Pos (12U)
#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
#define I2C_CR1_SWRST_Pos (13U)
#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
#define I2C_CR1_TXDMAEN_Pos (14U)
#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define I2C_CR1_RXDMAEN_Pos (15U)
#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define I2C_CR1_SBC_Pos (16U)
#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
#define I2C_CR1_NOSTRETCH_Pos (17U)
#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
#define I2C_CR1_WUPEN_Pos (18U)
#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
#define I2C_CR1_GCEN_Pos (19U)
#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
#define I2C_CR1_SMBHEN_Pos (20U)
#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
#define I2C_CR1_SMBDEN_Pos (21U)
#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
#define I2C_CR1_ALERTEN_Pos (22U)
#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
#define I2C_CR1_PECEN_Pos (23U)
#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
/****************** Bit definition for I2C_CR2 register ********************/
#define I2C_CR2_SADD_Pos (0U)
#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
#define I2C_CR2_RD_WRN_Pos (10U)
#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
#define I2C_CR2_ADD10_Pos (11U)
#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
#define I2C_CR2_HEAD10R_Pos (12U)
#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
#define I2C_CR2_START_Pos (13U)
#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
#define I2C_CR2_STOP_Pos (14U)
#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
#define I2C_CR2_NACK_Pos (15U)
#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
#define I2C_CR2_NBYTES_Pos (16U)
#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
#define I2C_CR2_RELOAD_Pos (24U)
#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
#define I2C_CR2_AUTOEND_Pos (25U)
#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
#define I2C_CR2_PECBYTE_Pos (26U)
#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
/******************* Bit definition for I2C_OAR1 register ******************/
#define I2C_OAR1_OA1_Pos (0U)
#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
#define I2C_OAR1_OA1MODE_Pos (10U)
#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
#define I2C_OAR1_OA1EN_Pos (15U)
#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
/******************* Bit definition for I2C_OAR2 register ******************/
#define I2C_OAR2_OA2_Pos (1U)
#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
#define I2C_OAR2_OA2MSK_Pos (8U)
#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
#define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
#define I2C_OAR2_OA2MASK01_Pos (8U)
#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
#define I2C_OAR2_OA2MASK02_Pos (9U)
#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
#define I2C_OAR2_OA2MASK03_Pos (8U)
#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
#define I2C_OAR2_OA2MASK04_Pos (10U)
#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
#define I2C_OAR2_OA2MASK05_Pos (8U)
#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
#define I2C_OAR2_OA2MASK06_Pos (9U)
#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
#define I2C_OAR2_OA2MASK07_Pos (8U)
#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
#define I2C_OAR2_OA2EN_Pos (15U)
#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
/******************* Bit definition for I2C_TIMINGR register *******************/
#define I2C_TIMINGR_SCLL_Pos (0U)
#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
#define I2C_TIMINGR_SCLH_Pos (8U)
#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
#define I2C_TIMINGR_SDADEL_Pos (16U)
#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
#define I2C_TIMINGR_SCLDEL_Pos (20U)
#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
#define I2C_TIMINGR_PRESC_Pos (28U)
#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
/******************* Bit definition for I2C_TIMEOUTR register *******************/
#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
#define I2C_TIMEOUTR_TIDLE_Pos (12U)
#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */
#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
/****************** Bit definition for I2C_ISR register *********************/
#define I2C_ISR_TXE_Pos (0U)
#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
#define I2C_ISR_TXIS_Pos (1U)
#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
#define I2C_ISR_RXNE_Pos (2U)
#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
#define I2C_ISR_ADDR_Pos (3U)
#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */
#define I2C_ISR_NACKF_Pos (4U)
#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
#define I2C_ISR_STOPF_Pos (5U)
#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
#define I2C_ISR_TC_Pos (6U)
#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
#define I2C_ISR_TCR_Pos (7U)
#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
#define I2C_ISR_BERR_Pos (8U)
#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
#define I2C_ISR_ARLO_Pos (9U)
#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
#define I2C_ISR_OVR_Pos (10U)
#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
#define I2C_ISR_PECERR_Pos (11U)
#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
#define I2C_ISR_TIMEOUT_Pos (12U)
#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
#define I2C_ISR_ALERT_Pos (13U)
#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
#define I2C_ISR_BUSY_Pos (15U)
#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
#define I2C_ISR_DIR_Pos (16U)
#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
#define I2C_ISR_ADDCODE_Pos (17U)
#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
/****************** Bit definition for I2C_ICR register *********************/
#define I2C_ICR_ADDRCF_Pos (3U)
#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
#define I2C_ICR_NACKCF_Pos (4U)
#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
#define I2C_ICR_STOPCF_Pos (5U)
#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
#define I2C_ICR_BERRCF_Pos (8U)
#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
#define I2C_ICR_ARLOCF_Pos (9U)
#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
#define I2C_ICR_OVRCF_Pos (10U)
#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
#define I2C_ICR_PECCF_Pos (11U)
#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
#define I2C_ICR_TIMOUTCF_Pos (12U)
#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
#define I2C_ICR_ALERTCF_Pos (13U)
#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
/****************** Bit definition for I2C_PECR register *********************/
#define I2C_PECR_PEC_Pos (0U)
#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
/****************** Bit definition for I2C_RXDR register *********************/
#define I2C_RXDR_RXDATA_Pos (0U)
#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/****************** Bit definition for I2C_TXDR register *********************/
#define I2C_TXDR_TXDATA_Pos (0U)
#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
/******************************************************************************/
/* */
/* Independent WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_KR_KEY_Pos (0U)
#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
/******************* Bit definition for IWDG_PR register ********************/
#define IWDG_PR_PR_Pos (0U)
#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
/******************* Bit definition for IWDG_RLR register *******************/
#define IWDG_RLR_RL_Pos (0U)
#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
/******************* Bit definition for IWDG_SR register ********************/
#define IWDG_SR_PVU_Pos (0U)
#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
#define IWDG_SR_RVU_Pos (1U)
#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
#define IWDG_SR_WVU_Pos (2U)
#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
/******************* Bit definition for IWDG_KR register ********************/
#define IWDG_WINR_WIN_Pos (0U)
#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
/******************************************************************************/
/* */
/* Operational Amplifier (OPAMP) */
/* */
/******************************************************************************/
/********************* Bit definition for OPAMPx_CSR register ***************/
#define OPAMP_CSR_OPAMPxEN_Pos (0U)
#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
#define OPAMP_CSR_FORCEVP_Pos (1U)
#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Connect the internal references to the plus input of the OPAMPX */
#define OPAMP_CSR_VPSEL_Pos (2U)
#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverting input selection */
#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
#define OPAMP_CSR_USERTRIM_Pos (4U)
#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00000010 */
#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
#define OPAMP_CSR_VMSEL_Pos (5U)
#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
#define OPAMP_CSR_HIGHSPEEDEN_Pos (7U)
#define OPAMP_CSR_HIGHSPEEDEN_Msk (0x1UL << OPAMP_CSR_HIGHSPEEDEN_Pos) /*!< 0x00000080 */
#define OPAMP_CSR_HIGHSPEEDEN OPAMP_CSR_HIGHSPEEDEN_Msk /*!< High speed mode enable */
#define OPAMP_CSR_OPAMPINTEN_Pos (8U)
#define OPAMP_CSR_OPAMPINTEN_Msk (0x1UL << OPAMP_CSR_OPAMPINTEN_Pos) /*!< 0x00000100 */
#define OPAMP_CSR_OPAMPINTEN OPAMP_CSR_OPAMPINTEN_Msk /*!< Internal output enable */
#define OPAMP_CSR_CALON_Pos (11U)
#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
#define OPAMP_CSR_CALSEL_Pos (12U)
#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
#define OPAMP_CSR_PGGAIN_Pos (14U)
#define OPAMP_CSR_PGGAIN_Msk (0x1FUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0007C000 */
#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Gain in PGA mode */
#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
#define OPAMP_CSR_PGGAIN_4 (0x10UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00040000 */
#define OPAMP_CSR_TRIMOFFSETP_Pos (19U)
#define OPAMP_CSR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETP_Pos) /*!< 0x00F80000 */
#define OPAMP_CSR_TRIMOFFSETP OPAMP_CSR_TRIMOFFSETP_Msk /*!< Offset trimming value (PMOS) */
#define OPAMP_CSR_TRIMOFFSETN_Pos (24U)
#define OPAMP_CSR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_CSR_TRIMOFFSETN_Pos) /*!< 0x1F000000 */
#define OPAMP_CSR_TRIMOFFSETN OPAMP_CSR_TRIMOFFSETN_Msk /*!< Offset trimming value (NMOS) */
#define OPAMP_CSR_OUTCAL_Pos (30U)
#define OPAMP_CSR_OUTCAL_Msk (0x1UL << OPAMP_CSR_OUTCAL_Pos) /*!< 0x40000000 */
#define OPAMP_CSR_OUTCAL OPAMP_CSR_OUTCAL_Msk /*!< OPAMP ouput status flag */
#define OPAMP_CSR_LOCK_Pos (31U)
#define OPAMP_CSR_LOCK_Msk (0x1UL << OPAMP_CSR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_CSR_LOCK OPAMP_CSR_LOCK_Msk /*!< OPAMP control/status register lock */
/********************* Bit definition for OPAMPx_TCMR register ***************/
#define OPAMP_TCMR_VMSSEL_Pos (0U)
#define OPAMP_TCMR_VMSSEL_Msk (0x1UL << OPAMP_TCMR_VMSSEL_Pos) /*!< 0x00000001 */
#define OPAMP_TCMR_VMSSEL OPAMP_TCMR_VMSSEL_Msk /*!< Secondary inverting input selection */
#define OPAMP_TCMR_VPSSEL_Pos (1U)
#define OPAMP_TCMR_VPSSEL_Msk (0x3UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000006 */
#define OPAMP_TCMR_VPSSEL OPAMP_TCMR_VPSSEL_Msk /*!< Secondary non inverting input selection */
#define OPAMP_TCMR_VPSSEL_0 (0x1UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000002 */
#define OPAMP_TCMR_VPSSEL_1 (0x2UL << OPAMP_TCMR_VPSSEL_Pos) /*!< 0x00000004 */
#define OPAMP_TCMR_T1CMEN_Pos (3U)
#define OPAMP_TCMR_T1CMEN_Msk (0x1UL << OPAMP_TCMR_T1CMEN_Pos) /*!< 0x00000008 */
#define OPAMP_TCMR_T1CMEN OPAMP_TCMR_T1CMEN_Msk /*!< Timer 1 controlled mux mode enable */
#define OPAMP_TCMR_T8CMEN_Pos (4U)
#define OPAMP_TCMR_T8CMEN_Msk (0x1UL << OPAMP_TCMR_T8CMEN_Pos) /*!< 0x00000010 */
#define OPAMP_TCMR_T8CMEN OPAMP_TCMR_T8CMEN_Msk /*!< Timer 8 controlled mux mode enable */
#define OPAMP_TCMR_T20CMEN_Pos (5U)
#define OPAMP_TCMR_T20CMEN_Msk (0x1UL << OPAMP_TCMR_T20CMEN_Pos) /*!< 0x00000020 */
#define OPAMP_TCMR_T20CMEN OPAMP_TCMR_T20CMEN_Msk /*!< Timer 20 controlled mux mode enable */
#define OPAMP_TCMR_LOCK_Pos (31U)
#define OPAMP_TCMR_LOCK_Msk (0x1UL << OPAMP_TCMR_LOCK_Pos) /*!< 0x80000000 */
#define OPAMP_TCMR_LOCK OPAMP_TCMR_LOCK_Msk /*!< OPAMP SW control register lock */
/******************************************************************************/
/* */
/* Power Control */
/* */
/******************************************************************************/
/******************** Bit definition for PWR_CR1 register ********************/
#define PWR_CR1_LPR_Pos (14U)
#define PWR_CR1_LPR_Msk (0x1UL << PWR_CR1_LPR_Pos) /*!< 0x00004000 */
#define PWR_CR1_LPR PWR_CR1_LPR_Msk /*!< Regulator low-power mode */
#define PWR_CR1_VOS_Pos (9U)
#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x00000600 */
#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */
#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00000200 */
#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00000400 */
#define PWR_CR1_DBP_Pos (8U)
#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
#define PWR_CR1_LPMS_Pos (0U)
#define PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) /*!< 0x00000007 */
#define PWR_CR1_LPMS PWR_CR1_LPMS_Msk /*!< Low-power mode selection field */
#define PWR_CR1_LPMS_STOP0 (0x00000000U) /*!< Stop 0 mode */
#define PWR_CR1_LPMS_STOP1_Pos (0U)
#define PWR_CR1_LPMS_STOP1_Msk (0x1UL << PWR_CR1_LPMS_STOP1_Pos) /*!< 0x00000001 */
#define PWR_CR1_LPMS_STOP1 PWR_CR1_LPMS_STOP1_Msk /*!< Stop 1 mode */
#define PWR_CR1_LPMS_STANDBY_Pos (0U)
#define PWR_CR1_LPMS_STANDBY_Msk (0x3UL << PWR_CR1_LPMS_STANDBY_Pos) /*!< 0x00000003 */
#define PWR_CR1_LPMS_STANDBY PWR_CR1_LPMS_STANDBY_Msk /*!< Stand-by mode */
#define PWR_CR1_LPMS_SHUTDOWN_Pos (2U)
#define PWR_CR1_LPMS_SHUTDOWN_Msk (0x1UL << PWR_CR1_LPMS_SHUTDOWN_Pos) /*!< 0x00000004 */
#define PWR_CR1_LPMS_SHUTDOWN PWR_CR1_LPMS_SHUTDOWN_Msk /*!< Shut-down mode */
/******************** Bit definition for PWR_CR2 register ********************/
/*!< PVME Peripheral Voltage Monitor Enable */
#define PWR_CR2_PVME_Pos (4U)
#define PWR_CR2_PVME_Msk (0xFUL << PWR_CR2_PVME_Pos) /*!< 0x000000F0 */
#define PWR_CR2_PVME PWR_CR2_PVME_Msk /*!< PVM bits field */
#define PWR_CR2_PVME4_Pos (7U)
#define PWR_CR2_PVME4_Msk (0x1UL << PWR_CR2_PVME4_Pos) /*!< 0x00000080 */
#define PWR_CR2_PVME4 PWR_CR2_PVME4_Msk /*!< PVM 4 Enable */
#define PWR_CR2_PVME3_Pos (6U)
#define PWR_CR2_PVME3_Msk (0x1UL << PWR_CR2_PVME3_Pos) /*!< 0x00000040 */
#define PWR_CR2_PVME3 PWR_CR2_PVME3_Msk /*!< PVM 3 Enable */
#define PWR_CR2_PVME2_Pos (5U)
#define PWR_CR2_PVME2_Msk (0x1UL << PWR_CR2_PVME2_Pos) /*!< 0x00000020 */
#define PWR_CR2_PVME2 PWR_CR2_PVME2_Msk /*!< PVM 2 Enable */
#define PWR_CR2_PVME1_Pos (4U)
#define PWR_CR2_PVME1_Msk (0x1UL << PWR_CR2_PVME1_Pos) /*!< 0x00000010 */
#define PWR_CR2_PVME1 PWR_CR2_PVME1_Msk /*!< PVM 1 Enable */
/*!< PVD level configuration */
#define PWR_CR2_PLS_Pos (1U)
#define PWR_CR2_PLS_Msk (0x7UL << PWR_CR2_PLS_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS PWR_CR2_PLS_Msk /*!< PVD level selection */
#define PWR_CR2_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
#define PWR_CR2_PLS_LEV1_Pos (1U)
#define PWR_CR2_PLS_LEV1_Msk (0x1UL << PWR_CR2_PLS_LEV1_Pos) /*!< 0x00000002 */
#define PWR_CR2_PLS_LEV1 PWR_CR2_PLS_LEV1_Msk /*!< PVD level 1 */
#define PWR_CR2_PLS_LEV2_Pos (2U)
#define PWR_CR2_PLS_LEV2_Msk (0x1UL << PWR_CR2_PLS_LEV2_Pos) /*!< 0x00000004 */
#define PWR_CR2_PLS_LEV2 PWR_CR2_PLS_LEV2_Msk /*!< PVD level 2 */
#define PWR_CR2_PLS_LEV3_Pos (1U)
#define PWR_CR2_PLS_LEV3_Msk (0x3UL << PWR_CR2_PLS_LEV3_Pos) /*!< 0x00000006 */
#define PWR_CR2_PLS_LEV3 PWR_CR2_PLS_LEV3_Msk /*!< PVD level 3 */
#define PWR_CR2_PLS_LEV4_Pos (3U)
#define PWR_CR2_PLS_LEV4_Msk (0x1UL << PWR_CR2_PLS_LEV4_Pos) /*!< 0x00000008 */
#define PWR_CR2_PLS_LEV4 PWR_CR2_PLS_LEV4_Msk /*!< PVD level 4 */
#define PWR_CR2_PLS_LEV5_Pos (1U)
#define PWR_CR2_PLS_LEV5_Msk (0x5UL << PWR_CR2_PLS_LEV5_Pos) /*!< 0x0000000A */
#define PWR_CR2_PLS_LEV5 PWR_CR2_PLS_LEV5_Msk /*!< PVD level 5 */
#define PWR_CR2_PLS_LEV6_Pos (2U)
#define PWR_CR2_PLS_LEV6_Msk (0x3UL << PWR_CR2_PLS_LEV6_Pos) /*!< 0x0000000C */
#define PWR_CR2_PLS_LEV6 PWR_CR2_PLS_LEV6_Msk /*!< PVD level 6 */
#define PWR_CR2_PLS_LEV7_Pos (1U)
#define PWR_CR2_PLS_LEV7_Msk (0x7UL << PWR_CR2_PLS_LEV7_Pos) /*!< 0x0000000E */
#define PWR_CR2_PLS_LEV7 PWR_CR2_PLS_LEV7_Msk /*!< PVD level 7 */
#define PWR_CR2_PVDE_Pos (0U)
#define PWR_CR2_PVDE_Msk (0x1UL << PWR_CR2_PVDE_Pos) /*!< 0x00000001 */
#define PWR_CR2_PVDE PWR_CR2_PVDE_Msk /*!< Power Voltage Detector Enable */
/******************** Bit definition for PWR_CR3 register ********************/
#define PWR_CR3_EIWF_Pos (15U)
#define PWR_CR3_EIWF_Msk (0x1UL << PWR_CR3_EIWF_Pos) /*!< 0x00008000 */
#define PWR_CR3_EIWF PWR_CR3_EIWF_Msk /*!< Enable Internal Wake-up line */
#define PWR_CR3_UCPD_DBDIS_Pos (14U)
#define PWR_CR3_UCPD_DBDIS_Msk (0x1UL << PWR_CR3_UCPD_DBDIS_Pos) /*!< 0x00004000 */
#define PWR_CR3_UCPD_DBDIS PWR_CR3_UCPD_DBDIS_Msk /*!< USB Type-C and Power Delivery Dead Battery disable. */
#define PWR_CR3_UCPD_STDBY_Pos (13U)
#define PWR_CR3_UCPD_STDBY_Msk (0x1UL << PWR_CR3_UCPD_STDBY_Pos) /*!< 0x00002000 */
#define PWR_CR3_UCPD_STDBY PWR_CR3_UCPD_STDBY_Msk /*!< USB Type-C and Power Delivery standby mode. */
#define PWR_CR3_APC_Pos (10U)
#define PWR_CR3_APC_Msk (0x1UL << PWR_CR3_APC_Pos) /*!< 0x00000400 */
#define PWR_CR3_APC PWR_CR3_APC_Msk /*!< Apply pull-up and pull-down configuration */
#define PWR_CR3_RRS_Pos (8U)
#define PWR_CR3_RRS_Msk (0x1UL << PWR_CR3_RRS_Pos) /*!< 0x00000100 */
#define PWR_CR3_RRS PWR_CR3_RRS_Msk /*!< SRAM2 Retention in Stand-by mode */
#define PWR_CR3_EWUP5_Pos (4U)
#define PWR_CR3_EWUP5_Msk (0x1UL << PWR_CR3_EWUP5_Pos) /*!< 0x00000010 */
#define PWR_CR3_EWUP5 PWR_CR3_EWUP5_Msk /*!< Enable Wake-Up Pin 5 */
#define PWR_CR3_EWUP4_Pos (3U)
#define PWR_CR3_EWUP4_Msk (0x1UL << PWR_CR3_EWUP4_Pos) /*!< 0x00000008 */
#define PWR_CR3_EWUP4 PWR_CR3_EWUP4_Msk /*!< Enable Wake-Up Pin 4 */
#define PWR_CR3_EWUP3_Pos (2U)
#define PWR_CR3_EWUP3_Msk (0x1UL << PWR_CR3_EWUP3_Pos) /*!< 0x00000004 */
#define PWR_CR3_EWUP3 PWR_CR3_EWUP3_Msk /*!< Enable Wake-Up Pin 3 */
#define PWR_CR3_EWUP2_Pos (1U)
#define PWR_CR3_EWUP2_Msk (0x1UL << PWR_CR3_EWUP2_Pos) /*!< 0x00000002 */
#define PWR_CR3_EWUP2 PWR_CR3_EWUP2_Msk /*!< Enable Wake-Up Pin 2 */
#define PWR_CR3_EWUP1_Pos (0U)
#define PWR_CR3_EWUP1_Msk (0x1UL << PWR_CR3_EWUP1_Pos) /*!< 0x00000001 */
#define PWR_CR3_EWUP1 PWR_CR3_EWUP1_Msk /*!< Enable Wake-Up Pin 1 */
#define PWR_CR3_EWUP_Pos (0U)
#define PWR_CR3_EWUP_Msk (0x1FUL << PWR_CR3_EWUP_Pos) /*!< 0x0000001F */
#define PWR_CR3_EWUP PWR_CR3_EWUP_Msk /*!< Enable Wake-Up Pins */
/******************** Bit definition for PWR_CR4 register ********************/
#define PWR_CR4_VBRS_Pos (9U)
#define PWR_CR4_VBRS_Msk (0x1UL << PWR_CR4_VBRS_Pos) /*!< 0x00000200 */
#define PWR_CR4_VBRS PWR_CR4_VBRS_Msk /*!< VBAT Battery charging Resistor Selection */
#define PWR_CR4_VBE_Pos (8U)
#define PWR_CR4_VBE_Msk (0x1UL << PWR_CR4_VBE_Pos) /*!< 0x00000100 */
#define PWR_CR4_VBE PWR_CR4_VBE_Msk /*!< VBAT Battery charging Enable */
#define PWR_CR4_WP5_Pos (4U)
#define PWR_CR4_WP5_Msk (0x1UL << PWR_CR4_WP5_Pos) /*!< 0x00000010 */
#define PWR_CR4_WP5 PWR_CR4_WP5_Msk /*!< Wake-Up Pin 5 polarity */
#define PWR_CR4_WP4_Pos (3U)
#define PWR_CR4_WP4_Msk (0x1UL << PWR_CR4_WP4_Pos) /*!< 0x00000008 */
#define PWR_CR4_WP4 PWR_CR4_WP4_Msk /*!< Wake-Up Pin 4 polarity */
#define PWR_CR4_WP3_Pos (2U)
#define PWR_CR4_WP3_Msk (0x1UL << PWR_CR4_WP3_Pos) /*!< 0x00000004 */
#define PWR_CR4_WP3 PWR_CR4_WP3_Msk /*!< Wake-Up Pin 3 polarity */
#define PWR_CR4_WP2_Pos (1U)
#define PWR_CR4_WP2_Msk (0x1UL << PWR_CR4_WP2_Pos) /*!< 0x00000002 */
#define PWR_CR4_WP2 PWR_CR4_WP2_Msk /*!< Wake-Up Pin 2 polarity */
#define PWR_CR4_WP1_Pos (0U)
#define PWR_CR4_WP1_Msk (0x1UL << PWR_CR4_WP1_Pos) /*!< 0x00000001 */
#define PWR_CR4_WP1 PWR_CR4_WP1_Msk /*!< Wake-Up Pin 1 polarity */
/******************** Bit definition for PWR_SR1 register ********************/
#define PWR_SR1_WUFI_Pos (15U)
#define PWR_SR1_WUFI_Msk (0x1UL << PWR_SR1_WUFI_Pos) /*!< 0x00008000 */
#define PWR_SR1_WUFI PWR_SR1_WUFI_Msk /*!< Wake-Up Flag Internal */
#define PWR_SR1_SBF_Pos (8U)
#define PWR_SR1_SBF_Msk (0x1UL << PWR_SR1_SBF_Pos) /*!< 0x00000100 */
#define PWR_SR1_SBF PWR_SR1_SBF_Msk /*!< Stand-By Flag */
#define PWR_SR1_WUF_Pos (0U)
#define PWR_SR1_WUF_Msk (0x1FUL << PWR_SR1_WUF_Pos) /*!< 0x0000001F */
#define PWR_SR1_WUF PWR_SR1_WUF_Msk /*!< Wake-up Flags */
#define PWR_SR1_WUF5_Pos (4U)
#define PWR_SR1_WUF5_Msk (0x1UL << PWR_SR1_WUF5_Pos) /*!< 0x00000010 */
#define PWR_SR1_WUF5 PWR_SR1_WUF5_Msk /*!< Wake-up Flag 5 */
#define PWR_SR1_WUF4_Pos (3U)
#define PWR_SR1_WUF4_Msk (0x1UL << PWR_SR1_WUF4_Pos) /*!< 0x00000008 */
#define PWR_SR1_WUF4 PWR_SR1_WUF4_Msk /*!< Wake-up Flag 4 */
#define PWR_SR1_WUF3_Pos (2U)
#define PWR_SR1_WUF3_Msk (0x1UL << PWR_SR1_WUF3_Pos) /*!< 0x00000004 */
#define PWR_SR1_WUF3 PWR_SR1_WUF3_Msk /*!< Wake-up Flag 3 */
#define PWR_SR1_WUF2_Pos (1U)
#define PWR_SR1_WUF2_Msk (0x1UL << PWR_SR1_WUF2_Pos) /*!< 0x00000002 */
#define PWR_SR1_WUF2 PWR_SR1_WUF2_Msk /*!< Wake-up Flag 2 */
#define PWR_SR1_WUF1_Pos (0U)
#define PWR_SR1_WUF1_Msk (0x1UL << PWR_SR1_WUF1_Pos) /*!< 0x00000001 */
#define PWR_SR1_WUF1 PWR_SR1_WUF1_Msk /*!< Wake-up Flag 1 */
/******************** Bit definition for PWR_SR2 register ********************/
#define PWR_SR2_PVMO4_Pos (15U)
#define PWR_SR2_PVMO4_Msk (0x1UL << PWR_SR2_PVMO4_Pos) /*!< 0x00008000 */
#define PWR_SR2_PVMO4 PWR_SR2_PVMO4_Msk /*!< Peripheral Voltage Monitoring Output 4 */
#define PWR_SR2_PVMO3_Pos (14U)
#define PWR_SR2_PVMO3_Msk (0x1UL << PWR_SR2_PVMO3_Pos) /*!< 0x00004000 */
#define PWR_SR2_PVMO3 PWR_SR2_PVMO3_Msk /*!< Peripheral Voltage Monitoring Output 3 */
#define PWR_SR2_PVMO2_Pos (13U)
#define PWR_SR2_PVMO2_Msk (0x1UL << PWR_SR2_PVMO2_Pos) /*!< 0x00002000 */
#define PWR_SR2_PVMO2 PWR_SR2_PVMO2_Msk /*!< Peripheral Voltage Monitoring Output 2 */
#define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
#define PWR_SR2_PVMO1 PWR_SR2_PVMO1_Msk /*!< Peripheral Voltage Monitoring Output 1 */
#define PWR_SR2_PVDO_Pos (11U)
#define PWR_SR2_PVDO_Msk (0x1UL << PWR_SR2_PVDO_Pos) /*!< 0x00000800 */
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power Voltage Detector Output */
#define PWR_SR2_VOSF_Pos (10U)
#define PWR_SR2_VOSF_Msk (0x1UL << PWR_SR2_VOSF_Pos) /*!< 0x00000400 */
#define PWR_SR2_VOSF PWR_SR2_VOSF_Msk /*!< Voltage Scaling Flag */
#define PWR_SR2_REGLPF_Pos (9U)
#define PWR_SR2_REGLPF_Msk (0x1UL << PWR_SR2_REGLPF_Pos) /*!< 0x00000200 */
#define PWR_SR2_REGLPF PWR_SR2_REGLPF_Msk /*!< Low-power Regulator Flag */
#define PWR_SR2_REGLPS_Pos (8U)
#define PWR_SR2_REGLPS_Msk (0x1UL << PWR_SR2_REGLPS_Pos) /*!< 0x00000100 */
#define PWR_SR2_REGLPS PWR_SR2_REGLPS_Msk /*!< Low-power Regulator Started */
/******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CSBF_Pos (8U)
#define PWR_SCR_CSBF_Msk (0x1UL << PWR_SCR_CSBF_Pos) /*!< 0x00000100 */
#define PWR_SCR_CSBF PWR_SCR_CSBF_Msk /*!< Clear Stand-By Flag */
#define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags */
#define PWR_SCR_CWUF5_Pos (4U)
#define PWR_SCR_CWUF5_Msk (0x1UL << PWR_SCR_CWUF5_Pos) /*!< 0x00000010 */
#define PWR_SCR_CWUF5 PWR_SCR_CWUF5_Msk /*!< Clear Wake-up Flag 5 */
#define PWR_SCR_CWUF4_Pos (3U)
#define PWR_SCR_CWUF4_Msk (0x1UL << PWR_SCR_CWUF4_Pos) /*!< 0x00000008 */
#define PWR_SCR_CWUF4 PWR_SCR_CWUF4_Msk /*!< Clear Wake-up Flag 4 */
#define PWR_SCR_CWUF3_Pos (2U)
#define PWR_SCR_CWUF3_Msk (0x1UL << PWR_SCR_CWUF3_Pos) /*!< 0x00000004 */
#define PWR_SCR_CWUF3 PWR_SCR_CWUF3_Msk /*!< Clear Wake-up Flag 3 */
#define PWR_SCR_CWUF2_Pos (1U)
#define PWR_SCR_CWUF2_Msk (0x1UL << PWR_SCR_CWUF2_Pos) /*!< 0x00000002 */
#define PWR_SCR_CWUF2 PWR_SCR_CWUF2_Msk /*!< Clear Wake-up Flag 2 */
#define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
#define PWR_SCR_CWUF1 PWR_SCR_CWUF1_Msk /*!< Clear Wake-up Flag 1 */
/******************** Bit definition for PWR_PUCRA register ********************/
#define PWR_PUCRA_PA15_Pos (15U)
#define PWR_PUCRA_PA15_Msk (0x1UL << PWR_PUCRA_PA15_Pos) /*!< 0x00008000 */
#define PWR_PUCRA_PA15 PWR_PUCRA_PA15_Msk /*!< Port PA15 Pull-Up set */
#define PWR_PUCRA_PA13_Pos (13U)
#define PWR_PUCRA_PA13_Msk (0x1UL << PWR_PUCRA_PA13_Pos) /*!< 0x00002000 */
#define PWR_PUCRA_PA13 PWR_PUCRA_PA13_Msk /*!< Port PA13 Pull-Up set */
#define PWR_PUCRA_PA12_Pos (12U)
#define PWR_PUCRA_PA12_Msk (0x1UL << PWR_PUCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PUCRA_PA12 PWR_PUCRA_PA12_Msk /*!< Port PA12 Pull-Up set */
#define PWR_PUCRA_PA11_Pos (11U)
#define PWR_PUCRA_PA11_Msk (0x1UL << PWR_PUCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PUCRA_PA11 PWR_PUCRA_PA11_Msk /*!< Port PA11 Pull-Up set */
#define PWR_PUCRA_PA10_Pos (10U)
#define PWR_PUCRA_PA10_Msk (0x1UL << PWR_PUCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PUCRA_PA10 PWR_PUCRA_PA10_Msk /*!< Port PA10 Pull-Up set */
#define PWR_PUCRA_PA9_Pos (9U)
#define PWR_PUCRA_PA9_Msk (0x1UL << PWR_PUCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PUCRA_PA9 PWR_PUCRA_PA9_Msk /*!< Port PA9 Pull-Up set */
#define PWR_PUCRA_PA8_Pos (8U)
#define PWR_PUCRA_PA8_Msk (0x1UL << PWR_PUCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PUCRA_PA8 PWR_PUCRA_PA8_Msk /*!< Port PA8 Pull-Up set */
#define PWR_PUCRA_PA7_Pos (7U)
#define PWR_PUCRA_PA7_Msk (0x1UL << PWR_PUCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PUCRA_PA7 PWR_PUCRA_PA7_Msk /*!< Port PA7 Pull-Up set */
#define PWR_PUCRA_PA6_Pos (6U)
#define PWR_PUCRA_PA6_Msk (0x1UL << PWR_PUCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PUCRA_PA6 PWR_PUCRA_PA6_Msk /*!< Port PA6 Pull-Up set */
#define PWR_PUCRA_PA5_Pos (5U)
#define PWR_PUCRA_PA5_Msk (0x1UL << PWR_PUCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PUCRA_PA5 PWR_PUCRA_PA5_Msk /*!< Port PA5 Pull-Up set */
#define PWR_PUCRA_PA4_Pos (4U)
#define PWR_PUCRA_PA4_Msk (0x1UL << PWR_PUCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PUCRA_PA4 PWR_PUCRA_PA4_Msk /*!< Port PA4 Pull-Up set */
#define PWR_PUCRA_PA3_Pos (3U)
#define PWR_PUCRA_PA3_Msk (0x1UL << PWR_PUCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PUCRA_PA3 PWR_PUCRA_PA3_Msk /*!< Port PA3 Pull-Up set */
#define PWR_PUCRA_PA2_Pos (2U)
#define PWR_PUCRA_PA2_Msk (0x1UL << PWR_PUCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PUCRA_PA2 PWR_PUCRA_PA2_Msk /*!< Port PA2 Pull-Up set */
#define PWR_PUCRA_PA1_Pos (1U)
#define PWR_PUCRA_PA1_Msk (0x1UL << PWR_PUCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PUCRA_PA1 PWR_PUCRA_PA1_Msk /*!< Port PA1 Pull-Up set */
#define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PUCRA_PA0 PWR_PUCRA_PA0_Msk /*!< Port PA0 Pull-Up set */
/******************** Bit definition for PWR_PDCRA register ********************/
#define PWR_PDCRA_PA14_Pos (14U)
#define PWR_PDCRA_PA14_Msk (0x1UL << PWR_PDCRA_PA14_Pos) /*!< 0x00004000 */
#define PWR_PDCRA_PA14 PWR_PDCRA_PA14_Msk /*!< Port PA14 Pull-Down set */
#define PWR_PDCRA_PA12_Pos (12U)
#define PWR_PDCRA_PA12_Msk (0x1UL << PWR_PDCRA_PA12_Pos) /*!< 0x00001000 */
#define PWR_PDCRA_PA12 PWR_PDCRA_PA12_Msk /*!< Port PA12 Pull-Down set */
#define PWR_PDCRA_PA11_Pos (11U)
#define PWR_PDCRA_PA11_Msk (0x1UL << PWR_PDCRA_PA11_Pos) /*!< 0x00000800 */
#define PWR_PDCRA_PA11 PWR_PDCRA_PA11_Msk /*!< Port PA11 Pull-Down set */
#define PWR_PDCRA_PA10_Pos (10U)
#define PWR_PDCRA_PA10_Msk (0x1UL << PWR_PDCRA_PA10_Pos) /*!< 0x00000400 */
#define PWR_PDCRA_PA10 PWR_PDCRA_PA10_Msk /*!< Port PA10 Pull-Down set */
#define PWR_PDCRA_PA9_Pos (9U)
#define PWR_PDCRA_PA9_Msk (0x1UL << PWR_PDCRA_PA9_Pos) /*!< 0x00000200 */
#define PWR_PDCRA_PA9 PWR_PDCRA_PA9_Msk /*!< Port PA9 Pull-Down set */
#define PWR_PDCRA_PA8_Pos (8U)
#define PWR_PDCRA_PA8_Msk (0x1UL << PWR_PDCRA_PA8_Pos) /*!< 0x00000100 */
#define PWR_PDCRA_PA8 PWR_PDCRA_PA8_Msk /*!< Port PA8 Pull-Down set */
#define PWR_PDCRA_PA7_Pos (7U)
#define PWR_PDCRA_PA7_Msk (0x1UL << PWR_PDCRA_PA7_Pos) /*!< 0x00000080 */
#define PWR_PDCRA_PA7 PWR_PDCRA_PA7_Msk /*!< Port PA7 Pull-Down set */
#define PWR_PDCRA_PA6_Pos (6U)
#define PWR_PDCRA_PA6_Msk (0x1UL << PWR_PDCRA_PA6_Pos) /*!< 0x00000040 */
#define PWR_PDCRA_PA6 PWR_PDCRA_PA6_Msk /*!< Port PA6 Pull-Down set */
#define PWR_PDCRA_PA5_Pos (5U)
#define PWR_PDCRA_PA5_Msk (0x1UL << PWR_PDCRA_PA5_Pos) /*!< 0x00000020 */
#define PWR_PDCRA_PA5 PWR_PDCRA_PA5_Msk /*!< Port PA5 Pull-Down set */
#define PWR_PDCRA_PA4_Pos (4U)
#define PWR_PDCRA_PA4_Msk (0x1UL << PWR_PDCRA_PA4_Pos) /*!< 0x00000010 */
#define PWR_PDCRA_PA4 PWR_PDCRA_PA4_Msk /*!< Port PA4 Pull-Down set */
#define PWR_PDCRA_PA3_Pos (3U)
#define PWR_PDCRA_PA3_Msk (0x1UL << PWR_PDCRA_PA3_Pos) /*!< 0x00000008 */
#define PWR_PDCRA_PA3 PWR_PDCRA_PA3_Msk /*!< Port PA3 Pull-Down set */
#define PWR_PDCRA_PA2_Pos (2U)
#define PWR_PDCRA_PA2_Msk (0x1UL << PWR_PDCRA_PA2_Pos) /*!< 0x00000004 */
#define PWR_PDCRA_PA2 PWR_PDCRA_PA2_Msk /*!< Port PA2 Pull-Down set */
#define PWR_PDCRA_PA1_Pos (1U)
#define PWR_PDCRA_PA1_Msk (0x1UL << PWR_PDCRA_PA1_Pos) /*!< 0x00000002 */
#define PWR_PDCRA_PA1 PWR_PDCRA_PA1_Msk /*!< Port PA1 Pull-Down set */
#define PWR_PDCRA_PA0_Pos (0U)
#define PWR_PDCRA_PA0_Msk (0x1UL << PWR_PDCRA_PA0_Pos) /*!< 0x00000001 */
#define PWR_PDCRA_PA0 PWR_PDCRA_PA0_Msk /*!< Port PA0 Pull-Down set */
/******************** Bit definition for PWR_PUCRB register ********************/
#define PWR_PUCRB_PB15_Pos (15U)
#define PWR_PUCRB_PB15_Msk (0x1UL << PWR_PUCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PUCRB_PB15 PWR_PUCRB_PB15_Msk /*!< Port PB15 Pull-Up set */
#define PWR_PUCRB_PB14_Pos (14U)
#define PWR_PUCRB_PB14_Msk (0x1UL << PWR_PUCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PUCRB_PB14 PWR_PUCRB_PB14_Msk /*!< Port PB14 Pull-Up set */
#define PWR_PUCRB_PB13_Pos (13U)
#define PWR_PUCRB_PB13_Msk (0x1UL << PWR_PUCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PUCRB_PB13 PWR_PUCRB_PB13_Msk /*!< Port PB13 Pull-Up set */
#define PWR_PUCRB_PB12_Pos (12U)
#define PWR_PUCRB_PB12_Msk (0x1UL << PWR_PUCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PUCRB_PB12 PWR_PUCRB_PB12_Msk /*!< Port PB12 Pull-Up set */
#define PWR_PUCRB_PB11_Pos (11U)
#define PWR_PUCRB_PB11_Msk (0x1UL << PWR_PUCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PUCRB_PB11 PWR_PUCRB_PB11_Msk /*!< Port PB11 Pull-Up set */
#define PWR_PUCRB_PB10_Pos (10U)
#define PWR_PUCRB_PB10_Msk (0x1UL << PWR_PUCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PUCRB_PB10 PWR_PUCRB_PB10_Msk /*!< Port PB10 Pull-Up set */
#define PWR_PUCRB_PB9_Pos (9U)
#define PWR_PUCRB_PB9_Msk (0x1UL << PWR_PUCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PUCRB_PB9 PWR_PUCRB_PB9_Msk /*!< Port PB9 Pull-Up set */
#define PWR_PUCRB_PB8_Pos (8U)
#define PWR_PUCRB_PB8_Msk (0x1UL << PWR_PUCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PUCRB_PB8 PWR_PUCRB_PB8_Msk /*!< Port PB8 Pull-Up set */
#define PWR_PUCRB_PB7_Pos (7U)
#define PWR_PUCRB_PB7_Msk (0x1UL << PWR_PUCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PUCRB_PB7 PWR_PUCRB_PB7_Msk /*!< Port PB7 Pull-Up set */
#define PWR_PUCRB_PB6_Pos (6U)
#define PWR_PUCRB_PB6_Msk (0x1UL << PWR_PUCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PUCRB_PB6 PWR_PUCRB_PB6_Msk /*!< Port PB6 Pull-Up set */
#define PWR_PUCRB_PB5_Pos (5U)
#define PWR_PUCRB_PB5_Msk (0x1UL << PWR_PUCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PUCRB_PB5 PWR_PUCRB_PB5_Msk /*!< Port PB5 Pull-Up set */
#define PWR_PUCRB_PB4_Pos (4U)
#define PWR_PUCRB_PB4_Msk (0x1UL << PWR_PUCRB_PB4_Pos) /*!< 0x00000010 */
#define PWR_PUCRB_PB4 PWR_PUCRB_PB4_Msk /*!< Port PB4 Pull-Up set */
#define PWR_PUCRB_PB3_Pos (3U)
#define PWR_PUCRB_PB3_Msk (0x1UL << PWR_PUCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PUCRB_PB3 PWR_PUCRB_PB3_Msk /*!< Port PB3 Pull-Up set */
#define PWR_PUCRB_PB2_Pos (2U)
#define PWR_PUCRB_PB2_Msk (0x1UL << PWR_PUCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PUCRB_PB2 PWR_PUCRB_PB2_Msk /*!< Port PB2 Pull-Up set */
#define PWR_PUCRB_PB1_Pos (1U)
#define PWR_PUCRB_PB1_Msk (0x1UL << PWR_PUCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PUCRB_PB1 PWR_PUCRB_PB1_Msk /*!< Port PB1 Pull-Up set */
#define PWR_PUCRB_PB0_Pos (0U)
#define PWR_PUCRB_PB0_Msk (0x1UL << PWR_PUCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PUCRB_PB0 PWR_PUCRB_PB0_Msk /*!< Port PB0 Pull-Up set */
/******************** Bit definition for PWR_PDCRB register ********************/
#define PWR_PDCRB_PB15_Pos (15U)
#define PWR_PDCRB_PB15_Msk (0x1UL << PWR_PDCRB_PB15_Pos) /*!< 0x00008000 */
#define PWR_PDCRB_PB15 PWR_PDCRB_PB15_Msk /*!< Port PB15 Pull-Down set */
#define PWR_PDCRB_PB14_Pos (14U)
#define PWR_PDCRB_PB14_Msk (0x1UL << PWR_PDCRB_PB14_Pos) /*!< 0x00004000 */
#define PWR_PDCRB_PB14 PWR_PDCRB_PB14_Msk /*!< Port PB14 Pull-Down set */
#define PWR_PDCRB_PB13_Pos (13U)
#define PWR_PDCRB_PB13_Msk (0x1UL << PWR_PDCRB_PB13_Pos) /*!< 0x00002000 */
#define PWR_PDCRB_PB13 PWR_PDCRB_PB13_Msk /*!< Port PB13 Pull-Down set */
#define PWR_PDCRB_PB12_Pos (12U)
#define PWR_PDCRB_PB12_Msk (0x1UL << PWR_PDCRB_PB12_Pos) /*!< 0x00001000 */
#define PWR_PDCRB_PB12 PWR_PDCRB_PB12_Msk /*!< Port PB12 Pull-Down set */
#define PWR_PDCRB_PB11_Pos (11U)
#define PWR_PDCRB_PB11_Msk (0x1UL << PWR_PDCRB_PB11_Pos) /*!< 0x00000800 */
#define PWR_PDCRB_PB11 PWR_PDCRB_PB11_Msk /*!< Port PB11 Pull-Down set */
#define PWR_PDCRB_PB10_Pos (10U)
#define PWR_PDCRB_PB10_Msk (0x1UL << PWR_PDCRB_PB10_Pos) /*!< 0x00000400 */
#define PWR_PDCRB_PB10 PWR_PDCRB_PB10_Msk /*!< Port PB10 Pull-Down set */
#define PWR_PDCRB_PB9_Pos (9U)
#define PWR_PDCRB_PB9_Msk (0x1UL << PWR_PDCRB_PB9_Pos) /*!< 0x00000200 */
#define PWR_PDCRB_PB9 PWR_PDCRB_PB9_Msk /*!< Port PB9 Pull-Down set */
#define PWR_PDCRB_PB8_Pos (8U)
#define PWR_PDCRB_PB8_Msk (0x1UL << PWR_PDCRB_PB8_Pos) /*!< 0x00000100 */
#define PWR_PDCRB_PB8 PWR_PDCRB_PB8_Msk /*!< Port PB8 Pull-Down set */
#define PWR_PDCRB_PB7_Pos (7U)
#define PWR_PDCRB_PB7_Msk (0x1UL << PWR_PDCRB_PB7_Pos) /*!< 0x00000080 */
#define PWR_PDCRB_PB7 PWR_PDCRB_PB7_Msk /*!< Port PB7 Pull-Down set */
#define PWR_PDCRB_PB6_Pos (6U)
#define PWR_PDCRB_PB6_Msk (0x1UL << PWR_PDCRB_PB6_Pos) /*!< 0x00000040 */
#define PWR_PDCRB_PB6 PWR_PDCRB_PB6_Msk /*!< Port PB6 Pull-Down set */
#define PWR_PDCRB_PB5_Pos (5U)
#define PWR_PDCRB_PB5_Msk (0x1UL << PWR_PDCRB_PB5_Pos) /*!< 0x00000020 */
#define PWR_PDCRB_PB5 PWR_PDCRB_PB5_Msk /*!< Port PB5 Pull-Down set */
#define PWR_PDCRB_PB3_Pos (3U)
#define PWR_PDCRB_PB3_Msk (0x1UL << PWR_PDCRB_PB3_Pos) /*!< 0x00000008 */
#define PWR_PDCRB_PB3 PWR_PDCRB_PB3_Msk /*!< Port PB3 Pull-Down set */
#define PWR_PDCRB_PB2_Pos (2U)
#define PWR_PDCRB_PB2_Msk (0x1UL << PWR_PDCRB_PB2_Pos) /*!< 0x00000004 */
#define PWR_PDCRB_PB2 PWR_PDCRB_PB2_Msk /*!< Port PB2 Pull-Down set */
#define PWR_PDCRB_PB1_Pos (1U)
#define PWR_PDCRB_PB1_Msk (0x1UL << PWR_PDCRB_PB1_Pos) /*!< 0x00000002 */
#define PWR_PDCRB_PB1 PWR_PDCRB_PB1_Msk /*!< Port PB1 Pull-Down set */
#define PWR_PDCRB_PB0_Pos (0U)
#define PWR_PDCRB_PB0_Msk (0x1UL << PWR_PDCRB_PB0_Pos) /*!< 0x00000001 */
#define PWR_PDCRB_PB0 PWR_PDCRB_PB0_Msk /*!< Port PB0 Pull-Down set */
/******************** Bit definition for PWR_PUCRC register ********************/
#define PWR_PUCRC_PC15_Pos (15U)
#define PWR_PUCRC_PC15_Msk (0x1UL << PWR_PUCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PUCRC_PC15 PWR_PUCRC_PC15_Msk /*!< Port PC15 Pull-Up set */
#define PWR_PUCRC_PC14_Pos (14U)
#define PWR_PUCRC_PC14_Msk (0x1UL << PWR_PUCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PUCRC_PC14 PWR_PUCRC_PC14_Msk /*!< Port PC14 Pull-Up set */
#define PWR_PUCRC_PC13_Pos (13U)
#define PWR_PUCRC_PC13_Msk (0x1UL << PWR_PUCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PUCRC_PC13 PWR_PUCRC_PC13_Msk /*!< Port PC13 Pull-Up set */
#define PWR_PUCRC_PC12_Pos (12U)
#define PWR_PUCRC_PC12_Msk (0x1UL << PWR_PUCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PUCRC_PC12 PWR_PUCRC_PC12_Msk /*!< Port PC12 Pull-Up set */
#define PWR_PUCRC_PC11_Pos (11U)
#define PWR_PUCRC_PC11_Msk (0x1UL << PWR_PUCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PUCRC_PC11 PWR_PUCRC_PC11_Msk /*!< Port PC11 Pull-Up set */
#define PWR_PUCRC_PC10_Pos (10U)
#define PWR_PUCRC_PC10_Msk (0x1UL << PWR_PUCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PUCRC_PC10 PWR_PUCRC_PC10_Msk /*!< Port PC10 Pull-Up set */
#define PWR_PUCRC_PC9_Pos (9U)
#define PWR_PUCRC_PC9_Msk (0x1UL << PWR_PUCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PUCRC_PC9 PWR_PUCRC_PC9_Msk /*!< Port PC9 Pull-Up set */
#define PWR_PUCRC_PC8_Pos (8U)
#define PWR_PUCRC_PC8_Msk (0x1UL << PWR_PUCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PUCRC_PC8 PWR_PUCRC_PC8_Msk /*!< Port PC8 Pull-Up set */
#define PWR_PUCRC_PC7_Pos (7U)
#define PWR_PUCRC_PC7_Msk (0x1UL << PWR_PUCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PUCRC_PC7 PWR_PUCRC_PC7_Msk /*!< Port PC7 Pull-Up set */
#define PWR_PUCRC_PC6_Pos (6U)
#define PWR_PUCRC_PC6_Msk (0x1UL << PWR_PUCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PUCRC_PC6 PWR_PUCRC_PC6_Msk /*!< Port PC6 Pull-Up set */
#define PWR_PUCRC_PC5_Pos (5U)
#define PWR_PUCRC_PC5_Msk (0x1UL << PWR_PUCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PUCRC_PC5 PWR_PUCRC_PC5_Msk /*!< Port PC5 Pull-Up set */
#define PWR_PUCRC_PC4_Pos (4U)
#define PWR_PUCRC_PC4_Msk (0x1UL << PWR_PUCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PUCRC_PC4 PWR_PUCRC_PC4_Msk /*!< Port PC4 Pull-Up set */
#define PWR_PUCRC_PC3_Pos (3U)
#define PWR_PUCRC_PC3_Msk (0x1UL << PWR_PUCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PUCRC_PC3 PWR_PUCRC_PC3_Msk /*!< Port PC3 Pull-Up set */
#define PWR_PUCRC_PC2_Pos (2U)
#define PWR_PUCRC_PC2_Msk (0x1UL << PWR_PUCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PUCRC_PC2 PWR_PUCRC_PC2_Msk /*!< Port PC2 Pull-Up set */
#define PWR_PUCRC_PC1_Pos (1U)
#define PWR_PUCRC_PC1_Msk (0x1UL << PWR_PUCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PUCRC_PC1 PWR_PUCRC_PC1_Msk /*!< Port PC1 Pull-Up set */
#define PWR_PUCRC_PC0_Pos (0U)
#define PWR_PUCRC_PC0_Msk (0x1UL << PWR_PUCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PUCRC_PC0 PWR_PUCRC_PC0_Msk /*!< Port PC0 Pull-Up set */
/******************** Bit definition for PWR_PDCRC register ********************/
#define PWR_PDCRC_PC15_Pos (15U)
#define PWR_PDCRC_PC15_Msk (0x1UL << PWR_PDCRC_PC15_Pos) /*!< 0x00008000 */
#define PWR_PDCRC_PC15 PWR_PDCRC_PC15_Msk /*!< Port PC15 Pull-Down set */
#define PWR_PDCRC_PC14_Pos (14U)
#define PWR_PDCRC_PC14_Msk (0x1UL << PWR_PDCRC_PC14_Pos) /*!< 0x00004000 */
#define PWR_PDCRC_PC14 PWR_PDCRC_PC14_Msk /*!< Port PC14 Pull-Down set */
#define PWR_PDCRC_PC13_Pos (13U)
#define PWR_PDCRC_PC13_Msk (0x1UL << PWR_PDCRC_PC13_Pos) /*!< 0x00002000 */
#define PWR_PDCRC_PC13 PWR_PDCRC_PC13_Msk /*!< Port PC13 Pull-Down set */
#define PWR_PDCRC_PC12_Pos (12U)
#define PWR_PDCRC_PC12_Msk (0x1UL << PWR_PDCRC_PC12_Pos) /*!< 0x00001000 */
#define PWR_PDCRC_PC12 PWR_PDCRC_PC12_Msk /*!< Port PC12 Pull-Down set */
#define PWR_PDCRC_PC11_Pos (11U)
#define PWR_PDCRC_PC11_Msk (0x1UL << PWR_PDCRC_PC11_Pos) /*!< 0x00000800 */
#define PWR_PDCRC_PC11 PWR_PDCRC_PC11_Msk /*!< Port PC11 Pull-Down set */
#define PWR_PDCRC_PC10_Pos (10U)
#define PWR_PDCRC_PC10_Msk (0x1UL << PWR_PDCRC_PC10_Pos) /*!< 0x00000400 */
#define PWR_PDCRC_PC10 PWR_PDCRC_PC10_Msk /*!< Port PC10 Pull-Down set */
#define PWR_PDCRC_PC9_Pos (9U)
#define PWR_PDCRC_PC9_Msk (0x1UL << PWR_PDCRC_PC9_Pos) /*!< 0x00000200 */
#define PWR_PDCRC_PC9 PWR_PDCRC_PC9_Msk /*!< Port PC9 Pull-Down set */
#define PWR_PDCRC_PC8_Pos (8U)
#define PWR_PDCRC_PC8_Msk (0x1UL << PWR_PDCRC_PC8_Pos) /*!< 0x00000100 */
#define PWR_PDCRC_PC8 PWR_PDCRC_PC8_Msk /*!< Port PC8 Pull-Down set */
#define PWR_PDCRC_PC7_Pos (7U)
#define PWR_PDCRC_PC7_Msk (0x1UL << PWR_PDCRC_PC7_Pos) /*!< 0x00000080 */
#define PWR_PDCRC_PC7 PWR_PDCRC_PC7_Msk /*!< Port PC7 Pull-Down set */
#define PWR_PDCRC_PC6_Pos (6U)
#define PWR_PDCRC_PC6_Msk (0x1UL << PWR_PDCRC_PC6_Pos) /*!< 0x00000040 */
#define PWR_PDCRC_PC6 PWR_PDCRC_PC6_Msk /*!< Port PC6 Pull-Down set */
#define PWR_PDCRC_PC5_Pos (5U)
#define PWR_PDCRC_PC5_Msk (0x1UL << PWR_PDCRC_PC5_Pos) /*!< 0x00000020 */
#define PWR_PDCRC_PC5 PWR_PDCRC_PC5_Msk /*!< Port PC5 Pull-Down set */
#define PWR_PDCRC_PC4_Pos (4U)
#define PWR_PDCRC_PC4_Msk (0x1UL << PWR_PDCRC_PC4_Pos) /*!< 0x00000010 */
#define PWR_PDCRC_PC4 PWR_PDCRC_PC4_Msk /*!< Port PC4 Pull-Down set */
#define PWR_PDCRC_PC3_Pos (3U)
#define PWR_PDCRC_PC3_Msk (0x1UL << PWR_PDCRC_PC3_Pos) /*!< 0x00000008 */
#define PWR_PDCRC_PC3 PWR_PDCRC_PC3_Msk /*!< Port PC3 Pull-Down set */
#define PWR_PDCRC_PC2_Pos (2U)
#define PWR_PDCRC_PC2_Msk (0x1UL << PWR_PDCRC_PC2_Pos) /*!< 0x00000004 */
#define PWR_PDCRC_PC2 PWR_PDCRC_PC2_Msk /*!< Port PC2 Pull-Down set */
#define PWR_PDCRC_PC1_Pos (1U)
#define PWR_PDCRC_PC1_Msk (0x1UL << PWR_PDCRC_PC1_Pos) /*!< 0x00000002 */
#define PWR_PDCRC_PC1 PWR_PDCRC_PC1_Msk /*!< Port PC1 Pull-Down set */
#define PWR_PDCRC_PC0_Pos (0U)
#define PWR_PDCRC_PC0_Msk (0x1UL << PWR_PDCRC_PC0_Pos) /*!< 0x00000001 */
#define PWR_PDCRC_PC0 PWR_PDCRC_PC0_Msk /*!< Port PC0 Pull-Down set */
/******************** Bit definition for PWR_PUCRD register ********************/
#define PWR_PUCRD_PD15_Pos (15U)
#define PWR_PUCRD_PD15_Msk (0x1UL << PWR_PUCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PUCRD_PD15 PWR_PUCRD_PD15_Msk /*!< Port PD15 Pull-Up set */
#define PWR_PUCRD_PD14_Pos (14U)
#define PWR_PUCRD_PD14_Msk (0x1UL << PWR_PUCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PUCRD_PD14 PWR_PUCRD_PD14_Msk /*!< Port PD14 Pull-Up set */
#define PWR_PUCRD_PD13_Pos (13U)
#define PWR_PUCRD_PD13_Msk (0x1UL << PWR_PUCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PUCRD_PD13 PWR_PUCRD_PD13_Msk /*!< Port PD13 Pull-Up set */
#define PWR_PUCRD_PD12_Pos (12U)
#define PWR_PUCRD_PD12_Msk (0x1UL << PWR_PUCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PUCRD_PD12 PWR_PUCRD_PD12_Msk /*!< Port PD12 Pull-Up set */
#define PWR_PUCRD_PD11_Pos (11U)
#define PWR_PUCRD_PD11_Msk (0x1UL << PWR_PUCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PUCRD_PD11 PWR_PUCRD_PD11_Msk /*!< Port PD11 Pull-Up set */
#define PWR_PUCRD_PD10_Pos (10U)
#define PWR_PUCRD_PD10_Msk (0x1UL << PWR_PUCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PUCRD_PD10 PWR_PUCRD_PD10_Msk /*!< Port PD10 Pull-Up set */
#define PWR_PUCRD_PD9_Pos (9U)
#define PWR_PUCRD_PD9_Msk (0x1UL << PWR_PUCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PUCRD_PD9 PWR_PUCRD_PD9_Msk /*!< Port PD9 Pull-Up set */
#define PWR_PUCRD_PD8_Pos (8U)
#define PWR_PUCRD_PD8_Msk (0x1UL << PWR_PUCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PUCRD_PD8 PWR_PUCRD_PD8_Msk /*!< Port PD8 Pull-Up set */
#define PWR_PUCRD_PD7_Pos (7U)
#define PWR_PUCRD_PD7_Msk (0x1UL << PWR_PUCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PUCRD_PD7 PWR_PUCRD_PD7_Msk /*!< Port PD7 Pull-Up set */
#define PWR_PUCRD_PD6_Pos (6U)
#define PWR_PUCRD_PD6_Msk (0x1UL << PWR_PUCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PUCRD_PD6 PWR_PUCRD_PD6_Msk /*!< Port PD6 Pull-Up set */
#define PWR_PUCRD_PD5_Pos (5U)
#define PWR_PUCRD_PD5_Msk (0x1UL << PWR_PUCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PUCRD_PD5 PWR_PUCRD_PD5_Msk /*!< Port PD5 Pull-Up set */
#define PWR_PUCRD_PD4_Pos (4U)
#define PWR_PUCRD_PD4_Msk (0x1UL << PWR_PUCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PUCRD_PD4 PWR_PUCRD_PD4_Msk /*!< Port PD4 Pull-Up set */
#define PWR_PUCRD_PD3_Pos (3U)
#define PWR_PUCRD_PD3_Msk (0x1UL << PWR_PUCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PUCRD_PD3 PWR_PUCRD_PD3_Msk /*!< Port PD3 Pull-Up set */
#define PWR_PUCRD_PD2_Pos (2U)
#define PWR_PUCRD_PD2_Msk (0x1UL << PWR_PUCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PUCRD_PD2 PWR_PUCRD_PD2_Msk /*!< Port PD2 Pull-Up set */
#define PWR_PUCRD_PD1_Pos (1U)
#define PWR_PUCRD_PD1_Msk (0x1UL << PWR_PUCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PUCRD_PD1 PWR_PUCRD_PD1_Msk /*!< Port PD1 Pull-Up set */
#define PWR_PUCRD_PD0_Pos (0U)
#define PWR_PUCRD_PD0_Msk (0x1UL << PWR_PUCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PUCRD_PD0 PWR_PUCRD_PD0_Msk /*!< Port PD0 Pull-Up set */
/******************** Bit definition for PWR_PDCRD register ********************/
#define PWR_PDCRD_PD15_Pos (15U)
#define PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) /*!< 0x00008000 */
#define PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk /*!< Port PD15 Pull-Down set */
#define PWR_PDCRD_PD14_Pos (14U)
#define PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) /*!< 0x00004000 */
#define PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk /*!< Port PD14 Pull-Down set */
#define PWR_PDCRD_PD13_Pos (13U)
#define PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) /*!< 0x00002000 */
#define PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk /*!< Port PD13 Pull-Down set */
#define PWR_PDCRD_PD12_Pos (12U)
#define PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) /*!< 0x00001000 */
#define PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk /*!< Port PD12 Pull-Down set */
#define PWR_PDCRD_PD11_Pos (11U)
#define PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) /*!< 0x00000800 */
#define PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk /*!< Port PD11 Pull-Down set */
#define PWR_PDCRD_PD10_Pos (10U)
#define PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) /*!< 0x00000400 */
#define PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk /*!< Port PD10 Pull-Down set */
#define PWR_PDCRD_PD9_Pos (9U)
#define PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) /*!< 0x00000200 */
#define PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk /*!< Port PD9 Pull-Down set */
#define PWR_PDCRD_PD8_Pos (8U)
#define PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) /*!< 0x00000100 */
#define PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk /*!< Port PD8 Pull-Down set */
#define PWR_PDCRD_PD7_Pos (7U)
#define PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) /*!< 0x00000080 */
#define PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk /*!< Port PD7 Pull-Down set */
#define PWR_PDCRD_PD6_Pos (6U)
#define PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) /*!< 0x00000040 */
#define PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk /*!< Port PD6 Pull-Down set */
#define PWR_PDCRD_PD5_Pos (5U)
#define PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) /*!< 0x00000020 */
#define PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk /*!< Port PD5 Pull-Down set */
#define PWR_PDCRD_PD4_Pos (4U)
#define PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) /*!< 0x00000010 */
#define PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk /*!< Port PD4 Pull-Down set */
#define PWR_PDCRD_PD3_Pos (3U)
#define PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) /*!< 0x00000008 */
#define PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk /*!< Port PD3 Pull-Down set */
#define PWR_PDCRD_PD2_Pos (2U)
#define PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) /*!< 0x00000004 */
#define PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk /*!< Port PD2 Pull-Down set */
#define PWR_PDCRD_PD1_Pos (1U)
#define PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) /*!< 0x00000002 */
#define PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk /*!< Port PD1 Pull-Down set */
#define PWR_PDCRD_PD0_Pos (0U)
#define PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) /*!< 0x00000001 */
#define PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk /*!< Port PD0 Pull-Down set */
/******************** Bit definition for PWR_PUCRE register ********************/
#define PWR_PUCRE_PE15_Pos (15U)
#define PWR_PUCRE_PE15_Msk (0x1UL << PWR_PUCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PUCRE_PE15 PWR_PUCRE_PE15_Msk /*!< Port PE15 Pull-Up set */
#define PWR_PUCRE_PE14_Pos (14U)
#define PWR_PUCRE_PE14_Msk (0x1UL << PWR_PUCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PUCRE_PE14 PWR_PUCRE_PE14_Msk /*!< Port PE14 Pull-Up set */
#define PWR_PUCRE_PE13_Pos (13U)
#define PWR_PUCRE_PE13_Msk (0x1UL << PWR_PUCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PUCRE_PE13 PWR_PUCRE_PE13_Msk /*!< Port PE13 Pull-Up set */
#define PWR_PUCRE_PE12_Pos (12U)
#define PWR_PUCRE_PE12_Msk (0x1UL << PWR_PUCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PUCRE_PE12 PWR_PUCRE_PE12_Msk /*!< Port PE12 Pull-Up set */
#define PWR_PUCRE_PE11_Pos (11U)
#define PWR_PUCRE_PE11_Msk (0x1UL << PWR_PUCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PUCRE_PE11 PWR_PUCRE_PE11_Msk /*!< Port PE11 Pull-Up set */
#define PWR_PUCRE_PE10_Pos (10U)
#define PWR_PUCRE_PE10_Msk (0x1UL << PWR_PUCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PUCRE_PE10 PWR_PUCRE_PE10_Msk /*!< Port PE10 Pull-Up set */
#define PWR_PUCRE_PE9_Pos (9U)
#define PWR_PUCRE_PE9_Msk (0x1UL << PWR_PUCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PUCRE_PE9 PWR_PUCRE_PE9_Msk /*!< Port PE9 Pull-Up set */
#define PWR_PUCRE_PE8_Pos (8U)
#define PWR_PUCRE_PE8_Msk (0x1UL << PWR_PUCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PUCRE_PE8 PWR_PUCRE_PE8_Msk /*!< Port PE8 Pull-Up set */
#define PWR_PUCRE_PE7_Pos (7U)
#define PWR_PUCRE_PE7_Msk (0x1UL << PWR_PUCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PUCRE_PE7 PWR_PUCRE_PE7_Msk /*!< Port PE7 Pull-Up set */
#define PWR_PUCRE_PE6_Pos (6U)
#define PWR_PUCRE_PE6_Msk (0x1UL << PWR_PUCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PUCRE_PE6 PWR_PUCRE_PE6_Msk /*!< Port PE6 Pull-Up set */
#define PWR_PUCRE_PE5_Pos (5U)
#define PWR_PUCRE_PE5_Msk (0x1UL << PWR_PUCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PUCRE_PE5 PWR_PUCRE_PE5_Msk /*!< Port PE5 Pull-Up set */
#define PWR_PUCRE_PE4_Pos (4U)
#define PWR_PUCRE_PE4_Msk (0x1UL << PWR_PUCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PUCRE_PE4 PWR_PUCRE_PE4_Msk /*!< Port PE4 Pull-Up set */
#define PWR_PUCRE_PE3_Pos (3U)
#define PWR_PUCRE_PE3_Msk (0x1UL << PWR_PUCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PUCRE_PE3 PWR_PUCRE_PE3_Msk /*!< Port PE3 Pull-Up set */
#define PWR_PUCRE_PE2_Pos (2U)
#define PWR_PUCRE_PE2_Msk (0x1UL << PWR_PUCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PUCRE_PE2 PWR_PUCRE_PE2_Msk /*!< Port PE2 Pull-Up set */
#define PWR_PUCRE_PE1_Pos (1U)
#define PWR_PUCRE_PE1_Msk (0x1UL << PWR_PUCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PUCRE_PE1 PWR_PUCRE_PE1_Msk /*!< Port PE1 Pull-Up set */
#define PWR_PUCRE_PE0_Pos (0U)
#define PWR_PUCRE_PE0_Msk (0x1UL << PWR_PUCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PUCRE_PE0 PWR_PUCRE_PE0_Msk /*!< Port PE0 Pull-Up set */
/******************** Bit definition for PWR_PDCRE register ********************/
#define PWR_PDCRE_PE15_Pos (15U)
#define PWR_PDCRE_PE15_Msk (0x1UL << PWR_PDCRE_PE15_Pos) /*!< 0x00008000 */
#define PWR_PDCRE_PE15 PWR_PDCRE_PE15_Msk /*!< Port PE15 Pull-Down set */
#define PWR_PDCRE_PE14_Pos (14U)
#define PWR_PDCRE_PE14_Msk (0x1UL << PWR_PDCRE_PE14_Pos) /*!< 0x00004000 */
#define PWR_PDCRE_PE14 PWR_PDCRE_PE14_Msk /*!< Port PE14 Pull-Down set */
#define PWR_PDCRE_PE13_Pos (13U)
#define PWR_PDCRE_PE13_Msk (0x1UL << PWR_PDCRE_PE13_Pos) /*!< 0x00002000 */
#define PWR_PDCRE_PE13 PWR_PDCRE_PE13_Msk /*!< Port PE13 Pull-Down set */
#define PWR_PDCRE_PE12_Pos (12U)
#define PWR_PDCRE_PE12_Msk (0x1UL << PWR_PDCRE_PE12_Pos) /*!< 0x00001000 */
#define PWR_PDCRE_PE12 PWR_PDCRE_PE12_Msk /*!< Port PE12 Pull-Down set */
#define PWR_PDCRE_PE11_Pos (11U)
#define PWR_PDCRE_PE11_Msk (0x1UL << PWR_PDCRE_PE11_Pos) /*!< 0x00000800 */
#define PWR_PDCRE_PE11 PWR_PDCRE_PE11_Msk /*!< Port PE11 Pull-Down set */
#define PWR_PDCRE_PE10_Pos (10U)
#define PWR_PDCRE_PE10_Msk (0x1UL << PWR_PDCRE_PE10_Pos) /*!< 0x00000400 */
#define PWR_PDCRE_PE10 PWR_PDCRE_PE10_Msk /*!< Port PE10 Pull-Down set */
#define PWR_PDCRE_PE9_Pos (9U)
#define PWR_PDCRE_PE9_Msk (0x1UL << PWR_PDCRE_PE9_Pos) /*!< 0x00000200 */
#define PWR_PDCRE_PE9 PWR_PDCRE_PE9_Msk /*!< Port PE9 Pull-Down set */
#define PWR_PDCRE_PE8_Pos (8U)
#define PWR_PDCRE_PE8_Msk (0x1UL << PWR_PDCRE_PE8_Pos) /*!< 0x00000100 */
#define PWR_PDCRE_PE8 PWR_PDCRE_PE8_Msk /*!< Port PE8 Pull-Down set */
#define PWR_PDCRE_PE7_Pos (7U)
#define PWR_PDCRE_PE7_Msk (0x1UL << PWR_PDCRE_PE7_Pos) /*!< 0x00000080 */
#define PWR_PDCRE_PE7 PWR_PDCRE_PE7_Msk /*!< Port PE7 Pull-Down set */
#define PWR_PDCRE_PE6_Pos (6U)
#define PWR_PDCRE_PE6_Msk (0x1UL << PWR_PDCRE_PE6_Pos) /*!< 0x00000040 */
#define PWR_PDCRE_PE6 PWR_PDCRE_PE6_Msk /*!< Port PE6 Pull-Down set */
#define PWR_PDCRE_PE5_Pos (5U)
#define PWR_PDCRE_PE5_Msk (0x1UL << PWR_PDCRE_PE5_Pos) /*!< 0x00000020 */
#define PWR_PDCRE_PE5 PWR_PDCRE_PE5_Msk /*!< Port PE5 Pull-Down set */
#define PWR_PDCRE_PE4_Pos (4U)
#define PWR_PDCRE_PE4_Msk (0x1UL << PWR_PDCRE_PE4_Pos) /*!< 0x00000010 */
#define PWR_PDCRE_PE4 PWR_PDCRE_PE4_Msk /*!< Port PE4 Pull-Down set */
#define PWR_PDCRE_PE3_Pos (3U)
#define PWR_PDCRE_PE3_Msk (0x1UL << PWR_PDCRE_PE3_Pos) /*!< 0x00000008 */
#define PWR_PDCRE_PE3 PWR_PDCRE_PE3_Msk /*!< Port PE3 Pull-Down set */
#define PWR_PDCRE_PE2_Pos (2U)
#define PWR_PDCRE_PE2_Msk (0x1UL << PWR_PDCRE_PE2_Pos) /*!< 0x00000004 */
#define PWR_PDCRE_PE2 PWR_PDCRE_PE2_Msk /*!< Port PE2 Pull-Down set */
#define PWR_PDCRE_PE1_Pos (1U)
#define PWR_PDCRE_PE1_Msk (0x1UL << PWR_PDCRE_PE1_Pos) /*!< 0x00000002 */
#define PWR_PDCRE_PE1 PWR_PDCRE_PE1_Msk /*!< Port PE1 Pull-Down set */
#define PWR_PDCRE_PE0_Pos (0U)
#define PWR_PDCRE_PE0_Msk (0x1UL << PWR_PDCRE_PE0_Pos) /*!< 0x00000001 */
#define PWR_PDCRE_PE0 PWR_PDCRE_PE0_Msk /*!< Port PE0 Pull-Down set */
/******************** Bit definition for PWR_PUCRF register ********************/
#define PWR_PUCRF_PF15_Pos (15U)
#define PWR_PUCRF_PF15_Msk (0x1UL << PWR_PUCRF_PF15_Pos) /*!< 0x00008000 */
#define PWR_PUCRF_PF15 PWR_PUCRF_PF15_Msk /*!< Port PF15 Pull-Up set */
#define PWR_PUCRF_PF14_Pos (14U)
#define PWR_PUCRF_PF14_Msk (0x1UL << PWR_PUCRF_PF14_Pos) /*!< 0x00004000 */
#define PWR_PUCRF_PF14 PWR_PUCRF_PF14_Msk /*!< Port PF14 Pull-Up set */
#define PWR_PUCRF_PF13_Pos (13U)
#define PWR_PUCRF_PF13_Msk (0x1UL << PWR_PUCRF_PF13_Pos) /*!< 0x00002000 */
#define PWR_PUCRF_PF13 PWR_PUCRF_PF13_Msk /*!< Port PF13 Pull-Up set */
#define PWR_PUCRF_PF12_Pos (12U)
#define PWR_PUCRF_PF12_Msk (0x1UL << PWR_PUCRF_PF12_Pos) /*!< 0x00001000 */
#define PWR_PUCRF_PF12 PWR_PUCRF_PF12_Msk /*!< Port PF12 Pull-Up set */
#define PWR_PUCRF_PF11_Pos (11U)
#define PWR_PUCRF_PF11_Msk (0x1UL << PWR_PUCRF_PF11_Pos) /*!< 0x00000800 */
#define PWR_PUCRF_PF11 PWR_PUCRF_PF11_Msk /*!< Port PF11 Pull-Up set */
#define PWR_PUCRF_PF10_Pos (10U)
#define PWR_PUCRF_PF10_Msk (0x1UL << PWR_PUCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PUCRF_PF10 PWR_PUCRF_PF10_Msk /*!< Port PF10 Pull-Up set */
#define PWR_PUCRF_PF9_Pos (9U)
#define PWR_PUCRF_PF9_Msk (0x1UL << PWR_PUCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PUCRF_PF9 PWR_PUCRF_PF9_Msk /*!< Port PF9 Pull-Up set */
#define PWR_PUCRF_PF8_Pos (8U)
#define PWR_PUCRF_PF8_Msk (0x1UL << PWR_PUCRF_PF8_Pos) /*!< 0x00000100 */
#define PWR_PUCRF_PF8 PWR_PUCRF_PF8_Msk /*!< Port PF8 Pull-Up set */
#define PWR_PUCRF_PF7_Pos (7U)
#define PWR_PUCRF_PF7_Msk (0x1UL << PWR_PUCRF_PF7_Pos) /*!< 0x00000080 */
#define PWR_PUCRF_PF7 PWR_PUCRF_PF7_Msk /*!< Port PF7 Pull-Up set */
#define PWR_PUCRF_PF6_Pos (6U)
#define PWR_PUCRF_PF6_Msk (0x1UL << PWR_PUCRF_PF6_Pos) /*!< 0x00000040 */
#define PWR_PUCRF_PF6 PWR_PUCRF_PF6_Msk /*!< Port PF6 Pull-Up set */
#define PWR_PUCRF_PF5_Pos (5U)
#define PWR_PUCRF_PF5_Msk (0x1UL << PWR_PUCRF_PF5_Pos) /*!< 0x00000020 */
#define PWR_PUCRF_PF5 PWR_PUCRF_PF5_Msk /*!< Port PF5 Pull-Up set */
#define PWR_PUCRF_PF4_Pos (4U)
#define PWR_PUCRF_PF4_Msk (0x1UL << PWR_PUCRF_PF4_Pos) /*!< 0x00000010 */
#define PWR_PUCRF_PF4 PWR_PUCRF_PF4_Msk /*!< Port PF4 Pull-Up set */
#define PWR_PUCRF_PF3_Pos (3U)
#define PWR_PUCRF_PF3_Msk (0x1UL << PWR_PUCRF_PF3_Pos) /*!< 0x00000008 */
#define PWR_PUCRF_PF3 PWR_PUCRF_PF3_Msk /*!< Port PF3 Pull-Up set */
#define PWR_PUCRF_PF2_Pos (2U)
#define PWR_PUCRF_PF2_Msk (0x1UL << PWR_PUCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PUCRF_PF2 PWR_PUCRF_PF2_Msk /*!< Port PF2 Pull-Up set */
#define PWR_PUCRF_PF1_Pos (1U)
#define PWR_PUCRF_PF1_Msk (0x1UL << PWR_PUCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PUCRF_PF1 PWR_PUCRF_PF1_Msk /*!< Port PF1 Pull-Up set */
#define PWR_PUCRF_PF0_Pos (0U)
#define PWR_PUCRF_PF0_Msk (0x1UL << PWR_PUCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PUCRF_PF0 PWR_PUCRF_PF0_Msk /*!< Port PF0 Pull-Up set */
/******************** Bit definition for PWR_PDCRF register ********************/
#define PWR_PDCRF_PF10_Pos (10U)
#define PWR_PDCRF_PF10_Msk (0x1UL << PWR_PDCRF_PF10_Pos) /*!< 0x00000400 */
#define PWR_PDCRF_PF10 PWR_PDCRF_PF10_Msk /*!< Port PF10 Pull-Down set */
#define PWR_PDCRF_PF9_Pos (9U)
#define PWR_PDCRF_PF9_Msk (0x1UL << PWR_PDCRF_PF9_Pos) /*!< 0x00000200 */
#define PWR_PDCRF_PF9 PWR_PDCRF_PF9_Msk /*!< Port PF9 Pull-Down set */
#define PWR_PDCRF_PF2_Pos (2U)
#define PWR_PDCRF_PF2_Msk (0x1UL << PWR_PDCRF_PF2_Pos) /*!< 0x00000004 */
#define PWR_PDCRF_PF2 PWR_PDCRF_PF2_Msk /*!< Port PF2 Pull-Down set */
#define PWR_PDCRF_PF1_Pos (1U)
#define PWR_PDCRF_PF1_Msk (0x1UL << PWR_PDCRF_PF1_Pos) /*!< 0x00000002 */
#define PWR_PDCRF_PF1 PWR_PDCRF_PF1_Msk /*!< Port PF1 Pull-Down set */
#define PWR_PDCRF_PF0_Pos (0U)
#define PWR_PDCRF_PF0_Msk (0x1UL << PWR_PDCRF_PF0_Pos) /*!< 0x00000001 */
#define PWR_PDCRF_PF0 PWR_PDCRF_PF0_Msk /*!< Port PF0 Pull-Down set */
/******************** Bit definition for PWR_PUCRG register ********************/
#define PWR_PUCRG_PG10_Pos (10U)
#define PWR_PUCRG_PG10_Msk (0x1UL << PWR_PUCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PUCRG_PG10 PWR_PUCRG_PG10_Msk /*!< Port PG10 Pull-Up set */
/******************** Bit definition for PWR_PDCRG register ********************/
#define PWR_PDCRG_PG10_Pos (10U)
#define PWR_PDCRG_PG10_Msk (0x1UL << PWR_PDCRG_PG10_Pos) /*!< 0x00000400 */
#define PWR_PDCRG_PG10 PWR_PDCRG_PG10_Msk /*!< Port PG10 Pull-Down set */
#define PWR_PDCRG_PG9_Pos (9U)
#define PWR_PDCRG_PG9_Msk (0x1UL << PWR_PDCRG_PG9_Pos) /*!< 0x00000200 */
#define PWR_PDCRG_PG9 PWR_PDCRG_PG9_Msk /*!< Port PG9 Pull-Down set */
#define PWR_PDCRG_PG8_Pos (8U)
#define PWR_PDCRG_PG8_Msk (0x1UL << PWR_PDCRG_PG8_Pos) /*!< 0x00000100 */
#define PWR_PDCRG_PG8 PWR_PDCRG_PG8_Msk /*!< Port PG8 Pull-Down set */
#define PWR_PDCRG_PG7_Pos (7U)
#define PWR_PDCRG_PG7_Msk (0x1UL << PWR_PDCRG_PG7_Pos) /*!< 0x00000080 */
#define PWR_PDCRG_PG7 PWR_PDCRG_PG7_Msk /*!< Port PG7 Pull-Down set */
#define PWR_PDCRG_PG6_Pos (6U)
#define PWR_PDCRG_PG6_Msk (0x1UL << PWR_PDCRG_PG6_Pos) /*!< 0x00000040 */
#define PWR_PDCRG_PG6 PWR_PDCRG_PG6_Msk /*!< Port PG6 Pull-Down set */
#define PWR_PDCRG_PG5_Pos (5U)
#define PWR_PDCRG_PG5_Msk (0x1UL << PWR_PDCRG_PG5_Pos) /*!< 0x00000020 */
#define PWR_PDCRG_PG5 PWR_PDCRG_PG5_Msk /*!< Port PG5 Pull-Down set */
#define PWR_PDCRG_PG4_Pos (4U)
#define PWR_PDCRG_PG4_Msk (0x1UL << PWR_PDCRG_PG4_Pos) /*!< 0x00000010 */
#define PWR_PDCRG_PG4 PWR_PDCRG_PG4_Msk /*!< Port PG4 Pull-Down set */
#define PWR_PDCRG_PG3_Pos (3U)
#define PWR_PDCRG_PG3_Msk (0x1UL << PWR_PDCRG_PG3_Pos) /*!< 0x00000008 */
#define PWR_PDCRG_PG3 PWR_PDCRG_PG3_Msk /*!< Port PG3 Pull-Down set */
#define PWR_PDCRG_PG2_Pos (2U)
#define PWR_PDCRG_PG2_Msk (0x1UL << PWR_PDCRG_PG2_Pos) /*!< 0x00000004 */
#define PWR_PDCRG_PG2 PWR_PDCRG_PG2_Msk /*!< Port PG2 Pull-Down set */
#define PWR_PDCRG_PG1_Pos (1U)
#define PWR_PDCRG_PG1_Msk (0x1UL << PWR_PDCRG_PG1_Pos) /*!< 0x00000002 */
#define PWR_PDCRG_PG1 PWR_PDCRG_PG1_Msk /*!< Port PG1 Pull-Down set */
#define PWR_PDCRG_PG0_Pos (0U)
#define PWR_PDCRG_PG0_Msk (0x1UL << PWR_PDCRG_PG0_Pos) /*!< 0x00000001 */
#define PWR_PDCRG_PG0 PWR_PDCRG_PG0_Msk /*!< Port PG0 Pull-Down set */
/******************** Bit definition for PWR_CR5 register ********************/
#define PWR_CR5_R1MODE_Pos (8U)
#define PWR_CR5_R1MODE_Msk (0x1U << PWR_CR5_R1MODE_Pos) /*!< 0x00000100 */
#define PWR_CR5_R1MODE PWR_CR5_R1MODE_Msk /*!< selection for Main Regulator in Range1 */
/******************************************************************************/
/* */
/* QUADSPI */
/* */
/******************************************************************************/
/***************** Bit definition for QUADSPI_CR register *******************/
#define QUADSPI_CR_EN_Pos (0U)
#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
#define QUADSPI_CR_ABORT_Pos (1U)
#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
#define QUADSPI_CR_DMAEN_Pos (2U)
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
#define QUADSPI_CR_TCEN_Pos (3U)
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
#define QUADSPI_CR_SSHIFT_Pos (4U)
#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */
#define QUADSPI_CR_DFM_Pos (6U)
#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual-flash mode */
#define QUADSPI_CR_FSEL_Pos (7U)
#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash memory selection */
#define QUADSPI_CR_FTHRES_Pos (8U)
#define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
#define QUADSPI_CR_TEIE_Pos (16U)
#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
#define QUADSPI_CR_TCIE_Pos (17U)
#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
#define QUADSPI_CR_FTIE_Pos (18U)
#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
#define QUADSPI_CR_SMIE_Pos (19U)
#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
#define QUADSPI_CR_TOIE_Pos (20U)
#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
#define QUADSPI_CR_APMS_Pos (22U)
#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Automatic Polling Mode Stop */
#define QUADSPI_CR_PMM_Pos (23U)
#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
#define QUADSPI_CR_PRESCALER_Pos (24U)
#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
/***************** Bit definition for QUADSPI_DCR register ******************/
#define QUADSPI_DCR_CKMODE_Pos (0U)
#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
#define QUADSPI_DCR_CSHT_Pos (8U)
#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
#define QUADSPI_DCR_FSIZE_Pos (16U)
#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
/****************** Bit definition for QUADSPI_SR register *******************/
#define QUADSPI_SR_TEF_Pos (0U)
#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
#define QUADSPI_SR_TCF_Pos (1U)
#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
#define QUADSPI_SR_FTF_Pos (2U)
#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
#define QUADSPI_SR_SMF_Pos (3U)
#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
#define QUADSPI_SR_TOF_Pos (4U)
#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
#define QUADSPI_SR_BUSY_Pos (5U)
#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
#define QUADSPI_SR_FLEVEL_Pos (8U)
#define QUADSPI_SR_FLEVEL_Msk (0x1FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001F00 */
#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
/****************** Bit definition for QUADSPI_FCR register ******************/
#define QUADSPI_FCR_CTEF_Pos (0U)
#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
#define QUADSPI_FCR_CTCF_Pos (1U)
#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
#define QUADSPI_FCR_CSMF_Pos (3U)
#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
#define QUADSPI_FCR_CTOF_Pos (4U)
#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
/****************** Bit definition for QUADSPI_DLR register ******************/
#define QUADSPI_DLR_DL_Pos (0U)
#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
/****************** Bit definition for QUADSPI_CCR register ******************/
#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
#define QUADSPI_CCR_IMODE_Pos (8U)
#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
#define QUADSPI_CCR_ADMODE_Pos (10U)
#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
#define QUADSPI_CCR_ADSIZE_Pos (12U)
#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
#define QUADSPI_CCR_ABMODE_Pos (14U)
#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
#define QUADSPI_CCR_ABSIZE_Pos (16U)
#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
#define QUADSPI_CCR_DCYC_Pos (18U)
#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
#define QUADSPI_CCR_DMODE_Pos (24U)
#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
#define QUADSPI_CCR_FMODE_Pos (26U)
#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
#define QUADSPI_CCR_SIOO_Pos (28U)
#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
#define QUADSPI_CCR_DHHC_Pos (30U)
#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold */
#define QUADSPI_CCR_DDRM_Pos (31U)
#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
/****************** Bit definition for QUADSPI_AR register *******************/
#define QUADSPI_AR_ADDRESS_Pos (0U)
#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
/****************** Bit definition for QUADSPI_ABR register ******************/
#define QUADSPI_ABR_ALTERNATE_Pos (0U)
#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
/****************** Bit definition for QUADSPI_DR register *******************/
#define QUADSPI_DR_DATA_Pos (0U)
#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
/****************** Bit definition for QUADSPI_PSMKR register ****************/
#define QUADSPI_PSMKR_MASK_Pos (0U)
#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
/****************** Bit definition for QUADSPI_PSMAR register ****************/
#define QUADSPI_PSMAR_MATCH_Pos (0U)
#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)/*!< 0xFFFFFFFF */
#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
/****************** Bit definition for QUADSPI_PIR register *****************/
#define QUADSPI_PIR_INTERVAL_Pos (0U)
#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
/****************** Bit definition for QUADSPI_LPTR register *****************/
#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/******************************************************************************/
/* */
/* Reset and Clock Control */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define RCC_HSI48_SUPPORT
#define RCC_PLLP_DIV_2_31_SUPPORT
/******************** Bit definition for RCC_CR register ********************/
#define RCC_CR_HSION_Pos (8U)
#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000100 */
#define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed oscillator (HSI16) clock enable */
#define RCC_CR_HSIKERON_Pos (9U)
#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000200 */
#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed oscillator (HSI16) clock enable for some IPs Kernel */
#define RCC_CR_HSIRDY_Pos (10U)
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed oscillator (HSI16) clock ready flag */
#define RCC_CR_HSEON_Pos (16U)
#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
#define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed oscillator (HSE) clock enable */
#define RCC_CR_HSERDY_Pos (17U)
#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed oscillator (HSE) clock ready */
#define RCC_CR_HSEBYP_Pos (18U)
#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed oscillator (HSE) clock bypass */
#define RCC_CR_CSSON_Pos (19U)
#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
#define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< HSE Clock Security System enable */
#define RCC_CR_PLLON_Pos (24U)
#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
#define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
#define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
/******************** Bit definition for RCC_ICSCR register ***************/
/*!< HSICAL configuration */
#define RCC_ICSCR_HSICAL_Pos (16U)
#define RCC_ICSCR_HSICAL_Msk (0xFFUL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00FF0000 */
#define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< HSICAL[7:0] bits */
#define RCC_ICSCR_HSICAL_0 (0x01UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00010000 */
#define RCC_ICSCR_HSICAL_1 (0x02UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00020000 */
#define RCC_ICSCR_HSICAL_2 (0x04UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00040000 */
#define RCC_ICSCR_HSICAL_3 (0x08UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00080000 */
#define RCC_ICSCR_HSICAL_4 (0x10UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00100000 */
#define RCC_ICSCR_HSICAL_5 (0x20UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00200000 */
#define RCC_ICSCR_HSICAL_6 (0x40UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00400000 */
#define RCC_ICSCR_HSICAL_7 (0x80UL << RCC_ICSCR_HSICAL_Pos) /*!< 0x00800000 */
/*!< HSITRIM configuration */
#define RCC_ICSCR_HSITRIM_Pos (24U)
#define RCC_ICSCR_HSITRIM_Msk (0x7FUL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x7F000000 */
#define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
#define RCC_ICSCR_HSITRIM_0 (0x01UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x01000000 */
#define RCC_ICSCR_HSITRIM_1 (0x02UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x02000000 */
#define RCC_ICSCR_HSITRIM_2 (0x04UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x04000000 */
#define RCC_ICSCR_HSITRIM_3 (0x08UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x08000000 */
#define RCC_ICSCR_HSITRIM_4 (0x10UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x10000000 */
#define RCC_ICSCR_HSITRIM_5 (0x20UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x20000000 */
#define RCC_ICSCR_HSITRIM_6 (0x40UL << RCC_ICSCR_HSITRIM_Pos) /*!< 0x40000000 */
/******************** Bit definition for RCC_CFGR register ******************/
/*!< SW configuration */
#define RCC_CFGR_SW_Pos (0U)
#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
#define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI16 oscillator selection as system clock */
#define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE oscillator selection as system clock */
#define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selection as system clock */
/*!< SWS configuration */
#define RCC_CFGR_SWS_Pos (2U)
#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
#define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI16 oscillator used as system clock */
#define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */
#define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */
/*!< HPRE configuration */
#define RCC_CFGR_HPRE_Pos (4U)
#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
#define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
#define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
#define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
#define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
#define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
#define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
#define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
#define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
/*!< PPRE1 configuration */
#define RCC_CFGR_PPRE1_Pos (8U)
#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
#define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */
/*!< PPRE2 configuration */
#define RCC_CFGR_PPRE2_Pos (11U)
#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
#define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */
#define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */
#define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */
#define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */
#define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */
/*!< MCOSEL configuration */
#define RCC_CFGR_MCOSEL_Pos (24U)
#define RCC_CFGR_MCOSEL_Msk (0xFUL << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */
#define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCOSEL [3:0] bits (Clock output selection) */
#define RCC_CFGR_MCOSEL_0 (0x1UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */
#define RCC_CFGR_MCOSEL_1 (0x2UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */
#define RCC_CFGR_MCOSEL_2 (0x4UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */
#define RCC_CFGR_MCOSEL_3 (0x8UL << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */
#define RCC_CFGR_MCOPRE_Pos (28U)
#define RCC_CFGR_MCOPRE_Msk (0x7UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
#define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
#define RCC_CFGR_MCOPRE_0 (0x1UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */
#define RCC_CFGR_MCOPRE_1 (0x2UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */
#define RCC_CFGR_MCOPRE_2 (0x4UL << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */
#define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
#define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
#define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
#define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
#define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
/* Legacy aliases */
#define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE
#define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1
#define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2
#define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4
#define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8
#define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16
/******************** Bit definition for RCC_PLLCFGR register ***************/
#define RCC_PLLCFGR_PLLSRC_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk
#define RCC_PLLCFGR_PLLSRC_0 (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000001 */
#define RCC_PLLCFGR_PLLSRC_1 (0x2UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI_Pos (1U)
#define RCC_PLLCFGR_PLLSRC_HSI_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSI_Pos)/*!< 0x00000002 */
#define RCC_PLLCFGR_PLLSRC_HSI RCC_PLLCFGR_PLLSRC_HSI_Msk /*!< HSI16 oscillator source clock selected */
#define RCC_PLLCFGR_PLLSRC_HSE_Pos (0U)
#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x3UL << RCC_PLLCFGR_PLLSRC_HSE_Pos)/*!< 0x00000003 */
#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk /*!< HSE oscillator source clock selected */
#define RCC_PLLCFGR_PLLM_Pos (4U)
#define RCC_PLLCFGR_PLLM_Msk (0xFUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x000000F0 */
#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk
#define RCC_PLLCFGR_PLLM_0 (0x1UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */
#define RCC_PLLCFGR_PLLM_1 (0x2UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */
#define RCC_PLLCFGR_PLLM_2 (0x4UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000040 */
#define RCC_PLLCFGR_PLLM_3 (0x8UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000080 */
#define RCC_PLLCFGR_PLLN_Pos (8U)
#define RCC_PLLCFGR_PLLN_Msk (0x7FUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007F00 */
#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk
#define RCC_PLLCFGR_PLLN_0 (0x01UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */
#define RCC_PLLCFGR_PLLN_1 (0x02UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */
#define RCC_PLLCFGR_PLLN_2 (0x04UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */
#define RCC_PLLCFGR_PLLN_3 (0x08UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */
#define RCC_PLLCFGR_PLLN_4 (0x10UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */
#define RCC_PLLCFGR_PLLN_5 (0x20UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */
#define RCC_PLLCFGR_PLLN_6 (0x40UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */
#define RCC_PLLCFGR_PLLPEN_Pos (16U)
#define RCC_PLLCFGR_PLLPEN_Msk (0x1UL << RCC_PLLCFGR_PLLPEN_Pos) /*!< 0x00010000 */
#define RCC_PLLCFGR_PLLPEN RCC_PLLCFGR_PLLPEN_Msk
#define RCC_PLLCFGR_PLLP_Pos (17U)
#define RCC_PLLCFGR_PLLP_Msk (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */
#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk
#define RCC_PLLCFGR_PLLQEN_Pos (20U)
#define RCC_PLLCFGR_PLLQEN_Msk (0x1UL << RCC_PLLCFGR_PLLQEN_Pos) /*!< 0x00100000 */
#define RCC_PLLCFGR_PLLQEN RCC_PLLCFGR_PLLQEN_Msk
#define RCC_PLLCFGR_PLLQ_Pos (21U)
#define RCC_PLLCFGR_PLLQ_Msk (0x3UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00600000 */
#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk
#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00200000 */
#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x00400000 */
#define RCC_PLLCFGR_PLLREN_Pos (24U)
#define RCC_PLLCFGR_PLLREN_Msk (0x1UL << RCC_PLLCFGR_PLLREN_Pos) /*!< 0x01000000 */
#define RCC_PLLCFGR_PLLREN RCC_PLLCFGR_PLLREN_Msk
#define RCC_PLLCFGR_PLLR_Pos (25U)
#define RCC_PLLCFGR_PLLR_Msk (0x3UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x06000000 */
#define RCC_PLLCFGR_PLLR RCC_PLLCFGR_PLLR_Msk
#define RCC_PLLCFGR_PLLR_0 (0x1UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x02000000 */
#define RCC_PLLCFGR_PLLR_1 (0x2UL << RCC_PLLCFGR_PLLR_Pos) /*!< 0x04000000 */
#define RCC_PLLCFGR_PLLPDIV_Pos (27U)
#define RCC_PLLCFGR_PLLPDIV_Msk (0x1FUL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0xF8000000 */
#define RCC_PLLCFGR_PLLPDIV RCC_PLLCFGR_PLLPDIV_Msk
#define RCC_PLLCFGR_PLLPDIV_0 (0x01UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x08000000 */
#define RCC_PLLCFGR_PLLPDIV_1 (0x02UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x10000000 */
#define RCC_PLLCFGR_PLLPDIV_2 (0x04UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x20000000 */
#define RCC_PLLCFGR_PLLPDIV_3 (0x08UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x40000000 */
#define RCC_PLLCFGR_PLLPDIV_4 (0x10UL << RCC_PLLCFGR_PLLPDIV_Pos)/*!< 0x80000000 */
/******************** Bit definition for RCC_CIER register ******************/
#define RCC_CIER_LSIRDYIE_Pos (0U)
#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
#define RCC_CIER_LSERDYIE_Pos (1U)
#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
#define RCC_CIER_HSIRDYIE_Pos (3U)
#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000008 */
#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
#define RCC_CIER_HSERDYIE_Pos (4U)
#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000010 */
#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
#define RCC_CIER_PLLRDYIE_Pos (5U)
#define RCC_CIER_PLLRDYIE_Msk (0x1UL << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000020 */
#define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk
#define RCC_CIER_LSECSSIE_Pos (9U)
#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
#define RCC_CIER_HSI48RDYIE_Pos (10U)
#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)/*!< 0x00000400 */
#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
/******************** Bit definition for RCC_CIFR register ******************/
#define RCC_CIFR_LSIRDYF_Pos (0U)
#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
#define RCC_CIFR_LSERDYF_Pos (1U)
#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
#define RCC_CIFR_HSIRDYF_Pos (3U)
#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000008 */
#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
#define RCC_CIFR_HSERDYF_Pos (4U)
#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000010 */
#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
#define RCC_CIFR_PLLRDYF_Pos (5U)
#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000020 */
#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
#define RCC_CIFR_CSSF_Pos (8U)
#define RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) /*!< 0x00000100 */
#define RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk
#define RCC_CIFR_LSECSSF_Pos (9U)
#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
#define RCC_CIFR_HSI48RDYF_Pos (10U)
#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000400 */
#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
/******************** Bit definition for RCC_CICR register ******************/
#define RCC_CICR_LSIRDYC_Pos (0U)
#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
#define RCC_CICR_LSERDYC_Pos (1U)
#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
#define RCC_CICR_HSIRDYC_Pos (3U)
#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000008 */
#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
#define RCC_CICR_HSERDYC_Pos (4U)
#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000010 */
#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
#define RCC_CICR_PLLRDYC_Pos (5U)
#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000020 */
#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
#define RCC_CICR_CSSC_Pos (8U)
#define RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) /*!< 0x00000100 */
#define RCC_CICR_CSSC RCC_CICR_CSSC_Msk
#define RCC_CICR_LSECSSC_Pos (9U)
#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
#define RCC_CICR_HSI48RDYC_Pos (10U)
#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000400 */
#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
/******************** Bit definition for RCC_AHB1RSTR register **************/
#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)/*!< 0x00000001 */
#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)/*!< 0x00000002 */
#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
#define RCC_AHB1RSTR_DMAMUX1RST_Pos (2U)
#define RCC_AHB1RSTR_DMAMUX1RST_Msk (0x1UL << RCC_AHB1RSTR_DMAMUX1RST_Pos)/*!< 0x00000004 */
#define RCC_AHB1RSTR_DMAMUX1RST RCC_AHB1RSTR_DMAMUX1RST_Msk
#define RCC_AHB1RSTR_CORDICRST_Pos (3U)
#define RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos)/*!< 0x00000008 */
#define RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk
#define RCC_AHB1RSTR_FMACRST_Pos (4U)
#define RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) /*!< 0x00000010 */
#define RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk
#define RCC_AHB1RSTR_FLASHRST_Pos (8U)
#define RCC_AHB1RSTR_FLASHRST_Msk (0x1UL << RCC_AHB1RSTR_FLASHRST_Pos)/*!< 0x00000100 */
#define RCC_AHB1RSTR_FLASHRST RCC_AHB1RSTR_FLASHRST_Msk
#define RCC_AHB1RSTR_CRCRST_Pos (12U)
#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)/*!< 0x00001000 */
#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
/******************** Bit definition for RCC_AHB2RSTR register **************/
#define RCC_AHB2RSTR_GPIOARST_Pos (0U)
#define RCC_AHB2RSTR_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR_GPIOARST_Pos)/*!< 0x00000001 */
#define RCC_AHB2RSTR_GPIOARST RCC_AHB2RSTR_GPIOARST_Msk
#define RCC_AHB2RSTR_GPIOBRST_Pos (1U)
#define RCC_AHB2RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOBRST_Pos)/*!< 0x00000002 */
#define RCC_AHB2RSTR_GPIOBRST RCC_AHB2RSTR_GPIOBRST_Msk
#define RCC_AHB2RSTR_GPIOCRST_Pos (2U)
#define RCC_AHB2RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOCRST_Pos)/*!< 0x00000004 */
#define RCC_AHB2RSTR_GPIOCRST RCC_AHB2RSTR_GPIOCRST_Msk
#define RCC_AHB2RSTR_GPIODRST_Pos (3U)
#define RCC_AHB2RSTR_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR_GPIODRST_Pos)/*!< 0x00000008 */
#define RCC_AHB2RSTR_GPIODRST RCC_AHB2RSTR_GPIODRST_Msk
#define RCC_AHB2RSTR_GPIOERST_Pos (4U)
#define RCC_AHB2RSTR_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR_GPIOERST_Pos)/*!< 0x00000010 */
#define RCC_AHB2RSTR_GPIOERST RCC_AHB2RSTR_GPIOERST_Msk
#define RCC_AHB2RSTR_GPIOFRST_Pos (5U)
#define RCC_AHB2RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOFRST_Pos)/*!< 0x00000020 */
#define RCC_AHB2RSTR_GPIOFRST RCC_AHB2RSTR_GPIOFRST_Msk
#define RCC_AHB2RSTR_GPIOGRST_Pos (6U)
#define RCC_AHB2RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR_GPIOGRST_Pos)/*!< 0x00000040 */
#define RCC_AHB2RSTR_GPIOGRST RCC_AHB2RSTR_GPIOGRST_Msk
#define RCC_AHB2RSTR_ADC12RST_Pos (13U)
#define RCC_AHB2RSTR_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR_ADC12RST_Pos)/*!< 0x00002000 */
#define RCC_AHB2RSTR_ADC12RST RCC_AHB2RSTR_ADC12RST_Msk
#define RCC_AHB2RSTR_ADC345RST_Pos (14U)
#define RCC_AHB2RSTR_ADC345RST_Msk (0x1UL << RCC_AHB2RSTR_ADC345RST_Pos)/*!< 0x00004000 */
#define RCC_AHB2RSTR_ADC345RST RCC_AHB2RSTR_ADC345RST_Msk
#define RCC_AHB2RSTR_DAC1RST_Pos (16U)
#define RCC_AHB2RSTR_DAC1RST_Msk (0x1UL << RCC_AHB2RSTR_DAC1RST_Pos)/*!< 0x00010000 */
#define RCC_AHB2RSTR_DAC1RST RCC_AHB2RSTR_DAC1RST_Msk
#define RCC_AHB2RSTR_DAC3RST_Pos (18U)
#define RCC_AHB2RSTR_DAC3RST_Msk (0x1UL << RCC_AHB2RSTR_DAC3RST_Pos)/*!< 0x00040000 */
#define RCC_AHB2RSTR_DAC3RST RCC_AHB2RSTR_DAC3RST_Msk
#define RCC_AHB2RSTR_AESRST_Pos (24U)
#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos)/*!< 0x01000000 */
#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk
#define RCC_AHB2RSTR_RNGRST_Pos (26U)
#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)/*!< 0x04000000 */
#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
/******************** Bit definition for RCC_AHB3RSTR register **************/
#define RCC_AHB3RSTR_QSPIRST_Pos (8U)
#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)/*!< 0x00000100 */
#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
/******************** Bit definition for RCC_APB1RSTR1 register **************/
#define RCC_APB1RSTR1_TIM2RST_Pos (0U)
#define RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk
#define RCC_APB1RSTR1_TIM3RST_Pos (1U)
#define RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos)/*!< 0x00000002 */
#define RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk
#define RCC_APB1RSTR1_TIM4RST_Pos (2U)
#define RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos)/*!< 0x00000004 */
#define RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk
#define RCC_APB1RSTR1_TIM6RST_Pos (4U)
#define RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos)/*!< 0x00000010 */
#define RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk
#define RCC_APB1RSTR1_TIM7RST_Pos (5U)
#define RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos)/*!< 0x00000020 */
#define RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk
#define RCC_APB1RSTR1_CRSRST_Pos (8U)
#define RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk
#define RCC_APB1RSTR1_SPI2RST_Pos (14U)
#define RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos)/*!< 0x00004000 */
#define RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk
#define RCC_APB1RSTR1_SPI3RST_Pos (15U)
#define RCC_APB1RSTR1_SPI3RST_Msk (0x1UL << RCC_APB1RSTR1_SPI3RST_Pos)/*!< 0x00008000 */
#define RCC_APB1RSTR1_SPI3RST RCC_APB1RSTR1_SPI3RST_Msk
#define RCC_APB1RSTR1_USART2RST_Pos (17U)
#define RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos)/*!< 0x00020000 */
#define RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk
#define RCC_APB1RSTR1_USART3RST_Pos (18U)
#define RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos)/*!< 0x00040000 */
#define RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk
#define RCC_APB1RSTR1_UART4RST_Pos (19U)
#define RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos)/*!< 0x00080000 */
#define RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk
#define RCC_APB1RSTR1_UART5RST_Pos (20U)
#define RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos)/*!< 0x00100000 */
#define RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk
#define RCC_APB1RSTR1_I2C1RST_Pos (21U)
#define RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos)/*!< 0x00200000 */
#define RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk
#define RCC_APB1RSTR1_I2C2RST_Pos (22U)
#define RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos)/*!< 0x00400000 */
#define RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk
#define RCC_APB1RSTR1_USBRST_Pos (23U)
#define RCC_APB1RSTR1_USBRST_Msk (0x1UL << RCC_APB1RSTR1_USBRST_Pos)/*!< 0x00800000 */
#define RCC_APB1RSTR1_USBRST RCC_APB1RSTR1_USBRST_Msk
#define RCC_APB1RSTR1_FDCANRST_Pos (25U)
#define RCC_APB1RSTR1_FDCANRST_Msk (0x1UL << RCC_APB1RSTR1_FDCANRST_Pos)/*!< 0x02000000 */
#define RCC_APB1RSTR1_FDCANRST RCC_APB1RSTR1_FDCANRST_Msk
#define RCC_APB1RSTR1_PWRRST_Pos (28U)
#define RCC_APB1RSTR1_PWRRST_Msk (0x1UL << RCC_APB1RSTR1_PWRRST_Pos)/*!< 0x10000000 */
#define RCC_APB1RSTR1_PWRRST RCC_APB1RSTR1_PWRRST_Msk
#define RCC_APB1RSTR1_I2C3RST_Pos (30U)
#define RCC_APB1RSTR1_I2C3RST_Msk (0x1UL << RCC_APB1RSTR1_I2C3RST_Pos)/*!< 0x40000000 */
#define RCC_APB1RSTR1_I2C3RST RCC_APB1RSTR1_I2C3RST_Msk
#define RCC_APB1RSTR1_LPTIM1RST_Pos (31U)
#define RCC_APB1RSTR1_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR1_LPTIM1RST_Pos)/*!< 0x80000000 */
#define RCC_APB1RSTR1_LPTIM1RST RCC_APB1RSTR1_LPTIM1RST_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1RSTR2_LPUART1RST_Pos (0U)
#define RCC_APB1RSTR2_LPUART1RST_Msk (0x1UL << RCC_APB1RSTR2_LPUART1RST_Pos)/*!< 0x00000001 */
#define RCC_APB1RSTR2_LPUART1RST RCC_APB1RSTR2_LPUART1RST_Msk
#define RCC_APB1RSTR2_UCPD1RST_Pos (8U)
#define RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos)/*!< 0x00000100 */
#define RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk
/******************** Bit definition for RCC_APB2RSTR register **************/
#define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos)/*!< 0x00000001 */
#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk
#define RCC_APB2RSTR_TIM1RST_Pos (11U)
#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)/*!< 0x00000800 */
#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
#define RCC_APB2RSTR_SPI1RST_Pos (12U)
#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)/*!< 0x00001000 */
#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
#define RCC_APB2RSTR_TIM8RST_Pos (13U)
#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)/*!< 0x00002000 */
#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
#define RCC_APB2RSTR_USART1RST_Pos (14U)
#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)/*!< 0x00004000 */
#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
#define RCC_APB2RSTR_TIM15RST_Pos (16U)
#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)/*!< 0x00010000 */
#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
#define RCC_APB2RSTR_TIM16RST_Pos (17U)
#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)/*!< 0x00020000 */
#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
#define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)/*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_TIM20RST_Pos (20U)
#define RCC_APB2RSTR_TIM20RST_Msk (0x1UL << RCC_APB2RSTR_TIM20RST_Pos)/*!< 0x00100000 */
#define RCC_APB2RSTR_TIM20RST RCC_APB2RSTR_TIM20RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)/*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
/******************** Bit definition for RCC_AHB1ENR register ***************/
#define RCC_AHB1ENR_DMA1EN_Pos (0U)
#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
#define RCC_AHB1ENR_DMA2EN_Pos (1U)
#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
#define RCC_AHB1ENR_DMAMUX1EN_Pos (2U)
#define RCC_AHB1ENR_DMAMUX1EN_Msk (0x1UL << RCC_AHB1ENR_DMAMUX1EN_Pos)/*!< 0x00000004 */
#define RCC_AHB1ENR_DMAMUX1EN RCC_AHB1ENR_DMAMUX1EN_Msk
#define RCC_AHB1ENR_CORDICEN_Pos (3U)
#define RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk
#define RCC_AHB1ENR_FMACEN_Pos (4U)
#define RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk
#define RCC_AHB1ENR_FLASHEN_Pos (8U)
#define RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk
#define RCC_AHB1ENR_CRCEN_Pos (12U)
#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */
#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
/******************** Bit definition for RCC_AHB2ENR register ***************/
#define RCC_AHB2ENR_GPIOAEN_Pos (0U)
#define RCC_AHB2ENR_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR_GPIOAEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2ENR_GPIOAEN RCC_AHB2ENR_GPIOAEN_Msk
#define RCC_AHB2ENR_GPIOBEN_Pos (1U)
#define RCC_AHB2ENR_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR_GPIOBEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2ENR_GPIOBEN RCC_AHB2ENR_GPIOBEN_Msk
#define RCC_AHB2ENR_GPIOCEN_Pos (2U)
#define RCC_AHB2ENR_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR_GPIOCEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2ENR_GPIOCEN RCC_AHB2ENR_GPIOCEN_Msk
#define RCC_AHB2ENR_GPIODEN_Pos (3U)
#define RCC_AHB2ENR_GPIODEN_Msk (0x1UL << RCC_AHB2ENR_GPIODEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2ENR_GPIODEN RCC_AHB2ENR_GPIODEN_Msk
#define RCC_AHB2ENR_GPIOEEN_Pos (4U)
#define RCC_AHB2ENR_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR_GPIOEEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2ENR_GPIOEEN RCC_AHB2ENR_GPIOEEN_Msk
#define RCC_AHB2ENR_GPIOFEN_Pos (5U)
#define RCC_AHB2ENR_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR_GPIOFEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2ENR_GPIOFEN RCC_AHB2ENR_GPIOFEN_Msk
#define RCC_AHB2ENR_GPIOGEN_Pos (6U)
#define RCC_AHB2ENR_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR_GPIOGEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2ENR_GPIOGEN RCC_AHB2ENR_GPIOGEN_Msk
#define RCC_AHB2ENR_ADC12EN_Pos (13U)
#define RCC_AHB2ENR_ADC12EN_Msk (0x1UL << RCC_AHB2ENR_ADC12EN_Pos) /*!< 0x00002000 */
#define RCC_AHB2ENR_ADC12EN RCC_AHB2ENR_ADC12EN_Msk
#define RCC_AHB2ENR_ADC345EN_Pos (14U)
#define RCC_AHB2ENR_ADC345EN_Msk (0x1UL << RCC_AHB2ENR_ADC345EN_Pos) /*!< 0x00004000 */
#define RCC_AHB2ENR_ADC345EN RCC_AHB2ENR_ADC345EN_Msk
#define RCC_AHB2ENR_DAC1EN_Pos (16U)
#define RCC_AHB2ENR_DAC1EN_Msk (0x1UL << RCC_AHB2ENR_DAC1EN_Pos) /*!< 0x00010000 */
#define RCC_AHB2ENR_DAC1EN RCC_AHB2ENR_DAC1EN_Msk
#define RCC_AHB2ENR_DAC3EN_Pos (18U)
#define RCC_AHB2ENR_DAC3EN_Msk (0x1UL << RCC_AHB2ENR_DAC3EN_Pos) /*!< 0x00040000 */
#define RCC_AHB2ENR_DAC3EN RCC_AHB2ENR_DAC3EN_Msk
#define RCC_AHB2ENR_AESEN_Pos (24U)
#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x01000000 */
#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk
#define RCC_AHB2ENR_RNGEN_Pos (26U)
#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x04000000 */
#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
/******************** Bit definition for RCC_AHB3ENR register ***************/
#define RCC_AHB3ENR_QSPIEN_Pos (8U)
#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000100 */
#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
/******************** Bit definition for RCC_APB1ENR1 register ***************/
#define RCC_APB1ENR1_TIM2EN_Pos (0U)
#define RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk
#define RCC_APB1ENR1_TIM3EN_Pos (1U)
#define RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos)/*!< 0x00000002 */
#define RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk
#define RCC_APB1ENR1_TIM4EN_Pos (2U)
#define RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos)/*!< 0x00000004 */
#define RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk
#define RCC_APB1ENR1_TIM6EN_Pos (4U)
#define RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos)/*!< 0x00000010 */
#define RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk
#define RCC_APB1ENR1_TIM7EN_Pos (5U)
#define RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos)/*!< 0x00000020 */
#define RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk
#define RCC_APB1ENR1_CRSEN_Pos (8U)
#define RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) /*!< 0x00000100 */
#define RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk
#define RCC_APB1ENR1_RTCAPBEN_Pos (10U)
#define RCC_APB1ENR1_RTCAPBEN_Msk (0x1UL << RCC_APB1ENR1_RTCAPBEN_Pos)/*!< 0x00000400 */
#define RCC_APB1ENR1_RTCAPBEN RCC_APB1ENR1_RTCAPBEN_Msk
#define RCC_APB1ENR1_WWDGEN_Pos (11U)
#define RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos)/*!< 0x00000800 */
#define RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk
#define RCC_APB1ENR1_SPI2EN_Pos (14U)
#define RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos)/*!< 0x00004000 */
#define RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk
#define RCC_APB1ENR1_SPI3EN_Pos (15U)
#define RCC_APB1ENR1_SPI3EN_Msk (0x1UL << RCC_APB1ENR1_SPI3EN_Pos)/*!< 0x00008000 */
#define RCC_APB1ENR1_SPI3EN RCC_APB1ENR1_SPI3EN_Msk
#define RCC_APB1ENR1_USART2EN_Pos (17U)
#define RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos)/*!< 0x00020000 */
#define RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk
#define RCC_APB1ENR1_USART3EN_Pos (18U)
#define RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos)/*!< 0x00040000 */
#define RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk
#define RCC_APB1ENR1_UART4EN_Pos (19U)
#define RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos)/*!< 0x00080000 */
#define RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk
#define RCC_APB1ENR1_UART5EN_Pos (20U)
#define RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos)/*!< 0x00100000 */
#define RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk
#define RCC_APB1ENR1_I2C1EN_Pos (21U)
#define RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos)/*!< 0x00200000 */
#define RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk
#define RCC_APB1ENR1_I2C2EN_Pos (22U)
#define RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos)/*!< 0x00400000 */
#define RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk
#define RCC_APB1ENR1_USBEN_Pos (23U)
#define RCC_APB1ENR1_USBEN_Msk (0x1UL << RCC_APB1ENR1_USBEN_Pos)/*!< 0x00800000 */
#define RCC_APB1ENR1_USBEN RCC_APB1ENR1_USBEN_Msk
#define RCC_APB1ENR1_FDCANEN_Pos (25U)
#define RCC_APB1ENR1_FDCANEN_Msk (0x1UL << RCC_APB1ENR1_FDCANEN_Pos)/*!< 0x02000000 */
#define RCC_APB1ENR1_FDCANEN RCC_APB1ENR1_FDCANEN_Msk
#define RCC_APB1ENR1_PWREN_Pos (28U)
#define RCC_APB1ENR1_PWREN_Msk (0x1UL << RCC_APB1ENR1_PWREN_Pos) /*!< 0x10000000 */
#define RCC_APB1ENR1_PWREN RCC_APB1ENR1_PWREN_Msk
#define RCC_APB1ENR1_I2C3EN_Pos (30U)
#define RCC_APB1ENR1_I2C3EN_Msk (0x1UL << RCC_APB1ENR1_I2C3EN_Pos)/*!< 0x40000000 */
#define RCC_APB1ENR1_I2C3EN RCC_APB1ENR1_I2C3EN_Msk
#define RCC_APB1ENR1_LPTIM1EN_Pos (31U)
#define RCC_APB1ENR1_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR1_LPTIM1EN_Pos)/*!< 0x80000000 */
#define RCC_APB1ENR1_LPTIM1EN RCC_APB1ENR1_LPTIM1EN_Msk
/******************** Bit definition for RCC_APB1RSTR2 register **************/
#define RCC_APB1ENR2_LPUART1EN_Pos (0U)
#define RCC_APB1ENR2_LPUART1EN_Msk (0x1UL << RCC_APB1ENR2_LPUART1EN_Pos)/*!< 0x00000001 */
#define RCC_APB1ENR2_LPUART1EN RCC_APB1ENR2_LPUART1EN_Msk
#define RCC_APB1ENR2_UCPD1EN_Pos (8U)
#define RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos)/*!< 0x00000100 */
#define RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk
/******************** Bit definition for RCC_APB2ENR register ***************/
#define RCC_APB2ENR_SYSCFGEN_Pos (0U)
#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos)/*!< 0x00000001 */
#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk
#define RCC_APB2ENR_TIM1EN_Pos (11U)
#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
#define RCC_APB2ENR_SPI1EN_Pos (12U)
#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
#define RCC_APB2ENR_TIM8EN_Pos (13U)
#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00002000 */
#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
#define RCC_APB2ENR_USART1EN_Pos (14U)
#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)/*!< 0x00004000 */
#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
#define RCC_APB2ENR_TIM15EN_Pos (16U)
#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)/*!< 0x00010000 */
#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
#define RCC_APB2ENR_TIM16EN_Pos (17U)
#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)/*!< 0x00020000 */
#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
#define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)/*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_TIM20EN_Pos (20U)
#define RCC_APB2ENR_TIM20EN_Msk (0x1UL << RCC_APB2ENR_TIM20EN_Pos)/*!< 0x00100000 */
#define RCC_APB2ENR_TIM20EN RCC_APB2ENR_TIM20EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)/*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ***************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB1SMENR_DMA1SMEN RCC_AHB1SMENR_DMA1SMEN_Msk
#define RCC_AHB1SMENR_DMA2SMEN_Pos (1U)
#define RCC_AHB1SMENR_DMA2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2SMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB1SMENR_DMA2SMEN RCC_AHB1SMENR_DMA2SMEN_Msk
#define RCC_AHB1SMENR_DMAMUX1SMEN_Pos (2U)
#define RCC_AHB1SMENR_DMAMUX1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMAMUX1SMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB1SMENR_DMAMUX1SMEN RCC_AHB1SMENR_DMAMUX1SMEN_Msk
#define RCC_AHB1SMENR_CORDICSMEN_Pos (3U)
#define RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk
#define RCC_AHB1SMENR_FMACSMEN_Pos (4U)
#define RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) /*!< 0x00000010 */
#define RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk
#define RCC_AHB1SMENR_FLASHSMEN_Pos (8U)
#define RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk
#define RCC_AHB1SMENR_SRAM1SMEN_Pos (9U)
#define RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos)/*!< 0x00000200 */
#define RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk
#define RCC_AHB1SMENR_CRCSMEN_Pos (12U)
#define RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos)/*!< 0x00001000 */
#define RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk
/******************** Bit definition for RCC_AHB2SMENR register *************/
#define RCC_AHB2SMENR_GPIOASMEN_Pos (0U)
#define RCC_AHB2SMENR_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOASMEN_Pos)/*!< 0x00000001 */
#define RCC_AHB2SMENR_GPIOASMEN RCC_AHB2SMENR_GPIOASMEN_Msk
#define RCC_AHB2SMENR_GPIOBSMEN_Pos (1U)
#define RCC_AHB2SMENR_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOBSMEN_Pos)/*!< 0x00000002 */
#define RCC_AHB2SMENR_GPIOBSMEN RCC_AHB2SMENR_GPIOBSMEN_Msk
#define RCC_AHB2SMENR_GPIOCSMEN_Pos (2U)
#define RCC_AHB2SMENR_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOCSMEN_Pos)/*!< 0x00000004 */
#define RCC_AHB2SMENR_GPIOCSMEN RCC_AHB2SMENR_GPIOCSMEN_Msk
#define RCC_AHB2SMENR_GPIODSMEN_Pos (3U)
#define RCC_AHB2SMENR_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIODSMEN_Pos)/*!< 0x00000008 */
#define RCC_AHB2SMENR_GPIODSMEN RCC_AHB2SMENR_GPIODSMEN_Msk
#define RCC_AHB2SMENR_GPIOESMEN_Pos (4U)
#define RCC_AHB2SMENR_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOESMEN_Pos)/*!< 0x00000010 */
#define RCC_AHB2SMENR_GPIOESMEN RCC_AHB2SMENR_GPIOESMEN_Msk
#define RCC_AHB2SMENR_GPIOFSMEN_Pos (5U)
#define RCC_AHB2SMENR_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOFSMEN_Pos)/*!< 0x00000020 */
#define RCC_AHB2SMENR_GPIOFSMEN RCC_AHB2SMENR_GPIOFSMEN_Msk
#define RCC_AHB2SMENR_GPIOGSMEN_Pos (6U)
#define RCC_AHB2SMENR_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR_GPIOGSMEN_Pos)/*!< 0x00000040 */
#define RCC_AHB2SMENR_GPIOGSMEN RCC_AHB2SMENR_GPIOGSMEN_Msk
#define RCC_AHB2SMENR_CCMSRAMSMEN_Pos (9U)
#define RCC_AHB2SMENR_CCMSRAMSMEN_Msk (0x1UL << RCC_AHB2SMENR_CCMSRAMSMEN_Pos) /*!< 0x00000200 */
#define RCC_AHB2SMENR_CCMSRAMSMEN RCC_AHB2SMENR_CCMSRAMSMEN_Msk
#define RCC_AHB2SMENR_SRAM2SMEN_Pos (10U)
#define RCC_AHB2SMENR_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR_SRAM2SMEN_Pos)/*!< 0x00000400 */
#define RCC_AHB2SMENR_SRAM2SMEN RCC_AHB2SMENR_SRAM2SMEN_Msk
#define RCC_AHB2SMENR_ADC12SMEN_Pos (13U)
#define RCC_AHB2SMENR_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC12SMEN_Pos)/*!< 0x00002000 */
#define RCC_AHB2SMENR_ADC12SMEN RCC_AHB2SMENR_ADC12SMEN_Msk
#define RCC_AHB2SMENR_ADC345SMEN_Pos (14U)
#define RCC_AHB2SMENR_ADC345SMEN_Msk (0x1UL << RCC_AHB2SMENR_ADC345SMEN_Pos)/*!< 0x00004000 */
#define RCC_AHB2SMENR_ADC345SMEN RCC_AHB2SMENR_ADC345SMEN_Msk
#define RCC_AHB2SMENR_DAC1SMEN_Pos (16U)
#define RCC_AHB2SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC1SMEN_Pos)/*!< 0x00010000 */
#define RCC_AHB2SMENR_DAC1SMEN RCC_AHB2SMENR_DAC1SMEN_Msk
#define RCC_AHB2SMENR_DAC3SMEN_Pos (18U)
#define RCC_AHB2SMENR_DAC3SMEN_Msk (0x1UL << RCC_AHB2SMENR_DAC3SMEN_Pos)/*!< 0x00040000 */
#define RCC_AHB2SMENR_DAC3SMEN RCC_AHB2SMENR_DAC3SMEN_Msk
#define RCC_AHB2SMENR_AESSMEN_Pos (24U)
#define RCC_AHB2SMENR_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR_AESSMEN_Pos)/*!< 0x01000000 */
#define RCC_AHB2SMENR_AESSMEN RCC_AHB2SMENR_AESSMEN_Msk
#define RCC_AHB2SMENR_RNGSMEN_Pos (26U)
#define RCC_AHB2SMENR_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR_RNGSMEN_Pos)/*!< 0x04000000 */
#define RCC_AHB2SMENR_RNGSMEN RCC_AHB2SMENR_RNGSMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register *************/
#define RCC_AHB3SMENR_QSPISMEN_Pos (8U)
#define RCC_AHB3SMENR_QSPISMEN_Msk (0x1UL << RCC_AHB3SMENR_QSPISMEN_Pos)/*!< 0x00000100 */
#define RCC_AHB3SMENR_QSPISMEN RCC_AHB3SMENR_QSPISMEN_Msk
/******************** Bit definition for RCC_APB1SMENR1 register *************/
#define RCC_APB1SMENR1_TIM2SMEN_Pos (0U)
#define RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk
#define RCC_APB1SMENR1_TIM3SMEN_Pos (1U)
#define RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos)/*!< 0x00000002 */
#define RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk
#define RCC_APB1SMENR1_TIM4SMEN_Pos (2U)
#define RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos)/*!< 0x00000004 */
#define RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk
#define RCC_APB1SMENR1_TIM6SMEN_Pos (4U)
#define RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos)/*!< 0x00000010 */
#define RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk
#define RCC_APB1SMENR1_TIM7SMEN_Pos (5U)
#define RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos)/*!< 0x00000020 */
#define RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk
#define RCC_APB1SMENR1_CRSSMEN_Pos (8U)
#define RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk
#define RCC_APB1SMENR1_RTCAPBSMEN_Pos (10U)
#define RCC_APB1SMENR1_RTCAPBSMEN_Msk (0x1UL << RCC_APB1SMENR1_RTCAPBSMEN_Pos)/*!< 0x00000400 */
#define RCC_APB1SMENR1_RTCAPBSMEN RCC_APB1SMENR1_RTCAPBSMEN_Msk
#define RCC_APB1SMENR1_WWDGSMEN_Pos (11U)
#define RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos)/*!< 0x00000800 */
#define RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk
#define RCC_APB1SMENR1_SPI2SMEN_Pos (14U)
#define RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk
#define RCC_APB1SMENR1_SPI3SMEN_Pos (15U)
#define RCC_APB1SMENR1_SPI3SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI3SMEN_Pos)/*!< 0x00008000 */
#define RCC_APB1SMENR1_SPI3SMEN RCC_APB1SMENR1_SPI3SMEN_Msk
#define RCC_APB1SMENR1_USART2SMEN_Pos (17U)
#define RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk
#define RCC_APB1SMENR1_USART3SMEN_Pos (18U)
#define RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk
#define RCC_APB1SMENR1_UART4SMEN_Pos (19U)
#define RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos)/*!< 0x00080000 */
#define RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk
#define RCC_APB1SMENR1_UART5SMEN_Pos (20U)
#define RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk
#define RCC_APB1SMENR1_I2C1SMEN_Pos (21U)
#define RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk
#define RCC_APB1SMENR1_I2C2SMEN_Pos (22U)
#define RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos)/*!< 0x00400000 */
#define RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk
#define RCC_APB1SMENR1_USBSMEN_Pos (23U)
#define RCC_APB1SMENR1_USBSMEN_Msk (0x1UL << RCC_APB1SMENR1_USBSMEN_Pos)/*!< 0x00800000 */
#define RCC_APB1SMENR1_USBSMEN RCC_APB1SMENR1_USBSMEN_Msk
#define RCC_APB1SMENR1_FDCANSMEN_Pos (25U)
#define RCC_APB1SMENR1_FDCANSMEN_Msk (0x1UL << RCC_APB1SMENR1_FDCANSMEN_Pos)/*!< 0x02000000 */
#define RCC_APB1SMENR1_FDCANSMEN RCC_APB1SMENR1_FDCANSMEN_Msk
#define RCC_APB1SMENR1_PWRSMEN_Pos (28U)
#define RCC_APB1SMENR1_PWRSMEN_Msk (0x1UL << RCC_APB1SMENR1_PWRSMEN_Pos)/*!< 0x10000000 */
#define RCC_APB1SMENR1_PWRSMEN RCC_APB1SMENR1_PWRSMEN_Msk
#define RCC_APB1SMENR1_I2C3SMEN_Pos (30U)
#define RCC_APB1SMENR1_I2C3SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C3SMEN_Pos)/*!< 0x40000000 */
#define RCC_APB1SMENR1_I2C3SMEN RCC_APB1SMENR1_I2C3SMEN_Msk
#define RCC_APB1SMENR1_LPTIM1SMEN_Pos (31U)
#define RCC_APB1SMENR1_LPTIM1SMEN_Msk (0x1UL << RCC_APB1SMENR1_LPTIM1SMEN_Pos)/*!< 0x80000000 */
#define RCC_APB1SMENR1_LPTIM1SMEN RCC_APB1SMENR1_LPTIM1SMEN_Msk
/******************** Bit definition for RCC_APB1SMENR2 register *************/
#define RCC_APB1SMENR2_LPUART1SMEN_Pos (0U)
#define RCC_APB1SMENR2_LPUART1SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPUART1SMEN_Pos)/*!< 0x00000001 */
#define RCC_APB1SMENR2_LPUART1SMEN RCC_APB1SMENR2_LPUART1SMEN_Msk
#define RCC_APB1SMENR2_UCPD1SMEN_Pos (8U)
#define RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos)/*!< 0x00000100 */
#define RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk
/******************** Bit definition for RCC_APB2SMENR register *************/
#define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U)
#define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB2SMENR_SYSCFGSMEN_Pos)/*!< 0x00000001 */
#define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk
#define RCC_APB2SMENR_TIM1SMEN_Pos (11U)
#define RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos)/*!< 0x00000800 */
#define RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk
#define RCC_APB2SMENR_SPI1SMEN_Pos (12U)
#define RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos)/*!< 0x00001000 */
#define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk
#define RCC_APB2SMENR_TIM8SMEN_Pos (13U)
#define RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos)/*!< 0x00002000 */
#define RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk
#define RCC_APB2SMENR_USART1SMEN_Pos (14U)
#define RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos)/*!< 0x00004000 */
#define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk
#define RCC_APB2SMENR_TIM15SMEN_Pos (16U)
#define RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos)/*!< 0x00010000 */
#define RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk
#define RCC_APB2SMENR_TIM16SMEN_Pos (17U)
#define RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos)/*!< 0x00020000 */
#define RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk
#define RCC_APB2SMENR_TIM17SMEN_Pos (18U)
#define RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos)/*!< 0x00040000 */
#define RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk
#define RCC_APB2SMENR_TIM20SMEN_Pos (20U)
#define RCC_APB2SMENR_TIM20SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM20SMEN_Pos)/*!< 0x00100000 */
#define RCC_APB2SMENR_TIM20SMEN RCC_APB2SMENR_TIM20SMEN_Msk
#define RCC_APB2SMENR_SAI1SMEN_Pos (21U)
#define RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos)/*!< 0x00200000 */
#define RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk
/******************** Bit definition for RCC_CCIPR register ******************/
#define RCC_CCIPR_USART1SEL_Pos (0U)
#define RCC_CCIPR_USART1SEL_Msk (0x3UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000003 */
#define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk
#define RCC_CCIPR_USART1SEL_0 (0x1UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000001 */
#define RCC_CCIPR_USART1SEL_1 (0x2UL << RCC_CCIPR_USART1SEL_Pos)/*!< 0x00000002 */
#define RCC_CCIPR_USART2SEL_Pos (2U)
#define RCC_CCIPR_USART2SEL_Msk (0x3UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x0000000C */
#define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk
#define RCC_CCIPR_USART2SEL_0 (0x1UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000004 */
#define RCC_CCIPR_USART2SEL_1 (0x2UL << RCC_CCIPR_USART2SEL_Pos)/*!< 0x00000008 */
#define RCC_CCIPR_USART3SEL_Pos (4U)
#define RCC_CCIPR_USART3SEL_Msk (0x3UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000030 */
#define RCC_CCIPR_USART3SEL RCC_CCIPR_USART3SEL_Msk
#define RCC_CCIPR_USART3SEL_0 (0x1UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000010 */
#define RCC_CCIPR_USART3SEL_1 (0x2UL << RCC_CCIPR_USART3SEL_Pos)/*!< 0x00000020 */
#define RCC_CCIPR_UART4SEL_Pos (6U)
#define RCC_CCIPR_UART4SEL_Msk (0x3UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x000000C0 */
#define RCC_CCIPR_UART4SEL RCC_CCIPR_UART4SEL_Msk
#define RCC_CCIPR_UART4SEL_0 (0x1UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000040 */
#define RCC_CCIPR_UART4SEL_1 (0x2UL << RCC_CCIPR_UART4SEL_Pos) /*!< 0x00000080 */
#define RCC_CCIPR_UART5SEL_Pos (8U)
#define RCC_CCIPR_UART5SEL_Msk (0x3UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000300 */
#define RCC_CCIPR_UART5SEL RCC_CCIPR_UART5SEL_Msk
#define RCC_CCIPR_UART5SEL_0 (0x1UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000100 */
#define RCC_CCIPR_UART5SEL_1 (0x2UL << RCC_CCIPR_UART5SEL_Pos) /*!< 0x00000200 */
#define RCC_CCIPR_LPUART1SEL_Pos (10U)
#define RCC_CCIPR_LPUART1SEL_Msk (0x3UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000C00 */
#define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk
#define RCC_CCIPR_LPUART1SEL_0 (0x1UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000400 */
#define RCC_CCIPR_LPUART1SEL_1 (0x2UL << RCC_CCIPR_LPUART1SEL_Pos)/*!< 0x00000800 */
#define RCC_CCIPR_I2C1SEL_Pos (12U)
#define RCC_CCIPR_I2C1SEL_Msk (0x3UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */
#define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk
#define RCC_CCIPR_I2C1SEL_0 (0x1UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */
#define RCC_CCIPR_I2C1SEL_1 (0x2UL << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */
#define RCC_CCIPR_I2C2SEL_Pos (14U)
#define RCC_CCIPR_I2C2SEL_Msk (0x3UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x0000C000 */
#define RCC_CCIPR_I2C2SEL RCC_CCIPR_I2C2SEL_Msk
#define RCC_CCIPR_I2C2SEL_0 (0x1UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00004000 */
#define RCC_CCIPR_I2C2SEL_1 (0x2UL << RCC_CCIPR_I2C2SEL_Pos) /*!< 0x00008000 */
#define RCC_CCIPR_I2C3SEL_Pos (16U)
#define RCC_CCIPR_I2C3SEL_Msk (0x3UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk
#define RCC_CCIPR_I2C3SEL_0 (0x1UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR_I2C3SEL_1 (0x2UL << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */
#define RCC_CCIPR_LPTIM1SEL_Pos (18U)
#define RCC_CCIPR_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x000C0000 */
#define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk
#define RCC_CCIPR_LPTIM1SEL_0 (0x1UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00040000 */
#define RCC_CCIPR_LPTIM1SEL_1 (0x2UL << RCC_CCIPR_LPTIM1SEL_Pos)/*!< 0x00080000 */
#define RCC_CCIPR_SAI1SEL_Pos (20U)
#define RCC_CCIPR_SAI1SEL_Msk (0x3UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00300000 */
#define RCC_CCIPR_SAI1SEL RCC_CCIPR_SAI1SEL_Msk
#define RCC_CCIPR_SAI1SEL_0 (0x1UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00100000 */
#define RCC_CCIPR_SAI1SEL_1 (0x2UL << RCC_CCIPR_SAI1SEL_Pos)/*!< 0x00200000 */
#define RCC_CCIPR_I2S23SEL_Pos (22U)
#define RCC_CCIPR_I2S23SEL_Msk (0x3UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00C00000 */
#define RCC_CCIPR_I2S23SEL RCC_CCIPR_I2S23SEL_Msk
#define RCC_CCIPR_I2S23SEL_0 (0x1UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00400000 */
#define RCC_CCIPR_I2S23SEL_1 (0x2UL << RCC_CCIPR_I2S23SEL_Pos)/*!< 0x00800000 */
#define RCC_CCIPR_FDCANSEL_Pos (24U)
#define RCC_CCIPR_FDCANSEL_Msk (0x3UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x03000000 */
#define RCC_CCIPR_FDCANSEL RCC_CCIPR_FDCANSEL_Msk
#define RCC_CCIPR_FDCANSEL_0 (0x1UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x01000000 */
#define RCC_CCIPR_FDCANSEL_1 (0x2UL << RCC_CCIPR_FDCANSEL_Pos) /*!< 0x02000000 */
#define RCC_CCIPR_CLK48SEL_Pos (26U)
#define RCC_CCIPR_CLK48SEL_Msk (0x3UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x0C000000 */
#define RCC_CCIPR_CLK48SEL RCC_CCIPR_CLK48SEL_Msk
#define RCC_CCIPR_CLK48SEL_0 (0x1UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x04000000 */
#define RCC_CCIPR_CLK48SEL_1 (0x2UL << RCC_CCIPR_CLK48SEL_Pos) /*!< 0x08000000 */
#define RCC_CCIPR_ADC12SEL_Pos (28U)
#define RCC_CCIPR_ADC12SEL_Msk (0x3UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x30000000 */
#define RCC_CCIPR_ADC12SEL RCC_CCIPR_ADC12SEL_Msk
#define RCC_CCIPR_ADC12SEL_0 (0x1UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x10000000 */
#define RCC_CCIPR_ADC12SEL_1 (0x2UL << RCC_CCIPR_ADC12SEL_Pos) /*!< 0x20000000 */
#define RCC_CCIPR_ADC345SEL_Pos (30U)
#define RCC_CCIPR_ADC345SEL_Msk (0x3UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
#define RCC_CCIPR_ADC345SEL RCC_CCIPR_ADC345SEL_Msk
#define RCC_CCIPR_ADC345SEL_0 (0x1UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x40000000 */
#define RCC_CCIPR_ADC345SEL_1 (0x2UL << RCC_CCIPR_ADC345SEL_Pos) /*!< 0x80000000 */
/******************** Bit definition for RCC_BDCR register ******************/
#define RCC_BDCR_LSEON_Pos (0U)
#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
#define RCC_BDCR_LSERDY_Pos (1U)
#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
#define RCC_BDCR_LSEBYP_Pos (2U)
#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
#define RCC_BDCR_LSEDRV_Pos (3U)
#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
#define RCC_BDCR_LSECSSON_Pos (5U)
#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
#define RCC_BDCR_LSECSSD_Pos (6U)
#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
#define RCC_BDCR_RTCSEL_Pos (8U)
#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
#define RCC_BDCR_RTCEN_Pos (15U)
#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
#define RCC_BDCR_BDRST_Pos (16U)
#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
#define RCC_BDCR_LSCOEN_Pos (24U)
#define RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) /*!< 0x01000000 */
#define RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk
#define RCC_BDCR_LSCOSEL_Pos (25U)
#define RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) /*!< 0x02000000 */
#define RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk
/******************** Bit definition for RCC_CSR register *******************/
#define RCC_CSR_LSION_Pos (0U)
#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
#define RCC_CSR_LSION RCC_CSR_LSION_Msk
#define RCC_CSR_LSIRDY_Pos (1U)
#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
#define RCC_CSR_RMVF_Pos (23U)
#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */
#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
#define RCC_CSR_OBLRSTF_Pos (25U)
#define RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
#define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk
#define RCC_CSR_PINRSTF_Pos (26U)
#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
#define RCC_CSR_BORRSTF_Pos (27U)
#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x08000000 */
#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk
#define RCC_CSR_SFTRSTF_Pos (28U)
#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
#define RCC_CSR_IWDGRSTF_Pos (29U)
#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
#define RCC_CSR_WWDGRSTF_Pos (30U)
#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
#define RCC_CSR_LPWRRSTF_Pos (31U)
#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
/******************** Bit definition for RCC_CRRCR register *****************/
#define RCC_CRRCR_HSI48ON_Pos (0U)
#define RCC_CRRCR_HSI48ON_Msk (0x1UL << RCC_CRRCR_HSI48ON_Pos) /*!< 0x00000001 */
#define RCC_CRRCR_HSI48ON RCC_CRRCR_HSI48ON_Msk
#define RCC_CRRCR_HSI48RDY_Pos (1U)
#define RCC_CRRCR_HSI48RDY_Msk (0x1UL << RCC_CRRCR_HSI48RDY_Pos) /*!< 0x00000002 */
#define RCC_CRRCR_HSI48RDY RCC_CRRCR_HSI48RDY_Msk
/*!< HSI48CAL configuration */
#define RCC_CRRCR_HSI48CAL_Pos (7U)
#define RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x0000FF80 */
#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[8:0] bits */
#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000080 */
#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000100 */
#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000200 */
#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000400 */
#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00000800 */
#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00001000 */
#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00002000 */
#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00004000 */
#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)/*!< 0x00008000 */
/******************** Bit definition for RCC_CCIPR2 register ******************/
#define RCC_CCIPR2_QSPISEL_Pos (20U)
#define RCC_CCIPR2_QSPISEL_Msk (0x3UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00030000 */
#define RCC_CCIPR2_QSPISEL RCC_CCIPR2_QSPISEL_Msk
#define RCC_CCIPR2_QSPISEL_0 (0x1UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00010000 */
#define RCC_CCIPR2_QSPISEL_1 (0x2UL << RCC_CCIPR2_QSPISEL_Pos) /*!< 0x00020000 */
/******************************************************************************/
/* */
/* RNG */
/* */
/******************************************************************************/
/******************** Bits definition for RNG_CR register *******************/
#define RNG_CR_RNGEN_Pos (2U)
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
#define RNG_CR_IE_Pos (3U)
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
#define RNG_CR_IE RNG_CR_IE_Msk
#define RNG_CR_CED_Pos (5U)
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000020 */
#define RNG_CR_CED RNG_CR_IE_Msk
/******************** Bits definition for RNG_SR register *******************/
#define RNG_SR_DRDY_Pos (0U)
#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
#define RNG_SR_DRDY RNG_SR_DRDY_Msk
#define RNG_SR_CECS_Pos (1U)
#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
#define RNG_SR_CECS RNG_SR_CECS_Msk
#define RNG_SR_SECS_Pos (2U)
#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
#define RNG_SR_SECS RNG_SR_SECS_Msk
#define RNG_SR_CEIS_Pos (5U)
#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
#define RNG_SR_CEIS RNG_SR_CEIS_Msk
#define RNG_SR_SEIS_Pos (6U)
#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
#define RNG_SR_SEIS RNG_SR_SEIS_Msk
/******************************************************************************/
/* */
/* Real-Time Clock (RTC) */
/* */
/******************************************************************************/
/******************** Bits definition for RTC_TR register *******************/
#define RTC_TR_PM_Pos (22U)
#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
#define RTC_TR_PM RTC_TR_PM_Msk
#define RTC_TR_HT_Pos (20U)
#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
#define RTC_TR_HT RTC_TR_HT_Msk
#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
#define RTC_TR_HU_Pos (16U)
#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TR_HU RTC_TR_HU_Msk
#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
#define RTC_TR_MNT_Pos (12U)
#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TR_MNT RTC_TR_MNT_Msk
#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TR_MNU_Pos (8U)
#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TR_MNU RTC_TR_MNU_Msk
#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TR_ST_Pos (4U)
#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
#define RTC_TR_ST RTC_TR_ST_Msk
#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
#define RTC_TR_SU_Pos (0U)
#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
#define RTC_TR_SU RTC_TR_SU_Msk
#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_DR register *******************/
#define RTC_DR_YT_Pos (20U)
#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
#define RTC_DR_YT RTC_DR_YT_Msk
#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
#define RTC_DR_YU_Pos (16U)
#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
#define RTC_DR_YU RTC_DR_YU_Msk
#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
#define RTC_DR_WDU_Pos (13U)
#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_DR_WDU RTC_DR_WDU_Msk
#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
#define RTC_DR_MT_Pos (12U)
#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
#define RTC_DR_MT RTC_DR_MT_Msk
#define RTC_DR_MU_Pos (8U)
#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
#define RTC_DR_MU RTC_DR_MU_Msk
#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
#define RTC_DR_DT_Pos (4U)
#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
#define RTC_DR_DT RTC_DR_DT_Msk
#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
#define RTC_DR_DU_Pos (0U)
#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
#define RTC_DR_DU RTC_DR_DU_Msk
#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_SSR register ******************/
#define RTC_SSR_SS_Pos (0U)
#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_SSR_SS RTC_SSR_SS_Msk
/******************** Bits definition for RTC_ICSR register ******************/
#define RTC_ICSR_RECALPF_Pos (16U)
#define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
#define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
#define RTC_ICSR_INIT_Pos (7U)
#define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
#define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
#define RTC_ICSR_INITF_Pos (6U)
#define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
#define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
#define RTC_ICSR_RSF_Pos (5U)
#define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
#define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
#define RTC_ICSR_INITS_Pos (4U)
#define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
#define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
#define RTC_ICSR_SHPF_Pos (3U)
#define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
#define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
#define RTC_ICSR_WUTWF_Pos (2U)
#define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
#define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
#define RTC_ICSR_ALRBWF_Pos (1U)
#define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
#define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
#define RTC_ICSR_ALRAWF_Pos (0U)
#define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
#define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
/******************** Bits definition for RTC_PRER register *****************/
#define RTC_PRER_PREDIV_A_Pos (16U)
#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
#define RTC_PRER_PREDIV_S_Pos (0U)
#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
/******************** Bits definition for RTC_WUTR register *****************/
#define RTC_WUTR_WUT_Pos (0U)
#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
/******************** Bits definition for RTC_CR register *******************/
#define RTC_CR_OUT2EN_Pos (31U)
#define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
#define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
#define RTC_CR_TAMPALRM_TYPE_Pos (30U)
#define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
#define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
#define RTC_CR_TAMPALRM_PU_Pos (29U)
#define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
#define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
#define RTC_CR_TAMPOE_Pos (26U)
#define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
#define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
#define RTC_CR_TAMPTS_Pos (25U)
#define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
#define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
#define RTC_CR_ITSE_Pos (24U)
#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
#define RTC_CR_ITSE RTC_CR_ITSE_Msk /*!<Timestamp on internal event enable */
#define RTC_CR_COE_Pos (23U)
#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
#define RTC_CR_COE RTC_CR_COE_Msk
#define RTC_CR_OSEL_Pos (21U)
#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
#define RTC_CR_OSEL RTC_CR_OSEL_Msk
#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
#define RTC_CR_POL_Pos (20U)
#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
#define RTC_CR_POL RTC_CR_POL_Msk
#define RTC_CR_COSEL_Pos (19U)
#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
#define RTC_CR_COSEL RTC_CR_COSEL_Msk
#define RTC_CR_BKP_Pos (18U)
#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
#define RTC_CR_BKP RTC_CR_BKP_Msk
#define RTC_CR_SUB1H_Pos (17U)
#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
#define RTC_CR_ADD1H_Pos (16U)
#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
#define RTC_CR_TSIE_Pos (15U)
#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
#define RTC_CR_TSIE RTC_CR_TSIE_Msk
#define RTC_CR_WUTIE_Pos (14U)
#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
#define RTC_CR_ALRBIE_Pos (13U)
#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
#define RTC_CR_ALRAIE_Pos (12U)
#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
#define RTC_CR_TSE_Pos (11U)
#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
#define RTC_CR_TSE RTC_CR_TSE_Msk
#define RTC_CR_WUTE_Pos (10U)
#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
#define RTC_CR_WUTE RTC_CR_WUTE_Msk
#define RTC_CR_ALRBE_Pos (9U)
#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
#define RTC_CR_ALRAE_Pos (8U)
#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
#define RTC_CR_FMT_Pos (6U)
#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
#define RTC_CR_FMT RTC_CR_FMT_Msk
#define RTC_CR_BYPSHAD_Pos (5U)
#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
#define RTC_CR_REFCKON_Pos (4U)
#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
#define RTC_CR_TSEDGE_Pos (3U)
#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
#define RTC_CR_WUCKSEL_Pos (0U)
#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
/******************** Bits definition for RTC_WPR register ******************/
#define RTC_WPR_KEY_Pos (0U)
#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
#define RTC_WPR_KEY RTC_WPR_KEY_Msk
/******************** Bits definition for RTC_CALR register *****************/
#define RTC_CALR_CALP_Pos (15U)
#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
#define RTC_CALR_CALP RTC_CALR_CALP_Msk
#define RTC_CALR_CALW8_Pos (14U)
#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
#define RTC_CALR_CALW16_Pos (13U)
#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
#define RTC_CALR_CALM_Pos (0U)
#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
#define RTC_CALR_CALM RTC_CALR_CALM_Msk
#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
/******************** Bits definition for RTC_SHIFTR register ***************/
#define RTC_SHIFTR_SUBFS_Pos (0U)
#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
#define RTC_SHIFTR_ADD1S_Pos (31U)
#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
/******************** Bits definition for RTC_TSTR register *****************/
#define RTC_TSTR_PM_Pos (22U)
#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
#define RTC_TSTR_PM RTC_TSTR_PM_Msk
#define RTC_TSTR_HT_Pos (20U)
#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
#define RTC_TSTR_HT RTC_TSTR_HT_Msk
#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
#define RTC_TSTR_HU_Pos (16U)
#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
#define RTC_TSTR_HU RTC_TSTR_HU_Msk
#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
#define RTC_TSTR_MNT_Pos (12U)
#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
#define RTC_TSTR_MNU_Pos (8U)
#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
#define RTC_TSTR_ST_Pos (4U)
#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
#define RTC_TSTR_ST RTC_TSTR_ST_Msk
#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
#define RTC_TSTR_SU_Pos (0U)
#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
#define RTC_TSTR_SU RTC_TSTR_SU_Msk
#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSDR register *****************/
#define RTC_TSDR_WDU_Pos (13U)
#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
#define RTC_TSDR_MT_Pos (12U)
#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
#define RTC_TSDR_MT RTC_TSDR_MT_Msk
#define RTC_TSDR_MU_Pos (8U)
#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
#define RTC_TSDR_MU RTC_TSDR_MU_Msk
#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
#define RTC_TSDR_DT_Pos (4U)
#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
#define RTC_TSDR_DT RTC_TSDR_DT_Msk
#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
#define RTC_TSDR_DU_Pos (0U)
#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
#define RTC_TSDR_DU RTC_TSDR_DU_Msk
#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_TSSSR register ****************/
#define RTC_TSSSR_SS_Pos (0U)
#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
/******************** Bits definition for RTC_ALRMAR register ***************/
#define RTC_ALRMAR_MSK4_Pos (31U)
#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
#define RTC_ALRMAR_WDSEL_Pos (30U)
#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
#define RTC_ALRMAR_DT_Pos (28U)
#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMAR_DU_Pos (24U)
#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMAR_MSK3_Pos (23U)
#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
#define RTC_ALRMAR_PM_Pos (22U)
#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
#define RTC_ALRMAR_HT_Pos (20U)
#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMAR_HU_Pos (16U)
#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMAR_MSK2_Pos (15U)
#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
#define RTC_ALRMAR_MNT_Pos (12U)
#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMAR_MNU_Pos (8U)
#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMAR_MSK1_Pos (7U)
#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
#define RTC_ALRMAR_ST_Pos (4U)
#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMAR_SU_Pos (0U)
#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMASSR_MASKSS_Pos (24U)
#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMASSR_SS_Pos (0U)
#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
/******************** Bits definition for RTC_ALRMBR register ***************/
#define RTC_ALRMBR_MSK4_Pos (31U)
#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
#define RTC_ALRMBR_WDSEL_Pos (30U)
#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
#define RTC_ALRMBR_DT_Pos (28U)
#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
#define RTC_ALRMBR_DU_Pos (24U)
#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
#define RTC_ALRMBR_MSK3_Pos (23U)
#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
#define RTC_ALRMBR_PM_Pos (22U)
#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
#define RTC_ALRMBR_HT_Pos (20U)
#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
#define RTC_ALRMBR_HU_Pos (16U)
#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
#define RTC_ALRMBR_MSK2_Pos (15U)
#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
#define RTC_ALRMBR_MNT_Pos (12U)
#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
#define RTC_ALRMBR_MNU_Pos (8U)
#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
#define RTC_ALRMBR_MSK1_Pos (7U)
#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
#define RTC_ALRMBR_ST_Pos (4U)
#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
#define RTC_ALRMBR_SU_Pos (0U)
#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
/******************** Bits definition for RTC_ALRMASSR register *************/
#define RTC_ALRMBSSR_MASKSS_Pos (24U)
#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
#define RTC_ALRMBSSR_SS_Pos (0U)
#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
/******************** Bits definition for RTC_SR register *******************/
#define RTC_SR_ITSF_Pos (5U)
#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
#define RTC_SR_ITSF RTC_SR_ITSF_Msk
#define RTC_SR_TSOVF_Pos (4U)
#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
#define RTC_SR_TSF_Pos (3U)
#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
#define RTC_SR_TSF RTC_SR_TSF_Msk
#define RTC_SR_WUTF_Pos (2U)
#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
#define RTC_SR_WUTF RTC_SR_WUTF_Msk
#define RTC_SR_ALRBF_Pos (1U)
#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
#define RTC_SR_ALRAF_Pos (0U)
#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
/******************** Bits definition for RTC_MISR register *****************/
#define RTC_MISR_ITSMF_Pos (5U)
#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
#define RTC_MISR_TSOVMF_Pos (4U)
#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
#define RTC_MISR_TSMF_Pos (3U)
#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
#define RTC_MISR_WUTMF_Pos (2U)
#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
#define RTC_MISR_ALRBMF_Pos (1U)
#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
#define RTC_MISR_ALRAMF_Pos (0U)
#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
/******************** Bits definition for RTC_SCR register ******************/
#define RTC_SCR_CITSF_Pos (5U)
#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
#define RTC_SCR_CTSOVF_Pos (4U)
#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
#define RTC_SCR_CTSF_Pos (3U)
#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
#define RTC_SCR_CWUTF_Pos (2U)
#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
#define RTC_SCR_CALRBF_Pos (1U)
#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
#define RTC_SCR_CALRAF_Pos (0U)
#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
/******************************************************************************/
/* */
/* Tamper and backup register (TAMP) */
/* */
/******************************************************************************/
/******************** Bits definition for TAMP_CR1 register *****************/
#define TAMP_CR1_TAMP1E_Pos (0U)
#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
#define TAMP_CR1_TAMP2E_Pos (1U)
#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
#define TAMP_CR1_TAMP3E_Pos (2U)
#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
#define TAMP_CR1_ITAMP3E_Pos (18U)
#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
#define TAMP_CR1_ITAMP4E_Pos (19U)
#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
#define TAMP_CR1_ITAMP5E_Pos (20U)
#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
#define TAMP_CR1_ITAMP6E_Pos (21U)
#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
/******************** Bits definition for TAMP_CR2 register *****************/
#define TAMP_CR2_TAMP1NOERASE_Pos (0U)
#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
#define TAMP_CR2_TAMP2NOERASE_Pos (1U)
#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
#define TAMP_CR2_TAMP3NOERASE_Pos (2U)
#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
#define TAMP_CR2_TAMP1MF_Pos (16U)
#define TAMP_CR2_TAMP1MF_Msk (0x1UL << TAMP_CR2_TAMP1MF_Pos) /*!< 0x00010000 */
#define TAMP_CR2_TAMP1MF TAMP_CR2_TAMP1MF_Msk
#define TAMP_CR2_TAMP2MF_Pos (17U)
#define TAMP_CR2_TAMP2MF_Msk (0x1UL << TAMP_CR2_TAMP2MF_Pos) /*!< 0x00020000 */
#define TAMP_CR2_TAMP2MF TAMP_CR2_TAMP2MF_Msk
#define TAMP_CR2_TAMP3MF_Pos (18U)
#define TAMP_CR2_TAMP3MF_Msk (0x1UL << TAMP_CR2_TAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_CR2_TAMP3MF TAMP_CR2_TAMP3MF_Msk
#define TAMP_CR2_TAMP1TRG_Pos (24U)
#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
#define TAMP_CR2_TAMP2TRG_Pos (25U)
#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
#define TAMP_CR2_TAMP3TRG_Pos (26U)
#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
/******************** Bits definition for TAMP_FLTCR register ***************/
#define TAMP_FLTCR_TAMPFREQ_0 (0x00000001UL)
#define TAMP_FLTCR_TAMPFREQ_1 (0x00000002UL)
#define TAMP_FLTCR_TAMPFREQ_2 (0x00000004UL)
#define TAMP_FLTCR_TAMPFREQ_Pos (0U)
#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
#define TAMP_FLTCR_TAMPFLT_0 (0x00000008UL)
#define TAMP_FLTCR_TAMPFLT_1 (0x00000010UL)
#define TAMP_FLTCR_TAMPFLT_Pos (3U)
#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
#define TAMP_FLTCR_TAMPPRCH_0 (0x00000020UL)
#define TAMP_FLTCR_TAMPPRCH_1 (0x00000040UL)
#define TAMP_FLTCR_TAMPPRCH_Pos (5U)
#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
#define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
/******************** Bits definition for TAMP_IER register *****************/
#define TAMP_IER_TAMP1IE_Pos (0U)
#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
#define TAMP_IER_TAMP2IE_Pos (1U)
#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
#define TAMP_IER_TAMP3IE_Pos (2U)
#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
#define TAMP_IER_ITAMP3IE_Pos (18U)
#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
#define TAMP_IER_ITAMP4IE_Pos (19U)
#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
#define TAMP_IER_ITAMP5IE_Pos (20U)
#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
#define TAMP_IER_ITAMP6IE_Pos (21U)
#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
/******************** Bits definition for TAMP_SR register ******************/
#define TAMP_SR_TAMP1F_Pos (0U)
#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
#define TAMP_SR_TAMP2F_Pos (1U)
#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
#define TAMP_SR_TAMP3F_Pos (2U)
#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
#define TAMP_SR_ITAMP3F_Pos (18U)
#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
#define TAMP_SR_ITAMP4F_Pos (19U)
#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
#define TAMP_SR_ITAMP5F_Pos (20U)
#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
#define TAMP_SR_ITAMP6F_Pos (21U)
#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
/******************** Bits definition for TAMP_MISR register ****************/
#define TAMP_MISR_TAMP1MF_Pos (0U)
#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
#define TAMP_MISR_TAMP2MF_Pos (1U)
#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
#define TAMP_MISR_TAMP3MF_Pos (2U)
#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
#define TAMP_MISR_ITAMP3MF_Pos (18U)
#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
#define TAMP_MISR_ITAMP4MF_Pos (19U)
#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
#define TAMP_MISR_ITAMP5MF_Pos (20U)
#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
#define TAMP_MISR_ITAMP6MF_Pos (21U)
#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
/******************** Bits definition for TAMP_SCR register *****************/
#define TAMP_SCR_CTAMP1F_Pos (0U)
#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
#define TAMP_SCR_CTAMP2F_Pos (1U)
#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
#define TAMP_SCR_CTAMP3F_Pos (2U)
#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
#define TAMP_SCR_CITAMP3F_Pos (18U)
#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
#define TAMP_SCR_CITAMP4F_Pos (19U)
#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
#define TAMP_SCR_CITAMP5F_Pos (20U)
#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
#define TAMP_SCR_CITAMP6F_Pos (21U)
#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
/******************** Bits definition for TAMP_BKP0R register ***************/
#define TAMP_BKP0R_Pos (0U)
#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP0R TAMP_BKP0R_Msk
/******************** Bits definition for TAMP_BKP1R register ***************/
#define TAMP_BKP1R_Pos (0U)
#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP1R TAMP_BKP1R_Msk
/******************** Bits definition for TAMP_BKP2R register ***************/
#define TAMP_BKP2R_Pos (0U)
#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP2R TAMP_BKP2R_Msk
/******************** Bits definition for TAMP_BKP3R register ***************/
#define TAMP_BKP3R_Pos (0U)
#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP3R TAMP_BKP3R_Msk
/******************** Bits definition for TAMP_BKP4R register ***************/
#define TAMP_BKP4R_Pos (0U)
#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP4R TAMP_BKP4R_Msk
/******************** Bits definition for TAMP_BKP5R register ***************/
#define TAMP_BKP5R_Pos (0U)
#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP5R TAMP_BKP5R_Msk
/******************** Bits definition for TAMP_BKP6R register ***************/
#define TAMP_BKP6R_Pos (0U)
#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP6R TAMP_BKP6R_Msk
/******************** Bits definition for TAMP_BKP7R register ***************/
#define TAMP_BKP7R_Pos (0U)
#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP7R TAMP_BKP7R_Msk
/******************** Bits definition for TAMP_BKP8R register ***************/
#define TAMP_BKP8R_Pos (0U)
#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP8R TAMP_BKP8R_Msk
/******************** Bits definition for TAMP_BKP9R register ***************/
#define TAMP_BKP9R_Pos (0U)
#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP9R TAMP_BKP9R_Msk
/******************** Bits definition for TAMP_BKP10R register ***************/
#define TAMP_BKP10R_Pos (0U)
#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP10R TAMP_BKP10R_Msk
/******************** Bits definition for TAMP_BKP11R register ***************/
#define TAMP_BKP11R_Pos (0U)
#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP11R TAMP_BKP11R_Msk
/******************** Bits definition for TAMP_BKP12R register ***************/
#define TAMP_BKP12R_Pos (0U)
#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP12R TAMP_BKP12R_Msk
/******************** Bits definition for TAMP_BKP13R register ***************/
#define TAMP_BKP13R_Pos (0U)
#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP13R TAMP_BKP13R_Msk
/******************** Bits definition for TAMP_BKP14R register ***************/
#define TAMP_BKP14R_Pos (0U)
#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP14R TAMP_BKP14R_Msk
/******************** Bits definition for TAMP_BKP15R register ***************/
#define TAMP_BKP15R_Pos (0U)
#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP15R TAMP_BKP15R_Msk
/******************** Bits definition for TAMP_BKP16R register ***************/
#define TAMP_BKP16R_Pos (0U)
#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP16R TAMP_BKP16R_Msk
/******************** Bits definition for TAMP_BKP17R register ***************/
#define TAMP_BKP17R_Pos (0U)
#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP17R TAMP_BKP17R_Msk
/******************** Bits definition for TAMP_BKP18R register ***************/
#define TAMP_BKP18R_Pos (0U)
#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP18R TAMP_BKP18R_Msk
/******************** Bits definition for TAMP_BKP19R register ***************/
#define TAMP_BKP19R_Pos (0U)
#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP19R TAMP_BKP19R_Msk
/******************** Bits definition for TAMP_BKP20R register ***************/
#define TAMP_BKP20R_Pos (0U)
#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP20R TAMP_BKP20R_Msk
/******************** Bits definition for TAMP_BKP21R register ***************/
#define TAMP_BKP21R_Pos (0U)
#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP21R TAMP_BKP21R_Msk
/******************** Bits definition for TAMP_BKP22R register ***************/
#define TAMP_BKP22R_Pos (0U)
#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP22R TAMP_BKP22R_Msk
/******************** Bits definition for TAMP_BKP23R register ***************/
#define TAMP_BKP23R_Pos (0U)
#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP23R TAMP_BKP23R_Msk
/******************** Bits definition for TAMP_BKP24R register ***************/
#define TAMP_BKP24R_Pos (0U)
#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP24R TAMP_BKP24R_Msk
/******************** Bits definition for TAMP_BKP25R register ***************/
#define TAMP_BKP25R_Pos (0U)
#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP25R TAMP_BKP25R_Msk
/******************** Bits definition for TAMP_BKP26R register ***************/
#define TAMP_BKP26R_Pos (0U)
#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP26R TAMP_BKP26R_Msk
/******************** Bits definition for TAMP_BKP27R register ***************/
#define TAMP_BKP27R_Pos (0U)
#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP27R TAMP_BKP27R_Msk
/******************** Bits definition for TAMP_BKP28R register ***************/
#define TAMP_BKP28R_Pos (0U)
#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP28R TAMP_BKP28R_Msk
/******************** Bits definition for TAMP_BKP29R register ***************/
#define TAMP_BKP29R_Pos (0U)
#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP29R TAMP_BKP29R_Msk
/******************** Bits definition for TAMP_BKP30R register ***************/
#define TAMP_BKP30R_Pos (0U)
#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP30R TAMP_BKP30R_Msk
/******************** Bits definition for TAMP_BKP31R register ***************/
#define TAMP_BKP31R_Pos (0U)
#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
#define TAMP_BKP31R TAMP_BKP31R_Msk
/******************************************************************************/
/* */
/* Serial Audio Interface */
/* */
/******************************************************************************/
/******************** Bit definition for SAI_GCR register *******************/
#define SAI_GCR_SYNCIN_Pos (0U)
#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
#define SAI_GCR_SYNCOUT_Pos (4U)
#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
/******************* Bit definition for SAI_xCR1 register *******************/
#define SAI_xCR1_MODE_Pos (0U)
#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
#define SAI_xCR1_PRTCFG_Pos (2U)
#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
#define SAI_xCR1_DS_Pos (5U)
#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
#define SAI_xCR1_LSBFIRST_Pos (8U)
#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
#define SAI_xCR1_CKSTR_Pos (9U)
#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
#define SAI_xCR1_SYNCEN_Pos (10U)
#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
#define SAI_xCR1_MONO_Pos (12U)
#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
#define SAI_xCR1_OUTDRIV_Pos (13U)
#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
#define SAI_xCR1_SAIEN_Pos (16U)
#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
#define SAI_xCR1_DMAEN_Pos (17U)
#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
#define SAI_xCR1_NODIV_Pos (19U)
#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
#define SAI_xCR1_MCKDIV_Pos (20U)
#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
#define SAI_xCR1_MCKDIV_0 (0x00100000U) /*!<Bit 0 */
#define SAI_xCR1_MCKDIV_1 (0x00200000U) /*!<Bit 1 */
#define SAI_xCR1_MCKDIV_2 (0x00400000U) /*!<Bit 2 */
#define SAI_xCR1_MCKDIV_3 (0x00800000U) /*!<Bit 3 */
#define SAI_xCR1_MCKDIV_4 (0x01000000U) /*!<Bit 4 */
#define SAI_xCR1_MCKDIV_5 (0x02000000U) /*!<Bit 5 */
#define SAI_xCR1_OSR_Pos (26U)
#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<Oversampling ratio for master clock */
#define SAI_xCR1_MCKEN_Pos (27U)
#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master clock generation enable */
/******************* Bit definition for SAI_xCR2 register *******************/
#define SAI_xCR2_FTH_Pos (0U)
#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
#define SAI_xCR2_FFLUSH_Pos (3U)
#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
#define SAI_xCR2_TRIS_Pos (4U)
#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
#define SAI_xCR2_MUTE_Pos (5U)
#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
#define SAI_xCR2_MUTEVAL_Pos (6U)
#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
#define SAI_xCR2_MUTECNT_Pos (7U)
#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
#define SAI_xCR2_CPL_Pos (13U)
#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!<CPL mode */
#define SAI_xCR2_COMP_Pos (14U)
#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
/****************** Bit definition for SAI_xFRCR register *******************/
#define SAI_xFRCR_FRL_Pos (0U)
#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */
#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
#define SAI_xFRCR_FSALL_Pos (8U)
#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */
#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
#define SAI_xFRCR_FSDEF_Pos (16U)
#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!< Frame Synchronization Definition */
#define SAI_xFRCR_FSPOL_Pos (17U)
#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
#define SAI_xFRCR_FSOFF_Pos (18U)
#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
/****************** Bit definition for SAI_xSLOTR register *******************/
#define SAI_xSLOTR_FBOFF_Pos (0U)
#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */
#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
#define SAI_xSLOTR_SLOTSZ_Pos (6U)
#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
#define SAI_xSLOTR_NBSLOT_Pos (8U)
#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
#define SAI_xSLOTR_SLOTEN_Pos (16U)
#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
/******************* Bit definition for SAI_xIMR register *******************/
#define SAI_xIMR_OVRUDRIE_Pos (0U)
#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
#define SAI_xIMR_MUTEDETIE_Pos (1U)
#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
#define SAI_xIMR_WCKCFGIE_Pos (2U)
#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
#define SAI_xIMR_FREQIE_Pos (3U)
#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
#define SAI_xIMR_CNRDYIE_Pos (4U)
#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
#define SAI_xIMR_AFSDETIE_Pos (5U)
#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
#define SAI_xIMR_LFSDETIE_Pos (6U)
#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
/******************** Bit definition for SAI_xSR register *******************/
#define SAI_xSR_OVRUDR_Pos (0U)
#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
#define SAI_xSR_MUTEDET_Pos (1U)
#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
#define SAI_xSR_WCKCFG_Pos (2U)
#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
#define SAI_xSR_FREQ_Pos (3U)
#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
#define SAI_xSR_CNRDY_Pos (4U)
#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
#define SAI_xSR_AFSDET_Pos (5U)
#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
#define SAI_xSR_LFSDET_Pos (6U)
#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
#define SAI_xSR_FLVL_Pos (16U)
#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
/****************** Bit definition for SAI_xCLRFR register ******************/
#define SAI_xCLRFR_COVRUDR_Pos (0U)
#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
#define SAI_xCLRFR_CMUTEDET_Pos (1U)
#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
#define SAI_xCLRFR_CWCKCFG_Pos (2U)
#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
#define SAI_xCLRFR_CFREQ_Pos (3U)
#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
#define SAI_xCLRFR_CCNRDY_Pos (4U)
#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
#define SAI_xCLRFR_CAFSDET_Pos (5U)
#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
#define SAI_xCLRFR_CLFSDET_Pos (6U)
#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
/****************** Bit definition for SAI_xDR register ******************/
#define SAI_xDR_DATA_Pos (0U)
#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
#define SAI_xDR_DATA SAI_xDR_DATA_Msk
/****************** Bit definition for SAI_PDMCR register *******************/
#define SAI_PDMCR_PDMEN_Pos (0U)
#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM enable */
#define SAI_PDMCR_MICNBR_Pos (4U)
#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<MICNBR[1:0] (Number of microphones) */
#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
#define SAI_PDMCR_CKEN1_Pos (8U)
#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock 1 enable */
#define SAI_PDMCR_CKEN2_Pos (9U)
#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock 2 enable */
#define SAI_PDMCR_CKEN3_Pos (10U)
#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock 3 enable */
#define SAI_PDMCR_CKEN4_Pos (11U)
#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock 4 enable */
/****************** Bit definition for SAI_PDMDLY register ******************/
#define SAI_PDMDLY_DLYM1L_Pos (0U)
#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
#define SAI_PDMDLY_DLYM1R_Pos (4U)
#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
#define SAI_PDMDLY_DLYM2L_Pos (8U)
#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
#define SAI_PDMDLY_DLYM2R_Pos (12U)
#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2) */
#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
#define SAI_PDMDLY_DLYM3L_Pos (16U)
#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3) */
#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
#define SAI_PDMDLY_DLYM3R_Pos (20U)
#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3) */
#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
#define SAI_PDMDLY_DLYM4L_Pos (24U)
#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4) */
#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
#define SAI_PDMDLY_DLYM4R_Pos (28U)
#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4) */
#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
/******************************************************************************/
/* */
/* Serial Peripheral Interface (SPI) */
/* */
/******************************************************************************/
/*
* @brief Specific device feature definitions (not present on all devices in the STM32G4 serie)
*/
#define SPI_I2S_SUPPORT /*!< I2S support */
/******************* Bit definition for SPI_CR1 register ********************/
#define SPI_CR1_CPHA_Pos (0U)
#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!<Clock Phase */
#define SPI_CR1_CPOL_Pos (1U)
#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!<Clock Polarity */
#define SPI_CR1_MSTR_Pos (2U)
#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!<Master Selection */
#define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<SPI Enable */
#define SPI_CR1_LSBFIRST_Pos (7U)
#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!<Frame Format */
#define SPI_CR1_SSI_Pos (8U)
#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal slave select */
#define SPI_CR1_SSM_Pos (9U)
#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!<Software slave management */
#define SPI_CR1_RXONLY_Pos (10U)
#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!<Receive only */
#define SPI_CR1_CRCL_Pos (11U)
#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
#define SPI_CR1_CRCNEXT_Pos (12U)
#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!<Transmit CRC next */
#define SPI_CR1_CRCEN_Pos (13U)
#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!<Hardware CRC calculation enable */
#define SPI_CR1_BIDIOE_Pos (14U)
#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!<Output enable in bidirectional mode */
#define SPI_CR1_BIDIMODE_Pos (15U)
#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!<Bidirectional data mode enable */
/******************* Bit definition for SPI_CR2 register ********************/
#define SPI_CR2_RXDMAEN_Pos (0U)
#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
#define SPI_CR2_TXDMAEN_Pos (1U)
#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
#define SPI_CR2_SSOE_Pos (2U)
#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
#define SPI_CR2_NSSP_Pos (3U)
#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
#define SPI_CR2_FRF_Pos (4U)
#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
#define SPI_CR2_ERRIE_Pos (5U)
#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
#define SPI_CR2_RXNEIE_Pos (6U)
#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
#define SPI_CR2_TXEIE_Pos (7U)
#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
#define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
#define SPI_CR2_LDMARX_Pos (13U)
#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
#define SPI_CR2_LDMATX_Pos (14U)
#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
/******************** Bit definition for SPI_SR register ********************/
#define SPI_SR_RXNE_Pos (0U)
#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
#define SPI_SR_TXE_Pos (1U)
#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
#define SPI_SR_CHSIDE_Pos (2U)
#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
#define SPI_SR_UDR_Pos (3U)
#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
#define SPI_SR_CRCERR_Pos (4U)
#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
#define SPI_SR_MODF_Pos (5U)
#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
#define SPI_SR_OVR_Pos (6U)
#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
#define SPI_SR_BSY_Pos (7U)
#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
#define SPI_SR_FRE_Pos (8U)
#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */
#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
#define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U)
#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
#define SPI_DR_DR SPI_DR_DR_Msk /*!<Data Register */
/******************* Bit definition for SPI_CRCPR register ******************/
#define SPI_CRCPR_CRCPOLY_Pos (0U)
#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!<CRC polynomial register */
/****************** Bit definition for SPI_RXCRCR register ******************/
#define SPI_RXCRCR_RXCRC_Pos (0U)
#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!<Rx CRC Register */
/****************** Bit definition for SPI_TXCRCR register ******************/
#define SPI_TXCRCR_TXCRC_Pos (0U)
#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!<Tx CRC Register */
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN_Pos (0U)
#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
#define SPI_I2SCFGR_DATLEN_Pos (1U)
#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
#define SPI_I2SCFGR_CKPOL_Pos (3U)
#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
#define SPI_I2SCFGR_I2SSTD_Pos (4U)
#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
#define SPI_I2SCFGR_I2SCFG_Pos (8U)
#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
#define SPI_I2SCFGR_I2SE_Pos (10U)
#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
#define SPI_I2SCFGR_I2SMOD_Pos (11U)
#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
#define SPI_I2SCFGR_ASTRTEN_Pos (12U)
#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */
#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */
/****************** Bit definition for SPI_I2SPR register *******************/
#define SPI_I2SPR_I2SDIV_Pos (0U)
#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
#define SPI_I2SPR_ODD_Pos (8U)
#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
#define SPI_I2SPR_MCKOE_Pos (9U)
#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
/******************************************************************************/
/* */
/* SYSCFG */
/* */
/******************************************************************************/
/****************** Bit definition for SYSCFG_MEMRMP register ***************/
#define SYSCFG_MEMRMP_MEM_MODE_Pos (0U)
#define SYSCFG_MEMRMP_MEM_MODE_Msk (0x7UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000007 */
#define SYSCFG_MEMRMP_MEM_MODE SYSCFG_MEMRMP_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MEMRMP_MEM_MODE_0 (0x1UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000001 */
#define SYSCFG_MEMRMP_MEM_MODE_1 (0x2UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000002 */
#define SYSCFG_MEMRMP_MEM_MODE_2 (0x4UL << SYSCFG_MEMRMP_MEM_MODE_Pos) /*!< 0x00000004 */
#define SYSCFG_MEMRMP_FB_MODE_Pos (8U)
#define SYSCFG_MEMRMP_FB_MODE_Msk (0x1UL << SYSCFG_MEMRMP_FB_MODE_Pos) /*!< 0x00000100 */
#define SYSCFG_MEMRMP_FB_MODE SYSCFG_MEMRMP_FB_MODE_Msk /*!< User Flash Bank mode selection */
/****************** Bit definition for SYSCFG_CFGR1 register ******************/
#define SYSCFG_CFGR1_BOOSTEN_Pos (8U)
#define SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
#define SYSCFG_CFGR1_ANASWVDD_Pos (9U)
#define SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) /*!< 0x00000200 */
#define SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk /*!< GPIO analog switch control voltage selection */
#define SYSCFG_CFGR1_I2C_PB6_FMP_Pos (16U)
#define SYSCFG_CFGR1_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB6_FMP_Pos)/*!< 0x00010000 */
#define SYSCFG_CFGR1_I2C_PB6_FMP SYSCFG_CFGR1_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB7_FMP_Pos (17U)
#define SYSCFG_CFGR1_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB7_FMP_Pos)/*!< 0x00020000 */
#define SYSCFG_CFGR1_I2C_PB7_FMP SYSCFG_CFGR1_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB8_FMP_Pos (18U)
#define SYSCFG_CFGR1_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB8_FMP_Pos)/*!< 0x00040000 */
#define SYSCFG_CFGR1_I2C_PB8_FMP SYSCFG_CFGR1_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_PB9_FMP_Pos (19U)
#define SYSCFG_CFGR1_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C_PB9_FMP_Pos)/*!< 0x00080000 */
#define SYSCFG_CFGR1_I2C_PB9_FMP SYSCFG_CFGR1_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C1_FMP_Pos (20U)
#define SYSCFG_CFGR1_I2C1_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C1_FMP_Pos) /*!< 0x00100000 */
#define SYSCFG_CFGR1_I2C1_FMP SYSCFG_CFGR1_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
#define SYSCFG_CFGR1_I2C2_FMP_Pos (21U)
#define SYSCFG_CFGR1_I2C2_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C2_FMP_Pos) /*!< 0x00200000 */
#define SYSCFG_CFGR1_I2C2_FMP SYSCFG_CFGR1_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
#define SYSCFG_CFGR1_I2C3_FMP_Pos (22U)
#define SYSCFG_CFGR1_I2C3_FMP_Msk (0x1UL << SYSCFG_CFGR1_I2C3_FMP_Pos) /*!< 0x00400000 */
#define SYSCFG_CFGR1_I2C3_FMP SYSCFG_CFGR1_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
#define SYSCFG_CFGR1_FPU_IE_0 (0x04000000U) /*!< Invalid operation Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_1 (0x08000000U) /*!< Divide-by-zero Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_2 (0x10000000U) /*!< Underflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_3 (0x20000000U) /*!< Overflow Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_4 (0x40000000U) /*!< Input denormal Interrupt enable */
#define SYSCFG_CFGR1_FPU_IE_5 (0x80000000U) /*!< Inexact Interrupt enable (interrupt disabled at reset) */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
#define SYSCFG_EXTICR1_EXTI0_Msk (0x7UL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
#define SYSCFG_EXTICR1_EXTI1_Msk (0x7UL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
#define SYSCFG_EXTICR1_EXTI2_Msk (0x7UL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
#define SYSCFG_EXTICR1_EXTI3_Msk (0x7UL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!<PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!<PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!<PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!<PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!<PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!<PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U) /*!<PG[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!<PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!<PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!<PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!<PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!<PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!<PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U) /*!<PG[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!<PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!<PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!<PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!<PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!<PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!<PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U) /*!<PG[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!<PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!<PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!<PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!<PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!<PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!<PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U) /*!<PG[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
#define SYSCFG_EXTICR2_EXTI4_Msk (0x7UL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
#define SYSCFG_EXTICR2_EXTI5_Msk (0x7UL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
#define SYSCFG_EXTICR2_EXTI6_Msk (0x7UL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
#define SYSCFG_EXTICR2_EXTI7_Msk (0x7UL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!<PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!<PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!<PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!<PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!<PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!<PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U) /*!<PG[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!<PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!<PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!<PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!<PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!<PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!<PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U) /*!<PG[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!<PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!<PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!<PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!<PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!<PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!<PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U) /*!<PG[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!<PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!<PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!<PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!<PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!<PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!<PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U) /*!<PG[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
#define SYSCFG_EXTICR3_EXTI8_Msk (0x7UL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
#define SYSCFG_EXTICR3_EXTI9_Msk (0x7UL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
#define SYSCFG_EXTICR3_EXTI10_Msk (0x7UL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
#define SYSCFG_EXTICR3_EXTI11_Msk (0x7UL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!<PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!<PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!<PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!<PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!<PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!<PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U) /*!<PG[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!<PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!<PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!<PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!<PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!<PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!<PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U) /*!<PG[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!<PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!<PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!<PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!<PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!<PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!<PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!<PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!<PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!<PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!<PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!<PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!<PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
#define SYSCFG_EXTICR4_EXTI12_Msk (0x7UL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x00000007 */
#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
#define SYSCFG_EXTICR4_EXTI13_Msk (0x7UL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x00000070 */
#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
#define SYSCFG_EXTICR4_EXTI14_Msk (0x7UL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000700 */
#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
#define SYSCFG_EXTICR4_EXTI15_Msk (0x7UL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x00007000 */
#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!<PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!<PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!<PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!<PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!<PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!<PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!<PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!<PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!<PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!<PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!<PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!<PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!<PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!<PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!<PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!<PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!<PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!<PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!<PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!<PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!<PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!<PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!<PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!<PF[15] pin */
/****************** Bit definition for SYSCFG_SCSR register ****************/
#define SYSCFG_SCSR_CCMER_Pos (0U)
#define SYSCFG_SCSR_CCMER_Msk (0x1UL << SYSCFG_SCSR_CCMER_Pos) /*!< 0x00000001 */
#define SYSCFG_SCSR_CCMER SYSCFG_SCSR_CCMER_Msk /*!< CCMSRAM Erase Request */
#define SYSCFG_SCSR_CCMBSY_Pos (1U)
#define SYSCFG_SCSR_CCMBSY_Msk (0x1UL << SYSCFG_SCSR_CCMBSY_Pos) /*!< 0x00000002 */
#define SYSCFG_SCSR_CCMBSY SYSCFG_SCSR_CCMBSY_Msk /*!< CCMSRAM Erase Ongoing */
/****************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_CLL_Pos (0U)
#define SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) /*!< 0x00000001 */
#define SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk /*!< Core Lockup Lock */
#define SYSCFG_CFGR2_SPL_Pos (1U)
#define SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) /*!< 0x00000002 */
#define SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk /*!< SRAM Parity Lock*/
#define SYSCFG_CFGR2_PVDL_Pos (2U)
#define SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) /*!< 0x00000004 */
#define SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk /*!< PVD Lock */
#define SYSCFG_CFGR2_ECCL_Pos (3U)
#define SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) /*!< 0x00000008 */
#define SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk /*!< ECC Lock*/
#define SYSCFG_CFGR2_SPF_Pos (8U)
#define SYSCFG_CFGR2_SPF_Msk (0x1UL << SYSCFG_CFGR2_SPF_Pos) /*!< 0x00000100 */
#define SYSCFG_CFGR2_SPF SYSCFG_CFGR2_SPF_Msk /*!< SRAM Parity Flag */
/****************** Bit definition for SYSCFG_SWPR register ****************/
#define SYSCFG_SWPR_PAGE0_Pos (0U)
#define SYSCFG_SWPR_PAGE0_Msk (0x1UL << SYSCFG_SWPR_PAGE0_Pos) /*!< 0x00000001 */
#define SYSCFG_SWPR_PAGE0 (SYSCFG_SWPR_PAGE0_Msk) /*!< CCMSRAM Write protection page 0 */
#define SYSCFG_SWPR_PAGE1_Pos (1U)
#define SYSCFG_SWPR_PAGE1_Msk (0x1UL << SYSCFG_SWPR_PAGE1_Pos) /*!< 0x00000002 */
#define SYSCFG_SWPR_PAGE1 (SYSCFG_SWPR_PAGE1_Msk) /*!< CCMSRAM Write protection page 1 */
#define SYSCFG_SWPR_PAGE2_Pos (2U)
#define SYSCFG_SWPR_PAGE2_Msk (0x1UL << SYSCFG_SWPR_PAGE2_Pos) /*!< 0x00000004 */
#define SYSCFG_SWPR_PAGE2 (SYSCFG_SWPR_PAGE2_Msk) /*!< CCMSRAM Write protection page 2 */
#define SYSCFG_SWPR_PAGE3_Pos (3U)
#define SYSCFG_SWPR_PAGE3_Msk (0x1UL << SYSCFG_SWPR_PAGE3_Pos) /*!< 0x00000008 */
#define SYSCFG_SWPR_PAGE3 (SYSCFG_SWPR_PAGE3_Msk) /*!< CCMSRAM Write protection page 3 */
#define SYSCFG_SWPR_PAGE4_Pos (4U)
#define SYSCFG_SWPR_PAGE4_Msk (0x1UL << SYSCFG_SWPR_PAGE4_Pos) /*!< 0x00000010 */
#define SYSCFG_SWPR_PAGE4 (SYSCFG_SWPR_PAGE4_Msk) /*!< CCMSRAM Write protection page 4 */
#define SYSCFG_SWPR_PAGE5_Pos (5U)
#define SYSCFG_SWPR_PAGE5_Msk (0x1UL << SYSCFG_SWPR_PAGE5_Pos) /*!< 0x00000020 */
#define SYSCFG_SWPR_PAGE5 (SYSCFG_SWPR_PAGE5_Msk) /*!< CCMSRAM Write protection page 5 */
#define SYSCFG_SWPR_PAGE6_Pos (6U)
#define SYSCFG_SWPR_PAGE6_Msk (0x1UL << SYSCFG_SWPR_PAGE6_Pos) /*!< 0x00000040 */
#define SYSCFG_SWPR_PAGE6 (SYSCFG_SWPR_PAGE6_Msk) /*!< CCMSRAM Write protection page 6 */
#define SYSCFG_SWPR_PAGE7_Pos (7U)
#define SYSCFG_SWPR_PAGE7_Msk (0x1UL << SYSCFG_SWPR_PAGE7_Pos) /*!< 0x00000080 */
#define SYSCFG_SWPR_PAGE7 (SYSCFG_SWPR_PAGE7_Msk) /*!< CCMSRAM Write protection page 7 */
#define SYSCFG_SWPR_PAGE8_Pos (8U)
#define SYSCFG_SWPR_PAGE8_Msk (0x1UL << SYSCFG_SWPR_PAGE8_Pos) /*!< 0x00000100 */
#define SYSCFG_SWPR_PAGE8 (SYSCFG_SWPR_PAGE8_Msk) /*!< CCMSRAM Write protection page 8 */
#define SYSCFG_SWPR_PAGE9_Pos (9U)
#define SYSCFG_SWPR_PAGE9_Msk (0x1UL << SYSCFG_SWPR_PAGE9_Pos) /*!< 0x00000200 */
#define SYSCFG_SWPR_PAGE9 (SYSCFG_SWPR_PAGE9_Msk) /*!< CCMSRAM Write protection page 9 */
#define SYSCFG_SWPR_PAGE10_Pos (10U)
#define SYSCFG_SWPR_PAGE10_Msk (0x1UL << SYSCFG_SWPR_PAGE10_Pos) /*!< 0x00000400 */
#define SYSCFG_SWPR_PAGE10 (SYSCFG_SWPR_PAGE10_Msk) /*!< CCMSRAM Write protection page 10*/
#define SYSCFG_SWPR_PAGE11_Pos (11U)
#define SYSCFG_SWPR_PAGE11_Msk (0x1UL << SYSCFG_SWPR_PAGE11_Pos) /*!< 0x00000800 */
#define SYSCFG_SWPR_PAGE11 (SYSCFG_SWPR_PAGE11_Msk) /*!< CCMSRAM Write protection page 11*/
#define SYSCFG_SWPR_PAGE12_Pos (12U)
#define SYSCFG_SWPR_PAGE12_Msk (0x1UL << SYSCFG_SWPR_PAGE12_Pos) /*!< 0x00001000 */
#define SYSCFG_SWPR_PAGE12 (SYSCFG_SWPR_PAGE12_Msk) /*!< CCMSRAM Write protection page 12*/
#define SYSCFG_SWPR_PAGE13_Pos (13U)
#define SYSCFG_SWPR_PAGE13_Msk (0x1UL << SYSCFG_SWPR_PAGE13_Pos) /*!< 0x00002000 */
#define SYSCFG_SWPR_PAGE13 (SYSCFG_SWPR_PAGE13_Msk) /*!< CCMSRAM Write protection page 13*/
#define SYSCFG_SWPR_PAGE14_Pos (14U)
#define SYSCFG_SWPR_PAGE14_Msk (0x1UL << SYSCFG_SWPR_PAGE14_Pos) /*!< 0x00004000 */
#define SYSCFG_SWPR_PAGE14 (SYSCFG_SWPR_PAGE14_Msk) /*!< CCMSRAM Write protection page 14*/
#define SYSCFG_SWPR_PAGE15_Pos (15U)
#define SYSCFG_SWPR_PAGE15_Msk (0x1UL << SYSCFG_SWPR_PAGE15_Pos) /*!< 0x00008000 */
#define SYSCFG_SWPR_PAGE15 (SYSCFG_SWPR_PAGE15_Msk) /*!< CCMSRAM Write protection page 15*/
/****************** Bit definition for SYSCFG_SKR register ****************/
#define SYSCFG_SKR_KEY_Pos (0U)
#define SYSCFG_SKR_KEY_Msk (0xFFUL << SYSCFG_SKR_KEY_Pos) /*!< 0x000000FF */
#define SYSCFG_SKR_KEY SYSCFG_SKR_KEY_Msk /*!< CCMSRAM write protection key for software erase */
/******************************************************************************/
/* */
/* TIM */
/* */
/******************************************************************************/
/******************* Bit definition for TIM_CR1 register ********************/
#define TIM_CR1_CEN_Pos (0U)
#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
#define TIM_CR1_UDIS_Pos (1U)
#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
#define TIM_CR1_URS_Pos (2U)
#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
#define TIM_CR1_OPM_Pos (3U)
#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
#define TIM_CR1_DIR_Pos (4U)
#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
#define TIM_CR1_CMS_Pos (5U)
#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
#define TIM_CR1_ARPE_Pos (7U)
#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
#define TIM_CR1_CKD_Pos (8U)
#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
#define TIM_CR1_UIFREMAP_Pos (11U)
#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
#define TIM_CR1_DITHEN_Pos (12U)
#define TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) /*!< 0x00001000 */
#define TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk /*!<Dithering enable */
/******************* Bit definition for TIM_CR2 register ********************/
#define TIM_CR2_CCPC_Pos (0U)
#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
#define TIM_CR2_CCUS_Pos (2U)
#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
#define TIM_CR2_CCDS_Pos (3U)
#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
#define TIM_CR2_MMS_Pos (4U)
#define TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) /*!< 0x02000070 */
#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[3:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
#define TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
#define TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
#define TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) /*!< 0x02000000 */
#define TIM_CR2_TI1S_Pos (7U)
#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
#define TIM_CR2_OIS1_Pos (8U)
#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
#define TIM_CR2_OIS1N_Pos (9U)
#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
#define TIM_CR2_OIS2_Pos (10U)
#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
#define TIM_CR2_OIS2N_Pos (11U)
#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
#define TIM_CR2_OIS3_Pos (12U)
#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
#define TIM_CR2_OIS3N_Pos (13U)
#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
#define TIM_CR2_OIS4_Pos (14U)
#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
#define TIM_CR2_OIS4N_Pos (15U)
#define TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) /*!< 0x00008000 */
#define TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk /*!<Output Idle state 4 (OC4N output) */
#define TIM_CR2_OIS5_Pos (16U)
#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 5 (OC5 output) */
#define TIM_CR2_OIS6_Pos (18U)
#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */
#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 6 (OC6 output) */
#define TIM_CR2_MMS2_Pos (20U)
#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
/******************* Bit definition for TIM_SMCR register *******************/
#define TIM_SMCR_SMS_Pos (0U)
#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
#define TIM_SMCR_OCCS_Pos (3U)
#define TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
#define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
#define TIM_SMCR_TS_Pos (4U)
#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
#define TIM_SMCR_MSM_Pos (7U)
#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
#define TIM_SMCR_ETF_Pos (8U)
#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
#define TIM_SMCR_ETPS_Pos (12U)
#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
#define TIM_SMCR_ECE_Pos (14U)
#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
#define TIM_SMCR_ETP_Pos (15U)
#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
#define TIM_SMCR_SMSPE_Pos (24U)
#define TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) /*!< 0x02000000 */
#define TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk /*!<SMS preload enable */
#define TIM_SMCR_SMSPS_Pos (25U)
#define TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) /*!< 0x04000000 */
#define TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk /*!<SMS preload source */
/******************* Bit definition for TIM_DIER register *******************/
#define TIM_DIER_UIE_Pos (0U)
#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
#define TIM_DIER_CC1IE_Pos (1U)
#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
#define TIM_DIER_CC2IE_Pos (2U)
#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
#define TIM_DIER_CC3IE_Pos (3U)
#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
#define TIM_DIER_CC4IE_Pos (4U)
#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
#define TIM_DIER_COMIE_Pos (5U)
#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
#define TIM_DIER_TIE_Pos (6U)
#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
#define TIM_DIER_BIE_Pos (7U)
#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
#define TIM_DIER_UDE_Pos (8U)
#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
#define TIM_DIER_CC1DE_Pos (9U)
#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
#define TIM_DIER_CC2DE_Pos (10U)
#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
#define TIM_DIER_CC3DE_Pos (11U)
#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
#define TIM_DIER_CC4DE_Pos (12U)
#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
#define TIM_DIER_COMDE_Pos (13U)
#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
#define TIM_DIER_TDE_Pos (14U)
#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
#define TIM_DIER_IDXIE_Pos (20U)
#define TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) /*!< 0x00100000 */
#define TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk /*!<Encoder index interrupt enable */
#define TIM_DIER_DIRIE_Pos (21U)
#define TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) /*!< 0x00200000 */
#define TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk /*!<Encoder direction change interrupt enable */
#define TIM_DIER_IERRIE_Pos (22U)
#define TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) /*!< 0x00400000 */
#define TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk /*!<Encoder index error enable */
#define TIM_DIER_TERRIE_Pos (23U)
#define TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) /*!< 0x00800000 */
#define TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk /*!<Encoder transition error enable */
/******************** Bit definition for TIM_SR register ********************/
#define TIM_SR_UIF_Pos (0U)
#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
#define TIM_SR_CC1IF_Pos (1U)
#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
#define TIM_SR_CC2IF_Pos (2U)
#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
#define TIM_SR_CC3IF_Pos (3U)
#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
#define TIM_SR_CC4IF_Pos (4U)
#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
#define TIM_SR_COMIF_Pos (5U)
#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
#define TIM_SR_TIF_Pos (6U)
#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
#define TIM_SR_BIF_Pos (7U)
#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
#define TIM_SR_B2IF_Pos (8U)
#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break 2 interrupt Flag */
#define TIM_SR_CC1OF_Pos (9U)
#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
#define TIM_SR_CC2OF_Pos (10U)
#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
#define TIM_SR_CC3OF_Pos (11U)
#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
#define TIM_SR_CC4OF_Pos (12U)
#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
#define TIM_SR_SBIF_Pos (13U)
#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */
#define TIM_SR_CC5IF_Pos (16U)
#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
#define TIM_SR_CC6IF_Pos (17U)
#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
#define TIM_SR_IDXF_Pos (20U)
#define TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) /*!< 0x00100000 */
#define TIM_SR_IDXF TIM_SR_IDXF_Msk /*!<Encoder index interrupt flag */
#define TIM_SR_DIRF_Pos (21U)
#define TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) /*!< 0x00200000 */
#define TIM_SR_DIRF TIM_SR_DIRF_Msk /*!<Encoder direction change interrupt flag */
#define TIM_SR_IERRF_Pos (22U)
#define TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) /*!< 0x00400000 */
#define TIM_SR_IERRF TIM_SR_IERRF_Msk /*!<Encoder index error flag */
#define TIM_SR_TERRF_Pos (23U)
#define TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) /*!< 0x00800000 */
#define TIM_SR_TERRF TIM_SR_TERRF_Msk /*!<Encoder transition error flag */
/******************* Bit definition for TIM_EGR register ********************/
#define TIM_EGR_UG_Pos (0U)
#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
#define TIM_EGR_CC1G_Pos (1U)
#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
#define TIM_EGR_CC2G_Pos (2U)
#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
#define TIM_EGR_CC3G_Pos (3U)
#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
#define TIM_EGR_CC4G_Pos (4U)
#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
#define TIM_EGR_COMG_Pos (5U)
#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
#define TIM_EGR_TG_Pos (6U)
#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
#define TIM_EGR_BG_Pos (7U)
#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
#define TIM_EGR_B2G_Pos (8U)
#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break 2 Generation */
/****************** Bit definition for TIM_CCMR1 register *******************/
#define TIM_CCMR1_CC1S_Pos (0U)
#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
#define TIM_CCMR1_OC1FE_Pos (2U)
#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
#define TIM_CCMR1_OC1PE_Pos (3U)
#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
#define TIM_CCMR1_OC1M_Pos (4U)
#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
#define TIM_CCMR1_OC1CE_Pos (7U)
#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1 Clear Enable */
#define TIM_CCMR1_CC2S_Pos (8U)
#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
#define TIM_CCMR1_OC2FE_Pos (10U)
#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
#define TIM_CCMR1_OC2PE_Pos (11U)
#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
#define TIM_CCMR1_OC2M_Pos (12U)
#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
#define TIM_CCMR1_OC2CE_Pos (15U)
#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR1_IC1PSC_Pos (2U)
#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR1_IC1F_Pos (4U)
#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
#define TIM_CCMR1_IC2PSC_Pos (10U)
#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR1_IC2F_Pos (12U)
#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR2 register *******************/
#define TIM_CCMR2_CC3S_Pos (0U)
#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
#define TIM_CCMR2_OC3FE_Pos (2U)
#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
#define TIM_CCMR2_OC3PE_Pos (3U)
#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
#define TIM_CCMR2_OC3M_Pos (4U)
#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */
#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
#define TIM_CCMR2_OC3CE_Pos (7U)
#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
#define TIM_CCMR2_CC4S_Pos (8U)
#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
#define TIM_CCMR2_OC4FE_Pos (10U)
#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
#define TIM_CCMR2_OC4PE_Pos (11U)
#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
#define TIM_CCMR2_OC4M_Pos (12U)
#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */
#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */
#define TIM_CCMR2_OC4CE_Pos (15U)
#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
/*----------------------------------------------------------------------------*/
#define TIM_CCMR2_IC3PSC_Pos (2U)
#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
#define TIM_CCMR2_IC3F_Pos (4U)
#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
#define TIM_CCMR2_IC4PSC_Pos (10U)
#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
#define TIM_CCMR2_IC4F_Pos (12U)
#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
/****************** Bit definition for TIM_CCMR3 register *******************/
#define TIM_CCMR3_OC5FE_Pos (2U)
#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
#define TIM_CCMR3_OC5PE_Pos (3U)
#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
#define TIM_CCMR3_OC5M_Pos (4U)
#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */
#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[3:0] bits (Output Compare 5 Mode) */
#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
#define TIM_CCMR3_OC5CE_Pos (7U)
#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
#define TIM_CCMR3_OC6FE_Pos (10U)
#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
#define TIM_CCMR3_OC6PE_Pos (11U)
#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 6 Preload enable */
#define TIM_CCMR3_OC6M_Pos (12U)
#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */
#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC6M[3:0] bits (Output Compare 6 Mode) */
#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */
#define TIM_CCMR3_OC6CE_Pos (15U)
#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 6 Clear Enable */
/******************* Bit definition for TIM_CCER register *******************/
#define TIM_CCER_CC1E_Pos (0U)
#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
#define TIM_CCER_CC1P_Pos (1U)
#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
#define TIM_CCER_CC1NE_Pos (2U)
#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
#define TIM_CCER_CC1NP_Pos (3U)
#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
#define TIM_CCER_CC2E_Pos (4U)
#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
#define TIM_CCER_CC2P_Pos (5U)
#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
#define TIM_CCER_CC2NE_Pos (6U)
#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
#define TIM_CCER_CC2NP_Pos (7U)
#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
#define TIM_CCER_CC3E_Pos (8U)
#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
#define TIM_CCER_CC3P_Pos (9U)
#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
#define TIM_CCER_CC3NE_Pos (10U)
#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
#define TIM_CCER_CC3NP_Pos (11U)
#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
#define TIM_CCER_CC4E_Pos (12U)
#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
#define TIM_CCER_CC4P_Pos (13U)
#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
#define TIM_CCER_CC4NE_Pos (14U)
#define TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) /*!< 0x00004000 */
#define TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk /*!<Capture/Compare 4 Complementary output enable */
#define TIM_CCER_CC4NP_Pos (15U)
#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
#define TIM_CCER_CC5E_Pos (16U)
#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
#define TIM_CCER_CC5P_Pos (17U)
#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
#define TIM_CCER_CC6E_Pos (20U)
#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
#define TIM_CCER_CC6P_Pos (21U)
#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT_CNT_Pos (0U)
#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
#define TIM_CNT_UIFCPY_Pos (31U)
#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */
/******************* Bit definition for TIM_PSC register ********************/
#define TIM_PSC_PSC_Pos (0U)
#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
/******************* Bit definition for TIM_ARR register ********************/
#define TIM_ARR_ARR_Pos (0U)
#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
/******************* Bit definition for TIM_RCR register ********************/
#define TIM_RCR_REP_Pos (0U)
#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */
#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
/******************* Bit definition for TIM_CCR1 register *******************/
#define TIM_CCR1_CCR1_Pos (0U)
#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
/******************* Bit definition for TIM_CCR2 register *******************/
#define TIM_CCR2_CCR2_Pos (0U)
#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
/******************* Bit definition for TIM_CCR3 register *******************/
#define TIM_CCR3_CCR3_Pos (0U)
#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
/******************* Bit definition for TIM_CCR4 register *******************/
#define TIM_CCR4_CCR4_Pos (0U)
#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
/******************* Bit definition for TIM_CCR5 register *******************/
#define TIM_CCR5_CCR5_Pos (0U)
#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
#define TIM_CCR5_GC5C1_Pos (29U)
#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
#define TIM_CCR5_GC5C2_Pos (30U)
#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
#define TIM_CCR5_GC5C3_Pos (31U)
#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
/******************* Bit definition for TIM_CCR6 register *******************/
#define TIM_CCR6_CCR6_Pos (0U)
#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
/******************* Bit definition for TIM_BDTR register *******************/
#define TIM_BDTR_DTG_Pos (0U)
#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
#define TIM_BDTR_LOCK_Pos (8U)
#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
#define TIM_BDTR_OSSI_Pos (10U)
#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
#define TIM_BDTR_OSSR_Pos (11U)
#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
#define TIM_BDTR_BKE_Pos (12U)
#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break 1 */
#define TIM_BDTR_BKP_Pos (13U)
#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break 1 */
#define TIM_BDTR_AOE_Pos (14U)
#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
#define TIM_BDTR_MOE_Pos (15U)
#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
#define TIM_BDTR_BKF_Pos (16U)
#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break 1 */
#define TIM_BDTR_BK2F_Pos (20U)
#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break 2 */
#define TIM_BDTR_BK2E_Pos (24U)
#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break 2 */
#define TIM_BDTR_BK2P_Pos (25U)
#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break 2 */
#define TIM_BDTR_BKDSRM_Pos (26U)
#define TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) /*!< 0x04000000 */
#define TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
#define TIM_BDTR_BK2DSRM_Pos (27U)
#define TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) /*!< 0x08000000 */
#define TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
#define TIM_BDTR_BKBID_Pos (28U)
#define TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) /*!< 0x10000000 */
#define TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk /*!<Break BIDirectional */
#define TIM_BDTR_BK2BID_Pos (29U)
#define TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) /*!< 0x20000000 */
#define TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk /*!<Break2 BIDirectional */
/******************* Bit definition for TIM_DCR register ********************/
#define TIM_DCR_DBA_Pos (0U)
#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
#define TIM_DCR_DBL_Pos (8U)
#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
/******************* Bit definition for TIM1_AF1 register *******************/
#define TIM1_AF1_BKINE_Pos (0U)
#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BRK BKIN input enable */
#define TIM1_AF1_BKCMP1E_Pos (1U)
#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BRK COMP1 enable */
#define TIM1_AF1_BKCMP2E_Pos (2U)
#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BRK COMP2 enable */
#define TIM1_AF1_BKCMP3E_Pos (3U)
#define TIM1_AF1_BKCMP3E_Msk (0x1UL << TIM1_AF1_BKCMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF1_BKCMP3E TIM1_AF1_BKCMP3E_Msk /*!<BRK COMP3 enable */
#define TIM1_AF1_BKCMP4E_Pos (4U)
#define TIM1_AF1_BKCMP4E_Msk (0x1UL << TIM1_AF1_BKCMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF1_BKCMP4E TIM1_AF1_BKCMP4E_Msk /*!<BRK COMP4 enable */
#define TIM1_AF1_BKINP_Pos (9U)
#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRK BKIN input polarity */
#define TIM1_AF1_BKCMP1P_Pos (10U)
#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BRK COMP1 input polarity */
#define TIM1_AF1_BKCMP2P_Pos (11U)
#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BRK COMP2 input polarity */
#define TIM1_AF1_BKCMP3P_Pos (12U)
#define TIM1_AF1_BKCMP3P_Msk (0x1UL << TIM1_AF1_BKCMP3P_Pos) /*!< 0x00001000 */
#define TIM1_AF1_BKCMP3P TIM1_AF1_BKCMP3P_Msk /*!<BRK COMP3 input polarity */
#define TIM1_AF1_BKCMP4P_Pos (13U)
#define TIM1_AF1_BKCMP4P_Msk (0x1UL << TIM1_AF1_BKCMP4P_Pos) /*!< 0x00002000 */
#define TIM1_AF1_BKCMP4P TIM1_AF1_BKCMP4P_Msk /*!<BRK COMP4 input polarity */
#define TIM1_AF1_ETRSEL_Pos (14U)
#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETR source selection) */
#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
/******************* Bit definition for TIM1_AF2 register *********************/
#define TIM1_AF2_BK2INE_Pos (0U)
#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BRK2 BKIN input enable */
#define TIM1_AF2_BK2CMP1E_Pos (1U)
#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BRK2 COMP1 enable */
#define TIM1_AF2_BK2CMP2E_Pos (2U)
#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BRK2 COMP2 enable */
#define TIM1_AF2_BK2CMP3E_Pos (3U)
#define TIM1_AF2_BK2CMP3E_Msk (0x1UL << TIM1_AF2_BK2CMP3E_Pos) /*!< 0x00000008 */
#define TIM1_AF2_BK2CMP3E TIM1_AF2_BK2CMP3E_Msk /*!<BRK2 COMP3 enable */
#define TIM1_AF2_BK2CMP4E_Pos (4U)
#define TIM1_AF2_BK2CMP4E_Msk (0x1UL << TIM1_AF2_BK2CMP4E_Pos) /*!< 0x00000010 */
#define TIM1_AF2_BK2CMP4E TIM1_AF2_BK2CMP4E_Msk /*!<BRK2 COMP4 enable */
#define TIM1_AF2_BK2INP_Pos (9U)
#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRK2 BKIN input polarity */
#define TIM1_AF2_BK2CMP1P_Pos (10U)
#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BRK2 COMP1 input polarity */
#define TIM1_AF2_BK2CMP2P_Pos (11U)
#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_BK2CMP3P_Pos (12U)
#define TIM1_AF2_BK2CMP3P_Msk (0x1UL << TIM1_AF2_BK2CMP3P_Pos) /*!< 0x00000400 */
#define TIM1_AF2_BK2CMP3P TIM1_AF2_BK2CMP3P_Msk /*!<BRK2 COMP3 input polarity */
#define TIM1_AF2_BK2CMP4P_Pos (13U)
#define TIM1_AF2_BK2CMP4P_Msk (0x1UL << TIM1_AF2_BK2CMP4P_Pos) /*!< 0x00000800 */
#define TIM1_AF2_BK2CMP4P TIM1_AF2_BK2CMP4P_Msk /*!<BRK2 COMP4 input polarity */
#define TIM1_AF2_OCRSEL_Pos (16U)
#define TIM1_AF2_OCRSEL_Msk (0x7UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00070000 */
#define TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk /*!<BRK2 COMP2 input polarity */
#define TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00010000 */
#define TIM1_AF2_OCRSEL_1 (0x2UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00020000 */
#define TIM1_AF2_OCRSEL_2 (0x4UL << TIM1_AF2_OCRSEL_Pos) /*!< 0x00040000 */
/******************* Bit definition for TIM_OR register *********************/
#define TIM_OR_HSE32EN_Pos (0U)
#define TIM_OR_HSE32EN_Msk (0x1UL << TIM_OR_HSE32EN_Pos) /*!< 0x00000001 */
#define TIM_OR_HSE32EN TIM_OR_HSE32EN_Msk /*!< HSE/32 clock enable */
/******************* Bit definition for TIM_TISEL register *********************/
#define TIM_TISEL_TI1SEL_Pos (0U)
#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
#define TIM_TISEL_TI2SEL_Pos (8U)
#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
#define TIM_TISEL_TI3SEL_Pos (16U)
#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM1 TI3 SEL)*/
#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
#define TIM_TISEL_TI4SEL_Pos (24U)
#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM1 TI4 SEL)*/
#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
/******************* Bit definition for TIM_DTR2 register *********************/
#define TIM_DTR2_DTGF_Pos (0U)
#define TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) /*!< 0x0000000F */
#define TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk /*!<DTGF[7:0] bits (Deadtime falling edge generator setup)*/
#define TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000001 */
#define TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000002 */
#define TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000004 */
#define TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000008 */
#define TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000010 */
#define TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000020 */
#define TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000040 */
#define TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) /*!< 0x00000080 */
#define TIM_DTR2_DTAE_Pos (16U)
#define TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) /*!< 0x00004000 */
#define TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk /*!<Deadtime asymmetric enable */
#define TIM_DTR2_DTPE_Pos (17U)
#define TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) /*!< 0x00008000 */
#define TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk /*!<Deadtime prelaod enable */
/******************* Bit definition for TIM_ECR register *********************/
#define TIM_ECR_IE_Pos (0U)
#define TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) /*!< 0x00000001 */
#define TIM_ECR_IE TIM_ECR_IE_Msk /*!<Index enable */
#define TIM_ECR_IDIR_Pos (1U)
#define TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) /*!< 0x00000006 */
#define TIM_ECR_IDIR TIM_ECR_IDIR_Msk /*!<IDIR[1:0] bits (Index direction)*/
#define TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) /*!< 0x00000001 */
#define TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) /*!< 0x00000002 */
#define TIM_ECR_FIDX_Pos (5U)
#define TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) /*!< 0x00000020 */
#define TIM_ECR_FIDX TIM_ECR_FIDX_Msk /*!<First index enable */
#define TIM_ECR_IPOS_Pos (6U)
#define TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) /*!< 0x0000000C0 */
#define TIM_ECR_IPOS TIM_ECR_IPOS_Msk /*!<IPOS[1:0] bits (Index positioning)*/
#define TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) /*!< 0x00000001 */
#define TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) /*!< 0x00000002 */
#define TIM_ECR_PW_Pos (16U)
#define TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) /*!< 0x00FF0000 */
#define TIM_ECR_PW TIM_ECR_PW_Msk /*!<PW[7:0] bits (Pulse width)*/
#define TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) /*!< 0x00010000 */
#define TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) /*!< 0x00020000 */
#define TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) /*!< 0x00040000 */
#define TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) /*!< 0x00080000 */
#define TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) /*!< 0x00100000 */
#define TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) /*!< 0x00200000 */
#define TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) /*!< 0x00400000 */
#define TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) /*!< 0x00800000 */
#define TIM_ECR_PWPRSC_Pos (24U)
#define TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) /*!< 0x07000000 */
#define TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk /*!<PWPRSC[2:0] bits (Pulse width prescaler)*/
#define TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) /*!< 0x01000000 */
#define TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) /*!< 0x02000000 */
#define TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) /*!< 0x04000000 */
/******************* Bit definition for TIM_DMAR register *******************/
#define TIM_DMAR_DMAB_Pos (0U)
#define TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0xFFFFFFFF */
#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
/******************************************************************************/
/* */
/* Low Power Timer (LPTIM) */
/* */
/******************************************************************************/
/****************** Bit definition for LPTIM_ISR register *******************/
#define LPTIM_ISR_CMPM_Pos (0U)
#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
#define LPTIM_ISR_ARRM_Pos (1U)
#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
#define LPTIM_ISR_EXTTRIG_Pos (2U)
#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
#define LPTIM_ISR_CMPOK_Pos (3U)
#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
#define LPTIM_ISR_ARROK_Pos (4U)
#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
#define LPTIM_ISR_UP_Pos (5U)
#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
#define LPTIM_ISR_DOWN_Pos (6U)
#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
/****************** Bit definition for LPTIM_ICR register *******************/
#define LPTIM_ICR_CMPMCF_Pos (0U)
#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
#define LPTIM_ICR_ARRMCF_Pos (1U)
#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
#define LPTIM_ICR_CMPOKCF_Pos (3U)
#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
#define LPTIM_ICR_ARROKCF_Pos (4U)
#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
#define LPTIM_ICR_UPCF_Pos (5U)
#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
#define LPTIM_ICR_DOWNCF_Pos (6U)
#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
/****************** Bit definition for LPTIM_IER register ********************/
#define LPTIM_IER_CMPMIE_Pos (0U)
#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
#define LPTIM_IER_ARRMIE_Pos (1U)
#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
#define LPTIM_IER_EXTTRIGIE_Pos (2U)
#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
#define LPTIM_IER_CMPOKIE_Pos (3U)
#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
#define LPTIM_IER_ARROKIE_Pos (4U)
#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
#define LPTIM_IER_UPIE_Pos (5U)
#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
#define LPTIM_IER_DOWNIE_Pos (6U)
#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
/****************** Bit definition for LPTIM_CFGR register *******************/
#define LPTIM_CFGR_CKSEL_Pos (0U)
#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
#define LPTIM_CFGR_CKPOL_Pos (1U)
#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
#define LPTIM_CFGR_CKFLT_Pos (3U)
#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
#define LPTIM_CFGR_TRGFLT_Pos (6U)
#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
#define LPTIM_CFGR_PRESC_Pos (9U)
#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
#define LPTIM_CFGR_TRIGSEL_Pos (13U)
#define LPTIM_CFGR_TRIGSEL_Msk (0x10007UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0200E000 */
#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
#define LPTIM_CFGR_TRIGSEL_0 (0x00001UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
#define LPTIM_CFGR_TRIGSEL_1 (0x00002UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
#define LPTIM_CFGR_TRIGSEL_2 (0x00004UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
#define LPTIM_CFGR_TRIGSEL_3 (0x10000UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x02000000 */
#define LPTIM_CFGR_TRIGEN_Pos (17U)
#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
#define LPTIM_CFGR_TIMOUT_Pos (19U)
#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
#define LPTIM_CFGR_WAVE_Pos (20U)
#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
#define LPTIM_CFGR_WAVPOL_Pos (21U)
#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
#define LPTIM_CFGR_PRELOAD_Pos (22U)
#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
#define LPTIM_CFGR_COUNTMODE_Pos (23U)
#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
#define LPTIM_CFGR_ENC_Pos (24U)
#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
/****************** Bit definition for LPTIM_CR register ********************/
#define LPTIM_CR_ENABLE_Pos (0U)
#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
#define LPTIM_CR_SNGSTRT_Pos (1U)
#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */
#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
#define LPTIM_CR_CNTSTRT_Pos (2U)
#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
#define LPTIM_CR_COUNTRST_Pos (3U)
#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */
#define LPTIM_CR_RSTARE_Pos (4U)
#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */
/****************** Bit definition for LPTIM_CMP register *******************/
#define LPTIM_CMP_CMP_Pos (0U)
#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
/****************** Bit definition for LPTIM_ARR register *******************/
#define LPTIM_ARR_ARR_Pos (0U)
#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
/****************** Bit definition for LPTIM_CNT register *******************/
#define LPTIM_CNT_CNT_Pos (0U)
#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
/****************** Bit definition for LPTIM_OR register *******************/
#define LPTIM_OR_IN1_Pos (0U)
#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */
#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< IN1[2:0] bits (Remap selection) */
#define LPTIM_OR_IN1_0 (0x1UL << LPTIM_OR_IN1_Pos) /*!< 0x00000001 */
#define LPTIM_OR_IN1_1 (0x4UL << LPTIM_OR_IN1_Pos) /*!< 0x00000004 */
#define LPTIM_OR_IN1_2 (0x8UL << LPTIM_OR_IN1_Pos) /*!< 0x00000008 */
#define LPTIM_OR_IN2_Pos (1U)
#define LPTIM_OR_IN2_Msk (0x19UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */
#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< IN2[2:0] bits (Remap selection) */
#define LPTIM_OR_IN2_0 (0x1UL << LPTIM_OR_IN2_Pos) /*!< 0x00000002 */
#define LPTIM_OR_IN2_1 (0x8UL << LPTIM_OR_IN2_Pos) /*!< 0x00000010 */
#define LPTIM_OR_IN2_2 (0x10UL << LPTIM_OR_IN2_Pos) /*!< 0x00000020 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
/* */
/******************************************************************************/
/****************** Bit definition for USART_CR1 register *******************/
#define USART_CR1_UE_Pos (0U)
#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
#define USART_CR1_UESM_Pos (1U)
#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
#define USART_CR1_RE_Pos (2U)
#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
#define USART_CR1_TE_Pos (3U)
#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
#define USART_CR1_IDLEIE_Pos (4U)
#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
#define USART_CR1_RXNEIE_Pos (5U)
#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos
#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */
#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
#define USART_CR1_TCIE_Pos (6U)
#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
#define USART_CR1_TXEIE_Pos (7U)
#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
#define USART_CR1_TXEIE_TXFNFIE_Pos USART_CR1_TXEIE_Pos
#define USART_CR1_TXEIE_TXFNFIE_Msk USART_CR1_TXEIE_Msk /*!< 0x00000080 */
#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
#define USART_CR1_PEIE_Pos (8U)
#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
#define USART_CR1_PS_Pos (9U)
#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
#define USART_CR1_PCE_Pos (10U)
#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
#define USART_CR1_WAKE_Pos (11U)
#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
#define USART_CR1_M_Pos (12U)
#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
#define USART_CR1_M0_Pos (12U)
#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
#define USART_CR1_MME_Pos (13U)
#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
#define USART_CR1_CMIE_Pos (14U)
#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
#define USART_CR1_OVER8_Pos (15U)
#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
#define USART_CR1_DEDT_Pos (16U)
#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
#define USART_CR1_DEAT_Pos (21U)
#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
#define USART_CR1_RTOIE_Pos (26U)
#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
#define USART_CR1_EOBIE_Pos (27U)
#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
#define USART_CR1_M1_Pos (28U)
#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
#define USART_CR1_FIFOEN_Pos (29U)
#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
#define USART_CR1_TXFEIE_Pos (30U)
#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
#define USART_CR1_RXFFIE_Pos (31U)
#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
/****************** Bit definition for USART_CR2 register *******************/
#define USART_CR2_SLVEN_Pos (0U)
#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */
#define USART_CR2_DIS_NSS_Pos (3U)
#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */
#define USART_CR2_ADDM7_Pos (4U)
#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
#define USART_CR2_LBDL_Pos (5U)
#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
#define USART_CR2_LBDIE_Pos (6U)
#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
#define USART_CR2_LBCL_Pos (8U)
#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
#define USART_CR2_CPHA_Pos (9U)
#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
#define USART_CR2_CPOL_Pos (10U)
#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
#define USART_CR2_CLKEN_Pos (11U)
#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
#define USART_CR2_STOP_Pos (12U)
#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
#define USART_CR2_LINEN_Pos (14U)
#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
#define USART_CR2_SWAP_Pos (15U)
#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
#define USART_CR2_RXINV_Pos (16U)
#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
#define USART_CR2_TXINV_Pos (17U)
#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
#define USART_CR2_DATAINV_Pos (18U)
#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
#define USART_CR2_MSBFIRST_Pos (19U)
#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
#define USART_CR2_ABREN_Pos (20U)
#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
#define USART_CR2_ABRMODE_Pos (21U)
#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
#define USART_CR2_RTOEN_Pos (23U)
#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
#define USART_CR2_ADD_Pos (24U)
#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
/****************** Bit definition for USART_CR3 register *******************/
#define USART_CR3_EIE_Pos (0U)
#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
#define USART_CR3_IREN_Pos (1U)
#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
#define USART_CR3_IRLP_Pos (2U)
#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
#define USART_CR3_HDSEL_Pos (3U)
#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
#define USART_CR3_NACK_Pos (4U)
#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
#define USART_CR3_SCEN_Pos (5U)
#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
#define USART_CR3_DMAR_Pos (6U)
#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
#define USART_CR3_DMAT_Pos (7U)
#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
#define USART_CR3_RTSE_Pos (8U)
#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
#define USART_CR3_CTSE_Pos (9U)
#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
#define USART_CR3_CTSIE_Pos (10U)
#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
#define USART_CR3_ONEBIT_Pos (11U)
#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
#define USART_CR3_OVRDIS_Pos (12U)
#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
#define USART_CR3_DDRE_Pos (13U)
#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
#define USART_CR3_DEM_Pos (14U)
#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
#define USART_CR3_DEP_Pos (15U)
#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
#define USART_CR3_SCARCNT_Pos (17U)
#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
#define USART_CR3_WUS_Pos (20U)
#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
#define USART_CR3_WUFIE_Pos (22U)
#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
#define USART_CR3_TXFTIE_Pos (23U)
#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
#define USART_CR3_TCBGTIE_Pos (24U)
#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */
#define USART_CR3_RXFTCFG_Pos (25U)
#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */
#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
#define USART_CR3_RXFTIE_Pos (28U)
#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
#define USART_CR3_TXFTCFG_Pos (29U)
#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */
#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
/****************** Bit definition for USART_BRR register *******************/
#define USART_BRR_LPUART_Pos (0U)
#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */
#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */
#define USART_BRR_BRR_Pos (0U)
#define USART_BRR_BRR_Msk (0xFFFFUL << USART_BRR_BRR_Pos) /*!< 0x0000FFFF */
#define USART_BRR_BRR USART_BRR_BRR_Msk /*!< USART Baud rate register [15:0] */
/****************** Bit definition for USART_GTPR register ******************/
#define USART_GTPR_PSC_Pos (0U)
#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
#define USART_GTPR_GT_Pos (8U)
#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
/******************* Bit definition for USART_RTOR register *****************/
#define USART_RTOR_RTO_Pos (0U)
#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
#define USART_RTOR_BLEN_Pos (24U)
#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
/******************* Bit definition for USART_RQR register ******************/
#define USART_RQR_ABRRQ_Pos (0U)
#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
#define USART_RQR_SBKRQ_Pos (1U)
#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
#define USART_RQR_MMRQ_Pos (2U)
#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
#define USART_RQR_RXFRQ_Pos (3U)
#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
#define USART_RQR_TXFRQ_Pos (4U)
#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
/******************* Bit definition for USART_ISR register ******************/
#define USART_ISR_PE_Pos (0U)
#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
#define USART_ISR_FE_Pos (1U)
#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
#define USART_ISR_NE_Pos (2U)
#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
#define USART_ISR_ORE_Pos (3U)
#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
#define USART_ISR_IDLE_Pos (4U)
#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
#define USART_ISR_RXNE_Pos (5U)
#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos
#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */
#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
#define USART_ISR_TC_Pos (6U)
#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
#define USART_ISR_TXE_Pos (7U)
#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */
#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos
#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */
#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
#define USART_ISR_LBDF_Pos (8U)
#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
#define USART_ISR_CTSIF_Pos (9U)
#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
#define USART_ISR_CTS_Pos (10U)
#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
#define USART_ISR_RTOF_Pos (11U)
#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
#define USART_ISR_EOBF_Pos (12U)
#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
#define USART_ISR_UDR_Pos (13U)
#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
#define USART_ISR_ABRE_Pos (14U)
#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
#define USART_ISR_ABRF_Pos (15U)
#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
#define USART_ISR_BUSY_Pos (16U)
#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
#define USART_ISR_CMF_Pos (17U)
#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
#define USART_ISR_SBKF_Pos (18U)
#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
#define USART_ISR_RWU_Pos (19U)
#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
#define USART_ISR_WUF_Pos (20U)
#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
#define USART_ISR_TEACK_Pos (21U)
#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
#define USART_ISR_REACK_Pos (22U)
#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
#define USART_ISR_TXFE_Pos (23U)
#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
#define USART_ISR_RXFF_Pos (24U)
#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */
#define USART_ISR_TCBGT_Pos (25U)
#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */
#define USART_ISR_RXFT_Pos (26U)
#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */
#define USART_ISR_TXFT_Pos (27U)
#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */
/******************* Bit definition for USART_ICR register ******************/
#define USART_ICR_PECF_Pos (0U)
#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
#define USART_ICR_FECF_Pos (1U)
#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
#define USART_ICR_NECF_Pos (2U)
#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
#define USART_ICR_ORECF_Pos (3U)
#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
#define USART_ICR_IDLECF_Pos (4U)
#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
#define USART_ICR_TXFECF_Pos (5U)
#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */
#define USART_ICR_TCCF_Pos (6U)
#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
#define USART_ICR_TCBGTCF_Pos (7U)
#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */
#define USART_ICR_LBDCF_Pos (8U)
#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
#define USART_ICR_CTSCF_Pos (9U)
#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
#define USART_ICR_RTOCF_Pos (11U)
#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
#define USART_ICR_EOBCF_Pos (12U)
#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
#define USART_ICR_UDRCF_Pos (13U)
#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */
#define USART_ICR_CMCF_Pos (17U)
#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
#define USART_ICR_WUCF_Pos (20U)
#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
/******************* Bit definition for USART_RDR register ******************/
#define USART_RDR_RDR_Pos (0U)
#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
/******************* Bit definition for USART_TDR register ******************/
#define USART_TDR_TDR_Pos (0U)
#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
/******************* Bit definition for USART_PRESC register ****************/
#define USART_PRESC_PRESCALER_Pos (0U)
#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
/******************************************************************************/
/* */
/* VREFBUF */
/* */
/******************************************************************************/
/******************* Bit definition for VREFBUF_CSR register ****************/
#define VREFBUF_CSR_ENVR_Pos (0U)
#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
#define VREFBUF_CSR_HIZ_Pos (1U)
#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
#define VREFBUF_CSR_VRR_Pos (3U)
#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
#define VREFBUF_CSR_VRS_Pos (4U)
#define VREFBUF_CSR_VRS_Msk (0x3UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000030 */
#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<VRS[5:0] bits (Voltage reference scale) */
#define VREFBUF_CSR_VRS_0 (0x1UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000010 */
#define VREFBUF_CSR_VRS_1 (0x2UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000020 */
/******************* Bit definition for VREFBUF_CCR register ******************/
#define VREFBUF_CCR_TRIM_Pos (0U)
#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
/******************************************************************************/
/* */
/* USB Device FS Endpoint registers */
/* */
/******************************************************************************/
#define USB_EP0R USB_BASE /*!< endpoint 0 register address */
#define USB_EP1R (USB_BASE + 0x0x00000004) /*!< endpoint 1 register address */
#define USB_EP2R (USB_BASE + 0x0x00000008) /*!< endpoint 2 register address */
#define USB_EP3R (USB_BASE + 0x0x0000000C) /*!< endpoint 3 register address */
#define USB_EP4R (USB_BASE + 0x0x00000010) /*!< endpoint 4 register address */
#define USB_EP5R (USB_BASE + 0x0x00000014) /*!< endpoint 5 register address */
#define USB_EP6R (USB_BASE + 0x0x00000018) /*!< endpoint 6 register address */
#define USB_EP7R (USB_BASE + 0x0x0000001C) /*!< endpoint 7 register address */
/* bit positions */
#define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
#define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
#define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
#define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
#define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
#define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
#define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
#define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
#define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
#define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
/* EndPoint REGister MASK (no toggle fields) */
#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
/*!< EP_TYPE[1:0] EndPoint TYPE */
#define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
#define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
#define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
#define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
#define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
#define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
#define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
/*!< STAT_TX[1:0] STATus for TX transfer */
#define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
#define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
#define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
#define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
#define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
#define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
/*!< STAT_RX[1:0] STATus for RX transfer */
#define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
#define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
#define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
#define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
#define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/******************************************************************************/
/* */
/* USB Device FS General registers */
/* */
/******************************************************************************/
#define USB_CNTR (USB_BASE + 0x00000040U) /*!< Control register */
#define USB_ISTR (USB_BASE + 0x00000044U) /*!< Interrupt status register */
#define USB_FNR (USB_BASE + 0x00000048U) /*!< Frame number register */
#define USB_DADDR (USB_BASE + 0x0000004CU) /*!< Device address register */
#define USB_BTABLE (USB_BASE + 0x00000050U) /*!< Buffer Table address register */
#define USB_LPMCSR (USB_BASE + 0x00000054U) /*!< LPM Control and Status register */
#define USB_BCDR (USB_BASE + 0x00000058U) /*!< Battery Charging detector register*/
/****************** Bits definition for USB_CNTR register *******************/
#define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
#define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
#define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
#define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
#define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
#define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
#define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
#define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
#define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
#define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
#define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
#define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
#define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
#define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
#define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
/****************** Bits definition for USB_ISTR register *******************/
#define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
#define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
#define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
#define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
#define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
#define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
#define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
#define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
#define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
#define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
#define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
#define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
#define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
#define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
#define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
#define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
#define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
#define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
#define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
#define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
/****************** Bits definition for USB_FNR register ********************/
#define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
#define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
#define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
#define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
#define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
/****************** Bits definition for USB_DADDR register ****************/
#define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< ADD[6:0] bits (Device Address) */
#define USB_DADDR_ADD0 ((uint8_t)0x01U) /*!< Bit 0 */
#define USB_DADDR_ADD1 ((uint8_t)0x02U) /*!< Bit 1 */
#define USB_DADDR_ADD2 ((uint8_t)0x04U) /*!< Bit 2 */
#define USB_DADDR_ADD3 ((uint8_t)0x08U) /*!< Bit 3 */
#define USB_DADDR_ADD4 ((uint8_t)0x10U) /*!< Bit 4 */
#define USB_DADDR_ADD5 ((uint8_t)0x20U) /*!< Bit 5 */
#define USB_DADDR_ADD6 ((uint8_t)0x40U) /*!< Bit 6 */
#define USB_DADDR_EF ((uint8_t)0x80U) /*!< Enable Function */
/****************** Bit definition for USB_BTABLE register ******************/
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< Buffer Table */
/****************** Bits definition for USB_BCDR register *******************/
#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
/******************* Bit definition for LPMCSR register *********************/
#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
/*!< Buffer descriptor table */
/***************** Bit definition for USB_ADDR0_TX register *****************/
#define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_TX register *****************/
#define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_TX register *****************/
#define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_TX register *****************/
#define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_TX register *****************/
#define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_TX register *****************/
#define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_TX register *****************/
#define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_TX register *****************/
#define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_TX register ****************/
#define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
/***************** Bit definition for USB_COUNT1_TX register ****************/
#define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
/***************** Bit definition for USB_COUNT2_TX register ****************/
#define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
/***************** Bit definition for USB_COUNT3_TX register ****************/
#define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
/***************** Bit definition for USB_COUNT4_TX register ****************/
#define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
/***************** Bit definition for USB_COUNT5_TX register ****************/
#define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
/***************** Bit definition for USB_COUNT6_TX register ****************/
#define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
/***************** Bit definition for USB_COUNT7_TX register ****************/
#define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_TX_0 register ***************/
#define USB_COUNT0_TX_0_COUNT0_TX_0 (0x000003FFU) /*!< Transmission Byte Count 0 (low) */
/**************** Bit definition for USB_COUNT0_TX_1 register ***************/
#define USB_COUNT0_TX_1_COUNT0_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 0 (high) */
/**************** Bit definition for USB_COUNT1_TX_0 register ***************/
#define USB_COUNT1_TX_0_COUNT1_TX_0 (0x000003FFU) /*!< Transmission Byte Count 1 (low) */
/**************** Bit definition for USB_COUNT1_TX_1 register ***************/
#define USB_COUNT1_TX_1_COUNT1_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 1 (high) */
/**************** Bit definition for USB_COUNT2_TX_0 register ***************/
#define USB_COUNT2_TX_0_COUNT2_TX_0 (0x000003FFU) /*!< Transmission Byte Count 2 (low) */
/**************** Bit definition for USB_COUNT2_TX_1 register ***************/
#define USB_COUNT2_TX_1_COUNT2_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 2 (high) */
/**************** Bit definition for USB_COUNT3_TX_0 register ***************/
#define USB_COUNT3_TX_0_COUNT3_TX_0 (0x000003FFU) /*!< Transmission Byte Count 3 (low) */
/**************** Bit definition for USB_COUNT3_TX_1 register ***************/
#define USB_COUNT3_TX_1_COUNT3_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 3 (high) */
/**************** Bit definition for USB_COUNT4_TX_0 register ***************/
#define USB_COUNT4_TX_0_COUNT4_TX_0 (0x000003FFU) /*!< Transmission Byte Count 4 (low) */
/**************** Bit definition for USB_COUNT4_TX_1 register ***************/
#define USB_COUNT4_TX_1_COUNT4_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 4 (high) */
/**************** Bit definition for USB_COUNT5_TX_0 register ***************/
#define USB_COUNT5_TX_0_COUNT5_TX_0 (0x000003FFU) /*!< Transmission Byte Count 5 (low) */
/**************** Bit definition for USB_COUNT5_TX_1 register ***************/
#define USB_COUNT5_TX_1_COUNT5_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 5 (high) */
/**************** Bit definition for USB_COUNT6_TX_0 register ***************/
#define USB_COUNT6_TX_0_COUNT6_TX_0 (0x000003FFU) /*!< Transmission Byte Count 6 (low) */
/**************** Bit definition for USB_COUNT6_TX_1 register ***************/
#define USB_COUNT6_TX_1_COUNT6_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 6 (high) */
/**************** Bit definition for USB_COUNT7_TX_0 register ***************/
#define USB_COUNT7_TX_0_COUNT7_TX_0 (0x000003FFU) /*!< Transmission Byte Count 7 (low) */
/**************** Bit definition for USB_COUNT7_TX_1 register ***************/
#define USB_COUNT7_TX_1_COUNT7_TX_1 (0x03FF0000U) /*!< Transmission Byte Count 7 (high) */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_ADDR0_RX register *****************/
#define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
/***************** Bit definition for USB_ADDR1_RX register *****************/
#define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
/***************** Bit definition for USB_ADDR2_RX register *****************/
#define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
/***************** Bit definition for USB_ADDR3_RX register *****************/
#define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
/***************** Bit definition for USB_ADDR4_RX register *****************/
#define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
/***************** Bit definition for USB_ADDR5_RX register *****************/
#define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
/***************** Bit definition for USB_ADDR6_RX register *****************/
#define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
/***************** Bit definition for USB_ADDR7_RX register *****************/
#define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)/*!< 0x0000FFFE */
#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
/*----------------------------------------------------------------------------*/
/***************** Bit definition for USB_COUNT0_RX register ****************/
#define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT0_RX_BLSIZE_Pos (15U)
#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT1_RX register ****************/
#define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT1_RX_BLSIZE_Pos (15U)
#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT2_RX register ****************/
#define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT2_RX_BLSIZE_Pos (15U)
#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT3_RX register ****************/
#define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT3_RX_BLSIZE_Pos (15U)
#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT4_RX register ****************/
#define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT4_RX_BLSIZE_Pos (15U)
#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT5_RX register ****************/
#define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT5_RX_BLSIZE_Pos (15U)
#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT6_RX register ****************/
#define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT6_RX_BLSIZE_Pos (15U)
#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
/***************** Bit definition for USB_COUNT7_RX register ****************/
#define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)/*!< 0x000003FF */
#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00007C00 */
#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000400 */
#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00000800 */
#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00001000 */
#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00002000 */
#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)/*!< 0x00004000 */
#define USB_COUNT7_RX_BLSIZE_Pos (15U)
#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)/*!< 0x00008000 */
#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
/*----------------------------------------------------------------------------*/
/**************** Bit definition for USB_COUNT0_RX_0 register ***************/
#define USB_COUNT0_RX_0_COUNT0_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT0_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT0_RX_1 register ***************/
#define USB_COUNT0_RX_1_COUNT0_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT0_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT1_RX_0 register ***************/
#define USB_COUNT1_RX_0_COUNT1_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT1_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT1_RX_1 register ***************/
#define USB_COUNT1_RX_1_COUNT1_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT1_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT2_RX_0 register ***************/
#define USB_COUNT2_RX_0_COUNT2_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT2_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT2_RX_1 register ***************/
#define USB_COUNT2_RX_1_COUNT2_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT2_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT3_RX_0 register ***************/
#define USB_COUNT3_RX_0_COUNT3_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT3_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT3_RX_1 register ***************/
#define USB_COUNT3_RX_1_COUNT3_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT3_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT4_RX_0 register ***************/
#define USB_COUNT4_RX_0_COUNT4_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT4_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT4_RX_1 register ***************/
#define USB_COUNT4_RX_1_COUNT4_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT4_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/**************** Bit definition for USB_COUNT5_RX_0 register ***************/
#define USB_COUNT5_RX_0_COUNT5_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT5_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT5_RX_1 register ***************/
#define USB_COUNT5_RX_1_COUNT5_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT5_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT6_RX_0 register ***************/
#define USB_COUNT6_RX_0_COUNT6_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT6_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/**************** Bit definition for USB_COUNT6_RX_1 register ***************/
#define USB_COUNT6_RX_1_COUNT6_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT6_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/*************** Bit definition for USB_COUNT7_RX_0 register ****************/
#define USB_COUNT7_RX_0_COUNT7_RX_0 (0x000003FFU) /*!< Reception Byte Count (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0 (0x00007C00U) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 (0x00000400U) /*!< Bit 0 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 (0x00000800U) /*!< Bit 1 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 (0x00001000U) /*!< Bit 2 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 (0x00002000U) /*!< Bit 3 */
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 (0x00004000U) /*!< Bit 4 */
#define USB_COUNT7_RX_0_BLSIZE_0 (0x00008000U) /*!< BLock SIZE (low) */
/*************** Bit definition for USB_COUNT7_RX_1 register ****************/
#define USB_COUNT7_RX_1_COUNT7_RX_1 (0x03FF0000U) /*!< Reception Byte Count (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1 (0x7C000000U) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 (0x04000000U) /*!< Bit 0 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 (0x08000000U) /*!< Bit 1 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 (0x10000000U) /*!< Bit 2 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 (0x20000000U) /*!< Bit 3 */
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 (0x40000000U) /*!< Bit 4 */
#define USB_COUNT7_RX_1_BLSIZE_1 (0x80000000U) /*!< BLock SIZE (high) */
/******************************************************************************/
/* */
/* UCPD */
/* */
/******************************************************************************/
/******************** Bits definition for UCPD_CFG1 register *******************/
#define UCPD_CFG1_HBITCLKDIV_Pos (0U)
#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */
#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */
#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */
#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */
#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */
#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */
#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */
#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */
#define UCPD_CFG1_IFRGAP_Pos (6U)
#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */
#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */
#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */
#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */
#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */
#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */
#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */
#define UCPD_CFG1_TRANSWIN_Pos (11U)
#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */
#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */
#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */
#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */
#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */
#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */
#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */
#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U)
#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */
#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */
#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */
#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */
#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */
#define UCPD_CFG1_RXORDSETEN_Pos (20U)
#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x1FF00000 */
#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */
#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00100000 */
#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00200000 */
#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00400000 */
#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x00800000 */
#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x01000000 */
#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x02000000 */
#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x04000000 */
#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x08000000 */
#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos)/*!< 0x10000000 */
#define UCPD_CFG1_TXDMAEN_Pos (29U)
#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */
#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */
#define UCPD_CFG1_RXDMAEN_Pos (30U)
#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */
#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */
#define UCPD_CFG1_UCPDEN_Pos (31U)
#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */
#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */
/******************** Bits definition for UCPD_CFG2 register *******************/
#define UCPD_CFG2_RXFILTDIS_Pos (0U)
#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */
#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */
#define UCPD_CFG2_RXFILT2N3_Pos (1U)
#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */
#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */
#define UCPD_CFG2_FORCECLK_Pos (2U)
#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */
#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */
#define UCPD_CFG2_WUPEN_Pos (3U)
#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */
#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */
/******************** Bits definition for UCPD_CR register ********************/
#define UCPD_CR_TXMODE_Pos (0U)
#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */
#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */
#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */
#define UCPD_CR_TXSEND_Pos (2U)
#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */
#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */
#define UCPD_CR_TXHRST_Pos (3U)
#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */
#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */
#define UCPD_CR_RXMODE_Pos (4U)
#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */
#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */
#define UCPD_CR_PHYRXEN_Pos (5U)
#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */
#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */
#define UCPD_CR_PHYCCSEL_Pos (6U)
#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */
#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */
#define UCPD_CR_ANASUBMODE_Pos (7U)
#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */
#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */
#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */
#define UCPD_CR_ANAMODE_Pos (9U)
#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */
#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */
#define UCPD_CR_CCENABLE_Pos (10U)
#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */
#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */
#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */
#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */
#define UCPD_CR_FRSRXEN_Pos (16U)
#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */
#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */
#define UCPD_CR_FRSTX_Pos (17U)
#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */
#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
#define UCPD_CR_RDCH_Pos (18U)
#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */
#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */
#define UCPD_CR_CC1TCDIS_Pos (20U)
#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */
#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */
#define UCPD_CR_CC2TCDIS_Pos (21U)
#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */
#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */
/******************** Bits definition for UCPD_IMR register *******************/
#define UCPD_IMR_TXISIE_Pos (0U)
#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */
#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */
#define UCPD_IMR_TXMSGDISCIE_Pos (1U)
#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */
#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */
#define UCPD_IMR_TXMSGSENTIE_Pos (2U)
#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */
#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */
#define UCPD_IMR_TXMSGABTIE_Pos (3U)
#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */
#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */
#define UCPD_IMR_HRSTDISCIE_Pos (4U)
#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */
#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */
#define UCPD_IMR_HRSTSENTIE_Pos (5U)
#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */
#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */
#define UCPD_IMR_TXUNDIE_Pos (6U)
#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */
#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */
#define UCPD_IMR_RXNEIE_Pos (8U)
#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */
#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */
#define UCPD_IMR_RXORDDETIE_Pos (9U)
#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */
#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */
#define UCPD_IMR_RXHRSTDETIE_Pos (10U)
#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */
#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */
#define UCPD_IMR_RXOVRIE_Pos (11U)
#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */
#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */
#define UCPD_IMR_RXMSGENDIE_Pos (12U)
#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */
#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */
#define UCPD_IMR_TYPECEVT1IE_Pos (14U)
#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */
#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */
#define UCPD_IMR_TYPECEVT2IE_Pos (15U)
#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */
#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */
#define UCPD_IMR_FRSEVTIE_Pos (20U)
#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */
#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */
/******************** Bits definition for UCPD_SR register ********************/
#define UCPD_SR_TXIS_Pos (0U)
#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */
#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */
#define UCPD_SR_TXMSGDISC_Pos (1U)
#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */
#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */
#define UCPD_SR_TXMSGSENT_Pos (2U)
#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */
#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */
#define UCPD_SR_TXMSGABT_Pos (3U)
#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */
#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */
#define UCPD_SR_HRSTDISC_Pos (4U)
#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */
#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */
#define UCPD_SR_HRSTSENT_Pos (5U)
#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */
#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */
#define UCPD_SR_TXUND_Pos (6U)
#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */
#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */
#define UCPD_SR_RXNE_Pos (8U)
#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */
#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */
#define UCPD_SR_RXORDDET_Pos (9U)
#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */
#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */
#define UCPD_SR_RXHRSTDET_Pos (10U)
#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */
#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */
#define UCPD_SR_RXOVR_Pos (11U)
#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */
#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */
#define UCPD_SR_RXMSGEND_Pos (12U)
#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */
#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */
#define UCPD_SR_RXERR_Pos (13U)
#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */
#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */
#define UCPD_SR_TYPECEVT1_Pos (14U)
#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */
#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */
#define UCPD_SR_TYPECEVT2_Pos (15U)
#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */
#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */
#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U)
#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00030000 */
#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */
#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00010000 */
#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos)/*!< 0x00020000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U)
#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x000C0000 */
#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!<Status of DC level on CC2 pin */
#define UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00040000 */
#define UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos)/*!< 0x00080000 */
#define UCPD_SR_FRSEVT_Pos (20U)
#define UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) /*!< 0x00100000 */
#define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role Swap detection event */
/******************** Bits definition for UCPD_ICR register *******************/
#define UCPD_ICR_TXMSGDISCCF_Pos (1U)
#define UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) /*!< 0x00000002 */
#define UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk /*!< Tx message discarded flag (TXMSGDISC) clear */
#define UCPD_ICR_TXMSGSENTCF_Pos (2U)
#define UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) /*!< 0x00000004 */
#define UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk /*!< Tx message sent flag (TXMSGSENT) clear */
#define UCPD_ICR_TXMSGABTCF_Pos (3U)
#define UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) /*!< 0x00000008 */
#define UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk /*!< Tx message abort flag (TXMSGABT) clear */
#define UCPD_ICR_HRSTDISCCF_Pos (4U)
#define UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) /*!< 0x00000010 */
#define UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk /*!< Hard reset discarded flag (HRSTDISC) clear */
#define UCPD_ICR_HRSTSENTCF_Pos (5U)
#define UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) /*!< 0x00000020 */
#define UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk /*!< Hard reset sent flag (HRSTSENT) clear */
#define UCPD_ICR_TXUNDCF_Pos (6U)
#define UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) /*!< 0x00000040 */
#define UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk /*!< Tx underflow flag (TXUND) clear */
#define UCPD_ICR_RXORDDETCF_Pos (9U)
#define UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) /*!< 0x00000200 */
#define UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk /*!< Rx ordered set detect flag (RXORDDET) clear */
#define UCPD_ICR_RXHRSTDETCF_Pos (10U)
#define UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) /*!< 0x00000400 */
#define UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk /*!< Rx Hard Reset detected flag (RXHRSTDET) clear */
#define UCPD_ICR_RXOVRCF_Pos (11U)
#define UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) /*!< 0x00000800 */
#define UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk /*!< Rx overflow flag (RXOVR) clear */
#define UCPD_ICR_RXMSGENDCF_Pos (12U)
#define UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) /*!< 0x00001000 */
#define UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk /*!< Rx message received flag (RXMSGEND) clear */
#define UCPD_ICR_TYPECEVT1CF_Pos (14U)
#define UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) /*!< 0x00004000 */
#define UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk /*!< TypeC event (CC1) flag (TYPECEVT1) clear */
#define UCPD_ICR_TYPECEVT2CF_Pos (15U)
#define UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) /*!< 0x00008000 */
#define UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk /*!< TypeC event (CC2) flag (TYPECEVT2) clear */
#define UCPD_ICR_FRSEVTCF_Pos (20U)
#define UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) /*!< 0x00100000 */
#define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role Swap event flag clear */
/******************** Bits definition for UCPD_TXORDSET register **************/
#define UCPD_TX_ORDSET_TXORDSET_Pos (0U)
#define UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos)/*!< 0x000FFFFF */
#define UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk /*!< Tx Ordered Set */
/******************** Bits definition for UCPD_TXPAYSZ register ****************/
#define UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U)
#define UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk /*!< Tx payload size in bytes */
/******************** Bits definition for UCPD_TXDR register *******************/
#define UCPD_TXDR_TXDATA_Pos (0U)
#define UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) /*!< 0x000000FF */
#define UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk /*!< Tx Data Register */
/******************** Bits definition for UCPD_RXORDSET register **************/
#define UCPD_RX_ORDSET_RXORDSET_Pos (0U)
#define UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000007 */
#define UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk /*!< Rx Ordered Set Code detected */
#define UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000001 */
#define UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000002 */
#define UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) /*!< 0x00000004 */
#define UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U)
#define UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos)/*!< 0x00000008 */
#define UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk /*!< Rx Ordered Set Debug indication */
#define UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U)
#define UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos)/*!< 0x00000070 */
#define UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
/******************** Bits definition for UCPD_RXPAYSZ register ****************/
#define UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U)
#define UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos)/*!< 0x000003FF */
#define UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk /*!< Rx payload size in bytes */
/******************** Bits definition for UCPD_RXDR register *******************/
#define UCPD_RXDR_RXDATA_Pos (0U)
#define UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) /*!< 0x000000FF */
#define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit receive data */
/******************** Bits definition for UCPD_RXORDEXT1 register **************/
#define UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U)
#define UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk /*!< RX Ordered Set Extension Register 1 */
/******************** Bits definition for UCPD_RXORDEXT2 register **************/
#define UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U)
#define UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos)/*!< 0x000FFFFF */
#define UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk /*!< RX Ordered Set Extension Register 1 */
/******************************************************************************/
/* */
/* Window WATCHDOG */
/* */
/******************************************************************************/
/******************* Bit definition for WWDG_CR register ********************/
#define WWDG_CR_T_Pos (0U)
#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
#define WWDG_CR_WDGA_Pos (7U)
#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
/******************* Bit definition for WWDG_CFR register *******************/
#define WWDG_CFR_W_Pos (0U)
#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
#define WWDG_CFR_WDGTB_Pos (11U)
#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
#define WWDG_CFR_EWI_Pos (9U)
#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
/******************* Bit definition for WWDG_SR register ********************/
#define WWDG_SR_EWIF_Pos (0U)
#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
/**
* @}
*/
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
((INSTANCE) == ADC2) || \
((INSTANCE) == ADC3))
#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) || \
((INSTANCE) == ADC345_COMMON) )
/******************************* AES Instances ********************************/
#define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES)
/******************************** FDCAN Instances ******************************/
#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1) || \
((INSTANCE) == FDCAN2))
#define IS_FDCAN_CONFIG_INSTANCE(INSTANCE) ((INSTANCE) == FDCAN_CONFIG)
/******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2) || \
((INSTANCE) == COMP3) || \
((INSTANCE) == COMP4))
/******************************* CORDIC Instances *****************************/
#define IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC)
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1) || \
((INSTANCE) == DAC3))
/******************************** DMA Instances *******************************/
#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
((INSTANCE) == DMA1_Channel2) || \
((INSTANCE) == DMA1_Channel3) || \
((INSTANCE) == DMA1_Channel4) || \
((INSTANCE) == DMA1_Channel5) || \
((INSTANCE) == DMA1_Channel6) || \
((INSTANCE) == DMA1_Channel7) || \
((INSTANCE) == DMA1_Channel8) || \
((INSTANCE) == DMA2_Channel1) || \
((INSTANCE) == DMA2_Channel2) || \
((INSTANCE) == DMA2_Channel3) || \
((INSTANCE) == DMA2_Channel4) || \
((INSTANCE) == DMA2_Channel5) || \
((INSTANCE) == DMA2_Channel6) || \
((INSTANCE) == DMA2_Channel7) || \
((INSTANCE) == DMA2_Channel8))
#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
((INSTANCE) == DMAMUX1_RequestGenerator1) || \
((INSTANCE) == DMAMUX1_RequestGenerator2) || \
((INSTANCE) == DMAMUX1_RequestGenerator3))
/******************************* FMAC Instances *******************************/
#define IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC)
/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB) || \
((INSTANCE) == GPIOC) || \
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOE) || \
((INSTANCE) == GPIOF) || \
((INSTANCE) == GPIOG))
/******************************* GPIO AF Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/**************************** GPIO Lock Instances *****************************/
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3))
/****************** I2C Instances : wakeup capability from stop modes *********/
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
/****************************** OPAMP Instances *******************************/
#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
((INSTANCE) == OPAMP2) || \
((INSTANCE) == OPAMP3) || \
((INSTANCE) == OPAMP6))
/******************************** PCD Instances *******************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/******************************* QSPI Instances *******************************/
#define IS_QSPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == QUADSPI)
/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
#define IS_TAMP_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TAMP)
/****************************** SMBUS Instances *******************************/
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2) || \
((INSTANCE) == I2C3))
/******************************** SAI Instances *******************************/
#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || ((INSTANCE) == SAI1_Block_B))
/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
((INSTANCE) == SPI2) || \
((INSTANCE) == SPI3))
/******************************** I2S Instances *******************************/
#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI2) || \
((__INSTANCE__) == SPI3))
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : supporting encoder interface **************/
#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** LPTIM Instances : All supported instances *****************/
#define IS_LPTIM_ENCODER_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
/****************** TIM Instances : All supported instances *******************/
#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 32 bits counter ****************/
#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
/****************** TIM Instances : supporting the break function *************/
#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************** TIM Instances : supporting Break source selection *************/
#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting 2 break inputs *****************/
#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : at least 1 capture/compare channel *************/
#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 2 capture/compare channels *************/
#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 3 capture/compare channels *************/
#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : at least 4 capture/compare channels *************/
#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 5 capture/compare channels *******/
#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : at least 6 capture/compare channels *******/
#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/
#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/
#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************** TIM Instances : DMA burst feature ***********************/
#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : output(s) available **********************/
#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM2) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM3) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM4) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))) \
|| \
(((INSTANCE) == TIM15) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))) \
|| \
(((INSTANCE) == TIM16) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM17) && \
(((CHANNEL) == TIM_CHANNEL_1))) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4) || \
((CHANNEL) == TIM_CHANNEL_5) || \
((CHANNEL) == TIM_CHANNEL_6))))
/****************** TIM Instances : supporting complementary output(s) ********/
#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
((((INSTANCE) == TIM1) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM8) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))) \
|| \
(((INSTANCE) == TIM15) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM16) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM17) && \
((CHANNEL) == TIM_CHANNEL_1)) \
|| \
(((INSTANCE) == TIM20) && \
(((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2) || \
((CHANNEL) == TIM_CHANNEL_3) || \
((CHANNEL) == TIM_CHANNEL_4))))
/****************** TIM Instances : supporting clock division *****************/
#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15)|| \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting commutation event generation ***/
#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting counting mode selection ********/
#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting encoder interface **************/
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting Hall sensor interface **********/
#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/**************** TIM Instances : external trigger input available ************/
#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/************* TIM Instances : supporting ETR source selection ***************/
#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/
#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM6) || \
((INSTANCE) == TIM7) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting OCxREF clear *******************/
#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting bitfield OCCS in SMCR register *******************/
#define IS_TIM_OCCS_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : remapping capability **********************/
#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting repetition counter *************/
#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input XOR function *****************/
#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM20))
/******************* TIM Instances : Timer input selection ********************/
#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM2) || \
((INSTANCE) == TIM3) || \
((INSTANCE) == TIM4) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM15) || \
((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : Advanced timer instances *******************/
#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
((INSTANCE) == TIM8) || \
((INSTANCE) == TIM20))
/****************** TIM Instances : supporting HSE/32 request instances *******************/
#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17))
/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** UART Instances : Asynchronous mode **********************/
#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/*********************** UART Instances : FIFO mode ***************************/
#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : SPI Slave mode **********************/
#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/****************** UART Instances : Auto Baud Rate detection ****************/
#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/****************** UART Instances : Driver Enable *****************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/******************** UART Instances : Wake-up from Stop mode **********************/
#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5) || \
((INSTANCE) == LPUART1))
/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == UART4) || \
((INSTANCE) == UART5))
/********************* USART Instances : Smard card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3))
/******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
/****************************** UCPD Instances ********************************/
#define IS_UCPD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == UCPD1)
/******************************* USB Instances *******************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
/**
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32G4xx device product */
/* lines, the aliases defined below are put in place to overcome the */
/* differences in the interrupt handlers and IRQn definitions. */
/* No need to update developed interrupt code when moving across */
/* product lines within the same STM32G4 Family */
/******************************************************************************/
/* Aliases for __IRQn */
/* Aliases for __IRQHandler */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32G4A1xx_H */
/**
* @}
*/
/**
* @}
*/
| 1,051,185 | C | 74.375448 | 180 | 0.510401 |
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